Semiconductor device

Abstract

To provide a transistor with high yield, which has high electrical characteristics though having a fine structure; and achieve high performance, high reliability and high productivity in a semiconductor device including the transistor.SOLUTION: In a semiconductor device which has a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions sandwiching the channel formation region, a gate insulation film and a gate electrode layer with an insulation film including an aluminum oxide film which covers a top face and lateral faces are sequentially laminated, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and a top face and part of lateral faces of the insulation film including the aluminum oxide film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called TFTs) is attracting attention. It is widely used in electronic devices such as ICs and image display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors are attracting attention.

[0004] For example, amorphous alloys containing indium (In), gallium (Ga), and zinc (Zn) A transistor using a semiconductor layer made of oxide (In-Ga-Zn-O amorphous oxide) A gyroscope is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-181801 A Summary of the Invention [Problem to be solved by the invention]

[0006] By the way, in order to achieve high speed operation of transistors, low power consumption, high integration, etc. In order to achieve this, miniaturization of transistors is essential.

[0007] In order to realize semiconductor devices with higher performance, the on-characteristics of miniaturized transistors (e.g. By improving the on-state current and field effect mobility, we aim to realize high-speed response and high-speed operation of semiconductor devices. It is an object of the present invention to provide a structure and a manufacturing method thereof.

[0008] In addition, there is a concern that the miniaturization of transistors will result in a decrease in yield in the manufacturing process.

[0009] We provide transistors with high electrical characteristics and reliability even with fine structures with good yield. One of the purposes of this organization is to provide

[0010] In addition, semiconductor devices including the transistors also have high performance, high reliability, and high productivity. One of the objectives is to achieve this. [Means for solving the problem]

[0011] An insulating film including an oxide semiconductor film, a gate insulating film, and an aluminum oxide film covering the top surface and side surfaces. In a semiconductor device having a transistor in which gate electrode layers each having a film are stacked in order, The source electrode layer and the drain electrode layer are formed of an insulating material including an oxide semiconductor film and an aluminum oxide film. The oxide semiconductor film is provided in contact with a top surface and a part of a side surface of the insulating film. and preferably includes low resistance regions sandwiching the channel formation region.

[0012] The upper and side surfaces of the gate electrode layer are covered with an insulating film containing an aluminum oxide film. Even if the source electrode layer and the drain electrode layer overlap with the top surface of the gate electrode layer, the aluminum oxide film is not formed. The insulating film may prevent short-circuiting between the source electrode layer or the drain electrode layer and the gate electrode layer. Electrical failure can be prevented, and thus the yield of transistors having fine structures can be increased. It can be produced more easily.

[0013] In addition, in the semiconductor device, oxygen is introduced into the oxide semiconductor film in a manufacturing process. The upper and side surfaces of the gate electrode layer are covered with an aluminum oxide film. By covering the gate electrode layer with an insulating film containing A part of the insulating film including an aluminum oxide film is formed on the insulating film. can be done.

[0014] Insulating films containing aluminum oxide are highly resistant to both impurities such as hydrogen and moisture, and oxygen. It has a high blocking effect that does not allow substances to pass through the membrane.

[0015] Therefore, the insulating film including the aluminum oxide film is subject to fluctuations during and after the manufacturing process. Impurities such as hydrogen and moisture are mixed into the oxide semiconductor film, and the oxide semiconductor is It functions as a protective film that prevents oxygen, which is a main component material, from being released from the oxide semiconductor film. This makes it possible to impart stable electrical characteristics to the transistor.

[0016] The oxide semiconductor film is provided with oxygen (at least any of oxygen radicals, oxygen atoms, and oxygen ions). The oxygen is supplied to the film by introducing oxygen into the film. The oxygen introduction method includes ion implantation, Ion doping method, plasma immersion ion implantation method, plasma treatment Theories, etc. can be used.

[0017] Further, a dopant is introduced into the oxide semiconductor film in a self-aligned manner by using the gate electrode layer as a mask; In the oxide semiconductor film, the resistance between the channel formation region and the drain region is lower than that between the channel formation region and the drain region. A low-resistance region containing a dopant is formed. The dopant changes the electrical conductivity of the oxide semiconductor film. Dopants are introduced by ion implantation and ion doping. , plasma immersion ion implantation, etc. can be used.

[0018] The present invention provides a method for manufacturing a semiconductor device comprising the steps of: forming a channel in a channel length direction; As a result, the transistor has high on-characteristics (e.g., on-current and field-effect mobility), High-speed operation and high-speed response are possible.

[0019] One embodiment of the invention disclosed in this specification is a semiconductor device having an oxide insulating film and an oxide semiconductor film. a gate insulating film over the oxide semiconductor film; and a gate insulating film overlapping with the channel formation region. a gate electrode layer; and an insulating film including an aluminum oxide film covering an upper surface and a side surface of the gate electrode layer. , the oxide semiconductor film, and the insulating film including the aluminum oxide film The semiconductor device has a wiring layer.

[0020] One embodiment of the present invention disclosed in this specification is a channel forming a low-resistance region between which a channel formation region is sandwiched; and an oxide semiconductor film including the low-resistance region and the channel formation region. A gate insulating film is formed on the channel forming region, a gate electrode layer is formed on the gate insulating film overlapping the channel forming region, and An insulating film including an aluminum oxide film covering the upper surface and side surfaces of the gate electrode layer, a low resistance region, and and a wiring layer in contact with the upper surface and part of the side surface of the insulating film including the aluminum oxide film. The resistive region is a semiconductor device that contains dopants.

[0021] One embodiment of the invention disclosed in this specification is a semiconductor device having an oxide insulating film and an oxide semiconductor film. a gate insulating film over the oxide semiconductor film; and a gate insulating film overlapping with the channel formation region. a gate electrode layer; and an insulating film including an aluminum oxide film covering an upper surface and a side surface of the gate electrode layer. an insulating film including an oxide semiconductor film, a gate insulating film, a gate electrode layer, and an aluminum oxide film; An interlayer insulating layer having an opening reaching the oxide semiconductor film is provided thereon, and an oxide semiconductor film is provided in the opening. Wiring contacting a part of the upper surface and side surface of an insulating film including an aluminum oxide film and a semiconductor film The semiconductor device has a layer.

[0022] One embodiment of the present invention disclosed in this specification is a channel forming a low-resistance region between which a channel formation region is sandwiched; and an oxide semiconductor film including the low-resistance region and the channel formation region. A gate insulating film is formed on the channel forming region, a gate electrode layer is formed on the gate insulating film overlapping the channel forming region, and an insulating film including an aluminum oxide film covering an upper surface and a side surface of a gate electrode layer; an oxide semiconductor film; A low resistance region is formed on the insulating film including the gate insulating film, the gate electrode layer, and the aluminum oxide film. The interlayer insulating layer has an opening extending to the surface of the insulating layer, and the low resistance region and the aluminum oxide are formed in the opening. and a wiring layer in contact with a top surface and a part of a side surface of the insulating film including the aluminum film. The semiconductor device includes a transistor.

[0023] The oxide semiconductor film overlaps with the gate electrode layer and the insulating film including the aluminum oxide film. The region is higher than a region that does not overlap with the gate electrode layer and the insulating film including the aluminum oxide film. It may also be configured to have an oxygen concentration.

[0024] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed on the nitride semiconductor film, and an oxide film is formed on the gate electrode layer to cover the upper and side surfaces of the gate electrode layer. An insulating film including an aluminum film is formed, and an oxide semiconductor film and an insulating film including an aluminum oxide film are formed. The method for manufacturing a semiconductor device includes forming a wiring layer in contact with a top surface and a part of a side surface of an insulating film.

[0025] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed so as to overlap with the oxide semiconductor film, and the gate electrode layer is used as a mask to form a gate electrode layer on the oxide semiconductor film. A dopant is selectively introduced into the film to form a low resistance region, and the top and side surfaces of the gate electrode layer are An insulating film including an aluminum oxide film covering the low resistance region and the aluminum oxide film is formed. A method for manufacturing a semiconductor device in which a wiring layer is formed in contact with a top surface and a part of a side surface of an insulating film including the insulating film. do.

[0026] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed on the nitride semiconductor film, and an oxide film is formed on the gate electrode layer to cover the upper and side surfaces of the gate electrode layer. An insulating film including an aluminum film is formed, and an oxide semiconductor film, a gate insulating film, a gate electrode layer, and and forming an interlayer insulating layer on the insulating film including the aluminum oxide film, and forming an oxide semiconductor layer on the interlayer insulating layer. and forming an opening through which a portion of the upper surface and side surface of the insulating film including the aluminum oxide film is exposed. The opening is provided with a top surface and a side surface of the insulating film including the oxide semiconductor film and the aluminum oxide film. This is a method for manufacturing a semiconductor device in which a wiring layer is formed in contact with a part of the semiconductor device.

[0027] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed so as to overlap with the oxide semiconductor film, and the gate electrode layer is used as a mask to form a gate electrode layer on the oxide semiconductor film. A dopant is selectively introduced into the film to form a low resistance region, and the top and side surfaces of the gate electrode layer are An insulating film including an aluminum oxide film is formed to cover the oxide semiconductor film, the gate insulating film, and the gate An interlayer insulating layer is formed on the electrode layer and the insulating film including the aluminum oxide film, and a low-temperature insulating film is formed on the interlayer insulating layer. An opening exposing a resistor region and a part of the top and side surfaces of an insulating film including an aluminum oxide film and forming a low resistance region and an upper surface and a side surface of the insulating film including the aluminum oxide film in the opening. The present invention relates to a method for manufacturing a semiconductor device, and a wiring layer is formed in contact with a part of the semiconductor device.

[0028] In the above structure, the gate insulating film is etched using the gate electrode layer as a mask to oxidize the gate insulating film. An insulating film including an aluminum film may be in contact with the oxide semiconductor film. A gate insulating film may be provided between the insulating film containing tungsten and the oxide semiconductor film. .

[0029] In the above structure, a wiring layer (a source electrode layer or An electrode layer overlapping with the drain electrode layer may be provided. The electrode layer may be provided over the oxide insulating film. Alternatively, the insulating film may be embedded in the oxide insulating film.

[0030] Under the oxide semiconductor film, a wiring layer (a source electrode layer or a drain electrode layer) and the oxide semiconductor film By providing an electrode layer in the contact region, a source electrode layer and a drain electrode layer are formed. The contact resistance between the wiring layer, which functions as a gate electrode layer, and the oxide semiconductor film can be reduced. Therefore, the on-characteristics of the transistor can be improved.

[0031] In the above structure, the surface of the oxide insulating film on which the oxide semiconductor film is formed is flattened by planarization treatment. A thin oxide semiconductor film can be provided with good coverage. The process includes chemical mechanical polishing, etching, plasma treatment, etc., either alone or in combination. It can be used in combination.

[0032] Further, a heat treatment for releasing hydrogen or moisture into the oxide semiconductor film (dehydration or dehydrogenation treatment) may be performed. In addition, when a crystalline oxide semiconductor film is used as the oxide semiconductor film, A heat treatment for crystallization may be carried out.

[0033] One embodiment of the present invention includes a transistor or a circuit including a transistor. The present invention relates to a semiconductor device, for example, a transistor in which a channel formation region is formed using an oxide semiconductor. The present invention relates to a semiconductor device having a circuit including a transistor. , LSI, CPU, power devices mounted on power circuits, memory, thyristors, converters, semiconductor integrated circuits including image sensors, and liquid crystal display panels. The present invention relates to electronic equipment that incorporates, as a component, a light-emitting display device having a magneto-optical device or a light-emitting element. Effect of the Invention

[0034] We provide transistors with high electrical characteristics and reliability even with fine structures with good yield. It can be provided.

[0035] In addition, semiconductor devices including the transistors also have high performance, high reliability, and high productivity. It is possible to achieve this. [Brief description of the drawings]

[0036] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Diagram 3] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 4] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 5] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 7] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 8] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 11] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 12] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and the forms and details thereof may be changed in various ways. It will be easily understood by those skilled in the art that the invention disclosed in this specification can be modified in any manner. The present invention should not be construed as being limited to the description of the following embodiments. The ordinal numbers 2 are used for convenience and do not indicate the order of steps or stacking. In addition, the present specification does not indicate specific names as matters for identifying the invention. do not have.

[0038] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor film is used as an example of a semiconductor device. Shows.

[0039] A transistor can have either a single-gate structure in which one channel formation region is formed or a structure in which two are formed. The gate structure may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. The semiconductor device has two gate electrode layers arranged above and below the channel forming region with a gate insulating film interposed therebetween. A dual gate type may also be used.

[0040] The transistor 440a shown in FIGS. 1A and 1B is a top-gate transistor. FIG. 1(A) is a plan view of the device taken along the dashed line X1-Y1 in FIG. The cross section corresponds to FIG. 1(B). Note that the interlayer insulating film 415 is omitted in FIG. 1(A). is.

[0041] As shown in FIG. 1B, which is a cross-sectional view in the channel length direction, a semiconductor device including a transistor 440a The semiconductor device is formed by forming a channel on a substrate 400 having an insulating surface provided with an oxide insulating film 436. a gate electrode forming region 409; an oxide semiconductor film 403 including low-resistance regions 404a and 404b; An insulating film 402, a gate electrode layer 401, and an aluminum oxide film covering the upper surface and side surfaces of the gate electrode layer 401. The insulating film 414 including a minium film, the interlayer insulating film 415, the source electrode layer 405a, the drain electrode It has a pole layer 405b.

[0042] The interlayer insulating film 415 is provided to flatten the unevenness caused by the transistor 440a. , low resistance regions 404a and 404b, an insulating film 414 including an aluminum oxide film, a gate insulating film The low-resistance region 4 of the oxide semiconductor film 403 is exposed through the opening. 04a, 404b, the gate insulating film 402, and the insulating film 414 including an aluminum oxide film A source electrode layer 405a and a drain electrode layer 405b are provided in contact with the upper surface and part of the side surface of the It is being done.

[0043] In this embodiment, an aluminum oxide film is used as the insulating film 414 including an aluminum oxide film. The aluminum oxide film is made of high density (film density 3.2 g / cm 3 Above 3.6, preferably 3.6 g / cm 3 or more), the transistor 440a can have stable electrical characteristics. The film density can be measured by Rutherford Backscattering Spectroscopy (RBS). Backscattering Spectrometry and X-ray reflectometry (X It can be measured by X-Ray Reflection (RR). The aluminum film has oxygen in the film (bulk) at least in an amount exceeding the stoichiometric ratio. For example, when an aluminum oxide film is used, AlO x (however, x>1.5).

[0044] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. Therefore, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate electrode layer 401. The insulating film 414 including the aluminum oxide film prevents the source electrode layer 405a from overlapping the surface of the insulating film 414. Alternatively, in order to prevent an electrical failure such as a short circuit between the drain electrode layer 405b and the gate electrode layer 401, Therefore, the transistor 440a having a fine structure can be manufactured with high yield. It is possible.

[0045] The insulating film including the aluminum oxide film may have a structure covering the top and side surfaces of the gate electrode layer. Alternatively, the transistor 440 may be provided over a gate insulating film like the transistor 440a. For example, a transistor 410a shown in FIG. Then, the gate insulating film 402 is etched using the gate electrode layer 401 as a mask to form a gate electrode An aluminum oxide film is formed on the top and sides of the stack of the layer 401 and the gate insulating film 402. In the transistor 410a, an insulating film 414 containing an oxide may be provided. The compound semiconductor film 403 and the insulating film 414 including the aluminum oxide film are in contact with each other.

[0046] The insulating film including the aluminum oxide film covering the upper surface and side surfaces of the gate electrode layer is A continuous single membrane can be used as shown in FIG. 1. Alternatively, multiple membranes can be used, e.g. For example, as in a transistor 410b shown in FIG. 3B, The insulating films 414a and 414b including the aluminum oxide film and the upper surface of the gate electrode layer 401 Alternatively, a structure may be used in which a plurality of insulating films 414c including an aluminum oxide film covering the insulating film 414 may be provided. .

[0047] In addition, in the manufacturing process of the semiconductor device, the oxide semiconductor film 403 is supplying oxygen into the film by introducing oxygen radicals, oxygen atoms, or oxygen ions The oxygen introduction method includes ion implantation, ion doping, plasma immersion, etc. For example, ion implantation, plasma treatment, etc. can be used.

[0048] The oxide semiconductor film 403 provided in the transistor 440a is in a crystalline state. It is preferable that the film contains a region in which the oxygen content is excessive with respect to the stoichiometric composition in the film. In this case, the oxygen content is set to a level exceeding the stoichiometric ratio of the oxide semiconductor. In other words, the oxygen content is set to a level exceeding that in the case of a single crystal. Oxygen may be present between the atoms.

[0049] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. As a result, the channel formation region 4 of the oxide semiconductor film 403 overlapping with the gate electrode layer 401 is 09 and a part of the low resistance regions 404a and 404b are covered with an insulating film 41 containing an aluminum oxide film. The structure can be such that it is covered with 4.

[0050] The insulating film 414 including the aluminum oxide film is resistant to both impurities such as hydrogen and moisture and oxygen. In contrast, it has a high blocking effect that prevents substances from passing through the membrane.

[0051] Therefore, the insulating film including the aluminum oxide film is subject to fluctuations during and after the manufacturing process. Impurities such as hydrogen and moisture are mixed into the oxide semiconductor film, and the oxide semiconductor is It functions as a protective film that prevents oxygen, which is a main component material, from being released from the oxide semiconductor film. This allows the transistor 440a to have stable electrical characteristics.

[0052] Note that the gate electrode layer 401 is used as a mask to form a dopant layer on the oxide semiconductor film 403 in a self-aligned manner. The oxide semiconductor film 403 is formed by introducing a channel-forming region 409 between the channel-forming region 409 and the oxide semiconductor film 403. The low resistance regions 404a and 404b are formed by doping the dopant. The dopant is an impurity that changes the electrical conductivity of the oxide semiconductor film 403. The methods of introducing ions include ion implantation, ion doping, and plasma immersion ion implantation. For example, a ion implantation method can be used.

[0053] The low resistance regions 404a and 404b are disposed on either side of the channel forming region 409 in the channel length direction. By including the oxide semiconductor film 403, the transistor 440a has on-state characteristics (for example, , on-state current and field effect mobility) are high, enabling high-speed operation and high-speed response.

[0054] The oxide semiconductor used for the oxide semiconductor film 403 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. A stabilizer for reducing variations in electrical characteristics of a transistor using the oxide In addition to these, it is preferable to have gallium (Ga) as a stabilizer. It is preferable to have tin (Sn) as a sintering agent, and hafnium as a stabilizer. It is preferable to use aluminum (Al) as a stabilizer. It is preferable that the stabilizer contains zirconium (Zr). is preferred.

[0055] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0056] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0057] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0058] In addition, InMO 3 (ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. The metal element is one or more metal elements. In 2 SnO 5 (ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0059] For example, In:Ga:Zn=1:1:1(=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxide with an atomic ratio of (=1 / 2:1 / 6:1 / 3) and its neighboring compositions Alternatively, the oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is preferable to use -Zn-based oxides or oxides having a composition close to that.

[0060] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to use an appropriate one.

[0061] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by lowering the defect density in the bulk. It can be done.

[0062] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0063] The oxide semiconductor film 403 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0064] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0065] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often small enough to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image by a microscope, the boundary between the amorphous and crystalline parts in the CAAC-OS film was In addition, the grain boundaries in the CAAC-OS film were not clearly observed by TEM. Therefore, the CAAC-OS film is not characterized by electron transfer caused by grain boundaries. The decrease in mobility is suppressed.

[0066] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that The range of 5° to 95° is also included. This also includes the range from 1° to 5°.

[0067] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0068] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0069] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0070] Note that part of oxygen contained in the oxide semiconductor film may be replaced with nitrogen.

[0071] In addition, in an oxide semiconductor having a crystalline part such as CAAC-OS, defects in the bulk can be further reduced. By improving the flatness of the surface, the mobility can be reduced more than that of an amorphous oxide semiconductor. In order to improve the flatness of the surface, it is necessary to deposit an oxide semiconductor on the flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0 It is advisable to form it on a surface that is 0.3 nm or less, more preferably 0.1 nm or less.

[0072] Ra is defined in JIS B 0601:2001 (ISO4287:1997). This is a three-dimensional extension of the arithmetic mean roughness, which is currently used, so that it can be applied to curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviation from the specified surface to the target surface" and is defined by the following formula.

[0073]

number

[0074] Here, the specified surface is the surface to be measured for roughness, and the coordinates (x 1 ,y 1 ,f(x1 ,y 1 )),(x 1 ,y 2 ,f(x 1 ,y 2 )),(x 2 ,y 1 ,f(x 2 ,y 1 )),(x 2 ,y 2 ,f(x 2 ,y 2 )) is a rectangular area represented by the four points, and the specified surface is the xy plane. The area of ​​the projected rectangle is S 0 , the height of the reference surface (the average height of the specified surface) is Z 0 Let us assume that Ra was measured using an atomic force microscope (AFM). It is possible to determine

[0075] The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). m or less) and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Dep The oxide semiconductor film 403 can be formed by a spatulation method or the like. Film deposition is performed on multiple substrate surfaces set approximately perpendicular to the target surface. Alternatively, the film may be formed using a sputtering apparatus which performs the above steps.

[0076] The CAAC-OS film can be formed, for example, by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions in the sputtering target cleave from the ab plane, forming a -b: The particles peel off as plate-like or pellet-like sputtered particles with surfaces parallel to the surface. In this case, the plate-like sputtered particles may be crystalline and may be crystalline. By reaching the plate, a CAAC-OS film can be formed.

[0077] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0078] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0079] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably The deposition temperature is set to 200°C or higher and 500°C or lower. When a plate-shaped sputtered particle reaches a substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0080] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0081] As an example of a sputtering target, an In-Ga-Zn-O compound target is The details are shown below.

[0082] InO X powder, GaO Y Powder and ZnOZ The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000 and 1500℃, polycrystalline In-Ga -Zn-O compound target, where X, Y and Z are any positive numbers. , the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. The setting can be changed as appropriate depending on the model.

[0083] 2A to 2D show an example of a method for manufacturing a semiconductor device including a transistor 440a. vinegar.

[0084] First, an oxide insulating film 436 is formed over a substrate 400 having an insulating surface.

[0085] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary to have heat resistance sufficient to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. In addition, a silicon substrate, a silicon carbide substrate, etc. can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A semiconductor device having a semiconductor element on a substrate such as a silicon-on-insulator (SOI) substrate can also be used. may be used as the substrate 400.

[0086] A semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture such a semiconductor device, a transistor including an oxide semiconductor film 403 is formed on a flexible substrate. Alternatively, the transistor 440a including the oxide semiconductor film 403 may be formed on another substrate. Alternatively, the resistor 440a may be fabricated and then peeled off and transferred to a flexible substrate. In order to peel and transfer the transistor 4 including the oxide semiconductor film from the substrate to a flexible substrate, A release layer may be provided between 40a and the film.

[0087] The oxide insulating film 436 is formed by a plasma CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide , gallium oxide, or a mixture of these materials.

[0088] The oxide insulating film 436 may be a single layer or a stacked layer. For example, Alternatively, the In-Hf-Zn oxide film and the oxide semiconductor film 403 may be laminated in this order on the substrate 4. 00, silicon oxide film, In-Zr-Zn with atomic ratio of In:Zr:Zn=1:1:1 A silicon oxide film and an oxide semiconductor film 403 may be stacked in this order. In-Gd-Zn oxide film with an atomic ratio of In:Gd:Zn=1:1:1, oxide The semiconductor films 403 may be stacked in order.

[0089] In this embodiment, the oxide insulating film 436 is formed by a silicon oxide film formed by a sputtering method. Use a Con membrane.

[0090] Alternatively, a nitride insulating film may be provided between the oxide insulating film 436 and the substrate 400. The insulating film is made of silicon nitride or silicon oxide nitride by plasma CVD or sputtering. It is made of aluminum nitride, aluminum oxide nitride, or a mixture of these materials. It is possible.

[0091] Next, the oxide semiconductor film 403 is formed over the oxide insulating film 436.

[0092] The oxide insulating film 436 is in contact with the oxide semiconductor film 403 and therefore contains at least In both cases, the amount of oxygen contained is preferably greater than the stoichiometric ratio. When a silicon oxide film is used as 6, SiO 2+α (where α>0). By using such an oxide insulating film 436, oxygen can be supplied to the oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, the characteristics can be improved. As a result, oxygen vacancies in the film can be compensated for.

[0093] For example, the oxide insulating film 436 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed as an oxide semiconductor. By providing the oxide insulating film 436 in contact with the oxide semiconductor film 403, The oxide semiconductor film 403 and the oxide insulating film 436 can be supplied with oxygen. By performing heat treatment in a state where the oxide semiconductor film 403 is at least partially in contact with the oxide semiconductor film 403, oxygen is introduced into the oxide semiconductor film 403. Supply may be provided.

[0094] In the process of forming the oxide semiconductor film 403, hydrogen or water is added to the oxide semiconductor film 403. In order to prevent the inclusion of the oxide semiconductor film 403, a sputtering process was performed as a pretreatment for the formation of the oxide semiconductor film 403. The substrate on which the oxide insulating film 436 is formed is preheated in a preheating chamber of a deposition apparatus. It is preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed in the oxide insulating film 436. The exhaust means provided in the preheating chamber is preferably a cryopump.

[0095] A planarization treatment is performed on a region of the oxide insulating film 436 which is in contact with the oxide semiconductor film 403. The planarization process may be, but is not limited to, a polishing process (e.g., chemical polishing). Mechanical polishing, dry etching, and plasma treatment can be used.

[0096] The plasma treatment may be, for example, a reverse sputtering treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma in the vicinity of the substrate to modify the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the oxide insulating film 436 is subjected to the cleaning, powdery substances (particles, dust, etc.) attached to the surface of the oxide insulating film 436 are removed. (also called) can be removed.

[0097] As the planarization process, the polishing process, the dry etching process, and the plasma process may be performed multiple times. In addition, when performing the steps in combination, the order of the steps is not particularly limited. The thickness is not limited to a specific value and may be appropriately set depending on the unevenness of the surface of the oxide insulating film 436.

[0098] The planarization treatment is performed by, for example, applying a chemical functional group to the surface of the silicon oxide film used as the oxide insulating film 436. The silicon oxide film surface is polished by mechanical polishing to an average surface roughness (Ra) of approximately 0. .15nm would be fine.

[0099] Note that the oxide semiconductor film 403 is formed under conditions in which a large amount of oxygen is contained (for example, The film is formed by sputtering in a 100% oxygen atmosphere. (preferably, the oxide semiconductor has a stoichiometric composition in a crystalline state, and the content of oxygen is It is preferable that the membrane is a membrane having an excess of ZnO.

[0100] Note that in this embodiment, the oxide semiconductor film 403 is formed by a sputtering method. The target for this purpose is a gold alloy with a composition of In:Ga:Zn=3:1:2 [atomic ratio]. An In-Ga-Zn oxide film (IGZO film) is formed using a metal oxide target.

[0101] The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The relative density is 95% or more and 99.9% or less. Use a metal oxide target with high relative density. As a result, the formed oxide semiconductor film can be a dense film.

[0102] The oxide semiconductor film 403 is formed using a sputtering gas of hydrogen, water, a hydroxyl group, or an arsenic compound. It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0103] The substrate is held in a film-forming chamber that is kept in a reduced pressure state. Then, the remaining moisture in the film-forming chamber is removed. A sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the above target. In order to remove residual moisture in the deposition chamber, an oxide semiconductor film 403 is formed on the substrate. type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps It is preferable to use a turbo molecular pump with a cold trap as the exhaust means. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen atom, water (H 2Compounds containing hydrogen atoms, such as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, Since gases such as impurities and impurities are exhausted from the deposition chamber, the oxide semiconductor film 403 formed in the deposition chamber is The concentration of substances can be reduced.

[0104] In addition, the oxide insulating film 436 and the oxide semiconductor film 403 are formed in succession without exposure to air. It is preferable that the oxide insulating film 436 and the oxide semiconductor film 403 be connected without being exposed to air. When the oxide insulating film 436 is formed in succession, impurities such as hydrogen and moisture are adsorbed on the surface of the oxide insulating film 436. It can be prevented.

[0105] Next, oxygen (at least oxygen radicals, oxygen atoms, or oxygen ions) is added to the oxide semiconductor film 403. (including any one of the above) is introduced to supply oxygen to the oxide semiconductor film. These include ion implantation, ion doping, plasma immersion ion implantation, etc. For example, deposition method, plasma treatment, etc. can be used.

[0106] In the manufacturing process of the transistor 440a in this embodiment, the oxygen introduction step is performed by using an oxygen It is preferable to perform this step after the formation of the nitride semiconductor film 403 and before the formation of the gate electrode layer 401. Oxygen may be introduced into the oxide semiconductor film 403 multiple times.

[0107] In the step of introducing oxygen, oxygen may be introduced directly into the oxide semiconductor film 403 or into the gate insulating film 404. Oxygen may be introduced into the oxide semiconductor film 403 through another film such as a fluorine-containing oxide film. When introducing the ions into 403 through other membranes, the ion implantation method, ion doping method, plasma Although it is possible to use a method such as myoblast ion implantation, In the case where the compound is directly introduced into the oxide semiconductor film 403, plasma treatment or the like can be used.

[0108] In this embodiment, oxygen is implanted into the oxide semiconductor film 403 by ion implantation. By the implantation process, the oxide semiconductor film 403 is stoichiometrically oriented when the oxide semiconductor is in a crystalline state. The oxide semiconductor film 403 includes a region where the oxygen content is excessive relative to the composition.

[0109] For example, the oxygen concentration in the oxide semiconductor film 403 introduced by the oxygen introduction step is set to 1 ×10 18 / cm 3 More than 3×10 21 / cm 3 It is preferable that the oxygen content is less than 100%. The region may be present in part of the oxide semiconductor film 403 (including the interface). By introducing an element, the oxide insulating film 436, the oxide semiconductor film 403, and the gate insulating film In the stack of the oxide insulating film 436 and the oxide semiconductor film 402, At least in the semiconductor film 403 or at the interface between the oxide semiconductor film 403 and the gate insulating film 402 Also contains oxygen.

[0110] The oxide semiconductor film 403 has a stoichiometric composition in which the oxide semiconductor is in a crystalline state. In this case, the oxygen content is insufficient to prevent the chemical reaction of the oxide semiconductor. The oxygen content is to be greater than the stoichiometric ratio, or to be greater than the amount of oxygen in the case of a single crystal. In some cases, oxygen may exist between the lattices of the oxide semiconductor. The conductor composition is InGaZn m O m+3x (x>1). For example, m=1 When the composition of the oxide semiconductor is InGaZnO 1+3x(x>1), resulting in excess oxygen If so, then 1+3x is a value greater than 4.

[0111] The supplied oxygen compensates for oxygen vacancies in the oxide semiconductor film 403. can.

[0112] In an oxide semiconductor, oxygen is one of the main components. The oxygen concentration in the conductive film was measured by SIMS (Secondary Ion Mass Spectroscopy) It is difficult to estimate the thickness of the oxide semiconductor precisely using methods such as rheometry. It can be said that it is difficult to determine whether or not oxygen has been intentionally added to the conductive film.

[0113] By the way, oxygen has 17 O and 18 There are isotopes such as O and their existence in nature The ratios of these atoms in the oxygen system are known to be approximately 0.037% and 0.204% of all oxygen atoms, respectively. In other words, the concentrations of these isotopes in the oxide semiconductor film can be measured by a method such as SIMS. Therefore, it is possible to estimate the oxide semiconductor concentration by measuring these concentrations. It may be possible to estimate the oxygen concentration in the conductive film more accurately. By measuring the concentration of oxygen, it may be possible to determine whether oxygen has been intentionally added to the oxide semiconductor film. stomach.

[0114] In the case of directly introducing oxygen into the oxide semiconductor film 403 as in this embodiment, The insulating films (oxide insulating film 436, gate insulating film 402, etc.) in contact with the base film 403 must be Although it is not necessary for the insulating film to contain a large amount of oxygen, The insulating film 436, the gate insulating film 402, etc. are made to be a film containing a large amount of oxygen, and oxygen is further directly A plurality of oxygen supply methods may be used for introducing oxygen into the oxide semiconductor film 403.

[0115] Next, the oxide semiconductor film 403 is formed into an island-shaped oxide semiconductor It is processed into a film 403 .

[0116] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not used. This reduces the manufacturing cost.

[0117] Note that the oxide semiconductor film 403 can be etched by either dry etching or wet etching. For example, the oxide semiconductor film 403 may be wet-etched using a The etching solution used may be a mixture of phosphoric acid, acetic acid, and nitric acid. ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Inductively Coupled Plasma Etching Method Dry etching may be used for etching. For example, the IGZO film is etched by ICP etching. Etching was performed by etching method (etching conditions: etching gas (BCl 3 :Cl 2 =6 0sccm:20sccm), power supply power 450W, bias power 100W, pressure 1.9P a) It can be processed into islands.

[0118] In addition, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300° C. or higher and 700° C. or lower. The temperature should be below ℃ or below the distortion point of the substrate. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment device, and an oxide semiconductor The film 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0119] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0120] For example, the substrate is placed in an inert gas heated to a high temperature of 650°C to 700°C as a heat treatment. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0121] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not included. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e. impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than ppm.

[0122] After the oxide semiconductor film 403 is heated by heat treatment, high-purity oxygen gas, high-purity 100°C nitrous oxide gas or ultra dry air (CRDS (Cavity Ring Down Laser Dispersion) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). (air having a concentration of 1 ppm or less, preferably 10 ppb or less) may be introduced. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, Preferably, the concentration is 0.1 ppm or less. The action of dehydration or dehydrogenation reduces the amount of impurities present in the process. By supplying oxygen, which is the main component of oxide semiconductors, The semiconductor film 403 can be highly purified and made to be of I-type (intrinsic).

[0123] Note that the timing of the heat treatment for dehydration or dehydrogenation is determined based on the time when the oxide semiconductor film is heated to 1000° C. The step may be performed after the island-shaped oxide semiconductor film 403 is formed or after the island-shaped oxide semiconductor film 403 is formed.

[0124] The heat treatment for dehydration or dehydrogenation may be carried out multiple times or may be carried out in combination with other heat treatments. You can sleep.

[0125] The heat treatment for dehydration or dehydrogenation is performed to form the oxide semiconductor film 403 into an island shape. When the oxide insulating film 436 is covered with the oxide semiconductor film 403, This prevents the oxygen contained in the insulating film 436 from being released by the heat treatment. preferable.

[0126] In addition, oxygen, which is a main component material of an oxide semiconductor, can be removed by the dehydration or dehydrogenation treatment. In the oxide semiconductor film, oxygen is released and the amount of the oxide semiconductor film is reduced. In the area where the oxygen is removed, oxygen vacancies exist, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. Therefore, donor levels are generated.

[0127] Therefore, when dehydration or dehydrogenation treatment is performed, oxygen is supplied to the oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film can be eliminated. can be compensated for.

[0128] Therefore, dehydration or dehydrogenation treatment is performed before the step of introducing oxygen into the oxide semiconductor film 403. It is preferable to keep

[0129] In addition, an oxide insulating film containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is used as the oxide semiconductor film 40. 3, oxygen can be supplied from the oxide insulating film to the oxide semiconductor film 403. In the above structure, a heat treatment is performed as the dehydration or dehydrogenation treatment. Heat treatment is performed while the oxide semiconductor film 403 and the oxide insulating film are at least partially in contact with each other. In this manner, oxygen may be supplied to the oxide semiconductor film.

[0130] Hydrogen or moisture is removed from the oxide semiconductor, and the semiconductor is highly purified to minimize the amount of impurities contained therein. By supplying oxygen to compensate for oxygen vacancies, an I-type (intrinsic) oxide semiconductor or an I-type By doing so, it is possible to obtain an oxide semiconductor that is as close to an intrinsic oxide semiconductor as possible. To bring the Fermi level (Ef) of a semiconductor to the same level as the intrinsic Fermi level (Ei) Therefore, by using the oxide semiconductor film in a transistor, the Reduces the variation in threshold voltage Vth of transistors and the threshold voltage shift ΔVth It is possible.

[0131] Next, a gate insulating film 442 covering the oxide semiconductor film 403 is formed.

[0132] In order to improve coverage of the gate insulating film 442, a film of The above-mentioned planarization process may be performed. In that case, it is preferable that the oxide semiconductor film 403 have a surface with good flatness.

[0133] The thickness of the gate insulating film 442 is set to 1 nm or more and 20 nm or less. Methods such as a CVD method, a pulsed laser deposition method, and an ALD method can be used as appropriate. The sputtering insulating film 442 is formed by forming a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. The film may be formed using a sputtering device that performs film formation in a set state.

[0134] The gate insulating film 442 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, A silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film The gate insulating film 442 can be formed using an oxide semiconductor film. In particular, the gate insulating film 442 preferably contains oxygen in the film (bulk). It is preferred that oxygen is present in an amount at least greater than the stoichiometric ratio in the gas (e.g., in the When a silicon oxide film is used as the gate insulating film 442, SiO2+α (However, α In this embodiment, the gate insulating film 442 is made of SiO 2+α (however, A silicon oxide film having a thickness of 0.01 to 0.01 mm is used as the gate insulating film 442. By using the oxide semiconductor film 403 as the second insulating film, oxygen can be supplied to the oxide semiconductor film 403, and the characteristics of the oxide semiconductor film 403 can be improved. Furthermore, the gate insulating film 442 can be formed according to the size and gate It is preferable that the insulating film 442 be formed in consideration of its step coverage.

[0135] The material of the gate insulating film 442 is hafnium oxide, yttrium oxide, hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and the use of high-k materials such as lanthanum oxide for the gate In addition, the gate insulating film 442 may have a single-layer structure or a stacked structure. It may also be a structure.

[0136] Next, a conductive film is formed over the gate insulating film 442, and the conductive film is etched to form a gate electrode layer. Form 401.

[0137] The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, aluminum, etc. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as their main components The gate electrode layer 401 can be formed using a gold material. Semiconductor films such as element-doped polycrystalline silicon films, nickel silicide, etc. The gate electrode layer 401 may have a single layer structure or a stacked layer structure. The structure may also be used.

[0138] The material of the gate electrode layer 401 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, oxide Conductive materials such as silicon doped indium tin oxide can also be used. A laminated structure of the conductive material and the metal material may also be used.

[0139] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 442 is made of a metal oxide film containing nitrogen. In-Ga-Zn-O films containing nitrogen, In-Sn-O films containing nitrogen, etc. film, In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn In-O film, nitrogen-containing In-O film, and metal nitride film (InN, SnN, etc.) can be used. These films have a valence of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the electrical characteristics of a transistor are This makes it possible to realize a so-called normally-off switching element. .

[0140] Next, a dopant 421 is introduced into the oxide semiconductor film 403 using the gate electrode layer 401 as a mask. Then, low resistance regions 404a and 404b are formed (see FIG. 2(A)).

[0141] The dopant 421 is an impurity that changes the electrical conductivity of the oxide semiconductor film 403. The 421st group of elements includes group 15 elements (typically phosphorus (P), arsenic (As), and antimony). Sb), Boron (B), Aluminum (Al), Nitrogen (N), Argon (Ar) , Helium (He), Neon (Ne), Indium (In), Fluorine (F), Chlorine (Cl ), titanium (Ti), and zinc (Zn) may be used. can.

[0142] The dopant 421 is implanted through other films (e.g., the gate insulating film 402) to The dopant 421 can also be introduced into the oxide semiconductor film 403. Ion implantation, ion doping, plasma immersion ion implantation In this case, the dopant 421 may be a single ion or a free ion. It is preferable to use fluoride and chloride ions.

[0143] The dopant 421 introduction process is performed by controlling the injection conditions such as the acceleration voltage and the dose amount, and the membrane through which the dopant 421 passes. In this embodiment, phosphorus is used as the dopant 421. The phosphorus ions are implanted by ion implantation using the dopant 421 at a dose of is 1×10 13 ions / cm 2 5×10 or more 16 ions / cm 2 The following would suffice.

[0144] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0145] The dopant 421 may be introduced while the substrate 400 is being heated.

[0146] Note that the treatment of introducing the dopant 421 into the oxide semiconductor film 403 may be performed multiple times. A plurality of dopants may be used.

[0147] After the dopant 421 is introduced, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out the heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be carried out.

[0148] In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The phosphorus (P) ion implantation conditions were an acceleration voltage of 30 kV and a dose of 1.0×1. 0 15 ions / cm 2 Let us assume that.

[0149] When the oxide semiconductor film 403 is a CAAC-OS film, the following can be achieved by introducing the dopant 421: In this case, a heat treatment is performed after the introduction of the dopant 421. As a result, the crystallinity of the oxide semiconductor film 403 can be restored.

[0150] Therefore, the oxide semiconductor layer 402 is formed by sandwiching the channel forming region 409 between the low resistance regions 404a and 404b. A nitride semiconductor film 403 is formed.

[0151] Next, an insulating film including an aluminum oxide film is formed to cover the gate electrode layer 401. The insulating film containing the aluminum film is etched to form an insulating film 414 containing an aluminum oxide film. Further, the gate electrode layer 401 and the insulating film 414 including the aluminum oxide film are masked. Then, the gate insulating film 442 is etched to form the gate insulating film 402 (FIG. 2(B) )reference).

[0152] The insulating film 414 containing the aluminum oxide film may be a single layer or a multilayer. Includes a minium membrane.

[0153] The insulating film 414 including the aluminum oxide film is formed by a plasma CVD method, a sputtering method, or The film can be formed by a deposition method or the like.

[0154] As the insulating film 414 containing an aluminum oxide film other than the aluminum oxide film, typically is a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film. In addition, inorganic insulating films such as hafnium oxide and magnesium oxide can be used. A film of titanium, zirconium oxide, lanthanum oxide, barium oxide, or a metal nitride film (e.g. For example, an aluminum nitride film can also be used.

[0155] In this embodiment, the insulating film 414 containing an aluminum oxide film is formed by a sputtering method. The aluminum oxide film is formed by sputtering the insulating film 414 including the aluminum oxide film. The deposition by the deposition method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare It can be carried out under a mixed atmosphere of gas and oxygen.

[0156] The insulating film 414 including the aluminum oxide film is formed by applying a method that prevents impurities such as water and hydrogen from being mixed in. It is preferable to form it appropriately.

[0157] In the same manner as in the formation of the oxide semiconductor film, the insulating film 414 including the aluminum oxide film was formed in the deposition chamber. To remove residual moisture, use an adsorption type vacuum pump (such as a cryopump). It is preferable to use an aluminum oxide film formed in a film forming chamber evacuated by a cryopump. The concentration of impurities in the insulating film 414 can be reduced. As an exhaust means for removing residual moisture in the deposition chamber of the insulating film 414, a turbo molecular pump was used. A cold trap may be added to the filter.

[0158] The insulating film 414 including the aluminum oxide film is formed using the following sputtering gas: It is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It is.

[0159] The insulating film 414 including an aluminum oxide film is provided over the oxide semiconductor film 403. The aluminum oxide film is permeable to both impurities such as hydrogen and moisture, and oxygen. It has a high blocking effect.

[0160] Therefore, the aluminum oxide film is free from hydrogen, which is a variable factor during and after the manufacturing process. Impurities such as moisture may be mixed into the oxide semiconductor film 403, and the main components of the oxide semiconductor may be The oxide semiconductor film 403 functions as a protective film for preventing oxygen, which is a material, from being released from the oxide semiconductor film 403. This allows the transistor 440a to have stable electrical characteristics.

[0161] An oxide semiconductor film 403, a gate insulating film 402, a gate electrode layer 401, and an aluminum oxide film. An interlayer insulating film 415 is formed on the insulating film 414 including the transistor. It is preferable that the thickness of the film is such that the unevenness caused by the resistor 440a can be flattened. A silicon oxynitride film is formed by the VD method.

[0162] The interlayer insulating film 415 is typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or a silicon nitride film. Aluminum oxide nitride film, silicon nitride film, aluminum nitride film, silicon oxide nitride film An inorganic insulating film such as an aluminum nitride oxide film or an inorganic insulating film can be used. The film 5 can be formed by using a plasma CVD method, a sputtering method or the like.

[0163] Furthermore, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistors. The planarizing insulating film is made of organic materials such as polyimide, acrylic, and benzocyclobutene resin. In addition to the above organic materials, low-dielectric constant materials (low-k materials) and the like can be used. In addition, by stacking multiple insulating films made of these materials, A planarizing insulating film may be formed.

[0164] The interlayer insulating film 415 is provided with the oxide semiconductor film 403 (low resistance regions 404a and 404b), the gate The insulating film 402 and the upper surface and side surface of the insulating film 414 including the aluminum oxide film are partially exposed. Openings 445a and 445b are formed (see FIG. 2(C)).

[0165] The openings 445a and 445b are formed by two etching processes using two masks. This is also fine.

[0166] When the openings 445a and 445b are formed, the insulating film 414 including the aluminum oxide film is etched. Since the opening 4 functions as a blocking stopper, the gate electrode layer 401 is not exposed. In the etching process for forming 45a and 45b, the interlayer insulating film 415 and the aluminum oxide The conditions for high selectivity with respect to the insulating film 414 including the silicon film (etching conditions, interlayer insulating film 415 and and the material of the insulating film 414 including an aluminum oxide film).

[0167] A source electrode layer 405a and a drain electrode layer 405b are formed in the openings 445a and 445b. The source electrode layer 405a and the drain electrode layer 405b are used to connect to other transistors. A variety of circuits can be constructed.

[0168] The source electrode layer 405a and the drain electrode layer 405b are formed of the same material as the gate electrode layer 401. For example, Al, Cr, Cu, Ta, Ti, Mo, W, etc. Metal films containing elements selected from the above, or metal nitride films containing the above elements (titanium nitride The following can be used: alumina film, molybdenum nitride film, tungsten nitride film, etc. A high melting point metal film such as Ti, Mo, W on either or both of the upper and lower sides of a metal film such as Cu or metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) The source electrode layer 405a and the drain electrode layer 405b may be stacked. The conductive film used in the step may be formed of a conductive metal oxide. Indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), acid Indium tin oxide (In 2 O 3 - SnO 2 ), indium zinc oxide (In 2 O 3 -ZnO) or these metal oxide materials containing silicon oxide can be used. can.

[0169] For example, the source electrode layer 405a and the drain electrode layer 405b may each be a single layer of a molybdenum film. A laminate of a tantalum nitride film and a copper film, or a laminate of a tantalum nitride film and a tungsten film, etc. is used. There can be.

[0170] Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 2D).

[0171] In addition, as in the case of a transistor 440b shown in FIG. The electrode layer 405b is polished by chemical mechanical polishing to expose the interlayer insulating film 415. In order to obtain a transistor, parts of the source electrode layer 405a and the drain electrode layer 405b may be removed. In the transistor 440b, the source electrode layer 405a and the drain electrode layer 405b are formed as an interlayer insulating film. 415 does not protrude from the surface, but is embedded in the structure. The wiring layers 435a and 435b can be provided in contact with the channel electrode layer 405b. The width of the wiring layer 435 is larger than that of the source electrode layer 405a and the drain electrode layer 405b in the direction Since the width between a and the wiring layer 435b can be increased, the processing is facilitated.

[0172] The wiring layer 435a and the wiring layer 435b are connected to the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b. The layer 405b can be formed using the same material and method as the layer 405b. For example, Al Cr, Cu, Ta, Ti, Mo, W, or the above-mentioned elements. Metal nitride films containing elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) In addition, a metal film such as Al or Cu may be used on either the upper or lower side or both sides. For example, high melting point metal films such as Ti, Mo, and W, or metal nitride films of these metals (titanium nitride film, nitrogen nitride film, etc.) The wiring layer 4 may be a laminate of a molybdenum nitride film, a tungsten nitride film, etc. The conductive film used for the wiring layer 435a and the wiring layer 435b may be formed of a conductive metal oxide. As a conductive metal oxide, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), Zinc oxide (ZnO), indium oxide, tin oxide (In 2 O 3 - SnO 2 ), indium oxide Zinc oxide (In 2 O 3 -ZnO) or these metal oxide materials containing silicon oxide The above-mentioned can be used.

[0173] The source electrode layer 405a and the drain electrode layer 405b can be removed by chemical mechanical polishing or other methods. Also, a cutting (grinding, polishing) method such as a chemical mechanical polishing method may be used. In addition to polishing, etching (dry etching, wet etching) and plasma treatment are also available. For example, after the removal process by chemical mechanical polishing, a dry etch process may be used. Chipping and plasma treatment (reverse sputtering, etc.) are performed to improve the flatness of the treated surface. Cutting (grinding, polishing) method may be combined with etching method, plasma treatment, etc. In this case, the order of steps is not particularly limited, and the materials for the source electrode layer 405a and the drain electrode layer 405b may be This may be appropriately set depending on the material, film thickness, and surface irregularities.

[0174] In addition, as in a transistor 440c shown in FIG. 4B, the interlayer insulating film 415 is not provided. It may also be of this structure.

[0175] The transistors 440a, 440b, and 440c of this embodiment include a source electrode layer 405a, The drain electrode layer 405b is formed on the exposed top surface of the oxide semiconductor film 403 and the aluminum oxide. The insulating film 414 is provided in contact with the upper surface and part of the side surface of the insulating film 414 including the silicon film.

[0176] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. Therefore, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate electrode layer 401. The insulating film 414 including the aluminum oxide film prevents the source electrode layer 405a from overlapping the surface of the insulating film 414. Alternatively, in order to prevent an electrical failure such as a short circuit between the drain electrode layer 405b and the gate electrode layer 401, Therefore, the transistors 440a, 440b, and 440b having a fine structure can be c can be produced with good yield.

[0177] Further, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 The distance between the contact region and the gate electrode layer 401 is determined by the aluminum oxide film. This is the width in the channel length direction of the insulating film 414 including This allows for more consistent control over the

[0178] For example, in a transistor 440d illustrated in FIG. Openings 445a and 445b are provided for the source electrode layer 405a and the drain electrode layer 405b to be formed. Even if the position of the source electrode layer 405a or the drain electrode layer 5b is slightly shifted during the manufacturing process, A region (contact region) where the gate electrode layer 405b and the oxide semiconductor film 403 are in contact with each other, The distance between the transistor and the electrode layer 401 can be the same. This can reduce defects and variations in the electrical characteristics of the resistor 440d.

[0179] In this manner, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 The distance between the gate electrode layer 401 and the contact region (contact region) can be shortened. Therefore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 can be The resistance between the contact region and the gate electrode layer 401 is reduced, and the transistor It is possible to improve the ON characteristics of the switches 440a, 440b, 440c, and 440d. .

[0180] As described above, in a semiconductor device, an on-state characteristic having a fine structure with little variation in characteristics can be obtained. The present invention provides highly reliable transistors 440a, 440b, 440c, and 440d with a high yield. It is possible.

[0181] Therefore, a semiconductor device that realizes miniaturization and has high electrical characteristics, and the semiconductor device It is possible to provide a method for making the device.

[0182] (Embodiment 2) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The parts and steps having the same or similar functions as those in the above embodiment are the same as those in the above embodiment. The embodiment can be carried out in the same manner as in the first embodiment, and the repeated explanation will be omitted. The details are omitted.

[0183] The transistors 430a and 430b shown in FIGS. 5A to 5C are top-gate transistors. FIG. 5A is a plan view of a transistor 430a. The cross section taken along the dashed line X2-Y2 in FIG. 5(B) corresponds to FIG. 5(A). In FIG. 5C, the interlayer insulating film 415 is omitted. FIG.

[0184] As shown in FIG. 5B and FIG. 5C, which are cross-sectional views in the channel length direction, the transistor 4 The semiconductor device including the transistor 430a and the transistor 430b is provided with an insulating film 436. On a substrate 400 having an edge surface, electrode layers 465a, 465b, 465b, and includes the channel forming region 409 and the low resistance regions 404a and 404b. A compound semiconductor film 403, a gate insulating film 402, a gate electrode layer 401, An insulating film 414 including an aluminum oxide film covering the top and side surfaces, an interlayer insulating film 415, a source The pixel includes an electrode layer 405a and a drain electrode layer 405b.

[0185] The transistors 430a and 430b in this embodiment each have a low resistance layer under the oxide semiconductor film 403. The source electrode layer 405a or the drain electrode layer 405b is in contact with the resistor regions 404a and 404b. In this example, electrode layers 465a and 465b are provided so as to overlap with each other.

[0186] The transistor 430a illustrated in FIGS. 5A and 5B includes an island-shaped electrode layer over an oxide insulating film 436. The electrode layers 465a and 465b are provided, and an oxide semiconductor is provided on the electrode layers 465a and 465b. The electrode layers 465a and 465b are formed on the oxide semiconductor film 403. The source electrode layer 405a or the drain electrode layer 405b is in contact with the resistor regions 404a and 404b. The transistor 430a includes a source electrode layer 405a and a drain electrode layer 5b. In this example, the source electrode layer 405a and the drain electrode layer 405b are polished. The height of the surface of the interlayer insulating film 415 (height from the surface of the substrate 400) is approximately the same as that of the surface of the interlayer insulating film 415.

[0187] The transistor 430b illustrated in FIG. 5C has a structure in which a metal oxide film is embedded in the oxide insulating film 436. Island-shaped electrode layers 465a and 465b are provided, and the electrode layers 465a and 465b are in contact with each other. The electrode layers 465a and 465b are formed of an oxide semiconductor film 403. The low resistance regions 404a and 404b of the semiconductor substrate 403 are in contact with the source electrode layer 405a and the drain electrode layer 405b. It overlaps with pole layer 405b.

[0188] Under the oxide semiconductor film 403, the source electrode layer 405a or the drain electrode layer 405b and the oxide Electrode layers 465a and 465b are provided in the contact region with the semiconductor film 403. As a result, the source electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor film 4 Since the contact resistance with the contact junction 03 can be reduced, the transistors 430a and 430b can be turned on. The characteristics can be improved.

[0189] The electrode layer 465a is used as a source terminal of the transistors 430a and 430b. The electrode layer 465b can also be used as the drain terminal of the transistors 430a and 430b. It can be used.

[0190] The electrode layers 465a and 465b may be made of molybdenum, titanium, tantalum, tungsten, or alumina. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or the above elements Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) Alternatively, the electrode layers 465a and 465b may be formed using an oxide semiconductor. The above-mentioned materials may be used in a single layer or a laminate.

[0191] Oxide semiconductors include In-Ga-Zn oxide (also written as IGZO), indium oxide Dium (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium oxide Tin(In 2 O 3 -SnO 2 ), indium zinc oxide (In 2 O 3 -ZnO) For the insulating layer 10, any of these oxide semiconductor materials containing silicon oxide can be used.

[0192] When an oxide semiconductor material is used for the electrode layers 465a and 465b, the oxide semiconductor When processing the film 403 into an island shape, the electrode layers 465a and 465b are etched as little as possible. As shown in FIG. 1, at least the electrode layers 465a and 465b exposed from the oxide insulating film 436 and the oxide It is necessary to use a material that has a selectivity for etching with the semiconductor film 403. Depending on the etching conditions, the electrode layers 465a and 465b may have a partially etched shape. In addition, the electrode layers 465a and 465b may be doped with a dopant (impurity element). It is also possible to use conductive materials and semiconductor materials that have been made to have low resistance by applying a heat treatment.

[0193] In addition, when an oxide semiconductor material is used for the electrode layers 465a and 465b, Depending on the material and film formation conditions, the interfaces between the electrode layers 465a and 465b and the oxide semiconductor film may be poor. In some cases, the interface may be unclear. In other cases, the interface may be unclear. A portion that can be called a mixed region or a mixed layer with the oxide semiconductor film may be formed. do.

[0194] At least a part of the electrode layers 465a and 465b corresponds to the source electrode layer 405a or the drain electrode layer 405b. It is sufficient that the insulating layer 405 is provided at a position overlapping the layer 405b, and the size and thickness of the insulating layer 405 are not particularly limited.

[0195] However, in the case of the transistor 430a, which is provided over the oxide insulating film 436, In consideration of the coverage of the thin oxide semiconductor film 403 to be formed, the electrode layers 465a and 465b It is preferable that the thickness of the film is not too large and that the end portion has a taper angle.

[0196] On the other hand, a transistor 430b is embedded in the oxide insulating film 436 and its surface is polished. In the case of polishing, the resistance becomes lower if the thickness of the electrode layers 465a and 465b is increased. Therefore, it is preferable.

[0197] The interlayer insulating film 415 is provided to flatten the irregularities caused by the transistors 430a and 430b. The insulating film 414 includes low resistance regions 404a and 404b, an aluminum oxide film, The gate insulating film 402 is exposed through an opening. The resistor regions 404a and 404b, the gate insulating film 402, and the insulating film including the aluminum oxide film The source electrode layer 405a and the drain electrode layer 405b are in contact with the upper surface and part of the side surface of the insulating film 414. 05b is provided.

[0198] In this embodiment, an aluminum oxide film is used as the insulating film 414 including an aluminum oxide film. Use.

[0199] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. Therefore, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate electrode layer 401. The insulating film 414 including the aluminum oxide film prevents the source electrode layer 405a from overlapping the surface of the insulating film 414. Alternatively, in order to prevent an electrical failure such as a short circuit between the drain electrode layer 405b and the gate electrode layer 401, Therefore, the yield of the transistors 430a and 430b having a fine structure can be increased. It can be produced more easily.

[0200] In addition, in the manufacturing process of the semiconductor device, the oxide semiconductor film 403 is supplying oxygen into the film by introducing oxygen radicals, oxygen atoms, or oxygen ions The oxygen introduction method includes ion implantation, ion doping, plasma immersion, etc. For example, ion implantation, plasma treatment, etc. can be used.

[0201] The oxide semiconductor film 403 provided in the transistors 430a and 430b is made of an oxide semiconductor. The film contains regions with an excess of oxygen compared to the stoichiometric composition in the crystalline state. In this case, the oxygen content is preferably set to a level exceeding the stoichiometric ratio of the oxide semiconductor. Alternatively, the oxygen content is set to a level that exceeds the amount of oxygen in the case of a single crystal. Oxide Oxygen may also exist between the lattices of semiconductors.

[0202] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. As a result, the channel formation region 4 of the oxide semiconductor film 403 overlapping with the gate electrode layer 401 is 09 and a part of the low resistance regions 404a and 404b are covered with an insulating film 41 containing an aluminum oxide film. The structure can be such that it is covered with 4.

[0203] Insulating films containing aluminum oxide are highly resistant to both impurities such as hydrogen and moisture, and oxygen. It has a high blocking effect that does not allow substances to pass through the membrane.

[0204] Therefore, the insulating film 414 including the aluminum oxide film is not changed during and after the manufacturing process. The intrusion of impurities such as hydrogen and moisture into the oxide semiconductor film, which are the causes of the breakdown of the oxide semiconductor, and the intrusion of impurities into the oxide semiconductor film, which are the causes of the breakdown of the oxide semiconductor, are considered. The oxide semiconductor film functions as a protective film to prevent oxygen, the main component of the oxide semiconductor film, from being released. Therefore, it is possible to provide the transistors 430a and 430b with stable electrical characteristics. Cut.

[0205] Note that the gate electrode layer 401 is used as a mask to form a dopant layer on the oxide semiconductor film 403 in a self-aligned manner. The oxide semiconductor film 403 is formed by introducing a channel-forming region 409 between the channel-forming region 409 and the oxide semiconductor film 403. The low resistance regions 404a and 404b are formed by doping the dopant. The dopant is an impurity that changes the electrical conductivity of the oxide semiconductor film 403. The methods of introducing ions include ion implantation, ion doping, and plasma immersion ion implantation. For example, a ion implantation method can be used.

[0206] The low resistance regions 404a and 404b are disposed on either side of the channel forming region 409 in the channel length direction. By including the oxide semiconductor film 403, the transistors 430a and 430b have improved on-state characteristics. The device has high properties (for example, on-state current and field-effect mobility) and enables high-speed operation and high-speed response.

[0207] In a semiconductor device, a transistor having a fine structure with little variation in characteristics and high on-characteristics is provided. This allows the transistors 430a and 430b to be provided with a high yield.

[0208] Therefore, a semiconductor device that realizes miniaturization and has high electrical characteristics, and the semiconductor device It is possible to provide a method for making the device.

[0209] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0210] (Embodiment 3) In this embodiment, the transistor shown in this specification is used, and even in a situation where power is not supplied, An example of a semiconductor device that can retain memory contents and has no limit to the number of times it can be written is shown in FIG. This will be explained using:

[0211] FIG. 6 shows an example of the configuration of a semiconductor device. FIG. 6(A) shows a cross-sectional view of the semiconductor device, and FIG. FIG. 6B is a plan view of the semiconductor device, and FIG. 6C is a circuit diagram of the semiconductor device. FIG. 6A corresponds to the cross sections taken along lines C1-C2 and D1-D2 in FIG. 6B.

[0212] The semiconductor device shown in FIG. 6(A) and FIG. 6(B) has a transistor using a first semiconductor material in the lower part. 160 and a transistor 162 made of a second semiconductor material on top. The transistor 162 may be the transistor described in Embodiment 1 or 2. In this embodiment, the transistor 162 in the first embodiment can be used. This is an example in which the structure of the transistor 440b is applied.

[0213] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this study can easily operate at high speed. The characteristics of the charge storage capacitor enable it to retain electric charge for a long period of time.

[0214] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. In order to hold the transistor, a transistor using an oxide semiconductor as described in Embodiment 1 is used. In addition to being used for resistor 162, materials used in semiconductor devices and the structure of semiconductor devices, etc. The specific configuration of the device is not necessarily limited to that shown here.

[0215] The transistor 160 in FIG. 6A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on a substrate 185, and a pair of electrodes are provided so as to sandwich the channel forming region 116. an impurity region 120 provided in the semiconductor substrate 10 and an intermetallic compound region 124 in contact with the impurity region 120; A gate insulating film 108 is provided on the channel forming region 116. and a gate electrode 110 provided on the source electrode 111. However, for convenience, the term "transistor" includes such a state. In this case, the source is sometimes called the transistor in order to explain the connection relationship. The source electrode and drain electrode may include the source region and drain region. In this specification, the term "source electrode" may include a source region.

[0216] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. An insulating layer 128 and an insulating layer 130 are provided to cover the transistor 160. In the transistor 160, a sidewall insulating layer (sidewall insulating layer) is formed on the side surface of the gate electrode 110. Alternatively, a thin insulating layer (wall insulating layer) may be provided to form impurity region 120 including regions with different impurity concentrations.

[0217] The transistor 160 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a read transistor, data can be read at high speed. Two insulating layers are formed to cover the transistor 160. As a process before forming the stator 162 and the capacitance element 164, the two insulating layers are subjected to CMP processing. Then, planarized insulating layers 128 and 130 are formed, and the upper surface of the gate electrode 110 is Expose.

[0218] The insulating layer 128 and the insulating layer 130 are typically made of a silicon oxide film, a silicon oxynitride film, or an oxide Aluminum film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, nitride An inorganic insulating film such as a silicon oxide film or an aluminum nitride oxide film can be used. The layer 128 and the insulating layer 130 are formed by using a plasma CVD method, a sputtering method, or the like. It is possible.

[0219] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric constant materials (low-k materials) can also be used. When using organic materials, the insulating layer can be formed by wet methods such as spin coating and printing. 128, and an insulating layer 130 may be formed.

[0220] In this embodiment, the insulating layer 128 is a silicon nitride film, and the insulating layer 130 is a silicon nitride film. A silicon oxide film is used.

[0221] A planarization treatment is performed on the surface of the insulating layer 130 in a region where the oxide semiconductor film 144 is to be formed. In this embodiment, the surface is sufficiently planarized by a polishing process (e.g., a CMP process). Preferably, the average surface roughness of the insulating layer 130 is 0.15 nm or less. A semiconductor film 144 is formed.

[0222] A transistor 162 illustrated in FIG. 6A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, the oxide semiconductor film 144 included in the transistor 162 is a high-purity By using a highly purified oxide semiconductor, In this way, the transistor 162 having excellent off-state characteristics can be obtained.

[0223] Since the off-state current of the transistor 162 is small, the use of the transistor 162 enables long-term recording. The contents of the memory can be retained, i.e., no refresh operation is required, or Therefore, it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0224] In this embodiment, the transistor 162 is provided over the interlayer insulating film 135 in the manufacturing process. The source electrode layer and the drain electrode are then removed by a process of removing the conductive film by chemical mechanical polishing. In this embodiment, the electrode layers 142a and 142b are formed to function as the conductive electrode layers. An electrode layer 142c electrically connected to the gate electrode 110 is formed in the same process as the layers 142a and 142b. Form.

[0225] In addition, a source wiring layer or In addition, wiring layers 138a and 138b that function as drain wiring layers are provided.

[0226] The transistor 162 is provided over the oxide semiconductor film 144 with a gate insulating film 146 interposed therebetween. The upper surface and side surfaces of the gate electrode 148 are covered with an insulating film 137 including an aluminum oxide film. Therefore, even if the electrode layers 142a and 142b overlap the upper surface of the gate electrode 148, the aluminum oxide The insulating film 137, which includes a tritium film, separates the electrode layers 142a and 142b and the gate electrode 148. This prevents electrical defects such as short circuits between the Transistors having a fine structure can be manufactured with high yield.

[0227] Therefore, the transistor 162 has an electrode layer functioning as a source electrode layer or a drain electrode layer. A region (contact region) where the oxide semiconductor film 144 contacts the gate electrodes 142a and 142b, Since the distance to the electrode 148 can be shortened, the electrode layers 142a and 142b and the oxide semiconductor The resistance between the gate electrode 148 and the contact region with the conductive film 144 is reduced. As a result, the on-characteristics of the transistor 162 can be improved.

[0228] In addition, oxygen is introduced into the oxide semiconductor film 144 during the manufacturing process. The upper surface and side surfaces of the gate electrode 148 are covered with an insulating film 1 containing an aluminum oxide film. 37, the channel of the oxide semiconductor film 144 overlapping with the gate electrode 148 is The formation region and a part of the low resistance region are covered with an insulating film 137 including an aluminum oxide film. It is possible.

[0229] In this embodiment, an aluminum oxide film is used as the insulating film 137 including an aluminum oxide film. The aluminum oxide film is made of high density (film density 3.2 g / cm 3 Above 3.6, preferably 3.6 g / cm 3 or more), the transistor 162 can have stable electrical characteristics. It is possible.

[0230] An insulating film 150 is provided over the transistor 162 as a single layer or a multilayer. In this embodiment, an aluminum oxide film is used as the insulating film 150.

[0231] In addition, the electrode layer 142 of the transistor 162 is connected via the interlayer insulating film 135 and the insulating film 150. A conductive layer 153 is provided in the region overlapping with the electrode layer 142c and the wiring layer 13a. 8a, the interlayer insulating film 135, the insulating film 150, and the conductive layer 153 form a capacitance element 16 That is, the electrode layer 142a of the transistor 162 is The conductive layer 153 functions as one electrode of the capacitor 164. If no capacitance is required, the capacitor 164 may be omitted. In addition, the capacitor 164 may be provided above the transistor 162 separately.

[0232] An insulating film 152 is provided over the transistor 162 and the capacitor 164. On the insulating film 152, a transistor 162 and wiring for connecting other transistors are provided. Although not shown in FIG. 6A, the wiring 156 is provided on the insulating film 150. The wiring layer 138b and the electrode layer 138a are connected to each other through an electrode formed in an opening in the insulating film 152 or the like. 142b, where the electrode is electrically connected to at least the oxide of the transistor 162. It is preferable that the insulating film 144 be provided so as to overlap with a part of the nitride semiconductor film 144 .

[0233] In FIG. 6A and FIG. 6B, the transistor 160 and the transistor 162 are The source region of the transistor 160 is provided so as to overlap at least a portion of the It is preferable that the drain region is provided so as to partially overlap the oxide semiconductor film 144. In addition, the transistor 162 and the capacitor 164 are at least For example, the conductive layer 153 of the capacitor 164 is At least a part of the gate electrode 110 of the transistor 160 is overlapped therewith. By adopting such a planar layout, it is possible to reduce the area occupied by the semiconductor device. This allows for high integration.

[0234] The electrical connection between the wiring layer 138b and the wiring 156 is This may be done by direct contact, or by providing an electrode on the insulating film between the wiring layer 138b and the wiring 156. The electrode may be disposed between the electrodes.

[0235] Next, an example of a circuit configuration corresponding to FIG. 6(A) and FIG. 6(B) is shown in FIG. 6(C).

[0236] In FIG. 6C, the first wiring (1st Line) and the source voltage of the transistor 160 The electrodes are electrically connected to the second wiring (2nd Line) and the drain of the transistor 160. The third line and the drain electrode are electrically connected. The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode. The wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected. The gate electrode of the transistor 160 and the source voltage of the transistor 162 are The other of the electrode and drain electrode is electrically connected to one of the electrodes of the capacitor 164. The wiring (5th Line) and the other electrode of the capacitor element 164 are electrically connected. .

[0237] In the semiconductor device shown in FIG. 6C, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, retain, and read information as follows.

[0238] The writing and holding of data will be described. First, the potential of the fourth wiring is set to The transistor 162 is turned on by applying a potential to the transistor 162. The potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (write Here, the charges that give two different potential levels (hereafter, low-level charges, H Then, the voltage of the fourth wire is The transistor 162 is turned off by setting the potential at which the transistor 162 is turned off. By this, the charge applied to the gate electrode of the transistor 160 is held (retained). Hold).

[0239] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long period of time.

[0240] Next, the reading of information will be explained. A state in which a predetermined potential (constant potential) is applied to the first wiring When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the electrode, the second wire takes on a different potential. If the transistor 160 is an n-channel type, a high level voltage is applied to the gate electrode of the transistor 160. Apparent threshold V when a load is applied th_H is the gate of transistor 160 Apparent threshold voltage V when a low-level charge is applied to the electrode th_L Lower Here, the apparent threshold voltage is the voltage at which transistor 160 is turned on. This refers to the potential of the fifth wiring required to achieve this. Therefore, the potential of the fifth wiring V th_H and V th_L The potential V between 0 By doing so, the gate of the transistor 160 For example, in writing, a high level charge is given, the potential of the fifth wire is V 0 (>V th_H ) Then, Tran When a low level charge is applied, the fifth resistor 160 is in the "ON state." The potential of the wiring is V 0 ( <V th_L ) transistor 160 is in the "off state" Therefore, the stored data can be read by checking the potential of the second wiring. It is possible.

[0241] When memory cells are arranged in an array, only the information in a desired memory cell can be read. If the information is not read out, the state of the gate electrode is Regardless of the potential at which transistor 160 is in the “off state,” i.e., V th_H Yo Alternatively, the transistor may be turned on regardless of the state of the gate electrode. The potential at which the transistor 160 is in the "on state," that is, V th_L A larger potential Just give it to the fifth wire.

[0242] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0243] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and is reliable. Furthermore, the on and off states of transistors allow the Since writing is performed, high speed operation can be easily achieved.

[0244] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0245] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0246] (Embodiment 4) In this embodiment, the transistors described in any of the embodiments 1 to 3 are used. A semiconductor device that can retain memory contents even when the data is not written to it and that has no limit on the number of times it can be written to. The configuration of the device that differs from that shown in the third embodiment will be described with reference to FIGS. 7 and 8. Make a statement.

[0247] FIG. 7(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 7(B) shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 7(A) will be described, followed by the semiconductor device shown in FIG. The semiconductor device shown in FIG.

[0248] In the semiconductor device shown in FIG. 7A, the bit line BL and the source electrode of the transistor 162 The word line WL and the gate electrode of the transistor 162 are electrically connected. The electrode is electrically connected to the source electrode or drain electrode of the transistor 162 and the capacitor element The first terminal of 254 is electrically connected to the first terminal of 254 .

[0249] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. The case where the above is performed will be explained.

[0250] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. This causes the potential of the bit line BL to change to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal of the transistor 1 By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the quantum element 254 is held (held).

[0251] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long period of time. It is possible to retain it.

[0252] Next, the reading of information will be described. When the transistor 162 is turned on, The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in the potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0253] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB*VB0+C*V) / (CB+C). Therefore, the state of memory cell 250 is In this case, the potential of the first terminal of the capacitance element 254 is assumed to be in two states, V1 and V0 (V1>V0). Then, the potential of the bit line BL when the potential V1 is held is (=(CB*VB0+C*V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB* VB0+C*V0) / (CB+C)).

[0254] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0255] As described above, in the semiconductor device illustrated in FIG. 7A, the off-state current of the transistor 162 is extremely small. Due to its small size, the charge stored in the capacitance element 254 can be held for a long time. In other words, refresh operations are not required or the frequency of refresh operations can be reduced. Since it is possible to extremely reduce the power consumption, Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0256] Next, the semiconductor device shown in FIG.

[0257] The semiconductor device shown in FIG. 7B has the memory cell 2 shown in FIG. 7A as a memory circuit in the upper portion. 50, and the memory cell arrays 251a and 251b are provided at the bottom. The peripheral circuits required to operate the array 251 (memory cell arrays 251a and 251b) The peripheral circuit 253 is electrically connected to the memory cell array 251. It is being done.

[0258] By configuring as shown in FIG. 7B, the peripheral circuit 253 is connected to the memory cell array 251 ( Since the memory cell arrays 251a and 251b can be provided directly under the It is possible to achieve miniaturization.

[0259] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, etc. Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can be used. In addition, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, driver circuits, etc.) that require operation in an optimal manner. do.

[0260] In the semiconductor device shown in FIG. 7B, two memory cell arrays 251 (memory cell In the above embodiment, the memory cell array 251a and the memory cell array 251b are stacked. The number of memory cells is not limited to this. A configuration in which three or more memory cells are stacked may also be used. good.

[0261] Next, a specific configuration of the memory cell 250 shown in FIG. 7A will be described with reference to FIG. conduct.

[0262] 8 shows an example of the configuration of a memory cell 250. FIG. 8A shows a cross section of the memory cell 250. 8(A) shows a schematic diagram of the memory cell 250, and FIG. 8(B) shows a plan view of the memory cell 250. These correspond to cross sections taken along lines F1-F2 and G1-G2 in FIG. 8(B).

[0263] The transistor 162 illustrated in FIGS. 8A and 8B is the same as that described in any one of Embodiments 1 to 3. The configuration may be the same as that shown in FIG.

[0264] The insulating film 256 is a single layer or a stacked layer over the transistor 162 provided over the insulating layer 180. The electrode layer 142a of the transistor 162 is provided with the insulating film 256 interposed therebetween. A conductive layer 262 is provided in a region overlapping with the wiring layer 138a that is electrically connected to the , a wiring layer 138a electrically connected to the electrode layer 142a, an interlayer insulating film 135, and an insulating film 2 The transistor 56 and the conductive layer 262 constitute a capacitance element 254. The electrode layer 142a of the capacitor 162 functions as one electrode of the capacitor 254, and the conductive layer 262 serves as the other electrode of the capacitor 254.

[0265] An insulating film 258 is provided over the transistor 162 and the capacitor 254. On the insulating film 258, a memory cell 250 and an adjacent memory cell 250 are connected to each other. Although not shown, the wiring 260 is formed by insulating film 256 and insulating film 258, etc., is electrically connected to the electrode layer 142a of the transistor 162 through an opening formed in the However, if another conductive layer is provided in the opening, the other The wiring 260 and the wiring layer 138a electrically connected to the electrode layer 142a are connected to each other through the conductive layer. The wiring 260 may be electrically connected to the bit line B in the circuit diagram of FIG. Equivalent to L.

[0266] In FIG. 8A and FIG. 8B, the electrode layer 142b of the transistor 162 is It can also function as a source electrode of a transistor included in the memory cell.

[0267] By adopting the planar layout shown in FIG. 8(A), the area occupied by the semiconductor device can be reduced. This allows for high integration.

[0268] As described above, the memory cells formed in multiple layers on the upper portion are transistors using oxide semiconductors. A transistor using an oxide semiconductor has a low off-state current. Therefore, by using this, it is possible to retain memory contents for a long period of time. This allows the frequency of refresh operations to be reduced significantly, resulting in significant power consumption savings. can be reduced to

[0269] In this way, transistors using materials other than oxide semiconductors (in other words, transistors that operate at sufficiently high speed) The peripheral circuits are made of transistors that can be operated with a semiconductor oxide. In a broader sense, the off-state current of the transistor is sufficiently small. This makes it possible to realize a semiconductor device having unprecedented features. By forming the gate and the memory circuit in a stacked structure, the integration of the semiconductor device can be promoted.

[0270] As described above, a semiconductor device that realizes miniaturization and high integration and is endowed with high electrical characteristics is provided. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0271] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0272] (Embodiment 5) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, An example of application to a portable device such as a child book will be described with reference to FIGS.

[0273] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following. SRAM or DRAM is used The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: do.

[0274] In a normal SRAM, as shown in FIG. 9A, one memory cell is made up of transistors 801 to 808. It is composed of six transistors, X decoder 807 and Y decoder 807. The transistor 803, the transistor 805, and the transistor 808 are driven by the 4 and transistor 806 form an inverter, enabling high-speed operation. The memory cell is composed of six transistors, so the cell area is large. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. stomach.

[0275] On the other hand, in a DRAM, the memory cell is made up of a transistor 811, a storage The signal is driven by an X decoder 813 and a Y decoder 814. Each cell is composed of one transistor and one capacitance, and has a small area. The memory cell area of ​​a RAM is usually 10F 2 However, DRAM is always refreshed. It requires a write operation and consumes power even if the data is not being rewritten.

[0276] However, the memory cell area of ​​the semiconductor device described in the above embodiment is 10F 2 Before and after and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0277] FIG. 10 shows a block diagram of a portable device. The portable device shown in FIG. A digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply Circuit 905, application processor 906, flash memory 910, display A controller 911, a memory circuit 912, a display 913, a touch sensor 919, The display 913 is a display. The image display device is configured with an application section 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface 909. In general, the memory circuit 912 is composed of an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment in this portion, It is possible to write and read information at high speed, retain data for a long period of time, and consume little power. The time required for the measurement can be reduced to minutes.

[0278] FIG. 11 shows a display memory circuit 950 using the semiconductor device described in the previous embodiment. The memory circuit 950 shown in FIG. The memory controller 951 is configured with a switch 954, a switch 955, and a memory controller 951. The memory circuit receives image data (input image data) from a signal line, and stores the image data in the memory 952. , and reads out data (stored image data) stored in the memory 953 and performs control. A display controller 956 and a signal from the display controller 956 A display 957 is connected to display the information.

[0279] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then The image is sent to a display 957 via a switch 955 and a display controller 956. , will be displayed.

[0280] When there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. The display controller 956 reads the data from the memory 952 via the switch 955. It is revealed.

[0281] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This readout is followed by the next new image data being stored in the memory. This continues until the data is stored in the memory 952.

[0282] In this way, the memory 952 and the memory 953 alternately write image data and receive image data. The display 957 is displayed by reading out the data from the memory 9 The memory 52 and the memory 953 are not limited to being separate memories, but may be one memory divided and used. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, it is possible to write and read information at high speed and retain data for a long period of time. This makes it possible to sufficiently reduce power consumption.

[0283] FIG. 12 shows a block diagram of an electronic book. , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard A code 1006, a memory circuit 1007, a touch panel 1008, a display 1009, The display controller 1010 is configured as a display controller.

[0284] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 is to temporarily store the contents of the book. An example of a feature is when a user uses the highlight feature. When reading an e-book, you may want to mark a specific part. The highlighting function is called the highlight function, and it can be used to change the display color, underline, make text bold, etc. The aim is to differentiate the device from its surroundings by making it brighter or changing the font of the text. This is a function that memorizes and retains information at specified locations. If you want to store this information for a long period of time, It may be copied to the flash memory 1004. In this case, the same as in the previous embodiment is also possible. By adopting the semiconductor device described in the above embodiment, writing and reading of information can be improved. It is possible to store data quickly and for a long period of time, and the power consumption can be sufficiently reduced.

[0285] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. Thus, a portable device with reduced noise is realized.

[0286] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

Claims

1. a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other, a first insulating layer having a region located on a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a third insulating layer having a region located above the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer, the oxide semiconductor layer including a channel formation region of the second transistor and a pair of impurity regions sandwiching the channel formation region; a second conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region overlying the second conductive layer; a third conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to one of the first conductive layer and the impurity region; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to the other of the impurity regions; a fifth insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; a fifth conductive layer having a region located above the fifth insulating layer; a sixth conductive layer having a region overlapping with the first conductive layer and a region overlapping with the third conductive layer and having a function as the other electrode of the capacitor; the fifth conductive layer overlaps with the first channel formation region and overlaps with the second channel formation region; a potential of the fifth conductive layer is supplied to a gate electrode of the first transistor through at least the other of the impurity regions, the second channel formation region, and the one of the impurity regions in this order; In a plan view, the second conductive layer has a region extending in a first direction, In a plan view, the sixth conductive layer has a region extending in the first direction.

2. a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other, a first insulating layer having a region located on a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a third insulating layer having a region located above the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer, the oxide semiconductor layer including a channel formation region of the second transistor and a pair of impurity regions sandwiching the channel formation region; a second conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region overlying the second conductive layer; a third conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to one of the first conductive layer and the impurity region; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to the other of the impurity regions; a fifth insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; a fifth conductive layer having a region located above the fifth insulating layer; a sixth conductive layer having a region overlapping with the first conductive layer and a region overlapping with the third conductive layer and having a function as the other electrode of the capacitor; the fifth conductive layer overlaps with the first channel formation region and overlaps with the second channel formation region; a potential of the fifth conductive layer is supplied to a gate electrode of the first transistor through at least the other of the impurity regions, the second channel formation region, and the one of the impurity regions in this order; In a plan view, the second conductive layer has a region extending in a first direction, the sixth conductive layer has a region extending in the first direction in a plan view, the second insulating layer comprises silicon nitride; The third insulating layer comprises silicon oxide.

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