Manufacturing method for semiconductor device

Abstract

To provide a semiconductor device with large on current and excellent reliability.SOLUTION: In a transistor 200, a fifth insulator 280 includes an opening for exposing a second oxide 230b; a third oxide 230c is disposed in contact with a bottom part of the opening and a side part of the opening; a second insulator 250 is disposed in contact with the third oxide; a third conductor 265 is disposed in contact with the second insulator; a third insulator 275 is disposed in contact with an upper surface of the third conductor and with the second insulator; a fourth conductor 260 is disposed in contact with the upper surface of the third conductor and the third insulator, and inside the opening through the third oxide, the second insulator, and the third insulator; a fourth insulator 272 is in contact with an upper surface of the first insulator 273, a side surface of a first oxide 230a, a side surface of the second oxide, a side surface and an upper surface of a first conductor 242a, and a side surface and an upper surface of a second conductor 242b; and the third insulator transmits one of or both oxygen and hydrogen less easily than the second insulator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect of the invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and There are cases where the child devices and the like can be said to have semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. An aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the issue of the [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin-film materials that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, oxides of single-component metals such as indium oxide and zinc oxide, as well as oxides of multi-component metals Among the oxides of multi-component metals, In-Ga-Zn oxide is particularly well known. (hereinafter referred to as IGZO) is currently being actively researched.

[0005] Transistors using IGZO as the active layer have extremely low leakage current when in a non-conducting state. For example, the ripple current of a transistor using IGZO as the active layer is small. A low-power CPU that utilizes the low-leakage current characteristic has been disclosed (Patent Document (See reference 1).

[0006] In addition, the crystal structure has a CAAC (c-axis aligned crystalline) structure. A technique for fabricating miniaturized transistors using oxide semiconductors has also been disclosed (Non-Patent (See Reference 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2012-257187 A [Non-patent literature]

[0008] [Non-Patent Document 1] D. Matsubayashi et al., “2015 IEEE International Electron Devices Meeting(IEDM) Technical Digests”, 2015, pp.6.5.1-6.5.4 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high heat resistance. An object of one embodiment of the present invention is to provide a semiconductor device with high thermal stability. Another object of one embodiment of the present invention is to provide a semiconductor device having a large on-state current. Another embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of the present invention is to provide a semiconductor device having excellent electrical characteristics. Another object of the present invention is to provide a semiconductor device having the above-mentioned. Another object of the present invention is to provide a semiconductor device that is easy to manufacture. It is an object of the present invention to provide a semiconductor device having high processing stability. Another object of the present invention is to provide a semiconductor device having uniform quality. Another object of the present invention is to provide a semiconductor device with high yield. It is another object of the present invention to provide a semiconductor device with high productivity.

[0010] One embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. One object of one embodiment of the present invention is to provide a semiconductor device in which data can be written at a high speed. One object of one embodiment of the present invention is to provide a semiconductor device having high design freedom. One object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. One object of the present invention is to provide a novel semiconductor device. is one of the challenges.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device comprising a first insulator, a first oxide on the first insulator, and a first oxide. a second oxide on the first oxide, a first conductor and a second conductor on the second oxide, and a third oxide on the substrate, a second insulator on the third oxide, and a third conductive layer on the second insulator. a third insulator, a fourth conductor on the third conductor, and a third insulator, a first insulator on the first insulator, a fourth insulator on the conductor and on the second conductor, and a fifth insulator on the fourth insulator; the fifth insulator has an opening exposing the second oxide, and the third oxide is a second insulator disposed adjacent the bottom and sides of the opening; and a third oxide disposed adjacent the third insulator. and a third conductor is disposed in contact with the second insulator, and the third insulator is disposed between the third conductor and the second insulator. a fourth conductor is disposed in contact with the upper surface of the first insulator and in contact with the second insulator, and a third oxide, a second insulator, and a third insulator in contact with the upper surface of the third conductor. A fourth insulator is disposed in the opening through the first oxide layer. surface, a side surface of the second oxide, a side surface of the first conductor, an upper surface of the first conductor, and a side of the second conductor. The third insulator is in contact with the upper surface of the second conductor and has a higher oxygen and hydrogen content than the second insulator. It is a semiconductor device that is difficult to transmit one or both of the light.

[0013] The third insulator preferably contains aluminum and oxygen.

[0014] The third insulator may also include silicon and nitrogen.

[0015] The first to third oxides each contain In and an element M (M is Al, Ga, Y, or S). n) and Zn.

[0016] In one embodiment of the present invention, a first insulator is formed on a substrate, and a first The oxide film and the first conductive film are formed in this order, and the first oxide film and the first conductive film are processed. A first oxide and a first conductive layer are formed by the above-mentioned method. A first insulating film and a second insulating film are sequentially formed to cover the substrate layer, and a planarization process is performed to form the first insulating film and the second insulating film. The surface of the second insulating film is planarized, and a first conductive layer, a first insulating film, and a second insulating film are formed on the first conductive layer, the first insulating film, and the second insulating film. By forming an opening through which the oxide of the first oxide is exposed, the first conductor, the second conductor, and the second insulating layer are A body is formed, a second oxide film and a third insulating film are formed, and a second conductive film is formed so that the thickness of the second conductive film at the bottom of the opening is The film is formed so that it is thicker than the film thickness on the sides of the opening, and the second conductive film located at the bottom of the opening remains. the second conductive film located on the side of the opening is etched so as to form a third insulating film; The third insulating film is anisotropically etched, a third conductive film is formed, and a planarization process is performed. The second oxide film, the third insulating film, the second conductive film, and the third conductive film are then formed as a second insulating film. The second oxide, the third insulator, the third conductor, and the and a fourth conductor are formed.

[0017] The second conductive film is formed by sputtering tantalum nitride and nitride It is preferred that either titanium or both be formed.

[0018] The second conductive film is formed by sputtering titanium and aluminum. Metal nitrides including may be formed.

[0019] In addition, a metal oxide containing aluminum is formed as the third insulating film by the ALD method. It is preferable that the above-mentioned method be performed.

[0020] In addition, the third insulating film is an insulating film containing silicon and nitrogen by the ALD method. It may be formed. Effect of the Invention

[0021] According to one embodiment of the present invention, a semiconductor device having high heat resistance can be provided. According to one embodiment of the present invention, a semiconductor device having high thermal stability can be provided. According to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device having favorable electrical characteristics is provided. According to one embodiment of the present invention, a semiconductor device that can be easily manufactured can be provided. According to one embodiment of the present invention, a semiconductor device with high processing stability can be provided. According to one embodiment of the present invention, a homogeneous semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high yield can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0022] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with a high data writing speed can be provided. It is possible to provide a semiconductor device having a high degree of freedom. It is possible to provide a semiconductor device. Alternatively, it is possible to provide a novel semiconductor device. .

[0023] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0024] [Figure 1] 1A is a top view illustrating the configuration of a semiconductor device, and FIGS. [Diagram 2] 1A is a top view illustrating the configuration of a semiconductor device, and FIGS. [Diagram 3] 1A is a top view illustrating the configuration of a semiconductor device, and FIGS. [Figure 4] 1A is a top view illustrating the configuration of a semiconductor device, and FIGS. [Diagram 5] 1A and 1B are cross-sectional views showing the configuration of a semiconductor device. [Figure 6] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 7] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 8]1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 9] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 10] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 11] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 12] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 13] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 14] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 15] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 16] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 17] 1A is a top view illustrating a method for manufacturing a semiconductor device, and FIGS. [Figure 18] 1A to 1C are diagrams illustrating an energy band structure of an oxide semiconductor; [Figure 19] 1A is a top view illustrating the configuration of a semiconductor device, and FIGS. [Figure 20] 1A is a top view illustrating the configuration of a semiconductor device, and FIGS. [Figure 21] FIG. 1 is a cross-sectional view showing a configuration of a storage device. [Figure 22] FIG. 1 is a cross-sectional view showing a configuration of a storage device. [Figure 23] 1A is a block diagram showing an example of the configuration of a storage device, and FIG. [Figure 24] 1A to 1H are circuit diagrams showing configuration examples of a memory device. [Diagram 25] 1A is a block diagram showing the configuration of a semiconductor device, and FIG. [Figure 26] (A) to (E) are schematic diagrams of a memory device. [Figure 27] 1A to 1F are diagrams showing electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. It is understood that the present invention can be practiced in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiment modes.

[0026] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in schematic form, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this is not reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In such cases, the hatch patterns may be the same and no particular reference numbers may be used.

[0027] In addition, in particular in top views (also called "plan views") and perspective views, etc., the invention is easily understood. In order to simplify the illustration, some of the components may be omitted. may be omitted.

[0028] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second "the" or "third" can be used as appropriate. The ordinal numbers described herein may not coincide with the ordinal numbers used to identify an aspect of the present invention. There are cases where this is the case.

[0029] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship is used for convenience in describing the drawings. The relationship changes accordingly depending on the direction in which each configuration is depicted. The terms are not limited to those described above, and may be rephrased appropriately depending on the situation.

[0030] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification, etc. Therefore, the connection relationship is limited to a specific one, for example, the connection relationship shown in the figure or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. It shall be so.

[0031] Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0032] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0033] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in the top view of the For example, if the gate electrode covers the side of the semiconductor, the effective channel The width of the channel may become larger than the apparent channel width, and the effect of this may become unignorable. For example, in a fine transistor in which the gate electrode covers the side of the semiconductor, In this case, the ratio of the channel formation region formed in the The effective channel width is larger than the channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0035] In this specification, when the term "channel width" is used, it refers to the apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel The channel length, channel width, effective channel width, apparent channel width, etc. The channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. can.

[0036] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor characteristics may be deteriorated. The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, for example: Hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Oxides In the case of a semiconductor, water may also function as an impurity. If impurities are mixed in, oxygen deficiency (V O :oxygen vacancy) is the form In addition, if the semiconductor is silicon, there may be a defect that changes the properties of the semiconductor. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0037] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains more oxygen than silicon. It has a high nitrogen content.

[0038] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0039] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes the case where the angle is between -5 degrees and 5 degrees. "Almost parallel" means that the two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. " refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0040] In this specification, the term "barrier film" refers to a film that prevents impurities such as water and hydrogen from passing through, and oxygen. If the barrier film is conductive, it is called a conductive barrier. It is sometimes called the a membrane.

[0041] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the semiconductor layer of a transistor, the Metal oxides are sometimes called oxide semiconductors. In the case of a transistor, a transistor having an oxide or an oxide semiconductor is used. In other words:

[0042] In this specification and the like, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate At room temperature, -20 A or less, 1×10 at 85℃ -18 A or below, or 1×10 at 125℃ -16 This means that it is A or lower.

[0043] (Embodiment 1) An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below. He explains.

[0044] <Configuration Example 1 of Semiconductor Device> 1A, 1B, and 1C show a transistor 2 according to one embodiment of the present invention. 00, and a top view and a cross-sectional view of the area around transistor 200.

[0045] FIG. 1A is a top view of a semiconductor device including a transistor 200. FIG. 1B) and FIG. 1C are cross-sectional views of the semiconductor device. FIG. 1(A) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. FIG. 1(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. 1(A). 1 is a cross-sectional view of the portion indicated by the arrow A in FIG. In the top view of FIG. 1(A), some elements are omitted for clarity.

[0046] The semiconductor device according to one embodiment of the present invention includes an insulator 214 on a substrate (not shown), A transistor 200 on the top, an insulator 280 on the transistor 200, and a an insulator 282, an insulator 274 on the insulator 282, and an insulator 281 on the insulator 274; The insulator 214, the insulator 280, the insulator 282, the insulator 274, and the insulator 2 81 functions as an interlayer film. Also, it is electrically connected to the transistor 200 and serves as a plug. The conductor 240 (conductor 240a and conductor 240b) functions as a The insulator 241 (insulator 241a, In addition, on the insulator 281 and the conductor 240, Conductor 246 (conductor 246a, and conductor 246b).

[0047] In addition, the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 274, and An insulator 241a is provided in contact with the side of the opening of the insulator 281, and a conductor is provided in contact with the side of the insulator 241a. A first conductor of the conductor 240a is provided, and a second conductor of the conductor 240a is provided on the inner side. In addition, an insulator 272, an insulator 273, an insulator 280, an insulator 282, an insulator An insulator 241b is provided in contact with the edge 274 and the side of the opening of the insulator 281. A first conductor of the conductor 240b is provided in contact with the side surface, and a second conductor of the conductor 240b is provided on the inner side. A second conductor is provided. Here, the height of the upper surface of the conductor 240 and the height of the insulator 281 are The height of the upper surface can be made to be approximately the same. Although the present invention shows a configuration in which the first conductor and the second conductor of conductor 240 are stacked, However, the present invention is not limited to this. For example, the conductor 240 may be a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, ordinal numbers are assigned to the layers in the order of formation. , a distinction may be made.

[0048] [Transistor 200] As shown in FIG. 1B, the transistor 200 includes an insulator 216 on an insulator 214, The conductors 205 (conductors 205a and 205b) are disposed so as to be embedded in the insulator 216. conductor 205b), insulator 222 on insulator 216 and on conductor 205, and insulator 2 22, an insulator 224, an oxide 230a on the insulator 224, and an oxide 230a on the oxide 230a. The oxide 230b and the conductor 242 (conductor 242a and conductor 242b) on the oxide 230b. b), an oxide 230c on the oxide 230b, an insulator 250 on the oxide 230c, Conductor 265 on edge 250 and conductor 260 on conductor 265 (conductor 260a, and conductor 260b), and insulator 275, and on insulator 224, on conductor 242a, and and an insulator 272 on the conductor 242b, and an insulator 273 on the insulator 272.

[0049] As shown in FIG. 1B, an insulator 280 on the insulator 273 exposes the oxide 230b. The oxide 230c is disposed adjacent to the bottom and sides of the opening, and the insulating layer 230c is disposed adjacent to the bottom and sides of the opening. The conductor 265 is disposed in contact with the oxide 230c. The insulator 275 is in contact with the upper surface of the conductor 265 and is in contact with the insulator 250. The conductor 260 is disposed in contact with the upper surface of the insulator 275 and the conductor 265. , and disposed in the opening via oxide 230c, insulator 250, and insulator 275. can be.

[0050] The insulator 272 is formed on the upper surface of the insulator 224, the side surface of the oxide 230a, and the oxide 230b. the side of the conductor 242a, the top surface of the conductor 242a, the side of the conductor 242b, The conductor 260 is in contact with the upper surface of the conductor 260a and the upper surface of the conductor 260b. The conductor 260a is disposed so as to surround the bottom and side surfaces of the conductor 260b. The top surface of the conductor 260 is connected to the top surface of the insulator 275, the top surface of the insulator 250, and the oxide 23. The upper surface of the insulating body 282 is disposed so as to be substantially aligned with the upper surface of the insulating body 280. , conductor 260, insulator 275, insulator 250, oxide 230c, and insulator 280. contact with the top surface of each.

[0051] The insulators 222, 272, 273, 275, and 282 are Hydrogen (e.g., hydrogen atoms and molecules containing hydrogen atoms, hydrogen molecules and ions containing hydrogen atoms) It is preferable that the insulator 2 has a function of suppressing the diffusion of at least one of the following: 22, insulator 272, insulator 273, insulator 275, and insulator 282 are oxygen-resistant (e.g., For example, at least oxygen atoms, molecules containing oxygen atoms, oxygen molecules, and ions containing oxygen. For example, the insulator 222 and the insulator 272, insulator 273, insulator 275, and insulator 282 are each larger than insulator 224. It is preferable that the insulator 222 has low permeability to either or both of oxygen and hydrogen. The edge 272, the insulator 273, the insulator 275, and the insulator 282 are the insulators 25 It is preferable that the insulator 222 has a permeability to oxygen and / or hydrogen lower than 0. , insulator 272, insulator 273, insulator 275, and insulator 282 are insulators. It is preferable that the permeability to either or both of oxygen and hydrogen is lower than 280.

[0052] As shown in FIGS. 1B and 1C, the insulator 272 is disposed on the upper and side surfaces of the conductor 242a and the conductor The top and side surfaces of the body 242b, the sides of the oxide 230a and the oxide 230b, and the insulator It is preferable that the insulator 273 is in contact with the upper surface of the insulator 272. In this way, the insulator 280 is preferably provided with the insulator 272 and the insulator The insulator 224 and the oxide 230a and the oxide 230b are separated by the body 273. do.

[0053] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the insulator 224. an oxide 230b disposed on the oxide 230a; and at least one and oxide 230c in contact with the upper surface of oxide 230b.

[0054] In the transistor 200, a region in which a channel is formed (hereinafter, a channel forming region (also referred to as "oxide layer 230") and in the vicinity thereof, oxide 230a, oxide 230b, and oxide 23 Although a configuration in which three layers of 0c are laminated is shown, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, A two-layer structure of 230b and oxide 230c, or a laminated structure of four or more layers may be used. In addition, in the transistor 200, the conductor 260 is shown as having a two-layer structure. However, the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure. Alternatively, it may have a laminated structure of three or more layers.

[0055] Here, the conductor 265 and the conductor 260 on the conductor 265 form the gate of the transistor. The conductor 242a and the conductor 242b function as a source electrode or serves as the drain electrode. Transistor 200 has a conductive The body 260 and the conductor 265 self-adhesively fill the openings formed in the insulator 280, etc. By forming the conductor 260 and the conductor 265 in this manner, The conductor 260 and the conductor 265 are positioned in the region between the conductor 242a and the conductor 242b. It can be positioned reliably and accurately without the need for alignment.

[0056] As shown in FIG. 1B and FIG. 1C, the conductor 265 functioning as a gate electrode is The transistor 200 is formed in the channel length direction and the channel width direction of the transistor 200. That is, in the top view of FIG. Therefore, the projected area is larger than that of the conductor 260. Therefore, the gate capacitance of the transistor 200 can be increased. The width of the offset region between the source region and the drain region can be reduced. As a result, the electrical characteristics of the transistor 200 can be improved.

[0057] As shown in FIG. 1B and FIG. 1C, the insulator 275 is in contact with the side surface of the conductor 260. The insulator 275 is also in contact with the insulator 250. An insulator 275 is disposed between the conductor 260 and the insulator 250. The structure is such that the insulator 250 does not come into contact with the insulator 250. By arranging the insulator 275 having the suppressing function in this manner, the insulator 250 This can prevent oxygen from diffusing into the conductor 260 or being absorbed into the conductor 260. In addition, the chlorine, fluorine, and hydrogen contained in the conductor 260 can be prevented from being oxidized. In this way, the diffusion of impurities such as water into the insulator 250 can be suppressed.

[0058] In addition, the presence of the insulator 275 prevents the oxygen contained in the insulator 280 from becoming the oxide 230c and When the electrons move through the insulator 250 to the oxide 230a and the oxide 230b, they are conductors on the way. For example, the heat treatment can suppress the absorption of the insulator 260. When oxygen contained in 280 is diffused, the loss of oxygen can be reduced. In the details, the oxygen that is released by heating is sometimes called excess oxygen. For example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxynitride, or Alternatively, hafnium oxide can be used.

[0059] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c) are metal oxides that function as oxide semiconductors. It is preferable to use an oxide semiconductor.

[0060] The transistor 200 having an oxide semiconductor in a channel formation region is in a non-conducting state. Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be formed into films by sputtering or the like, and therefore are suitable for use as highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0061] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum or gallium). Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, yttrium, or the like. The oxide 230 may be In-Ga oxide, In- Zn oxide may also be used.

[0062] In addition, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. The presence of impurities and oxygen vacancies in the region makes the electrical characteristics more variable and reduces reliability. In addition, oxygen vacancies may exist in a region in an oxide semiconductor where a channel is formed. Therefore, the transistor tends to have normally-on characteristics. It is preferable that the oxygen vacancies in the region to be insulated are reduced as much as possible. Oxygen can be supplied to the oxide 230 via oxygen or the like to compensate for the oxygen deficiency. This transistor has stable electrical characteristics and improved reliability by suppressing fluctuations in electrical characteristics. A transistor can be provided.

[0063] Also, a source electrode of the transistor 200 is provided on the oxide 230 so as to be in contact with the oxide 230. In this case, the element contained in the conductor 242 that functions as a drain electrode absorbs the oxygen of the oxide 230. When the oxide 230 has a function of absorbing the conductor, the oxide 230 is preferably disposed between the oxide 230 and the conductor 242 or on the surface of the oxide 230. In some cases, a low resistance region may be partially formed in the vicinity of the low resistance region. In this case, the low resistance region may include Impurities (hydrogen, nitrogen, metal elements, etc.) that fill the oxygen vacancies act as donors, In the following, the carrier density of hydrogen that has entered the oxygen vacancy may increase. That V o The oxide 230 may be referred to as H. The oxide 230 may be a conductor 242a and a conductor 242b. A region that does not overlap with 42b functions as a channel forming region of the transistor 200. This region has a lower carrier density than the low resistance region, and V o H is reduced It is preferable.

[0064] As shown in FIGS. 1B and 1C, a transistor 200 according to one embodiment of the present invention is an insulator. 282 is in direct contact with the insulator 250 and the insulator 275. With such a structure, oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 260. In addition, oxygen contained in the insulator 280 diffuses to the outside of the transistor due to heat or the like. Therefore, the oxygen contained in the insulator 280 can be prevented from being dissolved in the oxide 2 30c to the oxide 230a and the oxide 230b without loss. Since the oxide 230a and the oxide 230b can be introduced, oxygen vacancies in the oxide 230a and the oxide 230b can be reduced. , the electrical characteristics and reliability of the transistor 200 can be improved. Examples of the material include silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, and Hafnium oxide can be used.

[0065] FIG. 5(A) is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 1(A). 5 is a cross-sectional view of the source or drain region of the transistor 200 in the channel width direction. As shown in (A), the upper surface of the conductor 242b, the side surface of the conductor 242b, and the oxide 230a The side surface of the oxide 230b is covered with an insulator 272 and an insulator 273. Therefore, the conductor 242b is exposed from the side surface and the upper surface of the conductor 242b. Since the diffusion of impurities such as hydrogen and water and oxygen into the conductor 2b can be suppressed, The oxidation of the conductor 242b can be suppressed. The same effect can be obtained for the conductor 242a. In addition, the oxide 230 is formed from the side of the oxide 230a and the side of the oxide 230b. The diffusion of impurities such as hydrogen and water and oxygen into the oxide 230a and the oxide 230b can be suppressed. The insulator 272 may be, for example, a silicon nitride film or a silicon oxynitride film. The insulator 273 may be, for example, aluminum oxide or oxide. Hafnium oxide may be used.

[0066] FIG. 5(B) is a cross-sectional view of the portion indicated by the dashed line A7-A8 in FIG. 1(A). The channel width direction of the conductor 240b which is electrically connected to the transistor 200 and functions as a plug As shown in FIG. 5B, the conductor 240b has an insulator 241 on its side. Since b is arranged, impurities such as hydrogen and water from the insulator 280 and oxygen are condensed into the conductor The same effect can be seen with respect to the conductor 240a. The results are obtained.

[0067] As shown in FIG. 1C, the oxide 230a and the and oxide 230b and the bottom surface of conductor 265 in the area where conductor 265 does not overlap. The height is preferably lower than the height of the bottom surface of the oxide 230b. , the height of the bottom surface of the conductor 265 in the non-overlapping region and the oxide 230 The difference between the height of the bottom surface of b and m or less, and more preferably, from 5 nm to 20 nm.

[0068] In this manner, the conductor 260, which functions as a gate electrode, and the conductor 265 form a channel. The side and top surfaces of the oxide 230b in the hole formation region are covered with the oxide 230c and the insulator 250. The electric field of the conductor 260 and the conductor 265 is spread over the channel forming region. As a result, the switching of the transistor The characteristics can be improved. Specifically, the subthreshold swing value can be reduced. In addition, the off-current can be reduced and the on-current can be increased. The sum characteristics can be improved.

[0069] As a result, a semiconductor device having a transistor with good switching characteristics can be provided. Alternatively, a semiconductor having a transistor with a small subthreshold swing value can be A semiconductor device having a transistor with a large on-state current can be provided. Alternatively, a semiconductor device having a transistor with high frequency characteristics can be provided. Alternatively, it is possible to provide a semiconductor device having stable electrical characteristics by suppressing fluctuations in the electrical characteristics. In addition, a semiconductor device having improved reliability can be provided. In addition, a semiconductor device having a small transistor with good saturation characteristics can be provided. A semiconductor device having a transistor can be provided.

[0070] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0071] The conductor 205 is arranged to overlap the oxide 230, the conductor 260, and the conductor 265. In addition, the conductor 205 is preferably embedded in the insulator 216.

[0072] Here, the conductor 260 and the conductor 265 are the first gate (also called the top gate). The conductor 205 may also function as a second gate (bottom gate) electrode. In this case, the electric potential applied to the conductor 205 may be The potentials applied to the conductors 260 and 265 are changed independently of each other without being linked to each other. In particular, the conductor 205 is negatively charged. By applying the potential, the Vth of the transistor 200 is made larger than 0V, and the off-state Therefore, it is preferable to apply a negative potential to the conductor 205. When the potential applied to the conductor 260 and the conductor 265 is 0 V, the electric field is larger than when no electric field is applied. This allows the drain current to be reduced.

[0073] As shown in FIG. 1A, the conductor 205 is made of an oxide 230a and an oxide 23 0b in the channel width direction than the region that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 1C, the conductor 205 is made of an oxide 230a, and that the oxide 230b extends outward from the end portion intersecting with the channel width direction. In other words, the oxide 230a and the oxide 230b are preferably formed on the side in the channel width direction. On the outside of the surface, the conductor 205, the conductor 260, and the conductor 265 are insulated from each other. It is preferable that the conductor 205 is provided large so that the conductor 205 overlaps the conductor 205. In the plasma processing in the manufacturing process after the formation of the conductor 205, local charge However, one aspect of the present invention is that The conductor 205 is at least a conductor 242a and a conductor 242b. It is sufficient to overlap with oxide 230a and oxide 230b located therebetween.

[0074] With the above-mentioned configuration, the conductor 260 having the function of the first gate electrode, The electric field of the conductor 265 and the electric field of the conductor 205 functioning as the second gate electrode are Thus, the channel forming region of the oxide 230 can be electrically surrounded. In the above, the electric field of the first gate electrode and the second gate electrode forms a channel forming region. The structure of a transistor that electrically surrounds the This is called the (-channel) structure.

[0075] The conductor 205a has a conductive property that suppresses the permeation of impurities such as water or hydrogen and oxygen. It is preferable to use a material having a high resistance, such as titanium, titanium nitride, tantalum, or titanium nitride. The conductor 205b can be made of tungsten, copper, or aluminum. It is preferable to use a conductive material mainly composed of aluminum. However, a multi-layer structure of three or more layers may be used.

[0076] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and the oxide As an insulator or conductor located on top of a quartz semiconductor, it is possible to By successively depositing the film species, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high This is preferable because an oxide semiconductor film with intrinsic purity can be formed.

[0077] For example, a deposition apparatus having five process chambers is used to deposit the insulator 216 and the conductive layer 217. The insulating film that becomes the insulator 222 and the insulator 224, the oxide 230a, and the like are disposed on the substrate 205. The oxide film which becomes the oxide 230b, and the conductive film which becomes the conductor 242 are successively formed in this order. A film may be formed.

[0078] The insulators 214, 272, and 281 are configured to prevent impurities such as water or hydrogen from A barrier insulating film that prevents foreign matter from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 214, the insulator 272, and the insulator The body 281 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule (NO , NO, NO2, etc.), and has the function of suppressing the diffusion of impurities such as copper atoms (the above impurities It is preferable to use an insulating material through which oxygen (e.g., oxygen atoms) does not easily penetrate. The material has a function of suppressing the diffusion of at least one of oxygen molecules (the material is difficult for the oxygen to permeate). a) It is preferable to use an insulating material.

[0079] For example, the insulators 214, 272, and 281 may be made of silicon nitride. This allows impurities such as water or hydrogen to be absorbed into the base material rather than into the insulator 214. The insulator 202 can be prevented from diffusing from the plate side to the transistor 200 side. The oxygen contained in the insulating layer 214 can be prevented from diffusing toward the substrate side from the insulating layer 214. In addition, impurities such as water or hydrogen can be removed from the insulator 272 by removing the impurities from the insulator 272. Suppresses diffusion from the insulator 280 and the conductor 246 to the transistor 200 side. It is possible.

[0080] The insulator 214 may have a laminated structure. For example, an aluminum oxide film and a nitrogen A laminated structure with a silicon oxide film can be suitably used for the insulator 214. The silicon nitride film can supply oxygen to the area below the insulator 214. The film prevents impurities such as hydrogen and water from diffusing from the substrate side to the transistor 200 side. It can be suppressed.

[0081] Also, the insulators 216, 280, and 274 have a higher dielectric strength than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic For example, the capacitance of the insulator 216, the insulator 280, and the insulator 27 can be reduced. 4. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen Silicon or silicon oxide having voids may be used appropriately.

[0082] The insulator 222 and the insulator 224 function as gate insulators.

[0083] Here, it is preferable that the insulator 224 in contact with the oxide 230 is heated to release oxygen. For example, the insulator 224 may be made of silicon oxide or silicon oxynitride. By providing an insulator containing oxygen in contact with the oxide 230, The oxygen vacancies can be reduced, and the reliability of the transistor 200 can be improved.

[0084] Specifically, the insulator 224 is made of an oxide from which some oxygen is released when heated. The oxide that releases oxygen by heating is preferably TDS (Thermal Desulfurization System). The oxygen desorption rate was calculated as oxygen molecules by the oxygen sorption spectroscopy (Op-spectroscopy) analysis. The separation is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecule s / cm 3 or more than 3.0×10 20 molecules / cm 3 Oxide that is equal to or greater than Or, the amount of oxygen desorbed per area is 3.0×10 14 Molecules / cm 2 More than 1.0×10 15 molecules / cm 2 More than that, even more preferred Or 2.0×10 15 molecules / cm 2 The oxide is as above. The surface temperature of the oxide during the TDS analysis is 100°C to 700°C, or The range of 00°C or more and 400°C or less is preferable.

[0085] The insulator 222 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 is preferably a barrier insulating film that suppresses the It is preferable that the insulator 222 and the insulator 27 have a lower hydrogen permeability than the insulator 224. 2, the insulator 224 and the oxide 230 are surrounded, and water or Impurities such as hydrogen can be prevented from entering the transistor 200 .

[0086] Further, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). For example, Preferably, the body 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of impurities and oxygen contained in the insulator 2. This is preferable because it can reduce diffusion below 22. This can suppress reaction with oxygen contained in the body 224 and the oxide 230.

[0087] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Insulators containing oxides include aluminum oxide, hafnium oxide, aluminum and hafnium oxide, and It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The emission of hydrogen and the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0088] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, etc. may be added to these insulators. tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0089] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 (BST) or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progresses, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as the insulator, the physical thickness can be maintained while This makes it possible to reduce the gate potential during transistor operation.

[0090] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. good.

[0091] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b on the oxide 230a. The oxide 230c is located on the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0092] The oxide 230 has a layered structure made of oxides having different atomic ratios of metal atoms. Specifically, it is preferable that the metal oxide used for the oxide 230a has a composition element of The atomic ratio of element M in the metal oxide used for oxide 230b is It is preferable that the atomic ratio of M is larger than that of M. In addition, the metal oxide used for the oxide 230a is In the metal oxide used for the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element In. In the metal oxide, the atomic ratio of In to element M is In the metal oxide, the atomic ratio of In to the element M is preferably larger than that of In. The oxide 230c is a metal oxide that can be used for the oxide 230a or the oxide 230b. can be used.

[0093] In addition, the oxide 230b preferably has crystallinity. -OS(c-axis aligned crystalline oxide sem It is preferable to use a crystalline material such as CAAC-OS. Oxides have few impurities and defects (such as oxygen vacancies), high crystallinity, and a dense structure. Therefore, the source electrode or drain electrode is capable of drawing oxygen from the oxide 230b. This can prevent the oxide 230b from being oxidized by heat treatment. Since the transistor 200 can be manufactured at high temperatures, the It is stable against temperature (so-called thermal budget).

[0094] In addition, the energy of the conduction band minimum of the oxide 230a and the oxide 230c is It is preferable that the energy of the oxide is higher than the minimum energy of the conduction band of 0b. The electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. It is preferable that

[0095] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, The energy level of the conduction band minimum changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is In order to achieve this, the oxide At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c In this case, the defect level density of the mixed layer formed in the step (b) is preferably reduced.

[0096] Specifically, the oxide 230a is In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of In:Ga:Zn=1:1:0.5 may be used. , as the oxide 230b, In:Ga:Zn=4:2:3 [atomic ratio], or In:G A metal oxide having an atomic ratio of a:Zn=3:1:2 may be used. As the atomic ratio, In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3 atomic ratio], Ga:Zn=2:1[atomic ratio], or Ga:Zn=2:5[atomic ratio] In addition, a specific example of the oxide 230c having a laminated structure is as follows: The metal oxides with the atomic ratio of In:Ga:Zn=4:2:3 and Ga:Zn=2:1 [atomic ratio] of In:Ga:Zn=4:2:3 [atomic ratio] of metal oxides A layered structure of a metal oxide and a metal oxide with an atomic ratio of Ga:Zn=2:5, In:Ga Examples include a layered structure of gallium oxide and a metal oxide with an atomic ratio of Zn=4:2:3. can be done.

[0097] At this time, the main path of the carriers is the oxide 230b. By configuring the oxide 30c as described above, the interface between the oxide 230a and the oxide 230b and the oxide This can reduce the defect state density at the interface between the nitride 230b and the oxide 230c. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor 200 has high In addition, the oxide 230c is formed in a laminated structure. In this structure, the defect state density at the interface between the oxide 230b and the oxide 230c is In addition to the effect of lowering the temperature, the constituent elements of the oxide 230c diffuse to the insulator 250 side. More specifically, the oxide 230c has a laminated structure, and the laminated In order to position an oxide that does not contain In at the top of the structure, In that can diffuse to the insulator 250 side is The insulator 250 functions as a gate insulator, so that the diffusion of In can be suppressed. If the oxide 230c is dispersed, the transistor characteristics will be deteriorated. This makes it possible to provide a highly reliable semiconductor device.

[0098] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the energy gap should be 2 eV or more, preferably 2.5 eV or more. In this way, by using a metal oxide with a large energy gap, The off-state current of the transistor can be reduced. A semiconductor device with low power consumption can be provided.

[0099] The electron affinity or the energy level Ec of the conduction band minimum is the vacuum level as shown in FIG. The ionization potential Ip, which is the difference between Evac and the energy Ev at the top of the valence band, and the The ionization potential Ip can be calculated, for example, from the energy gap Eg. Ultraviolet Photoelectron Spectroscopy (UPS) The energy gap can be measured using a spectroscopy (Energy Gap) device. Eg can be measured, for example, using a spectroscopic ellipsometer.

[0100] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. The thickness of the conductor 242 is, for example, For example, the thickness may be from 1 nm to 50 nm, and preferably from 2 nm to 25 nm.

[0101] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, etc. Ru, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from rontium, lanthanum, etc., or containing the above-mentioned metal elements as components It is preferable to use an alloy or an alloy of the above-mentioned metal elements. For example, nitride Tantalum, titanium nitride, or nitrides containing tungsten, titanium, and aluminum; Tantalum and aluminum nitrides, ruthenium oxide, ruthenium nitride, strontium It is preferable to use an oxide containing ruthenium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, or nitrides containing titanium and aluminum, Ruthenium and aluminum nitrides, ruthenium oxide, ruthenium nitride, strontium Oxides containing ruthenium and oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation. It is preferable because it is a material that maintains its conductivity even when it absorbs oxygen.

[0102] The insulator 250 functions as a gate insulator. The insulator 250 is formed on the oxide 230c. The insulator 250 is preferably disposed in contact with the surface. , silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and oxide doped with carbon. Silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies were used. In particular, silicon oxide and silicon oxynitride are stable against heat, This is preferable.

[0103] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing it in contact with the upper surface of the oxide 230c, the channel forming region of the oxide 230b Oxygen can be effectively supplied through the oxide 230c. Similarly, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0104] A metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0105] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant, as the oxide. By making the base insulator have a laminated structure of the insulator 250 and the metal oxide, the base insulator is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0106] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tin, titanium, tantalum, nickel, germanium, magnesium, etc. The metal oxide may contain one or more metals selected from the following: Aluminum oxide, an insulator containing oxides of either or both of aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a material such as a laminate.

[0107] Alternatively, the metal oxide may function as a part of the gate electrode. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the material on the channel formation region side, oxygen desorbed from the conductive material This makes it easier for the material to be supplied to the formation area.

[0108] In particular, the metal oxide in which the channel is formed is a conductor that functions as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the metal. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Indium tin oxide, indium oxide containing tungsten oxide, etc. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, titanium oxide, indium zinc oxide, silicon-added Indium tin oxide containing nitrogen may also be used. By using such a material, a metal oxide in which a channel is formed may be used. In some cases, hydrogen contained in the insulator can be captured. In some cases, it may be possible to capture the hydrogen that is released by the reaction.

[0109] It is preferable that the conductor 265 contains a material that is difficult to oxidize. By using a non-oxidizing material, the conductor 265 itself can be prevented from being oxidized and becoming highly resistant. Examples of the oxidation-resistant material include tantalum nitride, tungsten nitride, titanium nitride, and platinum. , iridium, silver, gold, titanium aluminum alloy, titanium aluminum alloy nitride, etc. Alternatively, tantalum nitride, tungsten nitride, titanium nitride, platinum, Iridium, silver, gold, titanium aluminum alloys, titanium aluminum alloy nitrides, and titanium Nitrous oxide, tungsten, titanium, molybdenum, aluminum, copper, molybdenum tungsten It is possible to form a laminate film with a silicon alloy.

[0110] Alternatively, a conductive metal oxide may be used as the conductor 265. By using a metal oxide that is conductive even in the presence of oxygen, the conductor 265 can be As a result, the on-characteristics of the transistor can be improved. In addition, for example, conductive metal oxides include indium tin oxide (ITO) and silicon. Indium Tin Oxide (ITSO), Zinc Oxide (ZnO), Indium Tin Oxide with Zinc , gallium zinc oxide (GZO), aluminum zinc oxide (AZO), tin oxide (SnO2), fluorine-containing tin oxide (FTO), or aluminum-containing tin oxide (AT O), ruthenium oxide, etc. Also, for example, conductive In-Ga-Zn oxides Alternatively, a conductive film having a high work function may be used for the conductor 265. This may allow the threshold voltage of the transistor to be shifted in the positive direction.

[0111] The conductor 265 may be a semiconductor having high electrical conductivity, or may contain impurity elements such as phosphorus. Alternatively, polysilicon or a silicide such as nickel silicide may be used.

[0112] Although the conductor 260 is shown as having a two-layer structure in FIG. 1B and FIG. 1C, it may have a single-layer structure. It may have a laminated structure of three or more layers.

[0113] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of at least one of the above-mentioned elements.

[0114] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can suppress the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, nitride, and the like. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0115] The conductor 260b is a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated material. For example, a laminated structure of titanium, titanium nitride and the conductive material may be used. .

[0116] The insulator 280 may be, for example, silicon oxide, silicon oxynitride, silicon oxynitride, or fluorine. Silicon oxide doped with nitrogen, silicon oxide doped with carbon, and oxide doped with carbon and nitrogen. It is preferable that the silicon oxide has a vacancy. Silicon and silicon oxynitride are preferred because they are thermally stable. Materials such as silicon oxynitride, silicon oxide with voids, etc., have the advantage that they desorb oxygen when heated. This is preferable because it allows easy formation of a region containing the element.

[0117] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. In addition, the top surface of the insulator 280 may be planarized.

[0118] The insulator 282 prevents impurities such as water or hydrogen from entering the insulator 280 from above. It is preferable that the insulator 282 functions as a barrier insulating film that suppresses the electric field. An insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used. .

[0119] It is also preferable to provide an insulator 274 that functions as an interlayer film on the insulator 282. The insulator 274, like the insulator 224, has a low impurity concentration such as water or hydrogen in the film. is preferably reduced.

[0120] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material having the following components: 0b may each have a laminated structure.

[0121] In addition, when the conductor 240 has a laminated structure, the insulators 281, 274, and 28 2, the first conductor of the conductor 240 in contact with the insulator 280, the insulator 273, and the insulator 272 The conductive material used is one that has the function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, It is preferable to use ruthenium oxide or the like. In addition, impurities such as water or hydrogen are not included. The conductive material having the function of suppressing permeation may be used in a single layer or a multilayer structure. By using this material, impurities such as water or hydrogen from the upper layer of the insulator 281 are absorbed into the conductor 2 40a, conductor 240b, conductor 242a, and oxide 230 through conductor 242b. It is possible to suppress the contamination of the

[0122] The insulators 241a and 241b may be, for example, aluminum oxide or aluminum nitride. An insulator such as silicon nitride or silicon oxide nitride may be used. The insulator 241a and the insulator 241b are provided in contact with the insulator 272 and the insulator 273. Therefore, impurities such as water or hydrogen are absorbed from the insulator 280 and the like into the insulators 272 and 27. 3. Suppression of contamination of oxide 230 through conductor 240a and conductor 240b In addition, oxygen contained in the insulator 280 can be mixed with the conductor 240a and the conductor 240b. It can prevent absorption by b.

[0123] In addition, the conductive material 240a and the conductive material 240b are in contact with each other on the upper surface thereof and function as wiring. Conductor 246 (conductor 246a and conductor 246b) may be arranged. 46 shall be made of conductive materials mainly composed of tungsten, copper, or aluminum. The conductor may have a laminated structure, for example, titanium, titanium nitride, etc. The conductive material may be laminated to the insulating material. The insulating film 11 may be formed so as to be embedded in the insulating film 11 .

[0124] <Configuration Example 2 of Semiconductor Device> Here, a semiconductor device having a different configuration from the semiconductor device shown in FIG. 3(A), 3(B), and 3(C) show a transistor 200 according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a transistor 200 and its surroundings.

[0125] FIG. 3A is a top view of a semiconductor device including a transistor 200. FIG. 3B) and FIG. 3C are cross-sectional views of the semiconductor device. 3(A) is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. FIG. 3(C) is a cross-sectional view in the longitudinal direction of the panel. 1 is a cross-sectional view of a portion indicated by a solid line in FIG. 1, which is electrically connected to the transistor 200 and functions as a plug. 3A is a cross-sectional view of the conductor 240b in the channel width direction. For clarity of illustration, some elements have been omitted.

[0126] The semiconductor device shown in FIG. 3 is electrically connected to the transistor 200 and functions as a plug. The conductor 244 contacts the bottom of the conductor 240 (conductor 240a and conductor 240b). (conductor 244a and conductor 244b) is different from the semiconductor device shown in FIG. become.

[0127] As shown in FIG. 3B and FIG. 3C, the insulator 224, the insulator 272, and the insulator 27 3. Conductor 274, insulator 280, insulator 282, insulator 274, and insulator 281 are provided at the bottom of the openings. An electrical conductor 244 is disposed.

[0128] In addition, on the conductor 244, an insulator 241 (insulator 241a and insulator A first conductor of the conductor 240 is provided in contact with the side surface of the edge member 241b. Further inside, a second conductor of the conductors 240 is provided.

[0129] As shown in FIG. 3C, the insulator 224, the insulator 272, the insulator 273, and the insulator 280 The size of the openings in the insulators 282, 274, and 281 is determined based on the size of the oxide 2. It is preferable that the width of the opening 30a and the width of the oxide 230b in the channel width direction are larger than that of the opening 30a and the oxide 230b. At the bottom of the oxide 230b, the top surface of the oxide 230b, the side surface of the oxide 230b, and the oxide 230a Therefore, the conductor 244 is connected to the upper surface of the conductor 242 and the side surface of the conductor 242. Since the oxide 230a contacts the side of the oxide 230b, the contact resistance is The conductor 244 can be made of the same material as the conductor 265. For other configurations and effects, please refer to the configuration example 1 of the semiconductor device described above. It is possible.

[0130] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0131] <Substrate> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate The semiconductor substrate may be, for example, a semiconductor such as silicon or germanium. Solid substrate, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of zinc oxide, gallium oxide, etc. A semiconductor substrate having an insulating region inside the substrate, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, and alloy substrates. Substrates with metal nitrides, conductive resin substrates, etc. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, A substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate Alternatively, a substrate having an element provided thereon may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light-emitting element, a recording element, and a Memory elements, etc.

[0132] <Insulator> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0133] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. The material should be selected accordingly.

[0134] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum and hafnium, and oxides containing aluminum and hafnium oxide-nitride having silicon and hafnium; oxide-nitride having silicon and hafnium; Examples of suitable materials include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0135] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen, silicon oxide with voids, or resin, etc. be.

[0136] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, , for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon , phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulators containing tungsten, neodymium, hafnium, or tantalum are used in single or multilayer configurations. Specifically, the insulating material has a function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or metal oxides such as tantalum oxide, aluminum nitride, titanium aluminum nitride, Metal nitrides such as titanium oxide, silicon oxynitride, or silicon nitride can be used. .

[0137] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0138] <Conductor> Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from aluminum, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, or nitrides containing tungsten, titanium and aluminum, tantalum Ruthenium and aluminum nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, or the like. Also, tantalum nitride, titanium nitride, or nitrides containing titanium and aluminum, tantalum and aluminum nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize. It is also preferable because it is a material that maintains its conductivity even when it absorbs oxygen. Highly conductive semiconductors, such as polycrystalline silicon containing pure elements, nickel Silicides such as silicide may also be used.

[0139] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0140] In the case where an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminate structure in which an oxygen-containing conductive material is used as the It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen desorbed from the conductive material to be supplied to the channel formation region.

[0141] In particular, the metal oxide in which the channel is formed is a conductor that functions as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the metal. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. In addition, a conductive material containing nitrogen such as indium tin oxide or tungsten oxide may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may be used. By using such a material, the channel is formed In some cases, hydrogen can be captured from the metal oxide that is insulated from the outer In some cases, it may be possible to capture hydrogen that is mixed in from the surroundings, etc.

[0142] <Metal oxide> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0143] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or Or multiple types may be included.

[0144] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. The element M can be aluminum, gallium, yttrium, or The element M can be tin, etc. Other elements that can be used for M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, combinations of the aforementioned elements may be used.

[0145] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0146] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, CAAC-OS, polycrystalline Nanocrystalline oxide semiconductor, nc-OS conductor), pseudo-amorphous oxide semiconductor (a-like OS) us-like oxide semiconductor, and amorphous oxide semiconductor There are bodies, etc.

[0147] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0148] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. It is difficult to confirm the presence of the crystal structure due to the distortion of the lattice arrangement. This is because the CAAC-OS is aligned in the ab-plane direction. In the case of the ferroelectric material, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0149] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M tend to have a layered structure. When the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn ) layer. Also, when the indium in the In layer is replaced with the element M, (In, M) layer.

[0150] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of metal oxides having CAAC-OS are stable. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0151] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0152] In addition, indium oxide, which is a type of metal oxide containing indium, gallium, and zinc, In the case of IGZO, the nanocrystals mentioned above make it stable. In particular, IGZO tends to have difficulty growing crystals in air. , small crystals (e.g., For example, the nanocrystals mentioned above may be structurally more stable.

[0153] The a-like OS is a metal oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has voids or low density regions. The ke-OS has a lower crystallinity than the nc-OS and CAAC-OS.

[0154] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention can be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more kinds.

[0155] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0156] In addition, when an alkali metal or alkaline earth metal is contained in a metal oxide, a defect level is formed. Therefore, alkali metals or alkaline earth metals may form a carrier. A transistor that uses a metal oxide containing metals in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide Specifically, it is preferable to reduce the amount of alkali metal or alkali metal in the metal oxide. Concentration of earth metals (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by ss Spectrometry) is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0157] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the carrier In some cases, hydrogen atoms are formed by bonding with oxygen atoms that bond with metal atoms. Therefore, it is recommended to use metal oxides that contain hydrogen. Such a transistor is likely to have normally-on characteristics.

[0158] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5×1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, it is possible to impart stable electrical characteristics.

[0159] <Method for manufacturing semiconductor device> Next, a semiconductor device having a transistor 200 according to the present invention shown in FIG. The manufacturing method will be described with reference to Figs. 6 to 17. In Figs. 6 to 17, (B) of each figure shows the area indicated by the dashed line A1-A2 in (A). 1 is a corresponding cross-sectional view taken along the channel length direction of transistor 200. (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A), It is also a cross-sectional view in the channel width direction of the transistor 200. 1, some elements are omitted for clarity of illustration.

[0160] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The deposition of 14 was performed by sputtering, chemical vapor deposition (CVD), Deposition method, Molecular Beam Epitaxy (MBE) eam Epitaxy method, Pulsed Laser Deposition (PLD) Deposition) method or ALD (Atomic Layer Deposit) This can be done using the (ion) method or the like.

[0161] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are classified into two types: the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method.

[0162] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc., contained in a semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage occurs. Since the thermal CVD method does not require any heat treatment, the yield of the semiconductor device can be increased. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0163] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time. This allows for extremely thin film deposition, film deposition on structures with high aspect ratios, and pinhole It is possible to form films with few defects such as holes, excellent coating properties, and low temperature film formation. In addition, the ALD method includes a plasma-assisted deposition method called PEALD ( This includes the Plasma Enhanced ALD method. This may be preferable because it allows film formation at a lower temperature. Some of the films contain impurities such as carbon. For this reason, the films deposited by the ALD method are In comparison with the film formed by the film forming method of the first embodiment, the film may contain a large amount of impurities such as carbon. The quantity of impurities is determined by X-ray photoelectron spectroscopy (XPS). This can be done using NMR Spectroscopy.

[0164] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method achieves excellent step coverage and excellent thickness uniformity, making it ideal for aspect ratio However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0165] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0166] In this embodiment, the insulator 214 is formed of silicon nitride by CVD. In this way, an insulator that is difficult for copper to penetrate, such as silicon nitride, is used as the insulator 214. Therefore, a metal that easily diffuses, such as copper, is used for the conductor layer (not shown) below the insulator 214. Even if the metal is present, it is possible to suppress the metal from diffusing into layers above the insulator 214.

[0167] Next, the insulator 216 is deposited on the insulator 214. The deposition of the insulator 216 is carried out by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0168] Next, an opening is formed in the insulator 216 so as to reach the insulator 214. The opening may be, for example, a groove or This also includes slits. The area where an opening is formed may also be referred to as an opening. The openings may be formed by wet etching, but it is more preferable to use dry etching. Insulator 214 is preferably formed by etching insulator 216. It is preferable to select an insulator that functions as an etching stopper when etching the silicon substrate. For example, When silicon oxide is used for the insulator 216 forming the groove, the insulator 214 is silicon nitride. , aluminum oxide, and hafnium oxide may be used.

[0169] After the opening is formed, a conductive film that will become the conductor 205 is formed. The conductive film has properties that suppress the permeation of oxygen. For example, tantalum nitride, tungsten nitride, etc. Stainless steel, titanium nitride, etc. can be used. Alternatively, tantalum nitride, tungsten nitride, etc. can be used. tantalum, tungsten, titanium, molybdenum, aluminum, copper, The conductive film that becomes the conductor 205 can be a laminated film with a molybdenum tungsten alloy. The deposition of the film is performed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. This can be done.

[0170] In this embodiment, the conductive film that becomes the conductor 205 has a multi-layer structure. A tantalum nitride film is formed by a deposition method, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductive film that becomes the conductor 205, Even if a metal that easily diffuses, such as copper, is used as the conductive film on the conductive film that becomes the conductor 205, The metal can be prevented from diffusing downward from the conductor 205 .

[0171] Next, a conductive film is formed on the conductive film that will become the conductor 205. The conductive film is formed by plating. The method is performed using the deposition method, sputtering method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, the conductive film on the conductive film that becomes the conductor 205 is A film of a low resistance conductive material such as copper is deposited.

[0172] Next, CMP (Chemical Mechanical Polishing) processing By carrying out the above, the upper layer of the conductive film which becomes the conductor 205 and the A portion of the lower layer is removed to expose the insulator 216. As a result, only the opening contains the conductor 205 and Thus, a conductive film having a flat upper surface can be formed. (See FIG. 6.) It should be noted that the CMP process may remove a part of the insulator 216. be.

[0173] Hereinafter, a method for forming the conductor 205 that differs from the above will be described.

[0174] A conductive film that will become the conductor 205 is formed on the insulator 214. The deposition of the film is performed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The conductive film that becomes the conductor 205 can be a multi-layer film. In this embodiment mode, a tungsten film is formed as the conductive film to be the conductor 205.

[0175] Next, the conductive film that becomes the conductor 205 is processed by lithography. Form.

[0176] In the lithography method, first, the resist is exposed through a mask. The resist mask is formed by removing or leaving the resist-removed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. are used to A resist mask can be formed by exposing the photoresist to light. A liquid immersion technique may be used in which the substrate is filled with liquid (e.g., water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not necessary. The resist mask can be removed by ashing or the like. Which dry etching process is performed, which wet etching process is performed, and which dry etching process is performed After the treatment, wet etching is performed, or after the treatment, dry etching is performed. It is possible to carry out the filtering process.

[0177] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating layer that is a hard mask material is formed on the conductive film that is to be the conductor 205. An insulating film and a conductive film are formed, a resist mask is formed on the insulating film and a hard mask material is etched. By this etching, a hard mask of a desired shape can be formed. The etching of the conductive film may be performed after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be lost during etching. After etching the conductive film that becomes the conductor 205, the hard mask is removed by etching. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, If it is possible to do so, it is not necessary to remove the hard mask.

[0178] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. : Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power source may be applied to one of the parallel plate type electrodes. A configuration in which a plurality of different high frequency power sources are applied to the electrodes may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching apparatus or the like can be used.

[0179] Next, an insulating film that becomes the insulator 216 is formed on the insulator 214 and the conductor 205. The insulating film that becomes the body 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. In this embodiment, the insulating layer 216 is formed by depositing an insulating film on the insulating layer 216. The film is made of silicon oxide by the CVD method.

[0180] Here, the thickness of the insulating film that becomes the insulator 216 is preferably equal to or greater than the thickness of the conductor 205. For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film that becomes the insulator 216 is In this embodiment, the thickness of the conductor 205 is set to 150 nm. The thickness of the insulating film that becomes the insulator 216 is set to 350 nm.

[0181] Next, the insulating film that will become the insulator 216 is subjected to CMP (Chemical Mechanical Polishing). By carrying out a polishing process, a part of the insulating film that will become the insulator 216 is removed, The surface of the conductor 205 is exposed. This allows the conductor 205 and the insulator 206, which have a flat upper surface, to be bonded to each other. The above is a method for forming the conductor 205 that is different from the above method. The transistor 200 having the conductor 205 and the insulator 216 formed as described above is An example of such a semiconductor device is shown in FIG.

[0182] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulating layer, an insulator containing oxide of one or both of aluminum and hafnium is formed. In addition, the insulator containing oxide of either or both of aluminum and hafnium is As examples, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium It is preferable to use aluminum and hafnium aluminate. Insulators containing one or both oxides of aluminum provide excellent barrier properties against oxygen, hydrogen, and water. The insulator 222 has a barrier property against hydrogen and water, so that the transistor Hydrogen and water contained in the structure provided around the rotor 200 pass through the insulator 222. The inward diffusion of the transistor 200 is suppressed, and the generation of oxygen vacancies in the oxide 230 is suppressed. can be suppressed.

[0183] The insulator 222 is formed by sputtering, CVD, MBE, PLD, or A. This can be done using the LD method or the like.

[0184] Next, the insulating film 224A is formed on the insulator 222. The insulating film 224A is formed by sputtering. This can be done using deposition, CVD, MBE, PLD, or ALD methods. Cut.

[0185] Subsequently, a heat treatment is preferably performed. The reaction temperature is preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower. The heat treatment may be performed in a nitrogen or inert gas atmosphere, or in an atmosphere of oxidizing gas at a concentration of 10ppm. m or more, 1% or more, or 10% or more. Heat treatment is also performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by To compensate for the lost oxygen, the gas contains 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed in an atmosphere containing the above-mentioned.

[0186] In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour, and then the The heat treatment is then performed in an oxygen atmosphere at a temperature of 400°C for one hour. Impurities such as water and hydrogen contained in the film 224A can be removed.

[0187] The heat treatment may be performed after the formation of the insulator 222. Heat treatment conditions can be used.

[0188] Here, in order to form an excess oxygen region in the insulating film 224A, a plasma containing oxygen under reduced pressure is used. The oxygen-containing plasma treatment may be, for example, a high-density plasma treatment using microwaves. It is preferable to use a device having a power source for generating plasma. Alternatively, RF is provided on the substrate side. The high density plasma may be generated by a power source that applies a radio frequency (RF) to the plasma. By using this, high density oxygen radicals can be generated, and RF is applied to the substrate side. This allows oxygen radicals generated by high-density plasma to be efficiently introduced into the insulating film 224A. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, In addition, a plasma treatment containing oxygen may be performed to compensate for the desorbed oxygen. By appropriately selecting the conditions for the Zuma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be eliminated. Impurities can be removed, in which case heat treatment is not necessary.

[0189] Here, aluminum oxide is deposited on the insulating film 224A by, for example, a sputtering method. Then, the aluminum oxide is etched with CM until the insulating film 224A is exposed. By carrying out the CMP process, the surface of the insulating film 224A is flattened and The surface of the insulating film 224A can be smoothed. By placing it on A and performing CMP processing, it becomes easier to detect the end point of the CMP processing. By the MP treatment, a part of the insulating film 224A is polished, and the thickness of the insulating film 224A is reduced. However, the thickness of the insulating film 224A can be adjusted when the insulating film 224A is formed. 4A By flattening and smoothing the surface, it is possible to prevent deterioration of the coverage of the oxide film that will be formed later. As a result, it may be possible to prevent a decrease in the yield of the semiconductor device. Then, an insulating film 224 is formed by forming an aluminum oxide film on the insulating film 224 by a sputtering method. This is preferable because oxygen can be added to A.

[0190] Next, an oxide film 230A which becomes an oxide 230a, an oxide film 230b and an oxide film 230c which become an oxide 230b are formed on the insulating film 224A. The oxide film 230B is then formed in this order (see FIG. 6). It is preferable to form the oxide film 230 continuously without exposing the oxide film 230 to the atmosphere. A, and prevent impurities or moisture from the atmospheric environment from adhering onto the oxide film 230B. This makes it possible to keep the vicinity of the interface between the oxide film 230A and the oxide film 230B clean.

[0191] The oxide film 230A and the oxide film 230B are formed by sputtering, CVD, MBE, etc. The deposition can be performed by using a deposition method, a PLD method, an ALD method, or the like.

[0192] For example, the oxide film 230A and the oxide film 230B are formed by a sputtering method. In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed is reduced. In addition, when the oxide film is formed by sputtering, In this case, the above-mentioned In-M-Zn oxide target can be used.

[0193] In particular, when the oxide film 230A is formed, a part of the oxygen contained in the sputtering gas is mixed with the insulating film. Therefore, the sputtering gas for the oxide film 230A may be The percentage of oxygen contained is 70% or more, preferably 80% or more, and more preferably 100%. That's good.

[0194] In addition, when the oxide film 230B is formed by a sputtering method, the oxide film 230B is formed by sputtering. The ratio of oxygen to be added is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. The oxygen-deficient oxide semiconductor is formed in the channel formation region. A transistor using this region can achieve a relatively high field effect mobility.

[0195] In this embodiment, the oxide film 230A is formed by sputtering In:Ga: Zn=1:1:0.5[atomic ratio] (2:2:1[atomic ratio]), or 1:3:4[ The oxide film 230B is formed by sputtering a target having a ratio of 1:1 to 1:1. The GaN-GaAs / ZnAlN alloy was grown by the GaN-GaAs / ZnAlN alloy using a target with an atomic ratio of In:Ga:Zn=4:2:4.1. By appropriately selecting the film formation conditions and atomic ratio, each oxide film can be formed in a thickness of 200 nm. It is advisable to shape it according to the characteristics desired for 30.

[0196] Next, a heat treatment may be performed. The heat treatment may be performed under the above-mentioned heat treatment conditions. By the heat treatment, impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B are removed. In this embodiment, the wafer is heated at 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. cormorant.

[0197] Next, a conductive film 242A is formed on the oxide film 232B. This can be done using deposition, CVD, MBE, PLD, or ALD methods. (See Figure 6.)

[0198] Next, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into islands. The substrate 230a, the oxide 230b, and the conductive layer 242B are formed (see FIG. 7). Although not shown, in this process, the film in the region that does not overlap with the oxide 230a of the insulating film 224A is The thickness may be reduced.

[0199] Here, the oxide 230a, the oxide 230b and the conductive layer 242B are at least partially The oxide 230a, the oxide 230b, and the conductor 205 are formed to overlap each other. The side surface of the conductive layer 242B may be approximately perpendicular to the upper surface of the insulator 222. The sides of the substrate 230a, the oxide 230b, and the conductive layer 242B are in contact with the top surface of the insulator 222. In addition, since the transistors 200 are arranged substantially perpendicularly, the area can be reduced and the density can be increased. Alternatively, the oxide 230a, the oxide 230b, and the conductive layer 242B may be insulated from each other. The angle of the top surface of the edge 222 may be low. In that case, the oxide 230 a, the angle between the side surface of the oxide 230b and the conductive layer 242B and the top surface of the insulator 222 is 60°. It is preferable that the angle is 70° or more and less than 70°. The covering property of the insulator 272 etc. is improved, and defects such as voids can be reduced.

[0200] In addition, a curved surface is provided between the side surface and the upper surface of the conductive layer 242B. In other words, it is preferable that the ends of the side surfaces and the top surface are curved (hereinafter referred to as rounded). The curved surface has a radius of curvature of 3 nm or less at the end of the conductive layer 242B, for example. The thickness is preferably 5 nm to 6 nm. This improves the film coverage in the subsequent film formation process.

[0201] The oxide film and the conductive film may be processed by a lithography method. This processing can be performed by dry etching or wet etching. The etching method is suitable for microfabrication.

[0202] Next, on the insulating film 224A, the oxide 230a, the oxide 230b and the conductive layer 242B Then, an insulating film 272A is formed (see FIG. 8).

[0203] The insulating film 272A is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done by using an LD method or the like. The insulating film 272A has a function of suppressing oxygen permeation. In this embodiment, an insulating film having the following properties is preferably used: A silicon nitride film is formed.

[0204] Next, the insulating film 273A is formed on the insulating film 272A. This can be done using the sputtering method, CVD method, MBE method, PLD method, or ALD method. For example, it is preferable to form an aluminum oxide film by a sputtering method. In this embodiment, an aluminum oxide film is formed by sputtering. See Figure 8).

[0205] Next, an insulating film that will become the insulator 280 is formed on the insulating film 273A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. Next, a CMP process is performed on the insulating film that will become the insulator 280. A flat faced insulator 280 is formed (see FIG. 9).

[0206] Next, a part of the insulator 280, a part of the insulating film 273A, a part of the insulating film 272A, and the conductive layer A part of 242B and a part of the insulating film 224A are processed to form an opening reaching the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. Thus, the insulator 224, the conductor 242a, the conductor 242b, the insulator 272, and the insulator 273 (see FIG. 9).

[0207] As shown in FIG. 9C, the opening allows the oxide 230a of the insulating film 224A and In the non-overlapping region, the insulating film 224A is entirely removed to expose the surface of the insulator 222. For example, the insulating film 224A is formed with an acid. The insulating film 224A is left even in the region not overlapping with the insulating film 230a. In this case, the thickness of the insulating material 224 in the region not overlapping with the oxide 230a may be set to 1. may be thinner than the thickness of the region of the insulator 224 that overlaps with the oxide 230a. An example of a transistor 200 fabricated in this manner is shown in FIG.

[0208] In addition, a part of the insulator 280, a part of the insulating film 273A, a part of the insulating film 272A, and the conductive layer The processing of a part of 242B and a part of insulator 224A is performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching to form the insulating film 273A. A part of the insulating film 272A and the conductive layer 242B are processed by wet etching. A part of the insulating material 224A and a part of the insulating material 224B may be processed by dry etching.

[0209] By performing processes such as dry etching, etching gases, etc. The impurities caused by the oxidation are attached to or inside the oxide 230a and the oxide 230b. Impurities can diffuse into the silicon. Examples of impurities include fluorine and chlorine.

[0210] In order to remove the above impurities, cleaning is performed. These include wet cleaning, plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0211] Wet cleaning uses oxalic acid, phosphoric acid, ammonia water, or hydrofluoric acid. The cleaning process may be carried out using an aqueous solution diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using carbonated water may be performed.

[0212] Next, a heat treatment may be performed. The heat treatment is performed under reduced pressure without exposure to the atmosphere. Then, an oxide film 230C is formed (see FIG. 10). The moisture and hydrogen adsorbed on the surface of the oxide 230b are removed, and the oxide 230b is then oxidized. The moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. The processing temperature is 200°C.

[0213] The oxide film 230C is formed by sputtering, CVD, MBE, PLD, or A This can be done using the LD method or the like. The oxide film 230C can be selected according to the desired characteristics. The oxide film 230C is formed by using the same film forming method as the oxide film 230A or the oxide film 230B. In the present embodiment, the oxide film 230C is formed by sputtering In: Ga:Zn=1:3:4 [atomic ratio], or In:Ga:Zn=4:2:4.1 [atomic ratio] The film is formed using a target with a [atomic ratio].

[0214] The oxide film 230C may be a laminated film. For example, the oxide film 230C may be formed by sputtering. The film was formed using a target with an atomic ratio of n:Ga:Zn=4:2:4.1. The film may be formed using a target having an atomic ratio of In:Ga:Zn=1:3:4.

[0215] In particular, when the oxide film 230C is formed, a part of the oxygen contained in the sputtering gas is converted into the oxide. 230a and oxide 230b. Thus, the oxide film 230C The proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, and more preferably Preferably, it should be set to 100%.

[0216] Next, a heat treatment may be performed. The heat treatment is performed under reduced pressure without exposure to the atmosphere. Then, an insulating film 250A is formed (see FIG. 11). The moisture and hydrogen adsorbed on the surface of the oxide film 230C are removed, and the oxide film 230C is then heated to 300° C. The moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b and the oxide film 230C are reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0217] The insulating film 250A is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 250A can be formed by a CVD method. It is preferable to form a film of silicon hydride by using a silicon nitride film. The temperature is preferably 350° C. or higher and lower than 450° C., and more preferably about 400° C. By forming the film at 400°C, an insulator with few impurities can be formed.

[0218] Next, the conductive film 265A is formed. The conductive film 265A is formed by a sputtering method, a CV method, or the like. The conductive film 265 can be formed by a method such as a TEM method, a PLD method, or an ALD method. A is the thickness of the part parallel to the bottom surface of the insulator 224, and the thickness of the part parallel to the side of the opening of the insulator 280. For example, a low pressure long throw sputter is preferably used. sputtering, collimator sputtering, or ionized sputtering (unbalance The film can be formed by using methods such as magnetron sputtering (see Figure 12). .

[0219] Next, the conductive film 265A is isotropically etched to form an insulating The conductive film 265A in the portion parallel to the side of the opening of the body 280 is removed, and the bottom surface of the insulator 224 is left flat. The conductive film 265A in the row portion is left to form the conductor 265B (see FIG. 13).

[0220] Next, the insulating film 275A is formed. The insulating film 275A is formed by a sputtering method, a CV method, or the like. This can be done by using a deposition method, an MBE method, a PLD method, an ALD method, or the like. Next, an aluminum oxide film is formed using the ALD method (see FIG. 14).

[0221] Next, the insulating film 275A is anisotropically etched to form a layer parallel to the bottom surface of the insulator 224. The insulating film 275A in the portion is removed, and the insulating film 275 in the portion parallel to the side of the opening of the insulator 280 is removed. A is left to form insulator 275B (see FIG. 15).

[0222] In the anisotropic etching of the insulating film 275A, the conductor 265B serves as an etching stopper. It is preferable that the conductor 265B functions as an etching stopper. Damage during anisotropic etching (physical damage and charging damage) ) from reaching the insulating film 250A. The reactive etching should be performed under conditions in which the conductor 265B is hardly etched. Specifically, when the etching rate of the conductor 265B is set to 1, the etching rate of the insulating film 275 is preferably The etching rate of A is preferably 5 or more, and more preferably 10 or more. .

[0223] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Ab is formed by sputtering, CVD, MBE, PLD or A This can be done by using the LD method or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by the ALD method, and the conductive film 260B is formed by the CVD method. Deposit 260Ab (see Figure 16).

[0224] Next, the oxide film 230C, the insulating film 250A, the conductor 265B, and the insulating film 260A are removed by CMP processing. The body 275B, the conductive film 260Aa and the conductive film 260Ab are polished until the insulator 280 is exposed. By polishing, the oxide 230c, the insulator 250, the conductor 265, the insulator 275, and And the conductor 260 (conductor 260a and conductor 260b) is formed (see FIG. 17).

[0225] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is carried out for 1 hour. The moisture concentration in the insulator 250 and the insulator 280 is reduced by the heat treatment. The degree and hydrogen concentration can be reduced.

[0226] Next, on the oxide 230c, on the insulator 250, on the conductor 265, on the insulator 275, on the conductor An insulator 282 may be formed on the insulating layer 260 and on the insulating layer 280. The film is formed by sputtering, CVD, MBE, PLD, or ALD. The insulating film that becomes the insulator 282 can be formed by, for example, a sputtering method. In this way, it is preferable to form a film of aluminum oxide on the upper surface of the conductor 260. By forming the insulator 282 in contact with the insulating film 280, the insulator 280 becomes effective in the subsequent heat treatment. This is preferable because it can prevent oxygen from being absorbed into the conductor 260 (FIG. 17 reference).

[0227] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The treatment is carried out for 1 hour. The heat treatment causes the insulator 282 to be formed on the insulator 280. The added oxygen is injected into the oxide 230a and the oxide 230b via the oxide 230c. You can enter.

[0228] Next, the insulator 274 may be deposited on the insulator 282. This can be done using techniques such as CVD, MBE, PLD, or ALD. This is possible (see Figure 17).

[0229] Next, an insulator 281 may be formed on the insulator 274 (see FIG. 17). The deposition of the film is performed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. The insulator 281 can be formed by, for example, sputtering. It is preferable to deposit a silicon oxide film.

[0230] Next, the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 274, and An opening is formed in the insulating material 281 so as to reach the conductor 242a and the conductor 242b. The openings may be formed by using a lithography method.

[0231] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator The insulating film 241 is formed. The insulating film is formed by a sputtering method, a CVD method, an MBE method, a PL method, etc. The insulating film to be the insulator 241 can be formed by the ALD method or the ALD method. In the case of ALD, it is preferable to use an insulating film having a function of suppressing oxygen permeation. It is preferable to form an aluminum oxide film by anisotropic etching. For example, a dry etching method or the like may be used. By configuring the side of the opening in this way, , which suppresses the permeation of oxygen from the outside and prevents the conductors 240a and 240b from being formed next. In addition, the conductors 240a and 240b can be prevented from oxidizing. This can prevent impurities such as elements from diffusing to the outside.

[0232] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water and hydrogen. It is preferable to use a laminated structure containing a conductor such as tantalum nitride or titanium nitride. The conductor 24 may be a laminate of tungsten, molybdenum, copper, etc. The conductive film that becomes 0 is formed by sputtering, CVD, MBE, PLD or AL. This can be done using Method D or the like.

[0233] Next, a CMP process is performed to remove the conductive film that will become the conductor 240a and the conductor 240b. A portion of the conductive film is removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By this, it is possible to form the conductors 240a and 240b having flat upper surfaces ( (See FIG. 1.) Note that the CMP process may remove a portion of the insulator 281. .

[0234] A method for manufacturing an opening in the semiconductor device shown in FIG. 3 will be described below. The insulators 273, 280, 282, 274 and 281 are electrically conductive. An opening is formed that reaches the body 242a and the conductor 242b.

[0235] Next, a conductive film that will become the conductor 244 (conductor 244a and conductor 244b) is formed. The conductive film that becomes the conductor 244 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. The conductive film that becomes the conductor 244 is an insulating film. The thickness of the film parallel to the bottom surface of 224 is thicker than the thickness of the film parallel to the side of the opening. For example, a low pressure long throw sputtering method, a collimator sputtering method, etc. Sputtering method, or ionization sputtering (unbalanced magnet sputtering The film can be formed by using a method such as a photolithography method.

[0236] Next, the conductive film that will become the conductor 244 is subjected to isotropic etching. Thus, the conductive film that will become the conductor 244 in the portion parallel to the side of the opening is removed, and the bottom of the insulator 224 is The conductive film that becomes the conductor 244 in the portion parallel to the surface is left to form the conductor 244.

[0237] Next, an insulating film that will become the insulator 241 (insulator 241a and insulator 241b) is formed. The insulating film that becomes the insulator 241 can be formed by a sputtering method, a CVD method, an MBE method, or a PLD method. In this embodiment, the ALD method is used. An aluminum oxide film is formed.

[0238] Next, the insulating film that will become the insulator 241 is anisotropically etched to form the bottom of the insulator 224. The insulating film that will be the insulator 241 in the portion parallel to the surface is removed, and the insulator in the portion parallel to the side of the opening is removed. The insulating film that will become 241 is left to form the insulator 241 .

[0239] In the anisotropic etching of the insulating film that becomes the insulator 241, the conductor 244 is etched. It is preferable that the conductor 244 functions as an etching stopper. This reduces damage during anisotropic etching (physical damage and charging damage). This is preferable because it can prevent the image from reaching the conductor 242. The anisotropic etching of the insulating film is performed under the etching conditions in which the conductor 244 is hardly etched. Specifically, when the etching rate of the conductor 244 is taken as 1, the insulating The etching rate of the insulating film that becomes the insulator 241 is preferably 5 or more. The maximum number is 10 or more.

[0240] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water and hydrogen. It is preferable to use a laminated structure containing a conductor such as tantalum nitride or titanium nitride. The conductor 24 may be a laminate of tungsten, molybdenum, copper, etc. The conductive film that becomes 0 is formed by sputtering, CVD, MBE, PLD or AL. This can be done using Method D or the like.

[0241] Next, a CMP process is performed to remove the conductive film that will become the conductor 240a and the conductor 240b. A portion of the conductive film is removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By this, it is possible to form the conductors 240a and 240b having flat upper surfaces ( (See FIG. 3.) Note that the CMP process may remove a part of the insulator 281. The above is the method for manufacturing the opening of the semiconductor device shown in FIG.

[0242] Next, a conductive film that will become the conductor 246 is formed on the insulator 281 and the conductor 240. The conductive film that becomes the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. The method can be carried out by using the ALD method or the like.

[0243] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 240a. The conductor 246a contacts the upper surface of the conductor 240b, and the conductor 246b contacts the upper surface of the conductor 240b. (See Figure 1.)

[0244] Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 6 to 17, the semiconductor device can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment mode. In this manner, the transistor 200 can be manufactured.

[0245] According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated is provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0246] <Modifications of the semiconductor device> In the following, the above-mentioned <Configuration Example of Semiconductor Device> will be described with reference to FIGS. 19 and 20. Regarding an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, explain.

[0247] FIG. 19A is a top view of a semiconductor device including a transistor 200. 9(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 19(A), FIG. 19(C) is a cross-sectional view of the stadium 200 in the channel length direction. FIG. 3 is a cross-sectional view of a portion indicated by a dashed line A3-A4 in a channel width direction of the transistor 200. In addition, in the top view of FIG. 19(A), some elements are shown in order to clarify the drawing. It is omitted in the illustration.

[0248] In the semiconductor device shown in FIG. 19 and FIG. 20, The same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device (see FIG. 1). do.

[0249] The configuration of the transistor 200 will be described below with reference to FIG. The materials used for the constituents of the sta 200 are those described in detail in <Configuration Example 1 of the Semiconductor Device>. It is possible.

[0250] The transistor 200 shown in FIG. 19 is different from the transistor 200 shown in FIG. 19. In the transistor 200 shown in FIG. For example, the oxide 230 may be doped with an element that can increase the carrier density and reduce the resistance. By adding as a punt, the region 231 (region 231a and region 231b) It is sufficient to form the following.

[0251] The region 231 (region 231a and region 231b) is formed by adding the above-mentioned elements to the oxide 230b. Region 231 is formed by adding a dummy gate. It can be formed by:

[0252] Specifically, an insulating film that becomes the insulator 272 is formed on the insulator 224 and the oxide 230b. A dummy gate is provided on the insulating film that will become the insulator 272, and the dummy gate is used as a mask. It is preferable to add an element that reduces the resistance of the oxide 230b. However, the element is added to the region that does not overlap with the dummy gate, and a region 231 is formed. The method of adding the element is to add the ionized source gas by mass separation. and ion doping, in which ionized source gas is added without mass separation. , plasma immersion ion implantation, etc. can be used.

[0253] Representative elements that reduce the resistance of the oxide 230b include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas elements, etc. are used. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon. The concentration of the elements is measured by secondary ion mass spectrometry (SIMS). If we use ondary ion mass spectrometry, good.

[0254] In particular, boron and phosphorus are used in the manufacturing process of amorphous silicon or low-temperature polysilicon. This is preferable because existing equipment can be used. Existing facilities can be repurposed. Capital investment can be reduced.

[0255] Next, an insulator is formed on the oxide 230b, the insulating film that becomes the insulator 272, and the dummy gate. An insulating film serving as 273 may be formed.

[0256] Next, an insulating film that will become the insulator 280 is provided on the insulating film that will become the insulator 273, and then the insulator 28 CMP (Chemical Mechanical Polishing) is applied to the insulating film that becomes 0. g) By performing a process, a part of the insulating film that will become the insulator 280 is removed, so that the insulator 28 Then, when removing the dummy gate, the dummy gate is removed. A part of the insulating film that will become the insulator 272 in contact with the port is also removed to form the insulator 272. The insulator 273 is exposed on the side of the opening provided in the edge 280, and the insulator 273 is exposed on the bottom surface of the opening. A portion of region 231 provided in oxide 230b is exposed.

[0257] After this, the above-mentioned manufacturing method of the semiconductor device can be referred to. In addition, the other configurations of the semiconductor device and The effect can be seen in reference to the semiconductor device shown in FIG.

[0258] FIG. 20A is a top view of a semiconductor device including a transistor 200. FIG. 20B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. FIG. 20C is a cross-sectional view of the stadium 200 in the channel length direction. FIG. 7 is a cross-sectional view of a portion indicated by a dashed line A7-A8, which is electrically connected to the transistor 200. 2 is also a cross-sectional view in the channel width direction of the conductor 240b functioning as a plug. In the top view of FIG. 0(A), some elements are omitted for clarity.

[0259] The semiconductor device shown in FIG. 20 is electrically connected to a transistor 200 and functions as a plug. Conductor 240a and conductor 240b are in contact with the bottom of the conductive body 240. 44 (conductor 244a and conductor 244b) is the semiconductor device shown in FIG. This differs from the position.

[0260] As shown in FIG. 20B and FIG. 20C, the insulator 224, the insulator 272, the insulator 273, insulator 280, insulator 282, insulator 274, and the bottom of the opening of insulator 281 A conductor 244 is disposed on the

[0261] In addition, on the conductor 244, an insulator 241 (insulator 241a and insulator A first conductor of the conductor 240 is provided in contact with the side surface of the edge member 241b. Further inside, a second conductor of the conductors 240 is provided.

[0262] As shown in FIG. 20C, the insulator 224, the insulator 272, the insulator 273, and the insulator 28 0, the size of the openings provided in the insulators 282, 274, and 281 is the oxide It is preferable that the width of the oxide 230a and the width of the oxide 230b in the channel width direction are larger than that of the oxide 230a and the oxide 230b in the channel width direction. At the bottom of the mouth, the top surface of the oxide 230b, the side surface of the oxide 230b, and the oxide 230 Therefore, the conductor 244 is exposed on the top surface of the oxide 230b, the side surface of the oxide 230b, Since the side of the oxide 230a contacts the side of the oxide 230a, the contact resistance can be reduced. Other configurations and effects can be seen in the semiconductor device shown in FIG. come.

[0263] The configurations, structures, methods, etc. described in this embodiment may be the same as those described in other embodiments. , and the like can be used in appropriate combination.

[0264] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0265] [Storage device 1] FIG. 21 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention. The memory device shown in FIG. 1 includes a transistor 200, a transistor 300, and a capacitor 100. The transistor 200 is provided above the transistor 300, and the capacitor 100 is The transistor 300 is provided above the transistor 200. The transistor 200 may be the transistor 200 described in the previous embodiment. can.

[0266] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0267] In the semiconductor device shown in FIG. 21, a wiring 1001 is electrically connected to the source of a transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0268] In addition, the memory device shown in FIG. 21 has a memory cell array arranged in a matrix. It can be configured.

[0269] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 functioning as a gate electrode. 16, an insulator 315 acting as a gate insulator, a semiconductor region consisting of a portion of a substrate 311 313, and a low resistance region 314a which functions as a source region or a drain region, The transistor 300 may be a p-channel or n-channel type. Either a filter type or a filter panel type may be used.

[0270] Here, the transistor 300 shown in FIG. 21 has a semiconductor region 313 ( A part of the substrate 311 has a convex shape. The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may be used. Since it uses a protruding part, it is also called a FIN type transistor. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. Here, a case where a protrusion is formed by processing a part of a semiconductor substrate is shown, but a SOI substrate is also processed. A semiconductor film having a convex shape may be formed by the above-mentioned method.

[0271] Note that the transistor 300 shown in FIG. 21 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0272] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. a conductor 110 serving as the first electrode, a conductor 120 serving as the second electrode, and and an insulator 130 that functions as a dielectric.

[0273] In addition, for example, the conductor 112 and the conductor 110 provided on the conductor 245 are formed at the same time. Note that the conductor 112 can be used for the capacitor 100, the transistor 200, and has a function as a plug or wiring that is electrically connected to the transistor 300 .

[0274] In FIG. 21, the conductor 112 and the conductor 110 are shown to have a single-layer structure. However, the present invention is not limited to this, and may be a laminated structure of two or more layers. For example, Conductors that have barrier properties between weak conductors and those with high electrical conductivity have good adhesion to conductors with high electrical conductivity. may form a highly conductive material.

[0275] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrogen Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium The conductive layer may be formed as a laminate or a single layer.

[0276] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, or a material with high dielectric strength. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, so that it can ensure sufficient capacitance. By using an insulator having a large dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0277] In addition, oxide is an insulator for high dielectric constant (high-k) materials (materials with a high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium an oxide having silicon and hafnium, an oxide nitride having silicon and hafnium, or an oxide nitride having silicon and hafnium Nitrides containing fluorine.

[0278] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon oxide, silicon nitride, silicon nitride, silicon oxide with added fluorine, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, vacancy-containing silicon oxide Examples include concrete or resin.

[0279] <Wiring layer> Between each structure, a wiring layer is provided in which an interlayer film, wiring, plugs, etc. are provided. Also, a plurality of wiring layers may be provided according to the design. Conductors having functions as wiring or wiring are collectively given the same reference numerals. In addition, in the present specification and the like, the wiring and the plug electrically connected to the wiring may be the same. That is, when a part of the conductor functions as a wiring, or when the conductor In some cases, part of the plug may function as a plug.

[0280] For example, an insulator 320, an insulator 322, and an insulator 323 are provided on the transistor 300 as an interlayer film. The edge member 324 and the insulator 326 are laminated in this order. The insulators 322, 324, and 326 are connected to the capacitive element 100 or the transistor. A conductor 328 and a conductor 330 are embedded in the conductive layer 200. The conductor 328 and the conductor 330 function as plugs or wiring.

[0281] In addition, the insulator that functions as an interlayer film acts as a flattening film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be chemically mechanically polished ( The surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0282] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In the insulating layer 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0283] Similarly, the insulators 210, 212, 214, and 216 are each provided with a conductive The conductive material 218 and the conductive material that constitutes the transistor 200 are embedded. The body 218 may be a plug or a capacitor that is electrically connected to the capacitor element 100 or the transistor 300. Furthermore, on the conductor 120 and the insulator 130, an insulating layer is formed. A rim 150 is provided.

[0284] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0285] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0286] For example, the insulators 150, 212, 352, and 354 have relatively low resistance. It is preferable to use an insulator with a low dielectric constant. For example, the insulator may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon Silicon oxide doped with oxygen, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies The insulator preferably comprises silicon or resin, or silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine , silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. It is preferable that the insulating layer has a laminated structure of silicon oxide and a resin. Silicon oxynitride is thermally stable, so by combining it with resin, The laminated structure can have a low dielectric constant. Examples of the resin include polyester and Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Examples include plastic or acrylic.

[0287] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulator 210, the insulator 350, etc., do not contain impurities such as hydrogen and Insulators having a function of suppressing the permeation of oxygen may be used.

[0288] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon oxide nitride, silicon nitride, etc. can be used. .

[0289] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as arsenic, A silicide such as nickel silicide may also be used.

[0290] For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1 12, etc., may be a metal material, an alloy material, a metal nitride material, or the like formed from the above-mentioned materials. Conductive materials such as metal oxide materials can be used in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that is also electrically conductive. It is preferable to use tungsten. Alternatively, low resistance conductive materials such as aluminum and copper can be used. It is preferable to form the wiring from a low-resistance conductive material. can be done.

[0291] <Wiring or plug of layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In this case, the insulator having the excess oxygen region and an insulator having a barrier property is provided between the conductor and the insulator having the excess oxygen region. It is preferable to provide such a function.

[0292] For example, in FIG. 21, an insulating layer is formed between an insulator 224 having excess oxygen and a conductor 245. The insulator 276, the insulator 222, the insulator 272, and the insulator 273 may be provided. 73, the insulator 224 and the transistor 200 are in contact with each other. The insulator 276 can be sealed by using an insulating material having a sealing property. It is preferable that the insulating layer 280 is in contact with the insulating layer 280. By adopting such a structure, the diffusion of oxygen and impurities is prevented. This can further suppress dispersion.

[0293] In other words, by providing the insulator 276, the excess oxygen contained in the insulator 224 is absorbed by the conductor 24 In addition, the insulator 276 can prevent impurities from being absorbed by the insulator 276. The hydrogen, which is a substance, is prevented from diffusing into the transistor 200 via the conductor 245. It is possible.

[0294] The insulator 276 is made of a material that suppresses the diffusion of impurities such as water or hydrogen, and oxygen. It is advisable to use an insulating material that has the function of providing insulation. For example, aluminum oxide or hafnium oxide is In addition, for example, magnesium oxide, gallium oxide, etc. , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Metal oxides such as tantalum oxide or tantalum oxide, silicon oxide nitride or silicon nitride, etc. can be used.

[0295] The above is a description of the configuration example. By using this configuration, In a semiconductor device using a transistor, the fluctuation of electrical characteristics is suppressed and the reliability is improved. Alternatively, a transistor including an oxide semiconductor having a large on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. do.

[0296] [Storage device 2] FIG. 22 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention. The memory device shown in FIG. 2 includes the transistor 200, the transistor 300, and the capacitor In addition to the semiconductor device having the capacitor 100 , a transistor 400 is also included.

[0297] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source and the diode. The source of the transistor 400 is connected to the second gate of the transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 400 are In the transistor 400, the second gate voltage and the first gate voltage are set to 0 V. The drain current at 0V is very small, so the transistor 200 and the transistor Even if the power supply to the transistor 400 is not provided, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows the transistor 200 and the transistor 40 A memory device that has 0 can retain its contents for a long period of time.

[0298] Therefore, in FIG. 22, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is The back gate of the transistor 300 is electrically connected to the back gate of the transistor 200. The gate and the other of the source and drain of the transistor 200 are connected to the capacitor element 100. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the gate of the transistor 400. The wiring 1010 is electrically connected to the back gate of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and wiring 1009 are electrically connected.

[0299] 22 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. 0 can control the second gate voltages of the plurality of transistors 200. It is preferable to provide fewer transistors 400 than transistors 200.

[0300] <Transistor 400> Transistor 400 is formed in the same layer as transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. Conductor 465 and conductor 460 (conductor 460a and conductor 460b) functioning together a conductor 405 serving as a second gate electrode; and an insulating layer 406 serving as a gate insulating layer. The insulating layer 222, the insulating layer 224, and the insulating layer 450 are formed of an oxide having an area in which a channel is to be formed. The oxide 430c, the conductor 442a functioning as either the source or the drain, and the oxide 4 32a, and oxide 432b, and conductor 4 serving as the other of the source or drain. 42b, oxide 431a, and oxide 431b, and conductor 440 (conductor 440a, and conductor 440b).

[0301] In the transistor 400, the conductor 405 is the same layer as the conductor 205. 431a and oxide 432a are the same layers as oxide 230a, and oxide 431b, The oxide 432b is the same layer as the oxide 230b. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 465 is the same layer as the conductor 26 5. Conductor 460 is the same layer as conductor 260.

[0302] It should be noted that structures formed in the same layer can be formed simultaneously. For example, oxide 4 The oxide film 30c can be formed by processing the oxide film 230C.

[0303] The oxide 430c that functions as the active layer of the transistor 400 is the same as the oxide 230, etc. Similarly, oxygen vacancies are reduced, and impurities such as hydrogen and water are reduced. The threshold voltage of the transistor 400 is set to be greater than 0 V to reduce the off-current and to provide a second gate. The drain current when the first gate voltage and the first gate voltage are 0 V can be made very small. Cut.

[0304] <Dicing line> In the following, a large-area substrate is divided into individual semiconductor elements to produce multiple semiconductor devices. Dicing lines (scribe lines, dividing lines) are provided when extracting chips. The following describes the method of cutting the wire. First, grooves (dicing lines) for dividing the semiconductor elements are formed on the substrate, and then the dicing In some cases, the substrate is cut at a grinding line and divided (divided) into a plurality of semiconductor devices.

[0305] Here, for example, as shown in FIG. 22, the area where the insulator 272 and the insulator 222 contact each other It is preferable to design the dicing line so that the A memory cell having a dicing layer 200 and a transistor 400 on the outer edge of the memory cell. An opening is provided in the insulator 224 near the region to be in-line. An insulator 272 is provided to cover the

[0306] That is, the insulator 222 and the insulator 272 are connected to each other through the opening provided in the insulator 224. For example, insulator 222 and insulator 272 are made of the same material and by the same method. The insulator 222 and the insulator 272 may be formed of the same material and by the same method. For example, it is preferable to use aluminum oxide. I wish.

[0307] With this structure, the insulator 222 and the insulator 272 are insulated from the insulator 224 and the transistor 200, and the transistor 400 can be encapsulated. The body 272 has a function of suppressing the diffusion of oxygen, hydrogen, and water. The substrate is divided into a plurality of circuit regions each having a semiconductor element formed thereon, as shown in FIG. Even if the substrate is processed into a chip, impurities such as hydrogen or water may enter from the side of the cut substrate, causing the chip to break down. Diffusion into the transistor 200 and the transistor 400 can be prevented.

[0308] In addition, this structure allows excess oxygen in the insulator 224 to migrate to the insulators 272 and 222. Therefore, the excess oxygen in the insulator 224 can be prevented from diffusing out of the insulator 224. The oxide on which the channel of the transistor 200 or the transistor 400 is formed is The oxygen is supplied to the transistor 200 or the transistor 400. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel of the transistor 200 or 400 is formed is made defect-free. It is possible to obtain an oxide semiconductor having a low potential density and stable characteristics. The present invention suppresses the fluctuation of the electrical characteristics of the transistor 200 or the transistor 400 and improves reliability. It can be raised.

[0309] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0310] (Embodiment 3) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 23 and 24. Transistors used as conductors (hereinafter sometimes referred to as OS transistors) and capacitive elements This section describes a storage device to which the OS is applied (hereinafter, sometimes referred to as an OS memory device). The OS memory device includes at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. The off-state current of the OS transistor is extremely small, so The memory device has excellent retention characteristics and can function as a non-volatile memory.

[0311] <Storage device configuration example> FIG. 23A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1 411, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 142 0, column circuit 1430, output circuit 1440, and control logic circuit 1460.

[0312] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, and write The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying the data signal read from the memory cell. The above wiring is connected to the memory cells of the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal. RDATA is output to the outside of the memory device 1400. For example, the memory device may have a row decoder, a word line driver circuit, etc., and may select a row to be accessed. do.

[0313] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 11, and the high power supply voltage (VIL) for the memory cell array 1470. The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The decoder and column decoder are input to the data decoder, and WDATA is input to the write circuit.

[0314] The control logic circuit 1460 processes external input signals (CE, WE, RE). It processes the CLKIN pin to generate the row decoder or column decoder control signals. CE is the chip enable pin. WE is the write enable signal, and RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these. Instead, other input signals can be processed to control the row and / or column decoders, as required. A control signal may be generated.

[0315] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the recell MC, the number of memory cells MC in one row, etc.

[0316] In FIG. 23A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. Although an example of forming the insulating film on a surface has been shown, the present embodiment is not limited to this. For example, as shown in FIG. 23B, the memory cell array 1411 is provided on a part of the peripheral circuit 1411. 70 may be provided so as to overlap the memory cell array 1470. For example, In this way, a sense amplifier may be provided.

[0317] FIG. 24 illustrates an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0318] [DOSRAM] 24A to 24C show examples of circuit configurations of memory cells in a DRAM. In this study, a DRAM using a memory cell of one OS transistor and one capacitor element type is called DOSRA. M(Dynamic Oxide Semiconductor Random Acc The memory cell 1471 shown in FIG. The transistor M1 has a gate (sometimes called a front gate) and a back gate.

[0319] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0320] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low-level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the transistor The threshold voltage of M1 can be increased or decreased.

[0321] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. In addition, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 14 shown in FIG. As shown in FIG. 73, a transistor M1 having a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a transistor M1.

[0322] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This means that the leakage current of the transistor M1 can be made very low. The frequency of memory cell refresh can be reduced by using resistor M1 for long-term retention. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very low, the memory cells 1471, 1472, The memory cell 1473 can hold multi-level data or analog data.

[0323] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0324] [NOSRAM] FIG. 24(D) to (H) show a gain cell type memory cell having two transistors and one capacitor. A memory cell 1474 shown in FIG. The transistor M2 is a front-side transistor M3 and a capacitance element CB. The gate (sometimes simply referred to as a gate) and the back gate. The transistor M2 has a gain cell type memory cell. The storage device is NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called vector RAM.

[0325] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0326] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0327] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell shown in FIG. 1476, the transistor M2 has a single gate structure, i.e., it does not have a back gate. Alternatively, the memory cell may be configured with a transistor M2 that does not include the transistor M1. MC is a memory cell 1477 shown in FIG. 24(G) that has a wiring WBL and a wiring RBL. The wiring BIL may be arranged as one wiring.

[0328] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as M2, and the transistor 300 is used as M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very low. This allows the written data to be held for a long time by the transistor M2. This reduces the frequency of refreshing the memory cells. In addition, the memory cell refresh operation can be eliminated. Since the resistance is extremely low, multi-value data or analog data can be stored in the memory cell 1474. The same is true for memory cells 1475 to 1477.

[0329] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. In some cases, the field effect mobility is higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as the By using a Si transistor for transistor M3, a transistor Since the memory cell can be provided with a transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0330] The transistor M3 may be an OS transistor. When OS transistors are used, the memory cell array 1470 is configured with only n-type transistors. A circuit can be constructed using the same.

[0331] FIG. 24(H) shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 24(H) includes transistors M4 to M6 and a capacitor The memory cell 1478 has a capacitance element CC. The capacitance element CC is provided as appropriate. Electrically connected to L, RWL, WWL, BGL, and GNDL. Wire GNDL is a wiring for applying a low-level potential. , may be electrically connected to the wirings RBL and WBL.

[0332] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0333] The transistors M5 and M6 are n-channel Si transistors or p-channel Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 is circuited using only n-type transistors. A path can be constructed.

[0334] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor 200 is used as the transistor M4, and the transistors M5 and M6 are the transistors 300. The capacitance element CC can be a capacitance element 100. By using an OS transistor as the gate driver, the leakage current of transistor M4 is made very low. It can be made easier.

[0335] Note that the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are The configuration is not limited to the above. The arrangement or functions of lines, circuit elements, etc. may be changed, deleted, or added as necessary. stomach.

[0336] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0337] (Embodiment 4) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. An example of the chip 1200 is shown. A plurality of circuits (systems) are implemented on the chip 1200. The technology of integrating multiple circuits (systems) onto a single chip is called system-on-chip (SCC). This is sometimes called System on Chip (SoC).

[0338] As shown in FIG. 25A, the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing a memory controller 1212, one or more analog arithmetic units 1213, controller 1214, one or more interfaces 1215, one or more networks It has a work circuit 1216 and the like.

[0339] The chip 1200 is provided with bumps (not shown), and as shown in FIG. Printed Circuit Board (PCB) 1201 No. 1 The first surface of the PCB 1201 is connected to the second surface of the PCB 1202. 1203 is provided and connected to the motherboard 1203 .

[0340] The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0341] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. becomes possible.

[0342] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0343] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit and a digital / analog conversion circuit. The multiply-and-accumulate circuit may be provided in the

[0344] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0345] The interface 1215 includes a display device, a speaker, a microphone, a camera, a The controller has an interface circuit for connecting to external devices such as a Such interfaces include computers, mobile phones, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) There can be.

[0346] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0347] The above circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering process, and the chip 1200 can be produced at low cost.

[0348] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a DRAM 122 1, and the motherboard 1203 on which the flash memory 1222 is provided is a GPU module. It can be called module 1204.

[0349] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, its excellent image processing capabilities make it a smart device. Phones, tablet devices, laptop PCs, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep Neural Networks (DNNs), Convolutional Neural Networks (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can perform operations such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0350] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0351] (Embodiment 5) In this embodiment mode, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is used in, for example, various electronic devices (e.g., Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (e.g., D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 26 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a format and used in various storage devices and removable memory.

[0352] FIG. 26A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0353] FIG. 26(B) is a schematic diagram of the external appearance of an SD card, and FIG. 26(C) is a schematic diagram of the inside of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, the substrate 11 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, The capacity can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 1113. This allows the host device and the SD card 1110 to wirelessly communicate with each other. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0354] FIG. 26(D) is a schematic diagram of the external appearance of the SSD, and FIG. 26(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing 54, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0355] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible.

[0356] (Embodiment 6) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 27 shows a processor such as a CPU or a GPU according to an embodiment of the present invention. Specific examples of electronic devices equipped with the chip are given below.

[0357] <Electronic equipment and systems> A GPU or chip according to an embodiment of the present invention can be installed in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Personal computers, computer monitors, digital signage tal Signage, large game machines such as pachinko machines, etc. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos, Examples of the optical fiber include frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Furthermore, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, It is possible to equip child devices with artificial intelligence.

[0358] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. And if it has a secondary battery, the antenna may be used for contactless power transmission.

[0359] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Numbers, distance, light, liquids, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) It may have.

[0360] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar Functions such as displaying date or time, running various software (programs) a function to read out a program or data recorded on a recording medium; It can have functions, etc. FIG. 27 shows an example of an electronic device.

[0361] [mobile phone] FIG. 27(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551. It is provided at 0.

[0362] The information terminal 5500 uses artificial intelligence by applying the chip according to one embodiment of the present invention. It can run applications that use artificial intelligence. For example, an application that recognizes a conversation and displays the conversation content on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. The application to be displayed on the display unit 5511 and the application to perform biometric authentication such as fingerprint or voiceprint are displayed. Applications, etc.

[0363] [Information terminal] FIG. 27B shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. The present invention has a first embodiment and a second embodiment.

[0364] The desktop information terminal 5300 is similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop 5300, it is possible to develop new artificial intelligence.

[0365] In the above, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Fig. 27(A) and (B), One aspect of the present invention can also be applied to information terminals other than smartphone information terminals. Examples of information terminals other than desktop information terminals include PDAs (Personal Digital Assistants). sonal Digital Assistant), notebook type information terminal, workstation Examples include sion.

[0366] [electric appliances] FIG. 27(C) shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The refrigerator 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, etc. do.

[0367] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, The Electric Freezer Refrigerator 5800 is a refrigerator that can store food and drink. It also has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients, and the ... It can also have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0368] In this example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water servers, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0369] [Game consoles] FIG. 27(D) shows a portable game machine 5200, which is an example of a game machine. The computer 5200 includes a housing 5201, a display unit 5202, a button 5203, and the like.

[0370] By applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, It is possible to realize a portable game machine 5200 with low power consumption. In addition, the low power consumption allows: Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and This reduces the impact on the modules.

[0371] Furthermore, by applying a GPU or chip according to one embodiment of the present invention to the portable game machine 5200, This makes it possible to realize a portable game machine 5200 having artificial intelligence.

[0372] Originally, the game progress, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 520 By applying artificial intelligence to 0, it is possible to express things in ways that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, the characters that appear in the game, This makes it possible to express things such as a person's behavior changing as they change.

[0373] In addition, when playing a game that requires multiple players on the portable game machine 5200, the artificial intelligence This allows you to create anthropomorphic game players, so you can make your opponents artificially intelligent. By making the game a game player, you can play the game by yourself.

[0374] In FIG. 27(D), a portable game machine is illustrated as an example of a game machine. The game machine to which the GPU or chip of the present invention is applied is not limited to this. Examples of game machines that apply PU or chips include home game machines, Arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), sports facilities Examples include pitching machines for batting practice that will be installed in the stadium.

[0375] [Mobile object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the area around the driver's seat of the automobile. Can be applied to edges.

[0376] FIG. 27(E1) shows an automobile 5700 as an example of a moving object, and FIG. 27(E2) shows an automobile FIG. 27(E2) is a diagram showing the area around the windshield in the interior of a vehicle. The display panels 5701, 5702, and 5703 are attached to the board. Also shown is a pillar mounted display panel 5704.

[0377] The display panels 5701 to 5703 display a speedometer, a tachometer, It provides various information by displaying the distance traveled, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be customized by the user. It can be changed as needed to suit your taste, making it possible to enhance the design. The panels 5701 to 5703 can also be used as lighting devices.

[0378] The display panel 5704 displays images from an imaging device (not shown) installed in the automobile 5700. By projecting images, it is possible to compensate for blind spots that are blocked by pillars. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, This can compensate for blind spots and increase safety. By doing so, the driver can check for safety more naturally and without feeling uneasy. 4 can also be used as a lighting device.

[0379] The GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the 5700 automobile. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0380] In the above description, an automobile is used as an example of a moving object. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, etc.) These include drones, unmanned aerial vehicles (drones), airplanes, and rockets. Applying the chip of one embodiment of the present invention to a moving object and providing a system using artificial intelligence can be done.

[0381] [Broadcasting System] The GPU or chip according to one embodiment of the present invention can be applied to a broadcasting system.

[0382] FIG. 27(F) shows a schematic diagram of data transmission in a broadcasting system. Specifically, FIG. 27(F) shows how radio waves (broadcast signals) transmitted from a broadcasting station 5680 are received by televisions in each home. The diagram shows the path of the signal until it reaches the TV receiving device (TV) 5600. A broadcast signal received by an antenna 5650 is transmitted to the receiving device (not shown). The signal is then transmitted to the TV5600 via the

[0383] In FIG. 27(F), the antenna 5650 is a UHF (Ultra High Frequency) The antenna shown is a BS 110°CS Antennas and CS antennas can also be applied.

[0384] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with the Na5650, you can watch terrestrial TV broadcasts with the TV5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 27(F), but may be any other broadcasting system. It may also be satellite broadcasting using an industrial satellite, data broadcasting via optical fiber lines, or the like.

[0385] The above-mentioned broadcasting system applies the chip according to one embodiment of the present invention to broadcast programs using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is turned on, the broadcast data is compressed, and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be improved. In motion compensation prediction, which is one of the methods, the recognition of display patterns contained in the displayed image It is also possible to perform intraframe prediction using artificial intelligence. For example, low-resolution broadcast data is received and the high-resolution TV5600 displays that broadcast data. When displaying the image, the decoder restores the broadcast data by performing up-conversion, etc. Image interpolation can be performed.

[0386] The AI-based broadcasting system described above is expected to be useful in the future, as the amount of broadcast data increases. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0387] In addition, as an application of artificial intelligence on the TV5600 side, for example, A recording device having the above-mentioned function may be provided. By having artificial intelligence learn the user's preferences, the system can automatically record programs that match the user's preferences. It is possible to draw

[0388] Electronic device described in the present embodiment, functions of the electronic device, application examples of artificial intelligence, and effects thereof etc. can be appropriately combined with the descriptions of other electronic devices.

[0389] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments. is possible. [Explanation of symbols]

[0390] 100: Capacitive element, 110: Conductor, 112: Conductor, 120: Conductor, 130 : insulator, 150: insulator, 200: transistor, 205: conductor, 205a : conductor, 205b: conductor, 210: insulator, 212: insulator, 214: insulator Edge, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 2 24A: insulating film, 230: oxide, 230a: oxide, 230A: oxide film, 23 0b: Oxide, 230B: Oxide film, 230c: Oxide, 230C: Oxide film, 23 1: Region, 231a: Region, 231b: Region, 232B: Oxide film, 240: Conductive conductor, 240a: conductor, 240b: conductor, 241: insulator, 241a: insulator body, 241b: insulator, 242: conductor, 242a: conductor, 242A: conductive film , 242b: conductor, 242B: conductor layer, 244: conductor, 244a: conductor , 244b: conductor, 246: conductor, 246a: conductor, 246b: conductor, 250: insulator, 250A: insulating film, 260: conductor, 260a: conductor, 26 0Aa: Conductive film, 260Ab: Conductive film, 260b: Conductor, 265: Conductor, 2 65A: Conductive film, 265B: Conductor, 272: Insulator, 272A: Insulating film, 27 3: Insulator, 273A: Insulating film, 274: Insulator, 275: Insulator, 275A: Insulating film, 275B: insulator, 276: insulator, 280: insulator, 281: insulation body, 282: insulator, 300: transistor, 311: substrate, 313: semiconductor region region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: Conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator, 354: Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 430c: oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: Oxide, 440: conductor, 440a: conductor, 440b: conductor, 442a: Conductor, 442b: Conductor, 450: Insulator, 460: Conductor, 460a: Conductor body, 460b: conductor, 1001: wiring, 1002: wiring, 1003: wiring, 1 004: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring, 1009: Wiring, 1010: Wiring

Claims

[Claim 1] forming a first insulator on a substrate; forming a first oxide film and a first conductive film in this order on the first insulator; processing the first oxide film and the first conductive film to form a first oxide and a first conductive layer; forming a first insulating film and a second insulating film in sequence over the first oxide and the first conductive layer; A planarization process is performed to planarize the surface of the second insulating film; forming an opening through which the first oxide is exposed in the first conductive layer, the first insulating film, and the second insulating film to form a first conductor, a second conductor, and a second insulator; A second oxide film and a third insulating film are formed; forming a second conductive film such that the thickness of the second conductive film at the bottom of the opening is greater than the thickness of the second conductive film at the side of the opening; etching the second conductive film located on the side of the opening so that the second conductive film located on the bottom of the opening remains; A third insulating film is formed; anisotropically etching the third insulating film; A third conductive film is formed; A method for manufacturing a semiconductor device, comprising: performing a planarization treatment to remove the second oxide film, the third insulating film, the second conductive film, and the third conductive film until a part of the second insulating film is exposed, thereby forming a second oxide, a third insulator, a third conductor, and a fourth conductor.

Images