Image sensor

Abstract

To provide an image sensor including a smaller pixel while securing a dynamic range.SOLUTION: An image sensor includes a first semiconductor substrate 100 including first and second pixel regions PR1, PR2, a first photoelectric conversion element PD1 provided in the first pixel region, a second photoelectric conversion element PD2 provided in the second pixel region, first and second floating diffusion regions FD1, FD2a provided in the first and second pixel regions, respectively, a first transfer gate electrode TG1 disposed between the first photoelectric conversion element and the first floating diffusion region, a second transfer gate electrode TG2 disposed between the second photoelectric conversion element and second floating diffusion region, a second semiconductor substrate 200 on the first semiconductor substrate, and a plurality of pixel transistors connected to the first and second photoelectric conversion elements. A width of the second photoelectric conversion element is smaller than a width of the first photoelectric conversion element. At least a part of the pixel transistors is provided on the second semiconductor substrate.SELECTED DRAWING: Figure 5A

Description

[Technical field]

[0001] The present invention relates to image sensors, and more particularly to image sensors having smaller sized pixels while maintaining a high dynamic range. [Background technology]

[0002] The image sensor converts the optical image into an electrical signal. As the computer and communication industries continue to develop, the demand for image sensors with improved performance is increasing in various fields, including digital cameras, video cameras, PCS (Personal Communication Systems), game consoles, security cameras, and medical micro cameras. Image sensors include charge coupled devices (CCDs) and CMOS image sensors.

[0003] Among these, CMOS image sensors have a simple driving method and can integrate signal processing circuits on a single chip, making it possible to miniaturize products. CMOS image sensors also have very low power consumption, making them easy to apply to products where battery capacity is limited. In addition, CMOS image sensors can be used interchangeably with CMOS process technology, which reduces manufacturing costs. Therefore, the use of CMOS image sensors is rapidly increasing as higher resolutions become possible with technological development. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 11,600,651 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems with conventional image sensors, and an object of the present invention is to provide an image sensor that ensures a dynamic range and has smaller pixel sizes. [Means for solving the problem]

[0006] In order to achieve the above object, an image sensor according to the present invention includes a first semiconductor substrate including a first pixel region and a second pixel region, a first photoelectric conversion element provided in the first pixel region, a second photoelectric conversion element provided in the second pixel region, a first floating diffusion region provided in the first pixel region, a second floating diffusion region provided in the second pixel region, a first transfer gate electrode disposed between the first photoelectric conversion element and the first floating diffusion region, a second transfer gate electrode disposed between the second photoelectric conversion element and the second floating diffusion region, a second semiconductor substrate on the first semiconductor substrate, and a plurality of pixel transistors connected to the first and second photoelectric conversion elements, wherein a width of the second photoelectric conversion element is smaller than a width of the first photoelectric conversion element, and at least a portion of the pixel transistors are provided on the second semiconductor substrate.

[0007] In order to achieve the problem to be solved, an image sensor according to an embodiment of the present invention includes a photoelectric conversion circuit layer including first and second photoelectric conversion elements provided on a first semiconductor substrate, a pixel circuit layer including a second semiconductor substrate and disposed on the photoelectric conversion circuit layer, and a logic circuit layer including a logic circuit disposed on the pixel circuit layer and provided on a third semiconductor substrate, the photoelectric conversion circuit layer including a dual conversion gain transistor DCX provided on the first semiconductor substrate and connected between a first floating diffusion region and a third floating diffusion region, a source follower transistor SF provided on the first semiconductor substrate and connected to the first floating diffusion region, the first photoelectric conversion circuit layer including a first photoelectric conversion element, a second photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, a fourth photoelectric conversion element, a fourth photoelectric conversion element, a fifth photoelectric conversion element, a fifth photoelectric conversion element, a sixth photoelectric conversion element, a fifth photoelectric conversion element, a sixth photoelectric conversion element, a seventh ... the pixel circuit layer includes a first transfer gate electrode TG1 disposed between the second photoelectric conversion element and the first floating diffusion region, and a second transfer gate electrode TG2 disposed between the second photoelectric conversion element and the second floating diffusion region, the pixel circuit layer includes a reset transistor RX provided on the second semiconductor substrate and connected to the third floating diffusion region, a first switching transistor SG1 provided on the second semiconductor substrate and connected to the dual conversion gain transistor, and a second switching transistor SG2 provided on the second semiconductor substrate and connected to the second floating diffusion region, and a width of the second photoelectric conversion element is smaller than a width of the first photoelectric conversion element.

[0008] In order to achieve the problem to be solved, an image sensor according to an embodiment of the present invention includes a photoelectric conversion circuit layer including first and second photoelectric conversion elements provided on a first semiconductor substrate, a pixel circuit layer including a second semiconductor substrate and disposed on the photoelectric conversion circuit layer, and a logic circuit layer including a logic circuit disposed on the pixel circuit layer and provided on a third semiconductor substrate, the photoelectric conversion circuit layer including a first transfer gate electrode disposed between the first photoelectric conversion element and a first floating diffusion region and a second transfer gate electrode disposed between the second photoelectric conversion element and a second floating diffusion region, the pixel circuit layer is provided on the second semiconductor substrate and includes a transfer gate electrode between the first floating diffusion region and a third floating diffusion region, a double conversion gain transistor DCG connected between the first floating diffusion region and the source follower transistor SF provided on the second semiconductor substrate, a reset transistor RX provided on the second semiconductor substrate and connected to the third floating diffusion region, a first switching transistor SG1 provided on the second semiconductor substrate and connected to the double conversion gain transistor, a second switching transistor SG2 provided on the second semiconductor substrate and connected to the second floating diffusion region, and a third switching transistor SG3 provided on the second semiconductor substrate and connected to the source follower transistor and the first floating diffusion region, wherein a width of the second photoelectric conversion element is smaller than a width of the first photoelectric conversion element. Effect of the Invention

[0009] According to the image sensor of the present invention, pixel transistors can be separately arranged on a first semiconductor substrate and a second semiconductor substrate, and a high dynamic range (HDR) can be ensured by the first and second transfer gate electrodes and some of the pixel transistors arranged on the first semiconductor substrate, and in addition, the size of the unit pixel can be reduced by arranging some of the pixel transistors on the second semiconductor substrate. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 2A] 1 is a schematic exploded perspective view of an image sensor according to an embodiment of the present invention; [Figure 2B] 1 is a schematic exploded perspective view of an image sensor according to an embodiment of the present invention; [Figure 3A] 2 is a circuit diagram illustrating a unit pixel of a pixel array according to an embodiment of the present invention. [Figure 3B] 2 is a circuit diagram illustrating a unit pixel of a pixel array according to an embodiment of the present invention. [Figure 4A] 3B is a plan view illustrating an example of a unit pixel having the circuit diagram shown in FIG. 3A. [Figure 4B] 3C is a plan view illustrating an example of a unit pixel having the circuit diagram shown in FIG. 3B. [Figure 5A] 1 is a partial cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 5B] FIG. 11 is a partial cross-sectional view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 5C] FIG. 11 is a partial cross-sectional view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 6] FIG. 11 is a partial cross-sectional view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 7] FIG. 2 is a partial plan view of an image sensor according to an embodiment of the present invention. [Figure 8] 4 is a timing diagram illustrating an operation of an image sensor according to an embodiment of the present invention. [Figure 9A] 1 is a partial cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. [Figure 9B] 1 is a partial cross-sectional view showing a schematic configuration of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, a specific example of an embodiment of an image sensor according to the present invention will be described with reference to the drawings. Like reference numbers refer to like elements throughout this specification.

[0012] FIG. 1 is a schematic block diagram of an image sensor according to an embodiment of the present invention. Referring to FIG. 1, the image sensor includes an active pixel sensor array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog to digital converter (ADC) 7, and an input / output buffer 8.

[0013] The active pixel sensor array 1 includes a plurality of unit pixels arranged two-dimensionally, and converts an optical signal into an electrical signal. The active pixel sensor array 1 is driven by a number of drive signals, such as a pixel select signal, a reset signal, and a charge transfer signal, from a row driver 3 . The converted electrical signal is also provided to a correlated double sampler 6 . The row driver 3 provides a plurality of driving signals to the active pixel sensor array 1 for driving a plurality of unit pixels according to the result decoded by the row decoder 2 . When the unit pixels are arranged in a matrix, a drive signal is provided for each row.

[0014] A timing generator 5 provides timing and control signals to the row decoder 2 and the column decoder 4 . The correlated double sampler 6 receives, holds, and samples the electrical signals generated by the active pixel sensor array 1 . The correlated double sampler 6 double samples a specific noise level and a signal level of an electrical signal, and outputs a level corresponding to the difference between the noise level and the signal level. The analog-to-digital converter 7 converts the analog signal corresponding to the level output from the correlated double sampler 6 into a digital signal and outputs it. The input / output buffer 8 latches the digital signals, and outputs the latched signals to a video signal processor (not shown) in sequence according to the results of decoding by the column decoder 4 .

[0015] 2A and 2B are schematic exploded perspective views of an image sensor according to an embodiment of the present invention. Referring to FIG. 2A, the image sensor includes a sensor chip C1 and a logic chip C2. The sensor chip C1 converts an image from an external object into an electrical signal or a data signal. The sensor chip C1 includes the pixel array (see 1 in FIG. 1) previously described with reference to FIG. That is, the sensor chip C1 includes a plurality of unit pixels, and each of the unit pixels includes a photoelectric conversion circuit 10P and a pixel circuit 20P as previously described with reference to FIGS. 2A and 2B.

[0016] The sensor chip C1 includes a pixel array region R1 and a pad region R2. The pixel array region R1 includes a plurality of unit pixels two-dimensionally arranged along a first direction D1 and a second direction D2 intersecting each other. An electrical signal generated by incident light is output from each unit pixel of the pixel array region R1. The pixel array region R1 includes a light receiving region AR and a light blocking region OB. The light-shielding area OB surrounds the light-receiving area AR in a plan view. In other words, the light-shielding areas OB are disposed above, below, to the left and right of the light-receiving area AR in a plan view. A reference pixel to which no light is incident is provided in the light-shielding region OB, and the amount of charge sensed at a unit pixel of the light-receiving region AR is compared with the amount of reference charge generated at the reference pixel to calculate the size of the electrical signal sensed at the unit pixel.

[0017] A plurality of conductive pads CP used for inputting and outputting control signals, photoelectric signals, etc. are arranged in the pad region R2. The pad region R2 surrounds the pixel array region R1 in a plan view so as to facilitate electrical connection with external elements. The conductive pad CP inputs and outputs an electric signal generated in the unit pixel to and from an external device. The sensor chip C1 includes a photoelectric conversion circuit layer 10, a pixel circuit layer 20, and a light transmitting layer (not shown). From a vertical perspective, the pixel circuit layer 20 is disposed between the photoelectric conversion circuit layer 10 and the light-transmitting layer. In addition, the pixel circuit layer 20 is adjacent to the logic chip C2. The sensor chip C1 includes pixel transistors, and the pixel transistors are arranged separately in a photoelectric conversion circuit layer 10 and a pixel circuit layer 20. However, without being limited thereto, the pixel transistors may be disposed only in the pixel circuit layer 20 .

[0018] In detail, the photoelectric conversion circuit layer 10 includes a first semiconductor substrate (not shown) and a photoelectric conversion circuit 10P. The photoelectric conversion circuit 10P includes first and second transfer transistors (not shown), and may additionally include some pixel transistors provided on a first semiconductor substrate. The photoelectric conversion circuits 10P are arranged two-dimensionally along a first direction D1 and a second direction D2 that intersect with each other. Pixel circuit layer 20 includes a second semiconductor substrate (not shown) and pixel circuits 20P. The pixel circuits 20P include at least some pixel transistors provided on a second semiconductor substrate, and are provided corresponding to the photoelectric conversion circuits 10P, respectively.

[0019] The logic chip C2 includes a logic circuit (see reference numerals 2, 3, 4, 5, 6, 7, and 8 in FIG. 1), a power supply circuit, an input / output interface, and / or an image signal processor. That is, the logic chip C2 includes components other than the pixel array 1 in the image sensor of FIG. The logic chip C2 includes, for example, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler 6, an analog-to-digital converter 7, and an input / output buffer 8. The logic chip C2 includes a logic pad area R3 corresponding to the pad area R2 of the sensor chip C1. In logic pad region R3, a plurality of conductive pads CP used for inputting and outputting control signals are arranged. The conductive pads CP of the sensor chip C1 are electrically connected to the conductive pads CP of the logic chip C2. The logic chip C2 is bonded to the sensor chip C1 so as to be adjacent to the pixel circuit layer 20 of the sensor chip C1.

[0020] Referring to FIG. 2B, the image sensor includes a first chip C1a including photoelectric conversion circuits 10P of a plurality of unit pixels, a second chip C1b including pixel circuits 20P of a plurality of unit pixels, and a logic chip C2. The first chip C1a includes a pixel array region R1 and a pad region R2, and the pixel array region R1 includes a light receiving region AR and a light blocking region OB. The first chip C1a includes photoelectric conversion circuits 10P of a plurality of unit pixels. The photoelectric conversion circuits 10P are two-dimensionally arranged along a first direction D1 and a second direction D2 that intersect with each other in the pixel array region R1.

[0021] The second chip C1b includes pixel circuits 20P of a plurality of unit pixels. The pixel circuits 20P are provided corresponding to the respective photoelectric conversion circuits 10P. The second chip C1b includes conductive pads CP corresponding to the conductive pads CP of the first chip C1a. The conductive pads CP of the first chip C1a are electrically connected to the conductive pads CP of the second chip C1b. As described above, the logic chip C2 may include logic circuits (see reference numerals 2, 3, 4, 5, 6, 7, and 8 in FIG. 1), a power supply circuit, an input / output interface, and / or an image signal processor. The conductive pads CP of the logic chip C2 are electrically connected to the conductive pads CP of the second chip C1b.

[0022] 3A and 3B are circuit diagrams illustrating a unit pixel of a pixel array according to an embodiment of the present invention. Referring to FIG. 3A, a unit pixel UP includes a photoelectric conversion circuit 10P and a pixel circuit 20P. The photoelectric conversion circuit 10P includes first and second photoelectric conversion elements (PD1, PD2), first and second transfer transistors (TX1, TX2), a dual conversion gain transistor (DCX), a source follower transistor (SF), and first to third floating diffusion regions (FD1, FD2, FD3).

[0023] The pixel circuit 20P includes a selection transistor (SX), a reset transistor (RX), first and second switching transistors (SW1, SW2, i.e., switching elements), a capacitor (CFD, i.e., charge storage element), and second and third floating diffusion regions (FD2, FD3). The first and second photoelectric conversion elements (PD1, PD2), the first and second transfer transistors (TX1, TX2), the dual conversion gain transistor DCX, and the source follower transistor SF included in the photoelectric conversion circuit 10P are provided on a first semiconductor substrate (not shown). Meanwhile, the selection transistor SX, the reset transistor RX, the first and second switching transistors SW1, SW2, and the capacitor CFD included in the pixel circuit 20P are provided on a second semiconductor substrate (not shown).

[0024] In this embodiment, each unit pixel is disclosed as including six pixel transistors (RX, DCX, SF, SX, SW1, SW2), but the present invention is not limited thereto, and the number of pixel transistors may be changed. In detail, the first and second photoelectric conversion elements (PD1, PD2) generate and accumulate electric charges corresponding to incident light. The first and second photoelectric conversion elements (PD1, PD2) may be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0025] The first transfer transistor TX1 transfers the charge stored in the first photoelectric conversion element PD1 to the first floating diffusion region FD1. The second transfer transistor TX2 transfers the charge stored in the second photoelectric conversion element PD2 to the second floating diffusion region FD2. The charge generated in the second photoelectric conversion element PD2 is accumulated (or stored) in the capacitor CFD when the second transfer transistor TX2 is turned on. The first and second transfer transistors (TX1, TX2) are controlled by first and second transfer signals (TG1, TG2). The first floating diffusion region FD1 receives and cumulatively stores the charges generated in the first photoelectric conversion element PD1. The source follower transistor SF is controlled according to the amount of photocharges stored in the first floating diffusion region FD1.

[0026] The first switching transistor SW1 is connected between the second floating diffusion region FD2 and the third floating diffusion region FD3. The first switching transistor SW1 varies the capacitance of the first floating diffusion region FD1 in response to a first switching signal SG1, thereby varying the conversion gain of the unit pixel UP. The second switching transistor SW2 is coupled between the capacitor CFD (ie, the charge storage element) and the second floating diffusion region FD2. The second switching transistor SW2 varies the capacitance of the second floating diffusion region FD2 in response to a second switching signal SG2, thereby varying the conversion gain of the unit pixel UP.

[0027] The capacitor CFD is connected between the second floating diffusion region FD2 and the pixel power supply voltage VDD. More specifically, the capacitor CFD is connected between the second switching transistor SW2 and the pixel power supply voltage VDD. For example, the capacitor CFD may be a Metal-Oxide-Semiconductor (MOS) capacitor, a Metal-Insulator-Semiconductor (MIS) capacitor, or a MIM capacitor. The capacitor CFD stores charges in response to the amount of charges generated by the second photoelectric conversion element PD2 and the operation of the second transfer transistor TX2.

[0028] The dual conversion gain transistor DCX is connected between the first floating diffusion region FD1 and the third floating diffusion region FD3. The dual conversion gain transistor DCX is connected in series with the reset transistor RX through a third floating diffusion region FD3. That is, the dual conversion gain transistor DCX is connected between the first floating diffusion region FD1 and the reset transistor RX. The dual conversion gain transistor DCX varies the capacitance of the first floating diffusion region FD1 in response to a dual conversion gain control signal DCG, thereby varying the conversion gain of the unit pixel.

[0029] The reset transistor RX periodically resets the charges stored in the first and third floating diffusion regions FD1 and FD3 in response to a reset signal RG applied to a reset gate electrode. In detail, the drain terminal of the reset transistor RX is connected to the third floating diffusion region FD3, and the source terminal is connected to the pixel power supply voltage VDD. That is, the reset transistor RX is connected to the pixel power supply voltage VDD and the dual conversion gain transistor DCX. When the reset transistor RX and the dual conversion gain transistor DCX are turned on, the pixel power voltage VDD is transferred to the first and third floating diffusion regions FD1 and FD3. Therefore, the charges stored in the first and third floating diffusion regions FD1 and FD3 are discharged, and the first and third floating diffusion regions FD1 and FD3 are reset.

[0030] In multiple pixels, charges generated by first and second photoelectric conversion elements (PD1, PD2) such as photodiodes are accumulated in first to third floating diffusion regions (FD1, FD2, FD3), and the charges accumulated in the first to third floating diffusion regions (FD1, FD2, FD3) are converted into voltages. At this time, the ratio at which the charge stored in the floating diffusion regions (FD1, FD2, FD3) is converted into a voltage can be referred to as the conversion gain, and the conversion gain can be varied according to the capacitance of the floating diffusion regions (FD1, FD2, FD3). Specifically, if the capacitance of the floating diffusion regions (FD1, FD2, FD3) increases, the conversion gain decreases, and if the capacitance of the floating diffusion regions (FD1, FD2, FD3) decreases, the conversion gain increases.

[0031] In an embodiment of the present invention, each of the pixels operates in a dual gain mode (dual conversion gain). The dual gain mode includes a first conversion gain mode (or low conversion gain (LCG)) and a second conversion gain mode (or high conversion gain (HCG)). In the second conversion gain mode, the rate at which charges are converted into voltages is higher than in the first conversion gain mode. That is, the second conversion gain mode is applied to the generation operation of a pixel signal corresponding to low illuminance.

[0032] Depending on the operation of the dual conversion gain transistor DCX, it can be operated in a first conversion gain mode and a second conversion gain mode. When the dual conversion gain transistor DCX is turned off, the capacitance of the first floating diffusion region FD1 is small and the unit pixel operates in the first conversion gain mode. When the dual conversion gain transistor DCX is turned on, the first floating diffusion region FD1 is connected to the second floating diffusion region FD2, and the capacitance of the first and second floating diffusion regions FD1 and FD2 increases. That is, when the dual conversion gain transistor DCX is turned on, the unit pixel operates in the second conversion gain mode. In other words, when the dual conversion gain transistor DCX is turned on, the capacitance of the first or second floating diffusion region (FD1 or FD2) increases and the conversion gain is decreased, and when the dual conversion gain transistor DCX is turned off, the capacitance of the first floating diffusion region FD1 decreases and the conversion gain is increased.

[0033] The first pixel signal to the fourth pixel signal generated through the dual conversion gain mode of each of the first and second photoelectric conversion elements PD1 and PD2 can be combined into one image, and the combined image has a high dynamic range. The source follower transistor SF may be a source follower buffer amplifier that generates a source-drain current in proportion to the amount of charge of the first floating diffusion region FD1 input to the source follower gate electrode. The source follower transistor SF amplifies the potential change at the floating diffusion region FD, and outputs the amplified signal to the output line Vout through the selection transistor SX. The source terminal of the source follower transistor SF is connected to a pixel power supply voltage VDD, and the drain terminal of the source follower transistor SF is connected to the source terminal of the selection transistor SX. The selection transistor SX selects a unit pixel P to be read out row by row. When the selection transistor SX is turned on by a selection signal SG applied to the selection gate electrode, the electrical signal output to the drain electrode of the source follower transistor SF is output to the output line Vout.

[0034] Referring to FIG. 3B, the photoelectric conversion circuit 10P includes first and second photoelectric conversion elements (PD1, PD2), first and second transfer transistors (TX1, TX2), and a first floating diffusion region FD1. The pixel circuit 20P includes a dual conversion gain transistor DCX, a source follower transistor SF, a selection transistor SX, a reset transistor (RX), first to third switching transistors (SW1, SW2, SW3) (i.e., switching elements), a capacitor CFD (i.e., charge storage element), and second and third floating diffusion regions (FD2, FD3).

[0035] The first and second transfer transistors (TX1, TX2) and the first and second photoelectric conversion elements (PD1, PD2) included in the photoelectric conversion circuit 10P are provided on a first semiconductor substrate (not shown). Meanwhile, the dual conversion gain transistor DCX, the source follower transistor SF, the selection transistor SX, the reset transistor RX, the first to third switching transistors (SW1, SW2, SW3), and the capacitor CFD included in the pixel circuit 20P are provided on a second semiconductor substrate (not shown). The unit pixel UP may further include a third switching transistor SW3 connected between the first floating diffusion region FD1 and the source follower transistor SF. The charge generated in the first photoelectric conversion element PD1 is stored in the source / drain terminal of the third switching transistor SW3. In this embodiment, each unit pixel is disclosed as including seven pixel transistors (RX, DCX, SF, SX, SW1, SW2, SW3), but the present invention is not limited thereto and the number of pixel transistors may be changed.

[0036] FIG. 4A is a plan view illustrating an example of a unit pixel having the circuit diagram shown in FIG. 3A, and FIG. 5A is a partial cross-sectional view illustrating a schematic configuration of the image sensor shown in FIGS. 3A and 4A. 3A, 4A and 5A, the image sensor includes a plurality of pixels UP, and each unit pixel UP includes first and second pixel areas PR1 and PR2. The first and second pixel regions (PR1, PR2) are two-dimensionally arranged according to rows and columns. Each of the first and second pixel regions (PR1, PR2) is surrounded by a pixel separating structure PIS in a plan view.

[0037] As an example, the first pixel region PR1, that is, the first photoelectric conversion element PD1, can have an octagonal shape in a plan view. The second pixel region PR2, that is, the second photoelectric conversion element PD2, may have a rectangular shape in a plan view and is adjacent to one of the side surfaces of the first pixel region PR1. The planar configuration of the first and second pixel regions PR1 and PR2 is not limited thereto and may be variously changed. A first transfer gate electrode TG1, a source follower transistor SF, and a dual conversion gain transistor DCX are disposed on the first pixel region PR1, and a second transfer gate electrode TG2 is disposed on the second pixel region PR2. That is, the first and second transfer gate electrodes (TG1, TG2), the source follower transistor SF, and the dual conversion gain transistor DCX are provided on a first semiconductor substrate 100, and the remaining pixel transistors are provided on a second semiconductor substrate 200.

[0038] According to an embodiment of the present invention, at least a portion of pixel transistors may be disposed on the second semiconductor substrate 200 rather than on the first semiconductor substrate 100, thereby reducing the size of the unit pixel UP. The length W1 of the unit pixel UP in the second direction D2 may be 2.4 μm or less, and preferably 2.1 μm or less. The length W1 of the unit pixel UP in the second direction D2 means the distance in the second direction D2 between vertices located at both ends along the second direction D2 within the unit pixel UP. For example, referring to FIG. 4A, the length W1 in the second direction D2 means the distance in the second direction D2 between the vertex PR1a (the point located at the lowest point in the second direction D2) of the first pixel region PR1 and the vertex PR2a (the point located at the highest point in the second direction D2) of the second pixel region PR2.

[0039] The first and second semiconductor substrates (100, 200) each have a first surface (100a, 200a) (or front surface) and a second surface (100b, 200b) (or back surface) facing each other. The first and second semiconductor substrates (100, 200) are substrates in which a first conductive type (e.g., p-type) epitaxial layer is formed on a first conductive type (e.g., p-type) bulk silicon substrate, and in the manufacturing process of the image sensor, the bulk silicon substrate is removed and only the p-type epitaxial layer remains. Alternatively, the first and second semiconductor substrates (100, 200) may be bulk semiconductor substrates including a well of a first conductivity type.

[0040] The pixel separating structure PIS is disposed in the first semiconductor substrate 100 and defines first and second pixel regions (PR1, PR2). A pixel separating structure PIS is provided in the first semiconductor substrate 100 between the first and second pixel regions (PR1, PR2). The pixel separating structure PIS surrounds each of the first and second pixel regions (PR1, PR2) in a plan view. As an example, the pixel separating structure PIS has a top surface that is substantially coplanar with the first surface 100 a of the first semiconductor substrate 100 . The pixel separating structure PIS extends from the first surface 100a to the second surface 100b.

[0041] The pixel separating structure PIS is formed by patterning the first surface 100a of the first semiconductor substrate 100 to form a deep trench, and then burying a liner insulating film and a semiconductor film doped with impurities in the deep trench. In this case, the width of the pixel separating structure PIS gradually decreases from the first surface 100a to the second surface 100b of the first semiconductor substrate 100. Alternatively, the width of the pixel separating structure PIS may be substantially the same on the first surface 100a and the second surface 100b of the first semiconductor substrate 100. Alternatively, the pixel separating structure PIS may be formed by patterning the second surface 100b of the first semiconductor substrate 100 to form a deep trench, and then burying a liner insulating film and an impurity-doped semiconductor film in the deep trench. In such a case, the width of the pixel separating structure PIS may gradually increase from the first surface 100a to the second surface 100b.

[0042] The pixel separating structure PIS is formed of an insulating material having a refractive index lower than that of the semiconductor substrate 100 (eg, silicon), and includes one or more insulating films. As an example, the pixel separating structure PIS includes a liner insulating pattern 111 , a semiconductor pattern 113 and a capping insulating pattern 115 . The semiconductor pattern 113 extends vertically through a portion of the first semiconductor substrate 100 , and a liner insulating pattern 111 is provided between the semiconductor pattern 113 and the first semiconductor substrate 100 . The capping insulating pattern 115 is disposed on the semiconductor pattern 113 and has an upper surface that is substantially coplanar with the first surface 100 a of the first semiconductor substrate 100 . The liner insulating pattern 111 and the capping insulating pattern 115 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer. The semiconductor pattern 113 may include an undoped polysilicon film or an impurity-doped polysilicon film. The semiconductor pattern 113 may include air gaps or voids.

[0043] As an example, the pixel separating structure PIS passes through the first semiconductor substrate 100 . The pixel separating structure PIS extends vertically from the first surface 100a to the second surface 100b of the first semiconductor substrate 100. In particular, the pixel separating structure PIS has a vertical length in a direction perpendicular to the surface of the first semiconductor substrate 100 , and the vertical length is substantially the same as the vertical thickness of the first semiconductor substrate 100 . As another example, the pixel separating structure PIS may extend vertically through a portion of the first semiconductor substrate 100 and be spaced apart from the second surface 100 b of the first semiconductor substrate 100 . The pixel separating structure PIS prevents photocharges generated by incident light incident on the first and second pixel regions PR1 and PR2 from flowing into adjacent first and second pixel regions PR1 and PR2 due to random drift. That is, the pixel separating structure PIS can prevent a crosstalk phenomenon between the first and second pixel regions PR1 and PR2 adjacent to each other.

[0044] According to the embodiment, a first photoelectric conversion element PD1 is provided in a first semiconductor substrate 100 in a first pixel region PR1. A second photoelectric conversion element PD2 is provided in the first semiconductor substrate 100 in a second pixel region PR2. Light incident from the outside is converted into an electric signal by the first and second photoelectric conversion elements (PD1, PD2). The first and second photoelectric conversion elements PD1 and PD2 are a semiconductor substrate 100 of a first conductivity type and an impurity region doped with impurities of an opposite second conductivity type (eg, n-type). The first semiconductor substrate 100 of the first conductivity type and the first and second photoelectric conversion elements (PD1, PD2) of the second conductivity type constitute a photodiode. That is, a photodiode is formed by a junction between a first semiconductor substrate 100 of a first conductivity type and the first or second photoelectric conversion element (PD1, PD2). The first and second photoelectric conversion elements (PD1, PD2) constituting a photodiode generate and accumulate photoelectric charges in proportion to the intensity of incident light.

[0045] In the embodiment, the light receiving area of ​​the first photoelectric conversion element PD1 is larger than the light receiving area of ​​the second photoelectric conversion element PD2. In other words, the volume of the first photoelectric conversion element PD1 is larger than the volume of the second photoelectric conversion element PD2. That is, the first and second photoelectric conversion elements (PD1, PD2) have substantially the same vertical depth, and the width of the first photoelectric conversion element PD1 is smaller than the width of the second photoelectric conversion element PD2. Each of the first and second photoelectric conversion elements (PD1, PD2) is surrounded by a pixel separating structure PIS in a plan view. Therefore, the photoelectric charges stored in the first and second photoelectric conversion elements (PD1, PD2) are prevented from overflowing to the adjacent first and second photoelectric conversion elements (PD1, PD2).

[0046] The device isolation layer 105 defines at least one active portion on the first surface 100a of the first semiconductor substrate 100 in each of the first and second pixel regions PR1 and PR2. An isolation layer 105 is disposed adjacent to the first surface 100a of the first semiconductor substrate 100 in each pixel region PR1, PR2. The lower surface of the element isolation film 105 is separated from the first and second photoelectric conversion elements (PD1, PD2). The isolation layer 105 is provided in a trench formed by recessing the first surface 100 a of the first semiconductor substrate 100 . The element isolation film 105 is made of an insulating material. For example, the isolation layer 105 may include a liner oxide layer and a liner nitride layer conformally covering the surface of the trench, and a buried oxide layer filling the trench in which the liner oxide layer and the liner nitride layer are formed. The upper surface of the element isolation film 105 is substantially coplanar with the first surface 100 a of the first semiconductor substrate 100 . Moreover, the upper surface of the element isolation film 105 is substantially coplanar with the upper surface of the pixel isolation structure PIS. That is, the upper surface of the isolation film 105 is substantially coplanar with the first surface 100 a of the first semiconductor substrate 100 .

[0047] The first semiconductor substrate 100 is provided with first and second transfer transistors (TX1, TX2), a source follower transistor SF, and a dual conversion gain transistor DCX of the photoelectric conversion circuit 10P. Accordingly, on the first surface 100a of the first semiconductor substrate 100, first and second transfer gate electrodes (TG1, TG2), a source follower gate electrode SFG, and a dual conversion gain gate electrode DCGE are provided. More specifically, a first transfer gate electrode TG1 is disposed on the first surface 100a of the first semiconductor substrate 100 in the first pixel region PR1. A first floating diffusion region FD1 is disposed on one side of the first transfer gate electrode TG1, and the first floating diffusion region FD1 is connected to the dual conversion gain transistor DCX. A dual conversion gain gate electrode DCGE is provided on a first surface 100a of the first semiconductor substrate 100, and first and second floating diffusion regions (FD1, FD2a) are disposed on either side of the dual conversion gain gate electrode DCGE.

[0048] A second transfer gate electrode TG2 is disposed on the first surface 100a of the semiconductor substrate 100 in the second pixel region PR2. A third floating diffusion region FD3a is disposed in the semiconductor substrate 100 on one side of the second transfer gate electrode TG2. The first and second transfer gate electrodes (TG1, TG2) partially overlap with the first and second photoelectric conversion elements (PD1, PD2), respectively, in a plan view. The first and second transfer gate electrodes (TG1, TG2) are disposed in a first semiconductor substrate 100. The first and second transfer gate electrodes TG1 and TG2 each include a lower portion inserted into the first semiconductor substrate 100 and an upper portion connected to the lower portion and protruding above the first surface 100a of the first semiconductor substrate 100. The lower portions of the first and second transfer gate electrodes TG1 and TG2 each penetrate a portion of the first semiconductor substrate 100 vertically. The bottom surfaces of the first and second transfer gate electrodes (TG1, TG2) are located at a different level from the first surface 100a of the first semiconductor substrate 100. A gate insulating film is interposed between the first and second transfer gate electrodes TG1 and TG2 and the first semiconductor substrate 100, respectively.

[0049] In the first pixel region PR1, a source follower gate electrode SFG is provided on the first surface 100a of the first semiconductor substrate 100. On both sides of the source follower gate electrode SFG, source / drain regions SDR are arranged. Second floating diffusion regions (FD2a, FD2b) are disposed in the first and second semiconductor substrates (100, 200), respectively. The second floating diffusion region FD2a disposed in the first semiconductor substrate 100 and the second floating diffusion region FD2b disposed in the second semiconductor substrate 200 are electrically connected to each other by a conductive line ML and a contact plug CT. Similarly, third floating diffusion regions (FD3a, FD3b) are also disposed in the first and second semiconductor substrates (100, 200), respectively. The third floating diffusion region FD3a disposed in the first semiconductor substrate 100 and the third floating diffusion region FD3b disposed in the second semiconductor substrate 200 are electrically connected to each other by a conductive line ML and a contact plug CT.

[0050] By arranging the dual conversion gain gate electrode DCGE and the source follower gate electrode SFG in the first semiconductor substrate 100, the first floating diffusion region FD1 is arranged only in the first semiconductor substrate 100, unlike the second and third floating diffusion regions (FD2a, FD2b, FD3a, FD3b). If the dual conversion gain transistor DCX is turned off, the image sensor operates in the first conversion gain mode (or high illumination mode). More specifically, charges generated in the first photoelectric conversion element PD1 are stored in the first floating diffusion region FD1, and the stored charges are transferred to the source follower gate electrode SFG through the contact plug CT and the conductive line ML. The source follower transistor SF generates a source-drain current in proportion to the amount of charge in the first floating diffusion region FD1 input to the source follower gate electrode SFG.

[0051] As an example, if the first floating diffusion region FD1 is also disposed in the second semiconductor substrate 200, a process is required to connect the first transfer gate electrode TG1 disposed in the first semiconductor substrate 100 and the first floating diffusion region FD1 disposed in the second semiconductor substrate 200 to a conductive line or a contact plug, etc. Therefore, the parasitic capacitance of the first floating diffusion region FD1 may become large, and the conversion gain value of the first conversion gain mode may become small. However, according to one embodiment of the present invention, the dual conversion gain transistor DCX is provided in the first semiconductor substrate 100, and the first floating diffusion region FD1 is disposed only in the first semiconductor substrate 100, thereby preventing an increase in the parasitic capacitance of the first floating diffusion region FD1.

[0052] The second semiconductor substrate 200 is provided with some of the pixel transistors (RX, SX, SW1, SW2). For example, the select transistor SX, the reset transistor RX, and the first and second switching transistors (SW1, SW2) of the pixel circuit 20P are provided on a second semiconductor substrate. Accordingly, on the first surface 200a of the second semiconductor substrate 200, a selection gate electrode SXG, a reset gate electrode RXG, and first and second switching gate electrodes SWG1, SWG2 are provided.

[0053] First and second interlayer insulating films (110, 210) are disposed on the first and second semiconductor substrates (100, 200), respectively, and the first and second interlayer insulating films (110, 210) cover the pixel transistors (RX, DCX, SF, SX, SW1, SW2) or the first and second transfer gate electrodes (TG1, TG2), respectively. For example, the first interlayer insulating film 110 covers the first surface 100a of the first semiconductor substrate 100, and covers the first and second transfer gate electrodes TG1 and TG2, the source follower gate electrode SFG, and the dual conversion gain gate electrode DCGE. The second interlayer insulating film 210 covers the first surface 200a of the second semiconductor substrate 200, and covers the select gate electrode SXG, the reset gate electrode RXG, and the first and second switching gate electrodes (SWG1, SWG2).

[0054] A conductive line ML, a contact plug CT, a first and second bonding pads BP1, BP2, and a capacitor CAP are disposed in the first and second interlayer insulating films 110, 210. The conductive lines ML are connected to the contact plugs CT in the first and second interlayer insulating films (110, 210). As an example, the conductive lines ML and the contact plugs CT may include a metal such as tungsten, copper, aluminum, or an alloy thereof. The first bonding pad BP1 is disposed on the top of a first interlayer insulating film 110 located on the first semiconductor substrate 100, and the second bonding pad BP2 is disposed on the top of a second interlayer insulating film 210 located on the second semiconductor substrate 200. The first and second interlayer insulating films (110, 210) are in contact with each other, and the first bonding pad BP1 disposed on the top of the first interlayer insulating film 110 is in contact with the second bonding pad BP2 disposed on the top of the second interlayer insulating film 210.

[0055] The first and second bonding pads BP1, BP2 are connected to the first and second transfer gate electrodes TG1, TG2, the floating diffusion regions FD1, FD2a, FD2b, FD3a, FD3b, and the source / drain regions SDR through contact plugs CT and conductive lines ML. The first and second bonding pads (BP1, BP2) are electrically connected to each other, so that the third floating diffusion region FD3a arranged on the first semiconductor substrate 100 and the third floating diffusion region FD3b arranged on the second semiconductor substrate 200 are electrically connected to each other. Similarly, the second floating diffusion region FD2a arranged in the first semiconductor substrate 100 and the second floating diffusion region FD2b arranged in the second semiconductor substrate 200 are electrically connected to each other.

[0056] The first bonding pad BP1 and the second bonding pad BP2 are directly and electrically connected to each other by a hybrid bonding method. Hybrid bonding refers to a bond in which two components containing the same material fuse at their interface. For example, if the first and second bonding pads (BP1, BP2) are made of copper (Cu), they are physically and electrically connected by copper (Cu)-copper (Cu) bonding. Furthermore, the surface of the first interlayer insulating film 120 of the photoelectric conversion layer 10 and the surface of the second interlayer insulating film 220 of the pixel circuit layer 20 are joined by dielectric-dielectric bonding.

[0057] Referring to FIG. 5A, the capacitor CAP is disposed in a second interlayer insulating film 210. The capacitor CAP is the capacitor (CFD in FIGS. 3A and 3B) connected between the second switching transistor SW2 and the pixel power supply voltage VDD as described above with reference to FIGS. 3A and 3B. That is, the capacitor CAP may be a MOS (Metal-Oxide-Semiconductor) capacitor, a MIS (Metal-Insulator-Semiconductor) capacitor, or a MIM capacitor. One side of the capacitor CAP is connected to the source / drain region SDR of the second switching transistor SW2. Although not shown in FIG. 5A, the other side of the capacitor CAP is connected to the pixel power supply voltage (VDD in FIG. 3A).

[0058] Next, a planar insulating film 310 covers the second surface 100b of the first semiconductor substrate 100. The planar insulating film 310 may be made of a transparent insulating material and may include multiple layers. The planar insulating film 310 is made of an insulating material having a refractive index different from that of the first semiconductor substrate 100 . The planar insulating film 310 may include a metal oxide and / or a silicon oxide. A grating structure 320 is disposed on the planar insulating film 310 .

[0059] The grid structure 320 has a grid shape in a plan view, similar to the pixel separating structure PIS. The grid structure 320 overlaps with the pixel separating structure PIS in a plan view. That is, the lattice structure 320 includes a first portion extending in a first direction D1 and a second portion extending in a second direction D2 across the first portion. The width of the grid structure 320 is substantially the same as or smaller than the minimum width of the pixel separating structure PIS. The grating structure 320 may include conductive patterns and / or low refractive patterns. The conductive pattern may include a metallic material such as, for example, titanium, tantalum, or tungsten. The low refractive index pattern may be made of a material having a lower refractive index than the conductive pattern. The low refractive index pattern may be made of organic material and has a refractive index of about 1.1 to 1.3. For example, the grating structure 320 can be a polymer layer impregnated with silica nanoparticles.

[0060] A protective film 330 covers the surface of the grating structure 320 on the flat insulating film 310 with a substantially uniform thickness. The protective film 330 may include, for example, a single film or multiple films of at least one of an aluminum oxide film and a silicon oxycarbide film. A color filter 340 is formed corresponding to each unit pixel UP. That is, the first and second pixel regions PR1 and PR2 of each unit pixel UP share one color filter. The first and second photoelectric conversion elements (PD1, PD2) convert the light that has passed through the single color filter 340 into an electrical signal. The color filter 340 fills the space defined by the grid structure 320 . The color filter 340 may include a red, green, or blue color filter, or a magenta, cyan, or yellow color filter, depending on the unit pixel. As another example, the color filter 340 may partially include a white color filter or an infrared filter.

[0061] A microlens 350 is disposed above the color filter 340 . The microlens 350 has a convex shape and a predetermined radius of curvature. The microlenses 350 are made of a light-transmitting resin. A microlens 350 is disposed on the color filter 340 corresponding to each of the first and second pixel regions (PR1, PR2). Since the sum of the light receiving areas of the first photoelectric conversion elements PD1 is larger than the light receiving area of ​​the second photoelectric conversion elements PD2, the area of ​​the microlens 350 disposed on the first photoelectric conversion elements PD1 is larger than the area of ​​the microlens disposed on the second photoelectric conversion elements PD2. The radius of curvature of the microlens 350 disposed above the first photoelectric conversion element PD1 may be different from the radius of curvature of the microlens disposed above the second photoelectric conversion element PD2.

[0062] 5B and 5C are partial cross-sectional views showing a schematic configuration of an image sensor according to another embodiment of the present invention. For the sake of simplicity, the description of the same technical features as those of the image sensor previously described with reference to FIGS. 3A, 4A, and 5A will be omitted, and only differences will be described. 3A and 5B, first and second capacitors CAP1 and CAP2 are disposed in first and second interlayer insulating films 110 and 210, respectively. For example, the first capacitor CAP1 is disposed in the first interlayer insulating film 110, and the second capacitor CAP2 is disposed in the second interlayer insulating film 210.

[0063] A first electrode CAP2_a of the second capacitor CAP2 is connected to the source / drain region SDR of the second switching transistor SW2. Although not shown in FIG. 5B, the second electrode (CAP2_b) of the second capacitor CAP2 is connected to the pixel power supply voltage VDD. The first capacitor CAP1 and the second capacitor CAP2 are electrically connected in parallel to each other. For example, a first electrode (CAP1_a) of the first capacitor CAP1 and a first electrode (CAP2_a) of the second capacitor CAP2 are electrically connected through a contact plug CT, a conductive line ML, and first and second bonding pads (BP1, BP2). Similarly, the second electrode (CAP1_b) of the first capacitor CAP1 and the second electrode (CAP2_b) of the second capacitor CAP2 are electrically connected through the contact plug CT, the conductive line ML, and the first and second bonding pads (BP1, BP2). According to an embodiment of the present invention, even if the size of the first and second capacitors (CAP1, CAP2) becomes smaller as the size of the unit pixel UP becomes smaller, the total capacitor capacitance can be secured by arranging the first and second capacitors (CAP1, CAP2) in parallel connection.

[0064] Referring to FIG. 5C, a source follower gate electrode SFG, a dual conversion gain gate electrode DCGE, and first and second transfer gate electrodes TG1, TG2 are provided on a first surface 100a of a first semiconductor substrate 100. The first interlayer insulating film 110 is disposed on the first surface 100a of the first semiconductor substrate and covers the source follower gate electrode SFG, the dual conversion gain gate electrode DCGE, and the first and second transfer gate electrodes (TG1, TG2). The first interlayer insulating film 110 is disposed under the second semiconductor substrate 200 and is in contact with a second surface 200 b of the second semiconductor substrate 200 . A selection gate electrode SXG, a reset gate electrode RXG, and first and second switching gate electrodes SWG1 and SWG2 are provided on a first surface 200a of the second semiconductor substrate 200.

[0065] The second interlayer insulating film 210 covers the first surface 200a of the second semiconductor substrate, and covers the select gate electrode SXG, the reset gate electrode RXG, and the first and second switching gate electrodes (SWG1, SWG2). The first and second surfaces (200a, 200b) of the second semiconductor substrate 200 are covered by first and second interlayer insulating films (110, 210), respectively. The capacitor CAP is disposed in the second interlayer insulating film 210, but is not limited to this. For example, the capacitor CAP may be disposed in the first interlayer insulating film 110 and may be electrically connected to the source / drain region SDR through the conductive line ML, the contact plug CT, and the through plug TP.

[0066] The through plug TP penetrates the second semiconductor substrate 200 . A part of the through plug TP is disposed in the second interlayer insulating film 210 on the second semiconductor substrate 200 and the first interlayer insulating film 110 on the first semiconductor substrate 100 . The through plug TP is connected to the conductive line ML and the contact plug CT. The floating diffusion regions (FD2a, FD2b, FD3a, FD3b) and the source / drain regions SDR in the first and second semiconductor substrates (100, 200) are electrically connected by through plugs TP, conductive lines ML, and contact plugs CT. The via plug TP may include a metal such as, for example, tungsten, copper, aluminum, or an alloy thereof.

[0067] The through insulation pattern TIP surrounds the sidewall of the through plug TP. That is, the through insulation pattern TIP is disposed between the through plug TP and the second semiconductor substrate 200. An upper surface of the through insulation pattern TIP is coplanar with the first surface 200 a of the second semiconductor substrate 200 , and a lower surface of the through insulation pattern TIP is coplanar with the second surface 200 b of the second semiconductor substrate 200 . The through insulation pattern TIP may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The second floating diffusion region FD2a arranged in the first semiconductor substrate 100 is electrically connected to the second floating diffusion region FD2b arranged in the second semiconductor substrate 200 through a conductive line ML, a contact plug CT, and a through plug TP. Similarly, the third floating diffusion region FD3a arranged in the first semiconductor substrate 100 is electrically connected to the third floating diffusion region FD3b arranged in the second semiconductor substrate 200 via a conductive line ML, a contact plug CT, and a through plug TP.

[0068] Next, an image sensor according to another embodiment of the present invention will be described with reference to FIGS. 3B, 4B, and 6. FIG. However, for the sake of simplicity, a description of the same technical features as those of the image sensor previously described with reference to FIGS. 3A, 4A, and 5A will be omitted, and only differences will be described. Fig. 4B is a plan view illustrating an example of a unit pixel having the circuit diagram shown in Fig. 3B Fig. 6 is a partial cross-sectional view of the image sensor shown in Figs. 3B and 4B.

[0069] 3B, 4B and 6, the image sensor includes a plurality of unit pixels UP, and each unit pixel UP includes first and second pixel areas PR1 and PR2. The first and second pixel regions (PR1, PR2) are two-dimensionally arranged according to rows and columns. Each of the first and second pixel regions (PR1, PR2) is surrounded by a pixel separating structure PIS in a plan view. On the first semiconductor substrate 100, first and second transfer transistors (TX1, TX2) of the photoelectric conversion circuit 10P are provided. Accordingly, first and second transfer gate electrodes TG1 and TG2 are provided on the first surface 100a of the first semiconductor substrate 100.

[0070] More specifically, a first transfer gate electrode TG1 is disposed on the first surface 100a of the first semiconductor substrate 100 in the first pixel region PR1. A first floating diffusion region FD1a is disposed on one side of the first transfer gate electrode TG1. The first floating diffusion regions (FD1a, FD1b) are disposed in the first and second semiconductor substrates (100, 200), respectively. A first floating diffusion region FD1a arranged in the first semiconductor substrate 100 and a first floating diffusion region FD1b arranged in the second semiconductor substrate 200 are connected to each other by a conductive line ML, a contact plug CT, and first and second bonding pads (BP1, BP2). A second transfer gate electrode TG2 is disposed on the first surface 100a of the semiconductor substrate 100 in the second pixel region PR2. A third floating diffusion region FD3a is disposed in the semiconductor substrate 100 on one side of the second transfer gate electrode TG2.

[0071] The third floating diffusion regions (FD3a, FD3b) are disposed in the first and second semiconductor substrates (100, 200), respectively. The third floating diffusion region FD3a arranged in the first semiconductor substrate 100 and the third floating diffusion region FD3b arranged in the second semiconductor substrate 200 are connected to each other by a conductive line ML, a contact plug CT, and first and second bonding pads (BP1, BP2). The second semiconductor substrate 200 is provided with pixel transistors (DCX, SF, RX, SX, SW1, SW2, and SW3). For example, the dual conversion gain transistor DCX, the source follower transistor SF, the selection transistor SX, the reset transistor RX, and the first to third switching transistors (SW1, SW2, SW3) of the pixel circuit 20P are provided on a second semiconductor substrate. Therefore, on the first surface 200a of the second semiconductor substrate 200, a dual conversion gain gate electrode DCGE, a source follower gate electrode SFG, a select gate electrode SXG, a reset gate electrode RXG, and first to third switching gate electrodes (SWG1, SWG2, SWG3) are provided.

[0072] According to another embodiment of the present invention, the pixel transistors (DCX, SF, RX, SX, SW1, SW2, and SW3) may be disposed on the second semiconductor substrate 200 instead of the first semiconductor substrate 100. Therefore, only the first and second transfer transistors TX1 and TX2 are disposed on the first semiconductor substrate 100, and the size of the unit pixel UP can be further reduced. For example, the length W2 of the unit pixel UP in the second direction D2 is 2.4 μm or less, and preferably 1.8 μm or less. The length W2 of the unit pixel UP in the second direction D2 means the distance in the second direction D2 between vertices located at both ends along the second direction D2 within the unit pixel UP.

[0073] For example, referring to FIG. 4B, the length W2 in the second direction D2 means the distance in the second direction D2 between the vertex PR1a of the first pixel region PR1 (the point located at the lowest end in the second direction D2) and the vertex PR2a of the second pixel region PR2 (the point located at the highest end in the second direction D2). However, by disposing both the dual conversion gain transistor DCX and the source follower transistor SF on the second semiconductor substrate 200, the first floating diffusion regions (FD1a, FD1b) are disposed on the first and second semiconductor substrates (100, 200), respectively. Therefore, the first floating diffusion region FD1a arranged on the first semiconductor substrate 100 and the first floating diffusion region FD1b arranged on the second semiconductor substrate 200 are connected to the conductive line ML and the contact plug CT. That is, since only the first and second transfer transistors TX1 and TX2 can be disposed on the first semiconductor substrate 100, the pixel size can be further reduced compared to the above-described embodiment.

[0074] FIG. 7 is a partial plan view of an image sensor according to an embodiment of the present invention. With reference to FIG. 7, each of the first photoelectric conversion elements (PD1R, PD1G, PD1B) has an octagonal shape in a plan view. Each of the first photoelectric conversion elements (PD1R, PD1G, PD1B) has a first width in the first direction D1. The first width is the width measured at the first surface 100 a of the semiconductor substrate 100 . Additionally, the first width corresponds to the spacing between portions of the pixel separating structures PIS.

[0075] Each of the second photoelectric conversion elements (PD2R, PD2G, PD2B) has a rectangular shape in a plan view. The size of the second photoelectric conversion elements (PD2R, PD2G, PD2B) is smaller than the size of the first photoelectric conversion elements (PD1R, PD1G, PD1B). In other words, the light receiving area of ​​the second photoelectric conversion elements (PD2R, PD2G, PD2B) is smaller than the light receiving area of ​​the first photoelectric conversion elements (PD1R, PD1G, PD1B). For example, each of the second photoelectric conversion elements (PD2R, PD2G, PD2B) has a second width in the first direction D1 that is smaller than the first width. Herein, the width relationship of two given components is compared in the same direction and at the same vertical level.

[0076] Each of the multiple second photoelectric conversion elements (PD2R, PD2G, PD2B), that is, the second pixel region PR2, is surrounded by four adjacent first photoelectric conversion elements (PD1R, PD1G, PD1B) in a plan view. The second photoelectric conversion elements (PD2R, PD2G, PD2B) are arranged two-dimensionally along a first direction D1 and a second direction D2 in a plan view. The first photoelectric conversion elements (PD1R, PD1G, PD1B) and the second photoelectric conversion elements (PD2R, PD2G, PD2B) are alternately arranged along a first diagonal direction D3 and a second diagonal direction D4. The second photoelectric conversion elements (PD2R, PD2G, PD2B) are disposed between the first photoelectric conversion elements (PD1R, PD1G, PD1B) in the first diagonal direction D3 and the second diagonal direction D4.

[0077] The first photoelectric conversion elements (PD1R, PD1G, PD1B) and the second photoelectric conversion elements (PD2R, PD2G, PD2B) are arranged alternately along a first direction D1. The second photoelectric conversion elements (PD2R, PD2G, PD2B) are disposed between the first photoelectric conversion elements (PD1R, PD1G, PD1B) in the first direction D1 and the second direction D2. According to the embodiment, the planar shape and first width of the first photoelectric conversion elements (PD1R, PD1G, PD1B) and the planar shape and second width of the second photoelectric conversion elements (PD2R, PD2G, PD2B) are adjusted, thereby enabling the arrangement of unit pixels to be highly integrated. Therefore, the optical characteristics of the image sensor can be improved.

[0078] FIG. 8 is a timing diagram illustrating the operation of the image sensor according to the embodiment shown in FIG. 3A. 3A and 8, first, the reset signal RG is activated to turn on the reset transistor RX. Therefore, the pixel power supply voltage VDD is provided to the first floating diffusion region FD1, and the charges in the first floating diffusion region FD1 are discharged and reset (initialized). Meanwhile, when the reset signal RG is activated, the first and second switching signals SG1 and SG2 are activated, and the pixel power voltage VDD is also provided to the second and third floating diffusion regions FD2 and FD3. Therefore, the second and third floating diffusion regions (FD2, FD3) are also reset.

[0079] Subsequently, the reset signal RG is deactivated, and the reset transistor RX is turned off. Therefore, the first to third floating diffusion regions (FD1, FD2, FD3) are in a state in which charges can be stored. Immediately after the reset transistor RX is turned off, the selection signal SEL is activated to turn on the selection transistor SX. When the selection transistor SX is turned on, the pixel signal can be output through the output line Vout. First, at time t0, a first reset signal proportional to the potential at the first floating diffusion region FD1 is output. After reading out the first reset signal, the first transmission signal TRG1 is activated to turn on the first transfer transistor TX1. Therefore, in the first conversion gain mode, the charge stored in the first photoelectric conversion element PD1 is transferred to the first floating diffusion region FD1.

[0080] Next, the first transmission signal TRG1 is inactivated, the first transfer transistor TX1 is turned off, and at time t1, a first pixel signal proportional to the amount of photocharge accumulated in the first photoelectric conversion element PD1 in the first conversion gain mode is output. After outputting the first pixel signal, the dual conversion gain control signal DCG is activated to turn on the dual conversion gain transistor DCX. Therefore, the first photoelectric conversion element PD1 operates in the second conversion gain mode having a smaller conversion gain than the first conversion gain mode. When the dual conversion gain transistor DCX is turned on, a second pixel signal is outputted as the sum of the capacitances of the first and third floating diffusion regions FD1 and FD3. After turning on the dual conversion gain transistor DCX, at time t2, the first transmission signal TRG1 is activated to turn on the first transfer transistor TX1 again. Therefore, in the second conversion gain mode, the charges stored in the first photoelectric conversion element PD1 are transferred to the first and third floating diffusion regions FD1 and FD3.

[0081] Next, the first transmission signal TRG1 is inactivated, the first transfer transistor TX1 is turned off, and at time t3, a second pixel signal proportional to the amount of photocharge accumulated in the first photoelectric conversion element PD1 in the second conversion gain mode is output. That is, the second pixel signal is proportional to the amount of charge stored in the first and third floating diffusion regions FD1 and FD3. Subsequently, the reset signal RG is activated again to turn on the reset transistor RX. Therefore, the charges are discharged from the first and second floating diffusion regions FD1 and FD2 and the first and second floating diffusion regions FD1 and FD2 are reset.

[0082] After resetting the first and second floating diffusion regions FD1 and FD2, the first switching signal SG1 is activated to turn on the first switching transistor SW1. Therefore, the third pixel signal is outputted as the sum of the capacitances of the first to third floating diffusion regions (FD1, FD2, FD3). Therefore, the image sensor operates in a third conversion gain mode having a smaller conversion gain than the second conversion gain mode. At time t4, the second transmission signal TRG2 is activated to turn on the second transfer transistor TX2. Therefore, in the third conversion gain mode, the charge accumulated in the second photoelectric conversion element PD2 is transferred to the first to third floating diffusion regions (FD1, FD2, FD3).

[0083] Next, the second transmission signal TRG2 is inactivated, the second transfer transistor TX2 is turned off, and at time t5, a third pixel signal proportional to the amount of photocharge accumulated in the second photoelectric conversion element PD2 is output. That is, the third pixel signal is proportional to the amount of charge stored in the first to third floating diffusion regions (FD1, FD2, FD3). After outputting the third pixel signal, the second switching signal SG2 is activated to turn on the second switching transistor SW2. Therefore, a fourth pixel signal is outputted from the sum of the capacitances of the first to third floating diffusion regions (FD1, FD2, FD3) and the capacitor CAP. Therefore, the image sensor operates in a fourth conversion gain mode having a smaller conversion gain than the third conversion gain mode.

[0084] At time t6, the second transmission signal TRG2 is activated again to turn on the second transfer transistor TX2. Therefore, in the fourth conversion gain mode, the charge stored in the second photoelectric conversion element PD2 is transferred to the first to third floating diffusion regions FD1, FD2, and FD3 and the capacitor CAP. Next, the second transmission signal TRG2 is inactivated, the second transfer transistor TX2 is turned off, and at time t7, a fourth pixel signal proportional to the amount of photocharge accumulated in the second photoelectric conversion element PD2 is output. That is, the fourth pixel signal is proportional to the amount of charge stored in the first to third floating diffusion regions (FD1, FD2, FD3) and the capacitor CAP.

[0085] 9A and 9B are partial cross-sectional views showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to FIG. 9A, the image sensor includes a sensor chip C1 and a logic chip C2. The sensor chip C1 includes a pixel array region R1 and a pad region R2. As described above, the pixel array region R1 includes a plurality of unit pixels two-dimensionally arranged along a first direction D1 and a second direction D2 that intersect with each other. Each of the unit pixels includes first and second photoelectric conversion elements and a pixel transistor. Each unit pixel in the pixel array region R1 outputs an electrical signal generated by incident light.

[0086] The pixel array region R1 includes a light receiving region AR and a light blocking region OB. The light-shielding area OB surrounds the light-receiving area AR in a plan view. In other words, the light-shielding areas OB are disposed above, below, to the left and right of the light-receiving area AR in a plan view. A reference pixel to which no light is incident is provided in the light-shielding region OB, and the amount of charge sensed at a unit pixel of the light-receiving region AR is compared with the amount of reference charge generated at the reference pixel to calculate the size of the electrical signal sensed at the unit pixel. In the pad region R2, a plurality of conductive pads PAD used for inputting and outputting control signals, photoelectric signals, etc. are arranged. The pad region R2 surrounds the pixel array region R1 in a plan view so as to facilitate electrical connection with external elements. The conductive pad PAD inputs and outputs an electrical signal generated in the unit pixel to and from an external device.

[0087] The sensor chip C1 includes a photoelectric conversion circuit layer 10 between a pixel circuit layer 20 and a light-transmitting layer 30 in the vertical direction. As described above, the photoelectric conversion circuit layer 10 of the sensor chip C1 includes the first semiconductor substrate 100, a pixel separating structure PIS that defines a pixel region, and first and second photoelectric conversion elements (PD1, PD2). As described above, the pixel circuit layer 20 also includes the second semiconductor substrate 200, the pixel transistor TR at least a portion of which is provided on the second semiconductor substrate 200, and the second interlayer insulating film 210. In the light receiving area AR, the sensor chip C1 includes the same technical features as the image sensor described above.

[0088] The pixel separating structure PIS is in the light receiving area AR and extends into the light blocking area OB. A portion of the pixel separating structure PIS is electrically connected to the contact plug 522 in the light-shielding region OB. The flat insulating film 310 extends from the light receiving region AR to the light blocking region OB and the pad region R2. In the light-shielding region OB, a light-shielding pattern OBP is disposed on the flat insulating film 310. The light blocking pattern OBP blocks light from being incident on the photoelectric conversion elements PD provided in the light blocking region OB. In the reference pixel area of ​​the light-shielded area OB, the photoelectric conversion element PD does not output a photoelectric signal, but outputs a noise signal. The noise signal is generated by electrons generated by thermal generation or dark current, for example. The light blocking pattern OBP may include a metal such as tungsten, copper, aluminum, or an alloy thereof.

[0089] A filtering film 545 is provided on the light blocking pattern OBP. The filtering film 545 blocks light of a different wavelength than the color filter 340 . For example, the filtering film 545 blocks infrared radiation. The filtering film 545 may include, but is not limited to, a blue color filter. In the light-shielding region OB, the first through conductive pattern 511 penetrates the first semiconductor substrate 100 to be electrically connected to the metal wiring 221 of the pixel circuit layer 20 and the wiring structure 1111 of the logic chip C2. The first through conductive pattern 511 has a first bottom surface and a second bottom surface located at different levels. A first buried pattern 521 is provided inside the first through conductive pattern 511 . The first buried pattern 521 includes a low refractive index material and has insulating properties.

[0090] A conductive pad PAD is provided on the second surface 100b of the first semiconductor substrate 100 in the pad region R2. The conductive pad PAD is embedded in the second surface 100b of the semiconductor substrate 100. As an example, the conductive pad PAD is provided in a pad trench formed in the second surface 100b of the first semiconductor substrate 100 in the pad region R2. The conductive pad PAD may include a metal such as aluminum, copper, tungsten, titanium, tantalum, or alloys thereof. During the image sensor mounting process, bonding wires are bonded to the conductive pads PAD. The conductive pad PAD is electrically connected to an external device through a bonding wire.

[0091] In the pad region R2, the second through conductive pattern 513 penetrates the semiconductor substrate 100 and is electrically connected to the wiring structure 1111 of the logic chip C2. The second through conductive pattern 513 extends onto the second surface 100b of the first semiconductor substrate 100 and is electrically connected to the conductive pad PAD. A portion of the second through conductive pattern 513 covers the bottom surface and sidewall of the conductive pad PAD. A second buried pattern 523 is provided inside the second through conductive pattern 513 . The second buried pattern 523 includes a low refractive index material and has insulating properties. In the pad region R2, a pixel isolating structure PIS is provided around the second through conductive pattern 513.

[0092] The logic chip C2 includes a third semiconductor substrate 1000, a logic circuit LC, a wiring structure 1111 connected to the logic circuit, and a logic interlayer insulating film 1100. The top layer of the logic interlayer insulating film 1100 is bonded to the pixel circuit layer 20 of the sensor chip C1. The logic chip C2 is electrically connected to the sensor chip C1 through the first conductive through pattern 511 and the second conductive through pattern 513. As an example, the sensor chip C1 and the logic chip C2 are described as being electrically connected to each other through the first and second through conductive patterns 511 and 513, but the present invention is not limited thereto.

[0093] According to the embodiment shown in FIG. 9B, the sensor chip C1 and the logic chip C2 are electrically connected by directly bonding the third and fourth bonding pads (BP3, BP4) provided on the top metal layers of the sensor chip C1 and the logic chip C2 to each other. In detail, the sensor chip C1 of the image sensor includes a third bonding pad BP3 provided on the top metal layer of the pixel circuit layer 20, and the logic chip C2 includes a fourth bonding pad BP4 provided on the top metal layer of the wiring structure 1111. The third and fourth bonding pads (BP3, BP4) may include, for example, at least one of tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0094] The third bonding pad BP3 of the sensor chip C1 and the fourth bonding pad BP4 of the logic chip C2 are directly and electrically connected to each other by a hybrid bonding method. Hybrid bonding refers to a bond in which two components containing the same material fuse at their interface. For example, if the third and fourth bonding pads (BP3, BP4) are made of copper (Cu), they are physically and electrically connected by copper (Cu)-copper (Cu) bonding. In addition, the insulating film surface of the sensor chip C1 and the insulating film surface of the logic chip C2 are joined by dielectric-dielectric bonding.

[0095] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0096] 1 Active Pixel Sensor Array Two-line decoder 3 Row Driver 4-row decoder 5 Timing Generator 6. Correlated Double Sampler 7. Analog-to-Digital Converter 8 Input / Output Buffers 10 Photoelectric conversion circuit layer 10P photoelectric conversion circuit 20 pixel circuit layer 20P pixel circuit 100, 200 (first, second) semiconductor substrate 105 Element isolation film 110, 210 (first, second) interlayer insulating film 111 Liner insulation pattern 113 Semiconductor Pattern 115 Capping insulation pattern 310 Flat insulating film 320 Lattice Structure 330 Protective film 340 Color Filter 350 Micro Lens BP1~BP4 (1st~4th) bonding pads C1 Sensor Chip C1a 1st Chip C1b 2nd chip C2 Logic Chip CAP Capacitor CP Conductive Pad CT Contact Plug DCX Dual Conversion Gain Transistor ML Conductive Line PD1, PD2 (first and second) photoelectric conversion elements PIS Pixel Isolation Structure RXG Reset gate electrode SF source follower transistor SFG Source follower gate electrode SWG1, SWG2 (first and second) switching gate electrodes SXG Select gate electrode TG1, TG2 (first and second) transfer gate electrodes

Claims

1. a first semiconductor substrate including a first pixel region and a second pixel region; a first photoelectric conversion element provided in the first pixel region; a second photoelectric conversion element provided in the second pixel region; a first floating diffusion region provided in the first pixel region; a second floating diffusion region provided in the second pixel region; a first transfer gate electrode disposed between the first photoelectric conversion element and the first floating diffusion region; a second transfer gate electrode disposed between the second photoelectric conversion element and the second floating diffusion region; a second semiconductor substrate on the first semiconductor substrate; a plurality of pixel transistors connected to the first and second photoelectric conversion elements; The width of the second photoelectric conversion element is smaller than the width of the first photoelectric conversion element, At least a portion of the pixel transistor is provided on the second semiconductor substrate.

2. 2. The image sensor of claim 1, wherein a portion of the pixel transistor is provided in the first pixel region of the first semiconductor substrate.

3. The pixel transistor is a dual conversion gain transistor provided in the first semiconductor substrate and coupled to the first floating diffusion region; 2. The image sensor of claim 1, further comprising: a source follower transistor provided on the first semiconductor substrate.

4. The pixel transistor is a select transistor provided on the second semiconductor substrate and coupled to the source follower transistor; a reset transistor provided in the second semiconductor substrate and coupled to the dual conversion gain transistor; a first switching transistor provided in the second semiconductor substrate and coupled to the second floating diffusion region; 4. The image sensor of claim 3, further comprising: a second switching transistor provided on the second semiconductor substrate and connected to the second floating diffusion region.

5. The pixel transistor is a dual conversion gain transistor provided in the second semiconductor substrate and coupled to the first floating diffusion region; 2. The image sensor of claim 1, further comprising: a source follower transistor provided on the second semiconductor substrate.

6. The pixel transistor is a select transistor provided on the second semiconductor substrate and coupled to the source follower transistor; a reset transistor provided in the second semiconductor substrate and coupled to the dual conversion gain transistor; a first switching transistor provided on the second semiconductor substrate and coupled to the dual conversion gain transistor; 6. The image sensor of claim 5, further comprising: a second switching transistor provided on the second semiconductor substrate and connected to the second floating diffusion region.

7. 6. The image sensor of claim 5, wherein the pixel transistor further comprises a third switching transistor provided on the second semiconductor substrate and connected to the first floating diffusion region and the source follower transistor.

8. 2. The image sensor of claim 1, further comprising a capacitor connected between the second floating diffusion region and a pixel power supply voltage.

9. a first capacitor disposed in a first interlayer insulating film on the first semiconductor substrate; a second capacitor disposed in a second interlayer insulating film on the second semiconductor substrate, The image sensor of claim 1 , wherein the first and second capacitors are connected in parallel to each other.

10. 2. The image sensor of claim 1, wherein each of the first and second transfer gate electrodes vertically passes through a portion of the first semiconductor substrate.

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