Display device

Abstract

To improve the reliability of a display device using a transistor including an oxide semiconductor.SOLUTION: A display device includes a plurality of pixels arranged in a matrix in a first direction and a second direction intersecting with the first direction. Each of the pixels includes: a transistor including an oxide semiconductor layer, a gate wire extending in the first direction facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wire; a first conductive layer provided on at least one first insulating layer on the transistor and in contact with the oxide semiconductor layer; a second insulating layer provided on the first conductive layer; a first inorganic layer provided on the second insulating layer and having an opening part; and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening part. The coverage of the first inorganic layer covering the first insulating layer is 85% or more of the area of the pixels.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device. In particular, an embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor. Also, an embodiment of the present invention relates to a manufacturing method of the display device. [Background technology]

[0002] In recent years, development of transistors using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single crystal silicon has been progressing (see, for example, Patent Documents 1 and 2). Transistors using oxide semiconductors for the channel have a simple structure and are formed by a low-temperature process, similar to transistors using amorphous silicon for the channel. Transistors using oxide semiconductors for the channel are known to have higher mobility and very low off-current than transistors using amorphous silicon for the channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-146819 A [Patent Document 2] JP 2015-159315 A Summary of the Invention [Problem to be solved by the invention]

[0004] It is known that the characteristics of a transistor including an oxide semiconductor fluctuate when moisture penetrates into the oxide semiconductor. In addition, in a display device, a planarization film made of an organic resin layer is provided to reduce unevenness formed by the transistor. Since the organic resin layer contains a large amount of moisture, when hydrogen contained in the organic resin layer penetrates into the oxide semiconductor, the characteristics of the transistor fluctuate, and the reliability of the display device may decrease.

[0005] An object of one embodiment of the present invention is to improve the reliability of a display device including a transistor including an oxide semiconductor. [Means for solving the problem]

[0006] A display device according to one embodiment of the present invention is a display device including a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the plurality of pixels including a transistor having an oxide semiconductor layer, a gate wiring extending in the first direction opposite the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring, a first conductive layer provided on at least one first insulating layer above the transistor and in contact with the oxide semiconductor layer, a second insulating layer provided on the first conductive layer, a first inorganic layer provided on the second insulating layer and having an opening, and a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer at the opening, and a coverage rate of the first insulating layer by the first inorganic layer is 85% or more of the area of ​​the pixel. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Diagram 2] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Diagram 3] 1 is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view showing a configuration of a display device according to an embodiment of the present invention. [Diagram 5] 1 is a plan view showing a configuration of a display device according to an embodiment of the present invention; [Figure 6] 1 is a plan view showing a configuration of a display device according to an embodiment of the present invention; [Figure 7] FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 8]FIG. 4 is a sequence diagram illustrating a manufacturing method of a display device according to an embodiment of the present invention. [Figure 9] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 10] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 11] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 12] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 13] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 14] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 15] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 17] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 18] 5A to 5C are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment of the present invention. [Figure 19] FIG. 11 is a cross-sectional view showing a configuration of a display device according to another embodiment of the present invention. [Figure 20] FIG. 11 is a cross-sectional view showing a configuration of a display device according to another embodiment of the present invention. [Figure 21] FIG. 11 is a cross-sectional view showing a configuration of a display device according to another embodiment of the present invention. [Figure 22] FIG. 11 is a cross-sectional view showing a configuration of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, film thickness, shape, etc. of each part compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, the same symbols are used for configurations similar to those described above with respect to the previous figures, and detailed explanations may be omitted as appropriate.

[0009] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". In this way, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is different from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the stacking order in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0011] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0012] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0013] [First embodiment] [1. Overview of the display device 10] An overview of a display device 10 according to an embodiment of the present invention will be described with reference to Figures 1 to 3. Figure 1 is a plan view showing an overview of a display device 10 according to an embodiment of the present invention. In this embodiment, the configuration of a liquid crystal display device as the display device 10 will be described.

[0014] As shown in FIG. 1, the display device 10 includes an array substrate 300, a seal portion 400, a counter substrate 500, a flexible printed circuit board 600 (FPC), and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded together by the seal portion 400. In the liquid crystal region 22 surrounded by the seal portion 400, a plurality of pixels 310 are arranged in a matrix shape along a first direction D1 (row direction) and a second direction D2 (column direction) intersecting with the first direction D1. The plurality of pixels 310 include a red pixel R, a green pixel G, and a blue pixel B corresponding to a color filter provided on the counter substrate. Each of the red pixel R, the green pixel G, and the blue pixel B is also called a subpixel. The first direction D1 and the second direction D2 may be orthogonal to each other. The liquid crystal region 22 is a region that overlaps with a liquid crystal element 410 described later in a plan view. In the following, a region of the liquid crystal region 22 that includes a plurality of pixels may be called an image display region or an active region.

[0015] The display device 10 also has a backlight unit on the rear side of the array substrate 300, and when light emitted from the backlight unit passes through the image display area, the transmitted light is modulated in each pixel to display an image.

[0016] The seal area 24 in which the seal portion 400 is provided is a region surrounding the liquid crystal region 22. The FPC 600 is provided in the terminal area 26. The terminal area 26 is a region in which the array substrate 300 is exposed from the counter substrate 500, and is provided outside the seal area 24. The outside of the seal area 24 means the outside of the region in which the seal portion 400 is provided and the region surrounded by the seal portion 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 supplies signals for driving the pixel circuits of the pixels 310. In the following, the seal area 24 other than the image display area, the outside of the seal area 24, and the terminal area 26 may be collectively referred to as the peripheral area.

[0017] 2. Circuit configuration of display device 10 Fig. 2 is a block diagram showing a circuit configuration of a display device 10 according to an embodiment of the present invention. As shown in Fig. 2, a gate driver circuit 330 is provided at a position adjacent to the liquid crystal region 22 in which the pixels 310 are arranged in the first direction D1, and a source driver circuit 320 is provided at a position adjacent to the liquid crystal region 22 in the second direction D2. The source driver circuit 320 and the gate driver circuit 330 are provided in the above-mentioned sealing region 24. However, the region in which the source driver circuit 320 and the gate driver circuit 330 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits of the pixels 310 are provided.

[0018] Gate wiring 331 extends from the gate driver circuit 330 in a first direction D1 and is connected to pixel circuits of a plurality of pixels 310 arranged in the first direction D1. Source wiring 321 extends from the source driver circuit 320 in a second direction D2 and is connected to pixel circuits of a plurality of pixels 310 arranged in the second direction D2.

[0019] A terminal portion 333 is provided in the terminal region 26. The terminal portion 333 and the source driver circuit 320 are connected by a connection wiring 341. Similarly, the terminal portion 333 and the gate driver circuit 330 are connected by a connection wiring 342. By connecting the FPC 600 to the terminal portion 333, an external device to which the FPC 600 is connected is connected to the display device 10, and a pixel circuit included in each pixel 310 provided in the display device 10 is driven by a signal from the external device.

[0020] 3. Pixel circuit of pixel 310 of display device 10 FIG. 3 is a circuit diagram showing a pixel circuit of a pixel 310 of a display device 10 according to an embodiment of the present invention. As shown in FIG. 3, the pixel circuit includes elements such as a transistor 800, a storage capacitor 890, and a liquid crystal element 410. Although details will be described later, one electrode of the storage capacitor 890 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. Similarly, one electrode of the liquid crystal element 410 is a pixel electrode PTCO, and the other electrode is a common electrode CTCO. The transistor 800 has a gate electrode 810, a source electrode 830, and a drain electrode 840. The gate electrode 810 is connected to a gate wiring 331. The source electrode 830 is connected to a source wiring 321. The drain electrode 840 is connected to the storage capacitor 890 and the liquid crystal element 410. In this embodiment, for convenience of explanation, 830 is called a source electrode and 840 is called a drain electrode, but the function of each electrode as a source and the function as a drain may be interchanged.

[0021] [4. Configuration of display device 10] With reference to Figs. 4 to 6, the details of the configuration of the display device 10 according to an embodiment of the present invention will be described. Fig. 4 is a cross-sectional view showing the configuration of the display device 10 according to an embodiment of the present invention. Figs. 5 and 6 are plan views showing the configuration of the display device 10 according to an embodiment of the present invention. Note that the cross-sectional view of Fig. 4 is a cross-sectional view for explaining the layer structure of the display device 10, and the pixel circuit is actually provided in the image display region. In particular, in the pixel circuit in Fig. 4, the periphery of the contact hole in the pixel region is shown as the center, and only a part of the transmission region (aperture region) that contributes to display is shown. In Fig. 4, the liquid crystal layer and the counter substrate are omitted. Although Fig. 4 shows a liquid crystal display device of FFS (Fringe Field Switching) type, it may be a liquid crystal display device of IPS (In Plane Switching) type.

[0022] As shown in Fig. 4, the display device 10 is provided above a substrate SUB. The display device 10 has a transistor Tr, a wiring W1, a connection electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is an abbreviation for Transparent Conductive Oxide. The transistor Tr is a transistor included in the pixel circuit of the pixel 310 of the display device 10.

[0023] [5. Structure of transistor Tr] The transistor Tr is provided on a light-shielding layer LS and a first insulating layer IL1 provided on a substrate SUB. The transistor Tr has an oxide semiconductor layer POS, a second insulating layer IL2, and a gate wiring GL (corresponding to the gate electrode 810 and the gate wiring 331 shown in FIG. 3). The transistor Tr may also have a metal oxide layer MO1 provided between the oxide semiconductor layer POS and the first insulating layer IL1. The gate wiring GL faces the oxide semiconductor layer POS. The second insulating layer IL2 is provided between the oxide semiconductor layer POS and the gate wiring GL. In this embodiment, a top-gate transistor in which the oxide semiconductor layer POS is provided on the substrate SUB side of the gate wiring GL is exemplified, but a bottom-gate transistor in which the positional relationship between the gate wiring GL and the oxide semiconductor layer POS is reversed may also be used.

[0024] The oxide semiconductor layer POS has a polycrystalline structure including a plurality of crystal grains. Although the details will be described later, the oxide semiconductor layer POS having a polycrystalline structure can be formed by using a polycrystalline oxide semiconductor (Poly-OS) technique. Hereinafter, an oxide semiconductor having a polycrystalline structure may be referred to as a Poly-OS.

[0025] As will be described in detail later, the oxide semiconductor layer POS contains two or more metals including indium, and the ratio of indium in the two or more metals is 50% or more. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides are used. However, the oxide semiconductor layer POS only needs to contain Poly-OS, and may contain metal elements other than those mentioned above.

[0026] The oxide semiconductor layer POS includes a channel region CA, a source region SA, and a drain region DA. The channel region CA is a region of the oxide semiconductor layer that overlaps with the gate wiring GL in a planar view. The channel region CA is switched between a conductive state and a non-conductive state depending on a voltage supplied to the gate wiring GL. The source region SA and the drain region DA are regions with lower resistance than the channel region. For example, the source region SA and the drain region DA are regions whose resistance is reduced by doping impurities into the oxide semiconductor layer POS.

[0027] The gate wiring GL is arranged along a first direction D1. The oxide semiconductor layer POS is arranged to cross the gate wiring GL. A region of the gate wiring GL that overlaps with the oxide semiconductor layer POS functions as a gate electrode.

[0028] A third insulating layer IL3 is provided on the gate wiring GL. A wiring W1 (corresponding to the source electrode 830 and the source wiring 321 shown in FIG. 3) is provided on the third insulating layer IL3. The wiring W1 is arranged along the second direction D2. The wiring W1 is connected to the source region SA via a contact hole WCON provided in the second insulating layer IL2 and the third insulating layer IL3. A data signal related to the gradation of the pixel is transmitted to the wiring W1. A fourth insulating layer IL4 is provided on the third insulating layer IL3 and the wiring W1. A connection electrode ZTCO (corresponding to the drain electrode 840 shown in FIG. 3) is provided on the fourth insulating layer IL4. The connection electrode ZTCO is connected to the drain region DA via a contact hole ZCON provided in the second insulating layer IL2 to the fourth insulating layer IL4. The connection electrode ZTCO is in contact with the drain region DA at the bottom of the contact hole ZCON. The connection electrode ZTCO is a transparent conductive layer.

[0029] The region where the connection electrode ZTCO and the drain region DA contact each other is called the first contact region CON1. ​​Although details will be described later, the common electrode CTCO contacts the drain region DA in the first contact region CON1, which does not overlap with the gate line GL and the line W1 in a plan view. In a plan view, the first contact region CON1 is included in the display region of the pixel.

[0030] A fifth insulating layer IL5 is provided on the connection electrode ZTCO. The fifth insulating layer IL5 reduces a step formed by a structure provided below the fifth insulating layer IL5. The fifth insulating layer IL5 may be called a planarizing film. The fifth insulating layer is made of an organic resin. A pixel electrode PTCO is provided on the fifth insulating layer IL5. The pixel electrode PTCO is connected to the connection electrode ZTCO via a contact hole PCON provided in the fifth insulating layer IL5. The region where the connection electrode ZTCO and the pixel electrode PTCO contact each other is called a second contact region CON2. In a plan view, the second contact region CON2 overlaps with the gate line GL. The pixel electrode PTCO is a transparent conductive layer.

[0031] A sixth insulating layer IL6 is provided on the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are provided on the sixth insulating layer IL6. Although details will be described later, the common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The electrical resistance of the common auxiliary electrode CMTL is lower than the electrical resistance of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing the occurrence of color mixing. A spacer SP is provided on the common electrode CTCO.

[0032] The common auxiliary electrode CMTL is provided in a lattice pattern. The common auxiliary electrode CMTL is disposed so as to cross the contact hole PCON in the first direction D1, and is provided so as to overlap the wiring W1 in the second direction D2. The common auxiliary electrode CMTL is provided with an opening COP. The opening COP corresponds to the opening of the pixel. The common electrode CTCO is provided on the common auxiliary electrode CMTL, and is provided so as to cover the entire image display area. The common electrode CTCO is provided with a slit pattern in a region overlapping with the opening COP and the pixel electrode PTCO. The slit pattern also overlaps with the pixel electrode PTCO. The sixth insulating layer IL6 is provided with an opening IOP, which will be described in detail later.

[0033] The spacer SP is provided for some of the pixels. For example, the spacer SP may be provided for any one of the red pixel R, the green pixel G, and the blue pixel B. However, the spacer SP may be provided for all the pixels. The height of the spacer SP is half the height of the cell gap. A spacer is also provided on the counter substrate, and the spacer of the counter substrate and the above-mentioned spacer SP overlap in a plan view. A configuration in which the height of the spacer SP corresponds to the cell gap may also be applied. Also, as shown in FIG. 4, the spacer is filled in the contact hole PCON and protrudes toward the counter substrate side, but a configuration in which the contact hole is only filled with a filler can also be adopted.

[0034] A light-shielding layer LS is provided between the transistor Tr and the substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as the light-shielding layer LS. However, the light-shielding layer LS may be formed of only the light-shielding layer LS1 or only the light-shielding layer LS2. In plan view, the light-shielding layer LS is disposed along the first direction D1 and is provided in a region overlapping with the gate line GL. In addition, the light-shielding layer LS is provided so as to intersect with the oxide semiconductor layer POS. That is, in plan view, the light-shielding layer LS is provided in a region overlapping with the channel region. The light-shielding layer LS prevents light incident from the substrate SUB side from reaching the channel region. When a conductive layer is used as the light-shielding layer LS, a voltage may be applied to the light-shielding layer LS to control the channel region. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and the gate line GL may be connected in a peripheral region of the pixel circuit. In plan view, the first contact region CON1 is provided in a region not overlapping with the light-shielding layer LS.

[0035] It is known that the characteristics of a transistor including an oxide semiconductor change when moisture penetrates into the oxide semiconductor. In addition, in a display device, a planarization film made of an organic resin is provided to reduce unevenness formed by the transistor. Since the organic resin contains a large amount of moisture, when hydrogen contained in the organic resin penetrates into the oxide semiconductor, the characteristics of the transistor change, and the reliability of the display device may decrease.

[0036] In a display device using a transistor including an oxide semiconductor, it is necessary to sufficiently release moisture contained in an organic resin layer provided on the transistor. If an annealing treatment is performed in a state where the organic resin layer is exposed during a manufacturing process, moisture is again taken in from the exposed surface of the organic resin layer in a subsequent process.

[0037] For example, in the case of a liquid crystal display device, an inorganic layer such as a pixel electrode, a common electrode, an auxiliary electrode, or an inorganic insulating layer is provided on the organic resin layer. The inorganic layer has a function of suppressing moisture penetration compared to the organic resin layer. Even if an annealing process is performed in a state where a pixel electrode is formed on the organic resin layer, the surface of the organic resin layer is exposed from the pixel electrode, so moisture may be taken in from the outside again, which may cause the characteristics of the transistor to fluctuate. Similarly, even if an annealing process is performed in a state where a common electrode is formed on the organic resin layer, the surface of the organic resin layer is exposed from the common electrode, so moisture may be taken in from the outside again, which may cause the characteristics of the transistor to fluctuate. As the resolution of the display device improves, the area of ​​the pixel and the area occupied by the transistor are reduced. Therefore, the characteristic fluctuation of the transistor has a significant effect on the display quality of the display device.

[0038] Therefore, in order to suppress fluctuations in the characteristics of a transistor including an oxide semiconductor, it is important to release the moisture contained in the organic resin layer to the outside and to prevent the moisture from being re-introduced into the organic resin layer from the outside in the subsequent process.

[0039] In one embodiment of the present invention, a first inorganic layer is provided on the organic resin layer, and an opening IOP is provided in the first inorganic layer. The coverage of the organic resin layer by the first inorganic layer is 85% or more of the pixel area. A second inorganic layer is provided on the first inorganic layer, and the second inorganic layer contacts the organic resin layer at the opening. In other words, the opening IOP provided in the first inorganic layer is blocked by the second inorganic layer provided on the first inorganic layer.

[0040] In the manufacturing process of the display device 10, after forming the opening IOP in the first inorganic layer, an annealing process is performed, so that moisture contained in the organic resin layer is discharged to the outside through the opening IOP provided in the first inorganic layer. At this time, since the coverage rate of the organic resin layer covered by the first inorganic layer is 85% or more with respect to the area of ​​the pixel, moisture is discharged intensively from the opening IOP. In addition, it is possible to suppress the intrusion of moisture into the organic resin layer from the outside of the first inorganic layer. Furthermore, by blocking the opening IOP with the second inorganic layer provided on the first inorganic layer, it is possible to further suppress the intrusion of moisture into the organic resin layer from the outside.

[0041] In the display device 10 according to one embodiment of the present invention, the opening IOP provided in the first inorganic layer is blocked by the second inorganic layer, so that it is possible to suppress the intrusion of moisture into the organic resin layer not only during the manufacturing process but also when the display device is in use. Therefore, it is possible to suppress the moisture contained in the organic resin layer from re-intruding into the oxide semiconductor. This makes it possible to suppress the characteristics of the transistor from fluctuating, and improve the reliability of the display device.

[0042] In this specification and the like, the area of ​​a sub-pixel can be calculated by the following formula. Active area / resolution = subpixel area Depending on the display device, the areas of the red pixel R, the green pixel G, and the blue pixel B may differ from each other. In this case, the areas of the three sub-pixels may be calculated as the area of ​​one pixel. In this case, the coverage of the organic resin layer by the first inorganic layer may also be calculated by using the areas of the three sub-pixels as the area of ​​one pixel.

[0043] For example, the active area (mm 2 ) is 38.4mm x 38.4mm and the resolution is 1600(RGB) x 1600, the area of ​​each subpixel is 192μm 2 Therefore, in the subpixel, the first inorganic layer is 163.2 μm thick. 2If the first inorganic layer is covered to this extent, moisture contained in the organic resin layer can be released from the openings IOP of the first inorganic layer, and the moisture can be prevented from being re-incorporated into the organic resin layer in the subsequent steps.

[0044] Each of the first inorganic layer and the second inorganic layer is formed of a conductive layer, a transparent conductive layer, and an inorganic insulating layer. Each of the first inorganic layer and the second inorganic layer may have a single layer structure or a laminated structure. In the case of a laminated structure, for example, it may be a laminated structure of a transparent conductive layer and an inorganic insulating layer, or a structure in which a plurality of inorganic insulating layers are laminated. The thickness of each of the first inorganic layer and the second inorganic layer is not particularly limited, but is preferably at least 30 nm or more, 50 nm or more, and 200 nm or less. If the thickness of the first inorganic layer is less than 30 nm, the blocking effect of moisture from the outside may be weakened. In this case, a second inorganic layer thicker than the thickness of the first inorganic layer may be provided on the first inorganic layer to fill the opening IOP provided in the first inorganic layer. The thickness of the second inorganic layer may be 200 nm or more as long as it does not affect the driving of the liquid crystal element.

[0045] The area of ​​the opening IOP provided in the sixth insulating layer IL6 may be smaller than the area of ​​the contact hole provided in the fifth insulating layer IL5. In other words, the coverage of the organic resin layer with the first inorganic layer is 85% or more, preferably 95% or more, more preferably 98% or more, relative to the area of ​​the pixel. If the area of ​​the opening IOP is large, even if moisture is released from the organic resin layer to the outside through the opening IOP, moisture may be taken in from the outside through the opening IOP during the annealing process. By making the area of ​​the opening IOP smaller than the area of ​​the contact hole, it is possible to suppress the moisture released from the organic resin layer from being taken in again.

[0046] In the structure of the display device 10 shown in FIGS. 4 to 6, the first inorganic layer is the pixel electrode PTCO and the sixth insulating layer IL6, and the second inorganic layer is the common electrode CTCO. An opening IOP is provided in the sixth insulating layer IL6. The common electrode CTCO contacts the fifth insulating layer IL5 at the opening IOP. The common electrode CTCO is not connected to other conductive layers at the opening IOP provided in the pixel. In addition, the coverage rate of the sixth insulating layer IL6 over the fifth insulating layer IL5 is 85% or more with respect to the area of ​​the pixel.

[0047] Moreover, the opening IOP provided in the sixth insulating layer IL6 is preferably provided in a region overlapping the oxide semiconductor layer POS. By providing the opening IOP in the vicinity of the oxide semiconductor layer POS, the effect of moisture contained in the organic resin layer can be reduced. It is more preferable that the opening IOP is disposed so as to overlap a region of the oxide semiconductor layer POS where the gate wiring overlaps.

[0048] As described above, in the display device according to one embodiment of the present invention, after the moisture contained in the organic resin layer provided on the transistor is released, it is possible to suppress re-intake of moisture from the outside into the organic resin layer. This suppresses the intrusion of moisture from the organic resin layer into the oxide semiconductor layer, thereby suppressing fluctuations in the characteristics of the transistor. Therefore, it is possible to improve the reliability of the display device.

[0049] [6. Display device manufacturing method] A method for manufacturing the display device 10 according to one embodiment of the present invention will be described. Fig. 7 and Fig. 8 are sequence diagrams for explaining the method for manufacturing the display device 10 according to one embodiment of the present invention. Fig. 9 to Fig. 18 are cross-sectional views for explaining the method for manufacturing the display device 10 according to one embodiment of the present invention.

[0050] First, light-shielding layers LS1 and LS2 are formed as a light-shielding layer LS on a substrate SUB (see "LS formation" in step S1001 shown in FIG. 7 and FIG. 9).

[0051] As the substrate SUB, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, is used. When the substrate SUB needs to be flexible, a polyimide substrate, an acrylic substrate, a siloxane substrate, a fluororesin substrate, or a substrate containing an organic resin is used as the substrate SUB. When a substrate containing an organic resin is used as the substrate SUB, an impurity element may be introduced into the organic resin in order to improve the heat resistance of the substrate SUB.

[0052] The light-shielding layer LS is formed by processing a conductive layer formed by, for example, a sputtering method. A general metal material is used as the light-shielding layer LS. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as the light-shielding layer LS. As shown in FIG. 9, after forming a light-shielding layer LS1, a light-shielding layer LS2 is formed so as to cover the light-shielding layer LS1. In this embodiment, a case where the light-shielding layer LS1 and the light-shielding layer LS2 are formed as a laminated layer will be described, but the light-shielding layer LS2 may be formed as a single layer.

[0053] Next, a first insulating layer IL1 is formed as a base layer on the light-shielding layer LS (see step S1002 “IL1 formation” shown in FIG. 7 and FIG. 9).

[0054] The first insulating layer IL1 is formed by a chemical vapor deposition (CVD) method or a sputtering method. A general insulating material is used as the first insulating layer IL1. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y), aluminum oxide nitride (AlN x O y ), and aluminum nitride (AlN x ) and other inorganic insulating materials are used.

[0055] The above SiO x N y and AlO x N y is a silicon and aluminum compound that contains a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0056] The first insulating layer IL1 is formed in a single-layer structure or a laminated structure. When the first insulating layer IL1 is formed in a laminated structure, it is preferable that an insulating material containing nitrogen and an insulating material containing oxygen are formed in this order from the substrate SUB. By using an insulating material containing nitrogen, for example, it is possible to block impurities diffusing from the substrate SUB side toward the oxide semiconductor layer POS. In addition, by using an insulating material containing oxygen, it is possible to release oxygen by heat treatment. The temperature of the heat treatment at which the insulating material containing oxygen releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the insulating material containing oxygen releases oxygen at a heat treatment temperature performed in the manufacturing process of the display device when a glass substrate is used as the substrate SUB. In this embodiment, for example, silicon nitride is formed as the insulating material containing nitrogen. For example, silicon oxide is formed as the insulating material containing oxygen.

[0057] Next, a metal oxide layer MO1 containing aluminum as a main component is formed on the first insulating layer IL1 (see step S1003 “MO1 formation” shown in FIG. 7 and FIG. 9).

[0058] The metal oxide layer MO1 is formed by a sputtering method. The metal oxide layer mainly composed of aluminum is, for example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), Aluminum Nitride (AlN x ) is used. "Aluminum-based metal oxide layer" means that the ratio of aluminum contained in the metal oxide layer MO1 is 1% or more of the entire metal oxide layer MO1. The ratio of aluminum contained in the metal oxide layer MO1 may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer MO1. The above ratio may be a mass ratio or a weight ratio.

[0059] The thickness of the metal oxide layer MO1 is, for example, 2 nm to 100 nm, 2 nm to 50 nm, 2 nm to 30 nm, or 2 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer MO1. Aluminum oxide has high gas barrier properties.

[0060] Next, an amorphous oxide semiconductor layer AOS is formed on the metal oxide layer MO1 (see "OS formation" in step S1004 shown in FIG. 7 and FIG. 10).

[0061] The oxide semiconductor layer AOS is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor layer AOS is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm.

[0062] A metal oxide having semiconductor properties can be used as the oxide semiconductor layer AOS. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer AOS. The ratio of indium in the two or more metals is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), or a lanthanoid is used as the oxide semiconductor layer AOS. An element other than the above may be used as the oxide semiconductor layer AOS. In this embodiment, a metal oxide containing indium (In) and gallium (Ga) is used as the oxide semiconductor layer AOS.

[0063] When the oxide semiconductor layer AOS is crystallized by an OS annealing process described later, the oxide semiconductor layer AOS after deposition and before the OS annealing process is preferably amorphous (a state in which the oxide semiconductor has few crystalline components). In other words, the oxide semiconductor layer AOS is preferably deposited under conditions that prevent the oxide semiconductor layer AOS from crystallizing as much as possible immediately after deposition. For example, when the oxide semiconductor layer AOS is deposited by a sputtering method, the oxide semiconductor layer AOS is deposited while controlling the temperature of the deposition target (the substrate SUB and the structure formed thereon).

[0064] When a film is formed on a target object by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target object, and the temperature of the target object rises with the film formation process. If the temperature of the target object rises during the film formation process, the oxide semiconductor layer AOS contains microcrystals immediately after the film formation, and crystallization by the subsequent OS annealing process is inhibited. In order to control the temperature of the target object as described above, for example, the target object can be cooled while the film is formed. For example, the target object can be cooled from the surface opposite to the surface to be formed so that the temperature of the surface to be formed of the target object (hereinafter referred to as the "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. As described above, by forming the oxide semiconductor layer AOS while cooling the target object, the oxide semiconductor layer AOS having a small amount of crystalline components immediately after the film formation can be formed.

[0065] Next, a pattern of the oxide semiconductor layer AOS is formed ("OS pattern formation" in step S1005 shown in FIG. 7). Although not shown, a resist mask is formed on the oxide semiconductor layer AOS, and the oxide semiconductor layer AOS is etched using the resist mask. For etching the oxide semiconductor layer AOS, wet etching or dry etching may be used. For wet etching, etching can be performed using an acidic etchant. For example, oxalic acid or hydrofluoric acid can be used as the etchant.

[0066] It is preferable that the oxide semiconductor layer AOS is patterned before the OS annealing treatment. If the oxide semiconductor layer AOS is crystallized by the OS annealing treatment, it tends to be difficult to etch. In addition, even if the oxide semiconductor layer AOS is damaged by etching, the damage can be repaired by the OS annealing treatment, which is preferable.

[0067] After the patterning of the oxide semiconductor layer AOS, a heat treatment (OS annealing treatment) is performed on the oxide semiconductor layer AOS ("OS annealing treatment" in step S1006 shown in FIG. 7 and FIG. 11). In the OS annealing treatment, the oxide semiconductor layer AOS is held at a predetermined temperature for a predetermined time. The predetermined temperature is 300° C. or more and 500° C. or less, and preferably 350° C. or more and 450° C. or less. The holding time at the temperature is 15 minutes or more and 120 minutes or less, and preferably 30 minutes or more and 60 minutes or less. By performing the OS annealing treatment, the oxide semiconductor layer AOS is crystallized, and an oxide semiconductor layer POS having a polycrystalline structure is formed.

[0068] Next, a pattern of the metal oxide layer MO1 is formed using the oxide semiconductor layer POS as a mask (step S1007 "MO1 pattern formation" shown in FIG. 7 and FIG. 12). The metal oxide layer MO1 is etched using the crystallized oxide semiconductor layer POS as a mask. For etching the metal oxide layer MO1, wet etching or dry etching may be used. For wet etching, for example, diluted hydrofluoric acid (DHF) is used. The crystallized oxide semiconductor layer POS has etching resistance to diluted hydrofluoric acid compared to the amorphous oxide semiconductor layer AOS. Therefore, the metal oxide layer MO1 can be etched using the oxide semiconductor layer POS as a mask. This makes it possible to omit a photolithography process.

[0069] Next, the second insulating layer IL2 is formed on the oxide semiconductor layer POS ("IL2 formation" in step S1008 shown in FIG. 7).

[0070] The method of forming the second insulating layer IL2 and the insulating material thereof may be the same as those described for the first insulating layer IL1. The thickness of the second insulating layer IL2 is, for example, 50 nm or more and 150 nm or less.

[0071] It is preferable to use an insulating material containing oxygen for the second insulating layer IL2. It is also preferable to use an insulating layer with few defects for the second insulating layer IL2. For example, when the oxygen composition ratio in the second insulating layer IL2 is compared with the oxygen composition ratio in an insulating layer having the same composition as the second insulating layer IL2 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the second insulating layer IL2 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. For example, when silicon oxide (SiO x ) is used, the composition ratio of oxygen in the silicon oxide used as the second insulating layer IL2 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the third insulating layer IL3. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the second insulating layer IL2.

[0072] In order to form an insulating layer with few defects as the second insulating layer IL2, the second insulating layer IL2 may be formed at a film formation temperature of 350° C. or higher. In addition, after forming the second insulating layer IL2, a process of implanting oxygen into a part of the second insulating layer IL2 may be performed. In this embodiment, in order to form an insulating layer with few defects as the second insulating layer IL2, silicon oxide is formed at a film formation temperature of 350° C. or higher.

[0073] Next, a metal oxide layer MO2 containing aluminum as a main component is formed on the second insulating layer IL2 ("MO2 formation" in step S1009 shown in FIG. 7).

[0074] The method of forming the metal oxide layer MO2 and the insulating material may refer to the description of the metal oxide layer MO1. By forming the metal oxide layer MO2, oxygen is implanted into the second insulating layer IL2. The film thickness of the metal oxide layer MO2 is, for example, 2 nm to 100 nm, 2 nm to 50 nm, 2 nm to 30 nm, or 2 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer MO2. Aluminum oxide has high barrier properties against gas. In this embodiment, the aluminum oxide used as the metal oxide layer MO2 suppresses outward diffusion of oxygen implanted into the second insulating layer IL2 during the formation of the metal oxide layer MO2.

[0075] For example, when the metal oxide layer MO2 is formed by sputtering, the process gas used in the sputtering remains in the film of the metal oxide layer MO2. For example, when Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer MO2. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer MO2.

[0076] A second insulating layer IL2 is formed on the oxide semiconductor layer POS, and a metal oxide layer MO2 is formed on the second insulating layer IL2. In this state, a heat treatment (oxidation annealing treatment) is performed to supply oxygen to the oxide semiconductor layer POS ("oxidation annealing treatment" in step S1010 shown in FIG. 7 and FIG. 13).

[0077] During the process from when the oxide semiconductor layer POS is formed until when the second insulating layer IL2 is formed on the oxide semiconductor layer POS, many oxygen defects are generated on the upper surface and side surface of the oxide semiconductor layer POS. By the above-mentioned oxidation annealing treatment, oxygen released from the first insulating layer IL1 is supplied to the upper surface and side surface of the oxide semiconductor layer POS, and the oxygen defects are repaired.

[0078] In the above-mentioned oxidation annealing treatment, the oxygen implanted into the second insulating layer IL2 is blocked by the metal oxide layer MO2, and is therefore prevented from being released into the atmosphere. Therefore, the oxygen is efficiently supplied to the oxide semiconductor layer POS by the oxidation annealing treatment, and oxygen defects are repaired.

[0079] Next, after the oxidation annealing treatment, the metal oxide layer MO2 is etched (removed) ("MO2 removal" in step S1011 shown in FIG. 7 and FIG. 14). Wet etching or dry etching may be used for etching the metal oxide layer MO2. For example, diluted hydrofluoric acid (DHF) is used for wet etching. The metal oxide layer MO2 formed on the entire surface is removed by this etching. In other words, the metal oxide layer MO2 is removed without using a mask. In further other words, the etching removes all of the metal oxide layer MO2 in the region overlapping with the oxide semiconductor layer POS formed in a certain pattern, at least in a plan view.

[0080] Next, the gate line GL is formed on the second insulating layer IL2 (Step S1012 “GL formation” shown in FIG. 7). For the film formation method and insulating material of the gate line GL, refer to the description of the light-shielding layer LS. The gate line GL is arranged along the first direction D1.

[0081] Next, impurities are added to the oxide semiconductor layer POS using the gate line GL as a mask (step S1013 “SA, DA formation” shown in FIG. 7 and FIG. 15). In this embodiment, a case where the impurities are added by ion implantation will be described, but the addition may be performed by ion doping.

[0082] Specifically, the source region SA and the drain region DA are formed by doping the oxide semiconductor layer POS with an impurity element through the second insulating layer IL2 by ion implantation. As the impurity element, for example, argon (Ar), phosphorus (P), or boron (B) may be used. When doping boron (B) by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the doping amount of boron (B) is set to 1×10 14 cm -2 More than 1×10 16 cm -2 The following would suffice.

[0083] The concentration of impurity elements contained in the source region SA and the drain region DA is 1×10 18 cm -3 More than 1×10 21 cm -3 In addition, the source region SA and the drain region DA are preferably 1×10 18 cm -3 More than 1×10 21 cm -3 If the following is present, it is presumed that impurity elements have been intentionally added by ion implantation or doping.

[0084] Next, the third insulating layer IL3 is deposited on the second insulating layer IL2 and the gate line GL (Step S1014 “IL3 Deposition” shown in FIG. 7). The deposition method and insulating material of the third insulating layer IL3 may be the same as those described for the first insulating layer IL1.

[0085] Next, a contact hole WCON reaching the source region SA is formed in the third insulating layer IL3. After that, a wiring W1 is formed on the third insulating layer IL3, and the wiring W1 is connected to the source region SA via the contact hole ZCON (step S1015 "W1 formation" shown in FIG. 7). For the film formation method and insulating material of the wiring W1, refer to the description of the light-shielding layer LS. The wiring W1 is arranged along the second direction D2.

[0086] Next, the fourth insulating layer IL4 is deposited on the third insulating layer IL3 and the wiring W1 (Step S1016 “IL4 Deposition” shown in FIG. 8). For the deposition method and insulating material of the fourth insulating layer IL4, refer to the description of the first insulating layer IL1.

[0087] Next, a contact hole ZCON reaching the drain region DA is formed in the fourth insulating layer IL4. After that, a connection electrode ZTCO is formed on the fourth insulating layer IL4 and the connection electrode ZTCO is connected to the drain region DA via the contact hole ZCON (Step S1017 “ZTCO Formation” shown in FIG. 8 and FIG. 16).

[0088] The connection electrode ZTCO is formed by processing a light-transmitting oxide conductive layer (also called a transparent conductive layer) formed by a sputtering method. A transparent conductive material such as a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO) can be used as the oxide conductive layer. A transparent conductive material other than the above may also be used as the oxide conductive layer.

[0089] Next, the fifth insulating layer IL5 is deposited on the fourth insulating layer IL4 and the connection electrode ZTCO (Step S1018 “Deposit IL5” shown in FIG. 8).

[0090] The fifth insulating layer is formed by applying and baking an organic insulating material. The organic insulating material may be an organic resin such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin. After that, a part of the fifth insulating layer is exposed to light and removed to form a contact hole PCON that exposes the connection electrode ZTCO.

[0091] Next, the pixel electrode PTCO is formed on the fifth insulating layer IL5, and the pixel electrode PTCO is connected to the connection electrode ZTCO through the contact hole PCON (step S1019 “PTCO formation” shown in FIG. 8). For the film formation method and transparent conductive material of the pixel electrode PTCO, refer to the description of the connection electrode ZTCO.

[0092] Next, the sixth insulating layer IL6 is deposited on the pixel electrode PTCO (Step S1020 “Deposit IL6” shown in FIG. 8).

[0093] The sixth insulating layer IL6 may be formed using the same method and insulating material as that of the first insulating layer IL1. The sixth insulating layer IL6 functions as a dielectric for forming a capacitance. The sixth insulating layer IL6 also functions as a first inorganic layer. The sixth insulating layer IL6 has a thickness of at least 30 nm, and is between 50 nm and 200 nm. In this embodiment, the sixth insulating layer IL6 is formed using silicon nitride.

[0094] Next, an opening IOP is formed in the sixth insulating layer IL6 (Step S1021 “IOP Formation” shown in FIG. 8 and FIG. 17). As described above, the opening IOP is provided to release moisture contained in the fifth insulating layer IL5.

[0095] The area of ​​the opening IOP is preferably less than 15% of the area of ​​the pixel. In other words, the coverage of the sixth insulating layer IL6 on the fifth insulating layer IL5 is 85% or more, preferably 90% or more, more preferably 95% or more of the area of ​​the pixel. The opening IOP is not limited to one per pixel, and may be multiple. In addition, when multiple openings IOP are provided per pixel, the total area of ​​the multiple openings IOP may be less than 15% of the area of ​​the pixel. The opening IOP is preferably provided in a region overlapping with the oxide semiconductor layer POS. In addition, the opening IOP is more preferably disposed in a region of the oxide semiconductor layer POS that overlaps with a region where the gate wiring overlaps (i.e., the channel region CA). By providing the opening IOP in the oxide semiconductor layer POS or in a region of the oxide semiconductor layer POS that overlaps with the channel region CA, moisture contained in the organic resin layer can be released to the outside by an annealing treatment described later, and the moisture contained in the organic resin layer can be suppressed from entering the oxide semiconductor layer POS. However, the position where the opening IOP is provided is not limited to the above position, and may be provided, for example, at a position overlapping the wiring W1 or at a position not overlapping the oxide semiconductor layer POS.

[0096] Next, in a state where the sixth insulating layer IL6 covers the fifth insulating layer IL5, an annealing treatment is performed (step S1022 "annealing treatment" shown in FIG. 8). The temperature of the annealing treatment is, for example, 150° C. or more and 300° C. or less. By performing the annealing treatment, moisture contained in the fifth insulating layer IL5 can be released.

[0097] Next, the common auxiliary electrode CMTL is formed on the sixth insulating layer IL6 (Step S1023 “FORM CMTL” shown in FIG. 8).

[0098] For the film formation method and conductive material of the common auxiliary electrode CMTL, refer to the description of the light-shielding layer LS. The common auxiliary electrode CMTL is formed in a lattice shape so as to overlap with the gate lines GL and the lines W1.

[0099] Next, a common electrode CTCO is formed on the sixth insulating layer IL6 and the common auxiliary electrode CMTL (step S1024 "CTCO formation" shown in FIG. 8 and FIG. 18). For the film formation method and transparent conductive material of the common electrode CTCO, refer to the description of the connection electrode ZTCO. The common electrode CTCO functions as a second inorganic layer. The film thickness of the common electrode CTCO may be at least 30 nm or more, and may be 50 nm or more and 200 nm or less. By forming the common electrode CTCO, the common electrode CTCO contacts the fifth insulating layer IL5 at the opening IOP. That is, the common electrode CTCO can block the opening IOP provided in the sixth insulating layer IL6. This can suppress moisture from being taken into the fifth insulating layer IL5 from the outside through the opening IOP.

[0100] Next, a spacer SP is formed on the common electrode CTCO (step S1025 "SP formation" shown in FIG. 8). The spacer SP is formed in the contact hole PCON. Finally, the array substrate manufactured as described above and the counter substrate on which the color filter and spacer are formed are bonded together via a sealant and a liquid crystal layer.

[0101] Through the above steps, the display device 10 according to one embodiment of the present invention can be manufactured.

[0102] In general, in an FFS type liquid crystal display device, a pixel electrode, a capacitance insulating layer, and a common electrode are laminated on an organic resin layer, or a common electrode, a capacitance insulating layer, and a pixel electrode are laminated. When a pixel electrode is provided on an organic resin layer, the pixel electrode is often arranged so as not to overlap with a source wiring or the like in order to suppress capacitive coupling between the pixel electrode and the wiring. In addition, a slit pattern may be provided on the pixel electrode. Therefore, the coverage rate of the pixel electrode covering the pixel is less than 85% of the pixel area. In addition, when a common electrode is provided on an organic resin layer, a slit pattern may be provided on the common electrode, or an opening may be provided above the transistor. Therefore, the coverage rate of the pixel electrode covering the pixel is less than 85% of the pixel area. Therefore, even if an annealing process is performed with a pixel electrode or a common electrode disposed on the organic resin layer, moisture can be released from the organic resin layer, but moisture is re-absorbed in the subsequent process. The moisture contained in the organic resin layer penetrates into the oxide semiconductor layer, causing the characteristics of the transistor to fluctuate.

[0103] In addition, in an FFS-type liquid crystal display device, a capacitive insulating layer is provided on the entire surface of the organic resin layer, on the pixel electrode or the common electrode, so as to cover the active region. Even if an annealing process is performed with the capacitive insulating layer formed on the entire surface, the moisture contained in the organic resin layer is blocked by the capacitive insulating layer and the pixel electrode, and the moisture cannot be released from the organic resin layer. Therefore, if excess moisture remains in the organic resin layer, the moisture will penetrate into the oxide semiconductor layer, causing the transistor characteristics to fluctuate.

[0104] In the manufacturing method of the display device according to the embodiment of the present invention, the moisture contained in the fifth insulating layer IL5 made of organic resin is sufficiently released from the opening IOP formed in the first inorganic layer by annealing, and then the opening IOP is blocked by the second inorganic layer. This makes it possible to maintain a state in which the amount of moisture contained in the organic resin layer is reduced. Therefore, it is possible to suppress the moisture contained in the organic resin layer from penetrating into the oxide semiconductor layer. This makes it possible to suppress the fluctuation of the transistor characteristics, thereby improving the reliability of the display device.

[0105] [7. Crystal structure of oxide semiconductor layer] The oxide semiconductor layer POS described in this embodiment includes a Poly-OS. The crystal grains included in the Poly-OS observed from the top surface of the oxide semiconductor layer POS (or the thickness direction of the oxide semiconductor layer POS) have a crystal grain size of 0.1 μm or more, preferably 0.3 μm or more, and more preferably 0.5 μm or more. The crystal grain size of the crystal grains can be obtained, for example, by cross-sectional SEM observation, cross-sectional TEM observation, or an electron backscattered diffraction (EBSD) method.

[0106] In the Poly-OS, a plurality of crystal grains may have one type of crystal structure or a plurality of types of crystal structures. The crystal structure of the Poly-OS can be identified by an electron beam diffraction method, an XRD method, or the like. That is, the crystal structure of the oxide semiconductor layer POS can be identified by an electron beam diffraction method, an XRD method, or the like.

[0107] The crystal structure of the oxide semiconductor layer POS is preferably a cubic crystal. The cubic crystal structure has high symmetry, and even if oxygen defects are generated in the oxide semiconductor layer POS, structural relaxation is unlikely to occur, and the crystal structure is stable. As described above, by increasing the ratio of the indium element, the crystal structure of each of the multiple crystal grains is controlled, and the oxide semiconductor layer POS having a cubic crystal structure can be formed.

[0108] In the transistor including the oxide semiconductor layer POS manufactured by the above manufacturing method, when the channel length L of the channel region CA is in the range of 2 μm to 4 μm and the channel width of the channel region CA is in the range of 2 μm to 25 μm, the mobility is 50 [cm 2 / Vs] or more, 55[cm 2 / Vs] or more, or 60 [cm 2 / Vs] or more can be obtained. The mobility in this embodiment means the field effect mobility in the saturation region of the transistor, and refers to the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the transistor from the voltage (Vg) supplied to the gate electrode.

[0109] In the process of forming the transistor Tr, the formation of the metal oxide layer MO1 provided under the oxide semiconductor layer POS may be omitted. In this case, the processes of step S1003 and step S1007 shown in FIG. 7 may be omitted. In addition, in the process of forming the transistor Tr, the process of performing an annealing treatment after forming the metal oxide layer MO2 on the second insulating layer IL2 may be omitted. In this case, the processes of step S1009 and step S1011 shown in FIG. 7 may be omitted. Even when the formation of the metal oxide layer MO1 or the formation of the metal oxide layer MO2 is omitted, a good Poly-OS can be formed.

[0110] Even if the above steps are omitted in the process of forming a transistor, a Poly-OS can be formed. In a transistor using a Poly-OS as an oxide semiconductor layer POS, when the channel length L of the channel region CA is in the range of 2 μm to 4 μm and the channel width of the channel region CA is in the range of 2 μm to 25 μm, the mobility is 30 cm 2 / Vs or more, 35cm 2 / Vs or more, or 40cm 2 Electrical characteristics of at least / Vs can be obtained.

[0111] In addition, IGZO may be used instead of the oxide semiconductor layer POS. Even when IGZO is used as the oxide semiconductor material, it is preferable to perform an annealing process in a state where an opening is formed in the first inorganic layer provided on the fifth insulating layer IL5 made of an organic resin, so that moisture contained in the organic resin layer is released from the opening. Then, by forming a second inorganic layer so as to close the opening, it is possible to suppress the intake of moisture from the outside into the organic resin layer, and to suppress the fluctuation of the transistor characteristics. This can improve the reliability of the display device.

[0112] [8. Variation 1] In Modification 1, a display device 10A that is partially different from the display device shown in Fig. 4 will be described with reference to Fig. 19. Fig. 19 shows a structure in which an opening IOP provided in a sixth insulating layer IL6 is closed with a seventh insulating layer IL7.

[0113] In the display device 10A shown in FIG. 19, a sixth insulating layer IL6 and a seventh insulating layer IL7 are provided between the pixel electrode PTCO and the common electrode CTCO. The common electrode CTCO has a slit pattern in an area overlapping with the pixel electrode PTCO. The description of the first insulating layer IL1 may be referred to for the film formation method and insulating material of the seventh insulating layer IL7. The thicknesses of the sixth insulating layer IL6 and the seventh insulating layer IL7 may be appropriately set according to the capacitance of the storage capacitor 890. The thickness of the seventh insulating layer IL7 may be smaller than the thickness of the sixth insulating layer IL6. The common electrode CTCO is provided on the seventh insulating layer IL7. If the thicknesses of the seventh insulating layer IL7 and the common electrode CTCO are at least 30 nm or more and 50 nm or more and 200 nm or less, respectively, it is possible to suppress the intake of moisture from the outside. In the first modification, it is sufficient to include at least the sixth insulating layer IL6 as the first inorganic layer, and it is sufficient to include at least the seventh insulating layer IL7 as the second inorganic layer.

[0114] [9. Variation 2] In the second modification, a display device 10B that is partially different from the display device 10 shown in Fig. 4 will be described with reference to Fig. 20. Fig. 20 shows a structure in which an opening IOP provided in a sixth insulating layer IL6 is covered with a common auxiliary electrode CMTL. In addition, a color filter CF is provided between a fourth insulating layer IL4 and a fifth insulating layer IL5.

[0115] In the display device 10B shown in FIG. 20, an opening IOP provided in the sixth insulating layer IL6 is provided above the wiring W1. In this embodiment, a common auxiliary electrode CMTL is provided above the wiring W1. Therefore, the opening IOP may be blocked by the common auxiliary electrode CMTL. In addition, a common electrode CTCO is provided on the sixth insulating layer IL6 and the common auxiliary electrode CMTL. If the thickness of the common auxiliary electrode CMTL is at least 30 nm or more, 50 nm or more and 200 nm or less, it is possible to suppress the intake of moisture from the outside. In the second modification, it is sufficient to include at least the sixth insulating layer IL6 as the first inorganic layer, and to include at least the common auxiliary electrode CMTL as the second inorganic layer. This makes it possible to suppress the opening IOP and the intake of moisture from the outside.

[0116] In a liquid crystal display device, when a color filter is provided on the counter substrate, misalignment may occur when the array substrate on which transistors and the like are formed and the counter substrate are bonded together. In a high-definition liquid crystal display device used for VR and the like, a slight misalignment between the pixels of the array substrate and the color filter of the counter substrate reduces the display quality of the display device. Therefore, by forming a color filter CF between the fourth insulating layer IL and the fifth insulating layer IL5, it is possible to suppress misalignment between the array substrate and the color filter when bonding the array substrate and the counter substrate together. In addition, the color filter CF is also formed of an organic resin, and therefore contains moisture. The moisture contained in the color filter CF and the moisture contained in the fifth insulating layer IL5 are released from the opening IOP formed in the sixth insulating layer IL6 by annealing, and then the opening IOP is blocked by the common auxiliary electrode CMTL, thereby suppressing moisture from being taken in again from the outside into the opening IOP, the fifth insulating layer IL5, and the color filter CF.

[0117] Although not shown, a configuration in which a color filter CF is provided between the fourth insulating layer IL4 and the fifth insulating layer IL5 may also be applied to the display devices shown in Figures 4 and 19, and to the display devices shown in Figures 21 and 22 described later.

[0118] [10. Variation 3] In the third modification, a display device 10C that is partially different from the display device 10 shown in Fig. 4 will be described with reference to Fig. 21. Fig. 21 shows a configuration in which a capacitive electrode CTCO1 is provided on a fifth insulating layer IL5.

[0119] In the display device 10C shown in FIG. 21, a capacitive electrode CTCO1 is provided on a fifth insulating layer IL5. A storage capacitor is formed by the capacitive electrode CTCO1, a sixth insulating layer IL6, and a pixel electrode PTCO, and a storage capacitor is formed by the pixel electrode PTCO, a seventh insulating layer IL7, and a common electrode CTCO2. Since the sixth insulating layer IL6 is provided on the capacitive electrode CTCO1, the coverage of the fifth insulating layer IL5 by the capacitive electrode CTCO1 may be less than 85% of the area of ​​the pixel. An opening may be provided in the capacitive electrode CTCO1.

[0120] A sixth insulating layer IL6 is provided on the capacitive electrode CTCO1. The coverage of the sixth insulating layer IL6 on the fifth insulating layer IL5 is preferably 85% or more of the area of ​​the pixel. The opening IOP may overlap with an opening provided in the capacitive electrode CTCO1. A seventh insulating layer IL7 is provided on the sixth insulating layer IL6. The seventh insulating layer IL7 is provided so as to cover the opening IOP and the opening provided in the capacitive electrode CTCO1. Therefore, the seventh insulating layer IL7 contacts the fifth insulating layer IL5 at the opening.

[0121] In addition, a common electrode CTCO2 is provided on the seventh insulating layer IL7. FIG. 21 shows an example in which the opening provided in the capacitive electrode CTCO1 and the opening IOP overlap, but is not limited thereto. The opening IOP may be formed in the sixth insulating layer IL6 without forming an opening in the capacitive electrode CTCO1. In the third modification, it is sufficient to include at least the sixth insulating layer IL6 as the first inorganic layer, and to include at least the seventh insulating layer IL7 as the second inorganic layer.

[0122] The seventh insulating layer IL7 may have a thickness of at least 30 nm, and may have a thickness of 50 nm to 200 nm. The method of forming the capacitance electrode CTCO1 and the common electrode CTCO2 and the transparent conductive material may refer to the description of the connection electrode ZTCO. The thickness of the capacitance electrode CTCO1 and the common electrode CTCO2 may have a thickness of at least 30 nm, and may have a thickness of 50 nm to 200 nm.

[0123] [11. Variation 4] In the fourth modification, a display device 10D that is partially different from the display device 10 shown in Fig. 4 will be described with reference to Fig. 22. In the display device 10, the wiring W1 and the connection electrode ZTCO that functions as a drain electrode are provided on different insulating layers, but the wiring W1 and the connection electrode ZTCO may be provided on the same insulating layer.

[0124] In the display device 10D shown in FIG. 22, the fourth insulating layer IL4 is omitted, and the wiring W1 and the drain electrode DE are provided on the third insulating layer IL3. A fifth insulating layer IL5 is provided on the wiring W1 and the drain electrode DE, and a contact hole PCON is formed in the fifth insulating layer IL5. A pixel electrode PTCO is provided on the fifth insulating layer IL5, and the pixel electrode PTCO is connected to the pixel electrode PTCO and the drain electrode DE through the contact hole PCON. A sixth insulating layer IL6 is provided on the fifth insulating layer IL5 and the pixel electrode PTCO. An opening IOP is provided in the sixth insulating layer IL6. The opening IOP is blocked by a common electrode CTCO provided on the sixth insulating layer IL6. In the third modification, it is sufficient to include at least the sixth insulating layer IL6 as the first inorganic layer, and to include the common electrode CTCO as the second inorganic layer.

[0125] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. In addition, a display device according to any of the embodiments may be combined as appropriate by a person skilled in the art to add or remove components or modify the design, or to add or omit steps or modify conditions, and the combination is included in the scope of the present invention as long as it includes the gist of the present invention.

[0126] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0127] 10, 10A to 10D: display device, 22: liquid crystal region, 24: sealing region, 26: terminal region, 300: array substrate, 310: pixel, 320: source driver circuit, 321: source wiring, 330: gate driver circuit, 331: gate wiring, 333: terminal section, 341: connection wiring, 342: connection wiring, 400: sealing section, 410: liquid crystal element, 500: counter substrate, 600: flexible printed circuit board, 700: IC chip, 800: transistor, 810: gate electrode, 830: source electrode, 840: drain electrode, 890: storage capacitance, AOS: oxide semiconductor layer, CA: channel region, CMTL: common Auxiliary electrode, CON1, CON2: second contact region, CTCO: common electrode, DA: drain region, IL1: first insulating layer, IL2: second insulating layer, IL3: third insulating layer, IL4: fourth insulating layer, IL5: fifth insulating layer, IL6: sixth insulating layer, IL7: seventh insulating layer, LS: light-shielding layer, LS1: light-shielding layer, LS2: light-shielding layer, MO1, MO2: metal oxide layer, OS: oxide semiconductor layer, PCON: contact hole, POS: oxide semiconductor layer, PTCO: pixel electrode, SA: source region, SP: spacer, SUB: substrate, W1: wiring, WCON: contact hole, ZCON: contact hole, ZTCO: connection electrode

Claims

1. A display device including a plurality of pixels arranged in a matrix along a first direction and a second direction intersecting the first direction, Each of the plurality of pixels is a transistor including an oxide semiconductor layer, a gate wiring extending in the first direction opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first conductive layer provided on at least one first insulating layer on the transistor and in contact with the oxide semiconductor layer; a second insulating layer disposed on the first conductive layer; a first inorganic layer provided on the second insulating layer and having an opening; a second inorganic layer provided on the first inorganic layer and in contact with the second insulating layer in the opening; A display device, wherein a coverage of the first insulating layer by the first inorganic layer is 85% or more with respect to an area of ​​the pixel.

2. the first inorganic layer has a second transparent conductive layer and a first inorganic insulating layer provided on the second transparent conductive layer, the second transparent conductive layer is connected to the first conductive layer; The display device according to claim 1 , wherein the opening is provided in the first inorganic insulating layer.

3. the second inorganic layer has a third transparent conductive layer; The display device according to claim 2 , wherein the third transparent conductive layer is in contact with the second insulating layer at the opening and has a slit pattern in a region overlapping with the second transparent conductive layer.

4. The second inorganic layer has a second inorganic insulating layer, The display device according to claim 2 , wherein the second inorganic insulating layer is in contact with the second inorganic insulating layer at the opening.

5. the second inorganic layer further includes a fourth transparent conductive layer provided on the second inorganic insulating layer, The display device according to claim 4 , wherein the fourth transparent conductive layer has a slit pattern in an area overlapping with the second transparent conductive layer.

6. the second inorganic layer includes a metal layer; The display device according to claim 2 , wherein the metal layer is in contact with the second insulating layer in the opening.

7. the first inorganic layer includes a first inorganic insulating layer and a second transparent conductive layer provided on the first inorganic insulating layer; the second transparent conductive layer is connected to the first conductive layer through a contact hole provided in the first inorganic insulating layer; The display device according to claim 1 , wherein the opening is provided in the first inorganic insulating layer.

8. The second inorganic layer has a second inorganic insulating layer, The display device according to claim 7 , wherein the second inorganic insulating layer is in contact with the second inorganic insulating layer at the opening.

9. a first wiring provided between the transistor and the first conductive layer and in contact with the oxide semiconductor layer; The display device according to claim 1 , wherein the first conductive layer is light-transmitting.

10. a first wiring provided on the first insulating layer and in contact with the oxide semiconductor layer; The display device according to claim 1 , wherein the first wiring is provided along the second direction.

11. The display device according to claim 1 , wherein the opening is provided in a region overlapping the oxide semiconductor layer.

12. The display device according to claim 1 , wherein the opening is disposed in a region of the oxide semiconductor layer that overlaps with a region of the gate line.

13. The display device according to claim 1 , wherein the oxide semiconductor layer has a polycrystalline structure.

14. The display device according to claim 1 , further comprising an aluminum oxide layer between the gate insulating layer and the oxide semiconductor layer.

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