Semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device allowing diagnosis of a state of a bonding wire and a connection state of the bonding wire and a bonding pad without checking the internal state.SOLUTION: A semiconductor integrated circuit device 100 comprises: a lead frame terminal 111; a diagnostic input-side bonding pad 121A and a diagnostic output-side bonding pad 121B on a semiconductor substrate 120; bonding wires 131A, 131B connected to one another so as to series connect a path from the bonding pads 121A to 121B with the lead frame terminal 111 as a relay point; an input signal switch circuit 140 for supplying a DC voltage of specified value to the diagnostic input-side bonding pad 121A; and a determination circuit 150 connected to the diagnostic output-side bonding pad 121B and outputting an error signal when electrical resistance of the path from the bonding pads 121A to 121B exceeds a specified value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a diagnostic circuit capable of detecting the connection state of bonding wires. [Background technology]

[0002] There is a wire bonding technology that electrically connects electrodes on an integrated circuit to electrodes on a printed circuit board or semiconductor package using fine metal wires, i.e., bonding wires. In large-scale integrated circuits that employ packages using bonding wires, the bonding wires and bonding pads are sealed with molding resin, making it impossible to check the internal state from the outside.

[0003] Instead of using precious metal thin wires mainly composed of expensive gold, inexpensive copper is sometimes used as the main component of this bonding wire. For example, Patent Document 1 below discloses a bonding wire made of copper with a purity of 99.99% by weight or more as the base material, which contains 0.001 to 0.1% by weight of other elements. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 61-048543 Summary of the Invention [Problem to be solved by the invention]

[0005] However, bonding wires that are primarily made of copper can corrode or become unbonded due to factors such as temperature changes, vibration, stress, and the introduction of contaminants during manufacturing, which can disrupt the operation of large-scale integrated circuits.

[0006] In consideration of the above circumstances, the present invention aims to provide a semiconductor integrated circuit device that can diagnose the condition of the bonding wires and the connection condition between the bonding wires and the bonding pads without peeling off the molding resin of the semiconductor package to check the internal condition. [Means for solving the problem]

[0007] In order to solve the above problems, a semiconductor integrated circuit device of the present invention comprises a first electrode provided on a semiconductor package, a second electrode and a third electrode formed on an integrated circuit, thin metal wires connecting the first electrode to the second electrode, and the first electrode to the third electrode, respectively, so that a path from the second electrode to the third electrode is in series with the first electrode as a relay point, an input signal switch circuit connected to the second electrode and supplying a DC voltage of a predetermined voltage value to the second electrode when diagnosing the connection state of the thin metal wires, and a judgment circuit connected to the third electrode and outputting an error signal when the electrical resistance of the path from the second electrode to the third electrode exceeds a predetermined value. Effect of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor integrated circuit that can diagnose the state of the bonding wires and the connection state between the bonding wires and the bonding pads without peeling off the molding resin of the semiconductor package to check the internal state. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a semiconductor integrated circuit device including a diagnostic circuit capable of detecting the connection state of a bonding wire according to a first embodiment. [Diagram 2] 2 is a timing chart showing potential levels of various parts of the semiconductor integrated circuit device of FIG. 1. [Diagram 3] 11 is a schematic diagram of a semiconductor integrated circuit device including a diagnostic circuit capable of detecting the connection state of a bonding wire according to a second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0011] [Embodiment 1] Fig. 1 is a schematic diagram of a semiconductor integrated circuit device 100 equipped with a diagnostic circuit capable of detecting the connection state of a bonding wire according to embodiment 1. As shown in Fig. 1, the semiconductor integrated circuit device 100 has a semiconductor package 110 and a semiconductor substrate 120 sealed in the semiconductor package 110. A plurality of lead frame terminals 111, 112, 113... are formed on the semiconductor package 110.

[0012] A diagnostic input side bonding pad 121A which is a second electrode, and a diagnostic output side bonding pad 121B which is a third electrode are formed on the semiconductor substrate 120. The semiconductor substrate 120 further has bonding pads 122, 123, . . . formed thereon.

[0013] Lead frame terminal 111 and diagnostic input side bonding pad 121A are connected by first bonding wire 131A formed of a thin metal wire. Lead frame terminal 111 and diagnostic output side bonding pad 121B are connected by second bonding wire 131B formed of a thin metal wire. In other words, first bonding wire 131A and second bonding wire 131B are connected so that the path from diagnostic input side bonding pad 121A to diagnostic output side bonding pad 121B is in series with lead frame terminal 111 as the relay point.

[0014] An input signal switch circuit 140 provided on the semiconductor substrate 120 is connected to the diagnostic input side bonding pad 121A. The input signal switch circuit 140 supplies a DC voltage of a preset voltage value to the second electrode when diagnosing the connection state of the bonding wires 131A, 131B, 132, and 133. A determination circuit 150 also provided on the semiconductor substrate 120 is connected to the diagnostic output side bonding pad 121B. The determination circuit 150 outputs an error signal when the electrical resistance of a path from the diagnostic input side bonding pad 121A to the diagnostic output side bonding pad 121B via the lead frame terminal 111 exceeds a predetermined value.

[0015] Furthermore, the lead frame terminal 112 and the bonding pad 122 are connected by a bonding wire 132 , and the lead frame terminal 113 and the bonding pad 123 are connected by a bonding wire 133 .

[0016] The lead frame terminal 111 is used as a first electrode, which is not connected to any external circuits, etc. when the semiconductor integrated circuit device 100 is in use, and is used as an unconnected terminal used only for diagnosing the connection status of the bonding wire.

[0017] Meanwhile, the lead frame terminals 112, 113 are connected to an external circuit (not shown), and the bonding pads 122, 123 are each connected to an integrated circuit (not shown) formed on the semiconductor substrate 120, but a detailed description thereof will be omitted.

[0018] The bonding pads 121A, 121B, 122, and 123 are connected to the bonding wires 131A, 131B, 132, and 133 by using various wire bonding techniques, such as thermocompression bonding techniques such as wedge bonding or nail head bonding (ball bonding), ultrasonic bonding, or a combination of these techniques.

[0019] The input signal switch circuit 140 includes an inverter circuit 141 and a PMOS transistor 142 having a gate input that receives the output of the inverter circuit 141, a source connected to a DC power supply voltage VDD, and a drain connected to the diagnostic input side bonding pad 121A. The input node of the input signal switch circuit 140 is an EN (Enable) node 143, and the output is an OUT node 144 connected to the diagnostic input side bonding pad 121A.

[0020] The judgment circuit 150 includes a resistive element 152 connected between an AIN node 151 connected to the diagnostic output side bonding pad 121B and ground GND, and an inverter circuit 154 connected between the AIN node 151 and an output ERR node 153.

[0021] Here, the resistance value of the first bonding wire 131A is R1, the resistance value of the second bonding wire 131B is R2, the on-resistance value of the PMOS transistor 142 is P1, and the resistance value of the resistive element 152 is R3. In this case, the on-resistance value P1 of the PMOS transistor 142 is set to a value sufficiently smaller than the resistance value R3 of the resistive element 152. For example, the on-resistance value P1 of the PMOS transistor 142 is set to 100Ω, and the resistance value R3 of the resistive element 152 is set to 1 kΩ. Furthermore, in a normal state, the resistance value R1 of the first bonding wire 131A and the resistance value R2 of the second bonding wire 131B are both about 1 mΩ, which are extremely small compared to the on-resistance value P1 of the PMOS transistor 142 and the resistance value R3 of the resistive element 152.

[0022] Next, a method for diagnosing the connection state of the bonding wires 131A, 131B, 132, and 133 in the semiconductor integrated circuit device 100 will be described. As shown in FIG. 2, the input signal level of the EN node 143 of the inverter circuit 141 of the input signal switch circuit 140 is changed from the "L" level to the "H" level (T in FIG. 2). 212). Then, the gate input of the PMOS transistor 142 becomes "H" level, and the source and drain of the PMOS transistor 142 become conductive. Therefore, the output level of the OUT node 144 of the input signal switch circuit 140 becomes approximately equal to the DC power supply voltage VDD (T 22 ), a test voltage is applied to the diagnostic input side bonding pad 121 A. The value of the test voltage is not exactly the same as the potential of the DC power supply voltage VDD, but is approximately equal to or slightly lower than the potential of the DC power supply voltage VDD.

[0023] Here, a case will be described in which first bonding wire 131A and second bonding wire 131B are normally connected to lead frame terminal 111, diagnostic input side bonding pad 121A, and diagnostic output side bonding pad 121B.

[0024] At this time, the potential of the AIN node 151 of the determination circuit 150 is AIN=VDD×(R3 / (P1+R1+R2+R3)). For example, if the DC power supply voltage VDD is 5V, R3 is 1 kΩ, and P1 is 100Ω as described above, R1 and R2 are about 1 mΩ, which is sufficiently small and can be ignored, and the potential AIN of the AIN node 151 is 4.5V (T in FIG. 2). 23 ).

[0025] Therefore, since an "H" level signal is input to the inverter circuit 154, the output of the inverter circuit 154 becomes "L" level, and the output of the output ERR node 153 of the decision circuit 150 becomes "L" level (T 24 ). As a result, it is determined that the first bonding wire 131A and the second bonding wire 131B are normally connected. Based on this determination result, it is also assumed that the other bonding wires 132 and 133 are normally connected.

[0026] On the other hand, a case where an abnormality occurs in either or both of the first bonding wire 131A and the second bonding wire 131B will be described. Cases where an abnormality occurs include, for example, when the bonding wire is corroded, when the bonding wire is peeling off the bonding pad, when the bonding wire is chipped, etc. In such cases, the resistance value of the first bonding wire 131A and the second bonding wire 131B increases, for example, to about 1 kΩ.

[0027] In this case, the potential of the AIN node 151 of the decision circuit 150 is 2.5 V if the DC power supply voltage VDD is 5 V, R3 is 1 kΩ, P1 is 100 Ω as described above, and R1+R2 is 1 kΩ (T in FIG. 2). 25 2. Since the input potential of the inverter circuit 154 is lower than the threshold value, for example, 3V, the output of the inverter circuit 154 becomes the "H" level. As a result, the output of the output ERR node 153 of the decision circuit 150 becomes the "H" level (T 26 ), it can be detected that the first bonding wire 131A and the second bonding wire 131B are not normally connected.

[0028] Based on the diagnosis result, it is also assumed that there is a possibility that other bonding wires 132, 133 are not connected normally. In the semiconductor integrated circuit device 100 of the above-mentioned embodiment 1, it is possible to diagnose the connection state of the bonding wires without applying a voltage from the outside to the lead frame terminal 111 to which the first bonding wire 131A and the second bonding wire 131B are connected.

[0029] [Embodiment 2] In the above-mentioned embodiment 1, the case where the input signal switch circuit 140 is a dedicated input circuit for detecting the connection state of the bonding wires has been described. Then, this input signal switch circuit 140 and the determination circuit 150 are connected to the lead frame terminal 111 by the first bonding wire 131A and the second bonding wire 131B. Furthermore, the case where the lead frame terminal 111 is an unconnected terminal that is not connected to an external circuit during use has been described. On the other hand, in embodiment 2, a case where an output transistor of a general-purpose input / output port 160 is used as the input signal switch circuit will be described.

[0030] The semiconductor integrated circuit device 100 of the second embodiment differs from the semiconductor integrated circuit device 100 of the first embodiment only in that it uses a general-purpose input / output port 160 as an input signal switch circuit. Therefore, the same components are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0031] 3, the input signal switch circuit of the second embodiment is configured by a general-purpose input / output port 160. This general-purpose input / output port 160 includes an output buffer 162 connected to an output control circuit 161.

[0032] The output buffer 162 is composed of a PMOS transistor 163 and an NMOS transistor 164. The output of the output control circuit 161 is connected to the gates of the PMOS transistor 163 and the NMOS transistor 164, respectively, so that the PMOS transistor 163 and the NMOS transistor 164 can be controlled individually. In addition, the source of the PMOS transistor 163 is connected to a DC power supply voltage VDD, and the source of the NMOS transistor 164 is connected to ground GND. The drains of the PMOS transistor 163 and the NMOS transistor 164 are connected to each other and to the OUT node 144 of the input signal switch circuit.

[0033] The output control circuit 161 controls the PMOS transistor 163 and the NMOS transistor 164 in response to an instruction from the internal integrated circuit, and selectively outputs an "H" level, an "L" level, or HZ (high impedance) to the OUT node 144. Here, the on-resistance value P2 of the PMOS transistor 163 is set to 1 kΩ-100 kΩ. Meanwhile, the resistance value of the resistive element 152 connected between the AIN node 151 of the determination circuit 150 and the ground GND is set to a value approximately 10 times larger than the on-resistance value P2. For example, when the on-resistance value P2 is 100 kΩ, the resistance value of the resistive element 152 is set to 1 MΩ.

[0034] A method for diagnosing the connection state of the bonding wires 131A, 131B, 132, and 133 in the semiconductor integrated circuit device 100 of the second embodiment will be described. First, the output transistor of the general-purpose input / output port 160 is turned on in response to an instruction from the internal integrated circuit. That is, the output control circuit 161 of the general-purpose input / output port 160 turns on the PMOS transistor 163 of the output buffer 162 and turns off the NMOS transistor 164 in response to an instruction from the internal integrated circuit. Then, the output level of the OUT node 144 becomes the "H" level, and a test voltage is applied to the diagnosis input side bonding pad 121A. The value of the test voltage is not exactly the same as the potential of the DC power supply voltage VDD, but is approximately equal to or slightly lower than the potential of the DC power supply voltage VDD.

[0035] Here, a case will be described in which first bonding wire 131A and second bonding wire 131B are normally connected to lead frame terminal 111, diagnostic input side bonding pad 121A, and diagnostic output side bonding pad 121B.

[0036] At this time, the potential of AIN node 151 of decision circuit 150 is AIN=VDD×(R3 / (P2+R1+R2+R3)). For example, if the power supply voltage VDD is 5V, R3 is 1MΩ, and P2 is 100kΩ as described above, then R1 and R2 are about 1mΩ, which is sufficiently small that they can be ignored, and the potential AIN of AIN node 151 is about 4.5V.

[0037] Therefore, since an "H" level signal is input to the inverter circuit 154, the output of the inverter circuit 154 becomes "L" level, and the output of the output ERR node 153 of this determination circuit 150 becomes "L" level. As a result, it is determined that the first bonding wire 131A and the second bonding wire 131B are normally connected. Also, it is presumed that the other bonding wires 132 and 133 are normally connected based on this determination result.

[0038] On the other hand, a case where an abnormality occurs in either or both of the first bonding wire 131A and the second bonding wire 131B will be described. For example, when the first bonding wire 131A and the second bonding wire 131B are disconnected, the resistance value increases to, for example, about 1 MΩ.

[0039] In this case, the potential of the AIN node 151 of the decision circuit 150 is about 2.4V if the power supply voltage VDD is 5V, R3 is 1MΩ, P2 is 100kΩ as described above, and R1+R2 is 1MΩ. If the threshold of the inverter circuit 154 is set to about 3V, the input potential of the inverter circuit 154 becomes lower than the threshold, and the output of the inverter circuit 154 becomes the "H" level. As a result, the output of the output ERR node 153 of the decision circuit 150 becomes the "H" level, making it possible to detect that the first bonding wire 131A and the second bonding wire 131B are not connected normally.

[0040] Based on this diagnosis result, it is also presumed that there is a possibility that the other bonding wires 132, 133 are not connected normally. Note that in the semiconductor integrated circuit device 100 of the above-mentioned embodiment 2, it is not necessary to occupy a lead frame terminal just to diagnose the connection state of the bonding wires as in embodiment 1. That is, since the input signal switch circuit of embodiment 2 uses a general-purpose input / output port 160, the lead frame terminal 111 connected to this OUT node 144 by the diagnosis input side bonding pad 121A can also be used as a terminal for connecting an external circuit.

[0041] As described above, the semiconductor integrated circuit device 100 of the first and second embodiments can detect a defect in a bonding wire when the bonding wire peels off or corrodes and the resistance of the bonding wire increases. Also, the connection state between the bonding wire and the bonding pad can be diagnosed without peeling off the molding resin of the semiconductor package to check the internal state. [Explanation of symbols]

[0042] 100 Semiconductor integrated circuit device 110 Semiconductor Package 111, 112, 113 Lead frame terminal 120 Semiconductor Substrate 121A Diagnostic Input Bonding Pad 121B Diagnostic output bonding pad 122, 123 Bonding pads 131A, 131B, 132, 133 Bonding wire 140 Input signal switch circuit 141 Inverter circuit 142 PMOS transistor 143 EN Nodes 144 OUT Node 150 Judgment circuit 151 AIN nodes 152 Resistance element 153 Output ERR node 154 Inverter circuit 160 general purpose input / output ports 161 Output control circuit 162 Output Buffer 163 PMOS transistors 164 NMOS transistor

Claims

1. a first electrode provided on the semiconductor package; a second electrode and a third electrode formed on the integrated circuit; thin metal wires connecting the first electrode and the second electrode, and connecting the first electrode and the third electrode, respectively, such that paths from the second electrode to the third electrode are in series with the first electrode as a relay point; an input signal switch circuit connected to the second electrode and configured to supply a DC voltage of a preset voltage value to the second electrode when diagnosing the connection state of the thin metal wire; a determination circuit connected to the third electrode and configured to output an error signal when an electrical resistance of a path from the second electrode to the third electrode exceeds a predetermined value.

2. 2. The semiconductor integrated circuit device according to claim 1, wherein the input signal switch circuit includes an inverter circuit and a PMOS transistor having an output of the inverter circuit as a gate input, a source connected to a DC power supply voltage, and a drain connected to the second electrode, and applies a test voltage to the second electrode by setting the output of the inverter circuit to an "H" level.

3. 2. The semiconductor integrated circuit device according to claim 1, wherein the input signal switch circuit uses an output transistor of a general-purpose input / output port, and applies a test voltage to the second electrode by turning on the output transistor when diagnosing the connection state of the thin metal wire.

4. 4. The semiconductor integrated circuit device according to claim 1, wherein the determination circuit includes a resistor connected between the third electrode and a ground, and an inverter circuit connected between the third electrode and an output node.

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