ESD protection circuit and semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device including an ESD protection circuit that can be activated at low voltage.SOLUTION: An ESD protection circuit 110 includes an RC time constant circuit 120 connected in series between a power source wire 111 and a ground wire 112, an inverter circuit 130 whose input exists between a capacitor element 122 and a resistor element 121 included in the RC time constant circuit 120, and which is connected between the power source wire 111 and the ground wire 112, and a clamp NMOS transistor 140 whose gate input is the output of the inverter circuit 130 and whose drain is connected to the power source wire 111 and source and back gate are connected to the ground wire 112. The inverter circuit 130 includes a PMOS transistor 131 and an NMOS transistor 133 connected in series between the power source wire 111 and the ground wire 112, and a resistor element 132 for preventing breakage connected between a drain of the NMOS transistor 133 and an output of the inverter circuit 130.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a protection circuit against high voltage fluctuations and a semiconductor integrated circuit device having the protection circuit, and more particularly to an ESD protection circuit that operates at a low voltage and releases electrostatic discharge surges (hereinafter referred to as ESD surges), and a semiconductor integrated circuit device having the ESD protection circuit. [Background technology]

[0002] Semiconductor integrated circuit devices may be adversely affected by ESD surges, such as being damaged or malfunctioning. The following Patent Document 1 discloses a conventional ESD protection circuit that, when an ESD surge enters a circuit, directs the ESD surge to ground.

[0003] The ESD protection circuit disclosed in Patent Document 1 is composed of an RC series circuit composed of a resistor element and a capacitor element, a CMOS inverter, and a clamping NMOS transistor. In this ESD protection circuit, when an ESD surge occurs, the output of the CMOS inverter becomes "H" level, opening the channel path of the clamping NMOS transistor and allowing the ESD surge current to flow to the ground wiring. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-55102 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the invention disclosed in Patent Document 1, the PMOS transistor and NMOS transistor that constitute the CMOS inverter for controlling the clamp NMOS transistor must be designed to be robust so as not to be destroyed by an ESD surge. In other words, the on-resistance, which is the resistance between the drain and source when the PMOS transistor is turned on, cannot be made small. If the on-resistance is large, it takes time for the PMOS transistor to turn on in response to a voltage jump in the power supply wiring, resulting in a problem that it takes time for the ESD protection circuit to start up and the start-up voltage becomes high.

[0006] Therefore, in view of the above circumstances, an object of the present invention is to provide an ESD protection circuit that can be started up at a lower voltage. [Means for solving the problem]

[0007] In order to solve the above problems, the ESD protection circuit of the present invention includes an RC time constant circuit connected in series between a power supply wiring and a ground wiring, an inverter circuit having an input between a resistance element and a capacitor element constituting the RC time constant circuit and connected between the power supply wiring and the ground wiring, and a clamp NMOS transistor having an output of the inverter circuit as a gate input and having a drain connected to the power supply wiring and a source and a back gate connected to the ground wiring, respectively, wherein the inverter circuit has a PMOS transistor and an NMOS transistor connected in series between the power supply wiring and the ground wiring, and a first resistance element connected between the drain of the NMOS transistor and the output of the inverter circuit. Effect of the Invention

[0008] The present invention has an effect of providing an ESD protection circuit that can be started up at a lower voltage. [Brief description of the drawings]

[0009] [Figure 1]FIG. 1 is a schematic diagram illustrating a semiconductor integrated circuit including an ESD protection circuit according to a comparative example. [Diagram 2] 1 is a schematic explanatory diagram of a semiconductor integrated circuit device including an ESD protection circuit according to a first embodiment. [Diagram 3] FIG. 11 is a schematic explanatory diagram of a semiconductor integrated circuit device including an ESD protection circuit according to a second embodiment. [Figure 4] FIG. 11 is a schematic explanatory diagram of a semiconductor integrated circuit device including an ESD protection circuit according to a third embodiment. [Diagram 5] FIG. 5(A) is a schematic diagram of a semiconductor integrated circuit device including an ESD protection circuit according to the fourth embodiment, and FIG. 5(B) is a diagram illustrating the operation of the ESD protection circuit of FIG. 5(A). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

[0011] 1, a semiconductor integrated circuit device 500 including an ESD protection circuit 510 of a comparative example will be described. The semiconductor integrated circuit device 500 of the comparative example includes an internal circuit 505 and an ESD protection circuit 510. The internal circuit 505 and the ESD protection circuit 510 are connected to a power supply wiring 511 and a ground wiring 512. The power supply wiring 511 is connected to a power supply voltage VDD, and the ground wiring 512 is connected to a ground terminal GND.

[0012] The ESD protection circuit 510 is a GCNMOS (Gate Control NMOS) type ESD protection circuit including an RC time constant circuit 520, an inverter circuit 530, and a wide-gate clamp NMOS transistor 540. This ESD protection circuit 110 is also called an active clamp or RC timer type protection circuit.

[0013] The RC time constant circuit 520 is composed of a resistor element 521 and a capacitor element 522 connected in series between a power supply wiring 511 and a ground wiring 512. The inverter circuit 530 is connected between the power supply wiring 511 and the ground wiring 512. The inverter circuit 530 is composed of a PMOS transistor 531 connected to the power supply wiring 511 side and an NMOS transistor 533 connected to the ground side.

[0014] The inverter circuit 530 receives an input from a node between the resistor element 521 and the capacitor element 522 that constitute the RC time constant circuit 520. The drain of the PMOS transistor 531 and the drain of the NMOS transistor 533 are connected to each other, and this connection node is used as the output node of the inverter circuit 530 and is connected to the gate of the clamp NMOS transistor 540.

[0015] In this ESD protection circuit 510, when an ESD surge occurs, the output of the inverter circuit 530 becomes “H” level, opening the channel path between the drain and source of the clamp NMOS transistor 540, allowing the ESD surge current to flow to the ground wiring.

[0016] However, in the ESD protection circuit 510 of the comparative example, the PMOS transistor 531 and the NMOS transistor 533 that configure the inverter circuit 530 need to be designed to be robust so as not to be destroyed by an ESD surge.

[0017] The reason is that when the drain potential of the NMOS transistor 533 rises as a result of the PMOS transistor 531 being turned on, the gate potential of the NMOS transistor 533 also rises due to parasitic capacitance, resulting in conduction between the source and drain of the NMOS transistor 533.

[0018] If both PMOS transistor 531 and NMOS transistor 533 are turned on at the same time, a shoot-through current will flow from the power supply to ground, destroying the elements. To prevent this, PMOS transistor 531 and NMOS transistor 533 must be designed to be robust, and the on-resistance, which is the resistance between the drain and source when PMOS transistor 533 is turned on, cannot be made small.

[0019] If the on-resistance of the PMOS transistor 531 is large, it takes time for the PMOS transistor 531 to turn on in response to a voltage jump in the power supply wiring 511. As a result, the ESD protection circuit 510 of this comparative example takes time to start up and the start-up voltage is also high.

[0020] Therefore, in the first embodiment of the present invention, a circuit configuration as described below is used to reduce the on-resistance of the PMOS transistor that constitutes the inverter circuit, thereby realizing an ESD protection circuit that can be started up at a lower voltage.

[0021] [Embodiment 1] 1 includes an internal circuit 105 and an ESD protection circuit 110. The internal circuit 105 and the ESD protection circuit 110 are connected to a power supply wiring 111 and a ground wiring 112. The power supply wiring 111 is connected to a power supply voltage VDD. The ground wiring 112 is connected to a ground terminal GND.

[0022] The ESD protection circuit 110 is a circuit for preventing damage to the internal circuit 105 of the semiconductor integrated circuit device 100 by passing an ESD surge current therein when an ESD surge enters the semiconductor integrated circuit device 100. Although not shown in detail, the internal circuit 105 is, for example, a logic LSI circuit or a memory LSI circuit, and performs various types of arithmetic processing.

[0023] The ESD protection circuit 110 is a GCNMOS (Gate Control NMOS) type ESD protection circuit that includes an RC time constant circuit 120, an inverter circuit 130, and a large NMOS transistor 140 having a wide gate width as a first NMOS transistor (hereinafter referred to as the clamp NMOS transistor 140).

[0024] The RC time constant circuit 120 is composed of a resistor element 121 and a capacitor element 122 connected in series between the power supply wiring 111 and the ground wiring 112. The resistor element 121 has a resistance value of, for example, 220 kΩ, and the capacitor element 122 has a capacitance value of, for example, 100 pF.

[0025] The inverter circuit 130 is connected between the power supply wiring 111 and the ground wiring 112. The inverter circuit 130 includes a PMOS transistor 131 and an NMOS transistor 133 connected in series between the power supply wiring 111 and the ground wiring 112. A resistance element 132 for preventing breakdown is connected between the drain of the PMOS transistor 131 and the drain of the NMOS transistor 133. A connection node between the PMOS transistor 131 and the resistance element 132 for preventing breakdown serves as an output node of the inverter circuit 130. The PMOS transistor 131 used has a small on-resistance.

[0026] The inverter circuit 130 uses a node between the resistance element 121 and the capacitor element 122 that constitute the RC time constant circuit 120 as an input node. That is, the gate of the PMOS transistor 131 and the gate of the NMOS transistor 131 are both connected to the node between the resistance element 121 and the capacitor element 122.

[0027] The source and back gate of the PMOS transistor 131 are connected to the power supply wiring 111. The output node of the inverter circuit 130 is connected to the gate of the clamp NMOS transistor 140. The source and back gate of the NMOS transistor 133 are connected to the ground wiring 112, and the drain is connected to the breakdown prevention resistance element 132 as described above.

[0028] The clamp NMOS transistor 140 has the output of the inverter circuit 130 as its gate input, its drain connected to the power supply wiring 111, and its source and back gate connected to the ground wiring 112, respectively.

[0029] As described above, the inverter circuit 130 of the ESD protection circuit 110 includes a breakdown prevention circuit in which the resistance element 132 for preventing breakdown is interposed between the drain of the PMOS transistor 131 and the drain of the NMOS transistor 133 .

[0030] Next, the operation of the ESD protection circuit 110 will be described. When an ESD surge such as a positive surge enters the power supply wiring 111 from the power supply voltage VDD, the potential between the resistor element 121 and the capacitor element 122 of the time constant circuit 120 remains at the ground potential if the capacitance of the capacitor element 122 is sufficiently large. In other words, the input node of the inverter circuit 130 remains at the "L" level.

[0031] Then, the PMOS transistor 131 is turned on, the NMOS transistor 133 is turned off, and the output of the inverter circuit 130 becomes the “H” level. That is, a current flows from the power supply wiring 111 through the source-drain of the PMOS transistor 131 to the clamp NMOS transistor 140, and the gate potential of the clamp NMOS transistor 140 becomes approximately equal to the potential of the power supply wiring 111.

[0032] At this time, since the PMOS transistor 131 has a low resistance structure, the source-drain is conductive when the voltage value between the gate and source of the PMOS transistor 131 is smaller. In other words, the PMOS transistor 131 becomes on more quickly.

[0033] At this time, a voltage is also applied to the drain of the NMOS transistor 133, but a resistance element 132 for preventing breakdown is interposed between the drain of the NMOS transistor 133 and the output node of the inverter circuit 130. Without the resistance element 132 for preventing breakdown, the gate potential would rise due to the parasitic capacitance between the gate and source of the NMOS transistor 133, causing conduction between the source and drain, and the resulting shoot-through current would destroy the element.

[0034] However, in this embodiment, the breakdown prevention resistance element 132 prevents the drain potential of the NMOS transistor 133 from rising even when the drain potential of the PMOS transistor 131 rises. As a result, it is possible to suppress a rise in the gate potential due to the parasitic capacitance between the gate and drain of the NMOS transistor 133. Therefore, when the PMOS transistor 131 is on, the NMOS transistor 133 is prevented from being turned on at the same time, and as a result, the NMOS transistor 133 is prevented from being broken down.

[0035] When the output of the inverter circuit 130 becomes the "H" level, the gate of the clamp NMOS transistor 140 also becomes the "H" level. As a result, the drain-source of the clamp NMOS transistor 140 becomes the ON state, the power supply wiring 111 and the ground wiring 112 become conductive, and the ESD surge that has entered the ESD protection circuit 110 can be released to the ground.

[0036] On the other hand, when power is turned on and a power supply of a predetermined voltage value is supplied to VDD, the node potential between the resistor element 121 and the capacitor element 122 of the RC time constant circuit 120 rises over time. That is, the input node of the inverter circuit 130 goes from "L" level to "H" after a predetermined time determined by the resistance value of the resistor element 121 and the capacitance value of the capacitor element 122 has elapsed. Then, the PMOS transistor 131 goes to an OFF state, the NMOS transistor 133 goes to an ON state, and the output of the inverter circuit 130 goes to an "L" level. In response to this, the gate input of the clamp NMOS transistor 140 goes to an "L" level. As a result, the drain-source of the clamp NMOS transistor 140 goes to an OFF state, the power supply wiring 111 and the ground wiring 112 go into a non-conductive state, and a predetermined voltage value of power can be supplied to the internal circuit 105.

[0037] Thus, according to the ESD protection circuit 110 of the first embodiment, the breakdown prevention resistance element 132 prevents a large current from flowing between the drain and source of the NMOS transistor 133 when an ESD surge enters, thereby preventing the NMOS transistor 133 from being broken down.

[0038] Since the NMOS transistor 133 is not destroyed by the destruction prevention resistance element 132, there is no risk of a large current passing through the PMOS transistor 131, and the PMOS transistor 131 can be designed to have a smaller on-resistance. By making the on-resistance of the PMOS transistor 131 smaller, the PMOS transistor 131 can be turned on at a lower voltage applied to the source. As a result, the clamp NMOS transistor 140 can be turned on faster and at a lower voltage.

[0039] [Embodiment 2] 3, the ESD protection circuit 110A of the semiconductor integrated circuit device 100A of the second embodiment is similar to that of the first embodiment except that a capacitor element 134 is connected in parallel between the drain and source of the NMOS transistor 133 of the inverter circuit 130A. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description thereof will be omitted.

[0040] That is, one end of the breakdown prevention resistance element 132 is connected to the drain of the PMOS transistor 131, while the other end is connected to the drain of the NMOS transistor 133 and the capacitor element 134. The resistance value of the breakdown prevention resistance element 132 is, for example, 1 kΩ, and the capacitance value of the capacitor element 134 is, for example, 1 pF to 10 pF.

[0041] With this configuration, when the NMOS transistor 133 is in an off state, the charge applied to the drain of the NMOS transistor 133 is temporarily stored in the capacitor element 134. This slows down the rate at which the drain potential of the NMOS transistor 133 rises. This makes it possible to suppress the rise in the gate potential caused by the parasitic capacitance between the gate and drain of the NMOS transistor 133. This prevents the NMOS transistor 133 from also turning on while the PMOS transistor 131 is on, and as a result, prevents the NMOS transistor 133 from being destroyed.

[0042] [Embodiment 3] Next, an ESD protection circuit 110B of a semiconductor integrated circuit device 100B according to the third embodiment shown in Fig. 4 will be described. The ESD protection circuit 110B has the same configuration as that of the first embodiment, except that a second breakdown prevention resistance element 135 is connected between the source of the NMOS transistor 133 of the inverter circuit 130B and the ground wiring 112. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description thereof will be omitted.

[0043] In the ESD protection circuit 110B, a breakdown prevention resistance element 132, the drain-source of an NMOS transistor 133, and a second breakdown prevention resistance element 135 are connected in series between the output node of the inverter circuit 130B and the ground wiring 112.

[0044] When the PMOS transistor 131 is on and the NMOS transistor 133 is off, a current flows between the source and drain of the PMOS transistor 131. The potential of the output node of the inverter circuit 130B is approximately the same as that of the power supply line 111.

[0045] At this time, the potential of the drain of the NMOS transistor 133 also rises, but a resistance element 132 for preventing breakdown is interposed between this drain and the output node of the inverter circuit 130B. Furthermore, a second resistance element 135 for preventing breakdown is interposed between the source of the NMOS transistor 133 and the ground wiring 112.

[0046] Therefore, even if the drain potential of the NMOS transistor 133 rises and the gate potential rises due to the parasitic capacitance between the gate and drain, the source voltage also rises due to the parasitic capacitance between the gate and source. In other words, the drain and source potentials of the NMOS transistor 133 both rise. This prevents the NMOS transistor 133 from being turned on while the PMOS transistor 131 is on, and as a result, the NMOS transistor 133 is prevented from being destroyed.

[0047] [Embodiment 4] An ESD protection circuit 110C of a semiconductor integrated circuit device 100C of the fourth embodiment shown in FIG. 5A will be described. An inverter circuit 130C of the ESD protection circuit 110C is obtained by further connecting a second RC time constant circuit in parallel to the inverter circuit 130 of the first embodiment. The second RC time constant circuit is composed of a resistor element 136 and a capacitor element 137. The back gate of the PMOS transistor 131 of the inverter circuit 130C is connected between the resistor element 136 and the capacitor element 137 constituting the second RC time constant circuit. The configuration of the ESD protection circuit 110C of the fourth embodiment other than the above is the same as that of the ESD protection circuit 110 of the first embodiment. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description thereof will be omitted.

[0048] That is, as shown in the operation explanatory diagram of FIG. 5(B), in the ESD protection circuit 110C of the fourth embodiment, a capacitor element 137 is connected between the back gate of the PMOS transistor 131 and the ground wiring 112.

[0049] As shown in the operation explanatory diagram of FIG. 5(B), when an ESD surge enters the ESD protection circuit 110, the gate potential of the PMOS transistor 131 becomes approximately the ground potential (step S401A). Then, the source-drain of the PMOS transistor 131 becomes conductive. At this time, a parasitic PNP bipolar transistor 138 is formed between the source, backgate, and drain of the PMOS transistor 131. A capacitor element 137 is present between the backgate of the PMOS transistor 131, that is, between the base of the parasitic PNP bipolar transistor 138 and the ground wiring 112. While the capacitor element 137 is charged, a current flows between the emitter and base of the parasitic PNP bipolar transistor 138 (step S401B), which causes conduction between the emitter and collector, causing a current to flow (step S402A).

[0050] That is, the current flowing between the emitter and base of the parasitic PNP bipolar transistor 138 acts as a "priming agent" to connect the emitter and collector, so that a larger current flows between the source and drain of the PMOS transistor 131 (step S402B). In this way, the amount of charge reaching the gate of the clamp NMOS transistor 140 increases, so that the potential of the gate can be raised more quickly. As a result, the source and drain of the clamp NMOS transistor 140 can be brought into a conductive state more quickly, and the ESD surge can be released.

[0051] When charge is accumulated in the capacitor element 137, no current flows between the emitter and base of the parasitic PNP bipolar transistor 138. However, a current continues to flow between the source and drain of the PMOS transistor 131, and the source and drain of the clamp NMOS transistor 140 can be made conductive only for a period determined by the RC time constant circuit 120. The second RC time constant circuit is set so that the time constant determined by the resistor element and capacitor element constituting the circuit is smaller than the time constant of the RC time constant circuit 120. This reduces the physical area that the second RC time constant circuit occupies on the semiconductor substrate.

[0052] Instead of the resistor element 136 constituting the second RC time constant circuit, a coil or a meander inductor may be connected between the base of the parasitic PNP bipolar transistor 138 and the power supply wiring 111. This makes it possible to prevent high-frequency noise from flowing directly into the capacitor element 137. [Explanation of symbols]

[0053] 100, 100A, 100B, 100C Semiconductor integrated circuit device 105 Internal circuit 110, 110A, 110B, 110C ESD protection circuit 111 Power wiring 112 Ground wiring 120 Time constant circuit 121 Resistance element 122 Capacitor element 130, 130A, 130B, 130C inverter circuit 131 PMOS transistor 132 Resistance element for preventing destruction 133 NMOS transistor 134 Capacitor element 135 Second breakdown prevention resistor element 136 Resistance element 137 Capacitor Element 138 Parasitic PNP Bipolar Transistor 140 Clamp NMOS transistor

Claims

1. an RC time constant circuit connected in series between a power supply line and a ground line; an inverter circuit having an input between a resistor element and a capacitor element constituting the RC time constant circuit and connected between the power supply wiring and the ground wiring; a clamp NMOS transistor having a gate input connected to the output of the inverter circuit, a drain connected to the power supply wiring, and a source and a back gate connected to the ground wiring, the inverter circuit includes a PMOS transistor and an NMOS transistor connected in series between the power supply wiring and the ground wiring, and a first resistance element connected between the drain of the NMOS transistor and an output of the inverter circuit.

2. 2. The ESD protection circuit according to claim 1, further comprising a first capacitor element connected in parallel with said NMOS transistor between the drain and source of said NMOS transistor.

3. 2. The ESD protection circuit according to claim 1, further comprising a second resistive element inserted between the source of said NMOS transistor and said ground wiring.

4. 2. The ESD protection circuit of claim 1, wherein the RC time constant circuit is a first RC time constant circuit, a second RC time constant circuit is further connected in parallel between the power supply wiring and the ground wiring, and a back gate of the PMOS transistor of the inverter circuit is connected between a resistor element and a capacitor element constituting the second RC time constant circuit.

5. 5. The ESD protection circuit of claim 4, wherein the time constant of the second RC time constant circuit is smaller than the time constant of the first RC time constant circuit.

6. 6. A semiconductor integrated circuit device comprising: the ESD protection circuit according to claim 1; and an internal circuit.

Images