Electronic apparatus and method for controlling memory operation mode

Abstract

To provide an electronic apparatus and a method for controlling a memory operation mode.SOLUTION: A memory device (a memory box) 220 includes: memory devices 222 including memory cells for storing data; a sensor for measuring state information of the memory device; and a mode manager for dividing the memory devices into a plurality of groups, receiving a priority among the plurality of groups from a host device, receiving the state information from the sensor, and dynamically controlling operation modes of the plurality of groups on the basis of the priority and the state information.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The following embodiments relate to electronic devices and methods for controlling memory operating modes. [Background technology]

[0002] Dynamic throttling control may be used to control the temperature of the memory device. Dynamic throttling may be achieved by monitoring the temperature through a temperature sensor, regulating the bandwidth in a memory controller in a CPU to control the operating efficiency of the memory device, and adjusting the DRAM refresh time with a specific target. As a result, it is possible to create a configuration in which the overall power consumption of the memory device is controlled and a closed-loop is controlled at a target temperature.

[0003] A memory pool formed through various systems may be provided for any host through memory pooling using Compute Express Link (CXL). As a dynamic throttling control method for one memory device, it is difficult to efficiently control memory devices included in the memory pool. Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide an electronic device and method for controlling memory operating modes. [Means for solving the problem]

[0005] A memory box according to one embodiment includes a memory device including memory cells for storing data, a sensor for measuring status information of the memory device, and a mode manager for dividing the memory device into a plurality of groups, receiving priorities among the plurality of groups from a host device, receiving status information from the sensor, and dynamically adjusting operating modes of the plurality of groups based on the priorities and the status information.

[0006] To dynamically adjust the operating modes, the mode manager may determine current operating modes of the plurality of groups according to the priority, compare the status information with limit resource information corresponding to the status information, and change the current operating modes of the plurality of groups based on the comparison result.

[0007] The mode manager may divide the memory devices into a plurality of groups according to characteristics of the memory devices, to divide the memory devices into the plurality of groups.

[0008] The memory devices have the same characteristics, and the mode manager can divide the memory devices into the groups according to operational importance of the memory devices.

[0009] The mode manager may include a controller that controls the groups so that the groups can operate in a corresponding operation mode.

[0010] In order to dynamically adjust the operating mode, the mode manager can set the multiple high priority groups to a first operating mode that operates them with predetermined performance, and set the multiple low priority groups to a second operating mode that operates them within a range that does not exceed limit resource information corresponding to the status information.

[0011] The mode manager may include a first controller that controls the high priority group to operate in the first operating mode, and a second controller that controls the low priority group to operate in the second operating mode.

[0012] The memory device may include a Compute Express Link (CXL) memory device.

[0013] The memory device may further include a switch connecting the memory device and the host device, and the mode manager may receive priorities among the multiple groups from the host device via the switch for receiving the priorities.

[0014] A computing system according to one embodiment may include the memory box and a host device.

[0015] The computing system may further include a switch configured to connect the host device to the memory box.

[0016] In one embodiment, a switch includes a processor that divides memory devices into groups, receives priorities among the groups from a host device, receives status information of the memory devices from a sensor, and dynamically adjusts operating modes of the groups based on the priorities and the status information.

[0017] a bandwidth limiter for adjusting a bandwidth of data transmission between the host device and the plurality of groups;

[0018] The system may further include a controller that controls the bandwidth limiter so that the plurality of groups can operate in a corresponding operation mode.

[0019] In one embodiment, the memory box includes the switch (the switch is configured to connect the host device and the memory device), the memory device including memory cells that store data, and the sensor configured to measure the state information.

[0020] A computing system according to one embodiment includes a host device, a number of memory boxes including memory devices including memory cells for storing data, a sensor for measuring status information of the memory boxes, and a mode manager for dividing the memory boxes into a number of groups, receiving status information from the sensor, and dynamically adjusting operating modes of the multiple groups based on the status information.

[0021] To divide the memory boxes, the mode manager can divide the memory boxes into the plurality of groups according to characteristics of the memory boxes.

[0022] The memory boxes have the same characteristics as each other, and the mode manager can divide the memory boxes into the plurality of groups according to the operational importance of the memory boxes in order to divide the memory boxes.

[0023] In one embodiment, the rack includes the computing system and a plurality of compute servers including the host device, the status information relates to the compute servers and the memory boxes, and the mode manager divides the compute servers and the memory boxes into a plurality of groups, receives priorities among the plurality of groups, and dynamically adjusts operating modes of the plurality of groups based on the priorities and the status information.

[0024] A control method according to one embodiment includes the steps of acquiring status information of memory devices, dividing the memory devices into a plurality of groups, acquiring priorities among the plurality of groups, and dynamically adjusting operating modes of the plurality of groups based on the priorities and the status information.

[0025] The step of dynamically adjusting the operating modes may include the steps of determining current operating modes of the plurality of groups according to the priority order, comparing the status information with limit resource information corresponding to the status information, and changing the current operating modes of the plurality of groups based on the comparison result.

[0026] The dividing step may include dividing the memory devices into the plurality of groups according to characteristics of the memory devices.

[0027] The memory devices may have the same characteristics, and the dividing step may include dividing the memory devices into the groups according to operational criticality of the memory devices. Effect of the Invention

[0028] According to the present invention, an electronic device and method for controlling memory operating modes can be provided. [Brief description of the drawings]

[0029] [Figure 1] 1 is a diagram illustrating a memory device control method according to an embodiment; [Figure 2A] FIG. 2 is a diagram showing a schematic configuration of a host device and a memory box according to an embodiment. [Figure 2B] 1 is a diagram illustrating an operation method of a mode manager according to an embodiment. [Figure 2C] FIG. 2 is a diagram showing a schematic configuration of a host device and a CXL memory device according to an embodiment. [Diagram 3] FIG. 2 is a diagram illustrating an example of a memory box configured with homogeneous memory devices according to one embodiment. [Figure 4] FIG. 2 illustrates an example of a memory box configured with heterogeneous memory devices according to one embodiment. [Diagram 5] FIG. 2 illustrates an example of a memory box configured with heterogeneous memory devices according to one embodiment. [Figure 6] FIG. 13 is a diagram showing a schematic configuration of a host device and a memory box according to another embodiment. [Figure 7] FIG. 13 is a diagram showing a schematic configuration of a host device and a memory box according to a further embodiment. [Figure 8] FIG. 1 is a diagram showing a schematic configuration of a rack cabinet according to an embodiment. [Figure 9] 1 is a flowchart illustrating a control method according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0030] Specific structural or functional descriptions for the embodiments are disclosed for the purpose of illustration only, and may be modified in various forms. Therefore, the embodiments are not limited to the specific disclosed forms, and the scope of the present specification includes modifications, equivalents, or alternatives within the technical spirit.

[0031] Although terms such as first or second may be used to describe multiple components, such terms should be construed only for the purpose of distinguishing one component from the other components. For example, a first component may be named a second component, and similarly, a second component may be named a first component.

[0032] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that although it is directly coupled or connected to the other component, there may be other components in between.

[0033] The singular expression includes the plural expression unless the context clearly indicates otherwise. In this specification, the terms "comprise" and "have" are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and should be understood as not precluding the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] In this specification, each phrase such as "at least one of A or B" and "at least one of A, B, or C" may include any one or all possible combinations of the items listed with that phrase.

[0035] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms commonly used and defined in advance should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as ideal or overly formal unless expressly defined in this specification.

[0036] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the description with reference to the drawings, the same components are given the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted.

[0037] FIG. 1 is a diagram illustrating a memory device control method according to an embodiment.

[0038] Referring to FIG. 1, a memory box in which multiple memory devices are integrated is provided in an interface technology such as CXL (Compute Express Link). CXL (Compute Express Link) is a connecting technology that supports cache coherency for processors, memory expansion, and accelerators. When a processor and an additional component are connected using CXL, the CXL technology maintains memory coherency between the memory space of the processor and the memory space of the additional component, and it is possible to improve performance through resource sharing, reduce the complexity of the software stack, and reduce the cost of the overall system. CXL is provided as an open standard interface for high-speed communication in accelerators that complement processors to support new applications such as artificial intelligence and machine running. CXL can provide a comprehensive interface environment that connects multiple components such as a central processing unit (CPU), memory, accelerators, and other peripheral devices. For example, a memory pool formed through various systems for any host may be provided through CXL memory pooling based on the scalability of CXL.

[0039] Hereinafter, an embodiment of a method for controlling multiple memory devices in a memory pool environment will be described. For convenience of explanation, an embodiment of a memory pool environment provided by CXL will be described, but the memory pool environment is not limited thereto, and may be provided by various interface technologies that can provide an interface environment for connecting multiple components such as memories, accelerators, and other peripheral devices.

[0040] The diagram 110 shows the power consumed when the memory devices in a memory box are divided into group 1 and group 2 and operate at 100% performance without special control for the two groups. In this case, during a certain time period, the sum of the power consumption of the two groups exceeds the overall limit power of the memory box.

[0041] FIG. 120 is a diagram showing power consumed when a memory device in a memory box operates according to a memory device control method according to an embodiment. As will be described in detail below, the control method according to an embodiment can operate a target group (e.g., group 1) first (Priority) with a specific performance, and control the remaining group (e.g., group 2) with the remaining resources (e.g., power) using a closed-loop controller (e.g., proportional integral / derivative controller, dynamic thermal throttling controller) so that the sum of the power consumption of the two groups does not exceed the overall limit power of the memory box.

[0042] 2A is a diagram showing a schematic configuration of a host device and a memory box according to an embodiment of the present invention, and the contents described with reference to FIG. 1 may be equally applied to FIG. 2A.

[0043] Referring to FIG. 2A, a computing system according to one embodiment includes a host device 210 (e.g., one or more processors) and a memory device 220. The host device 210 uses an interface (e.g., a CXL interface) to access and use a memory element 222 of the memory device 220. The memory device 220 includes the memory element 222, a mode manager 221 (e.g., one or more processors), a switch (e.g., a CXL switch) 223, and a sensor 224 (e.g., one or more sensors). The switch 223 may provide connectivity between the host device 210 and the memory device 220. The memory element 222 may store data. An interface technology (e.g., a CXL interface technology) may be used for the connection between the host device 210 and the memory device 220 and / or the connection between the mode manager 221 and the memory element 222.

[0044] Memory elements 222 refer to various levels of memory configurations. For example, memory elements 222 may refer to memory cell groups or memory devices. A memory cell group refers to a group (e.g., a memory chip) that includes multiple memory cells. A memory device refers to a device that includes one or more memory modules. Each memory module includes multiple memory groups. A memory device refers to a device that has a large capacity compared to a memory cell group.

[0045] When the memory element 222 corresponds to a memory cell group, the memory device 220 corresponds to a memory device. When the memory element 222 corresponds to a memory device, the memory device 220 corresponds to a memory box. A memory box corresponds to a large-capacity memory storage having a larger capacity than a memory device. For convenience of explanation, the following description will be given on the basis that the memory element 222 is a memory device and the memory device 220 is a memory box, but is not limited thereto. In other words, the description of the memory cell group, memory module, memory device, and memory box is one example, and the memory device 220 and the memory element 222 correspond to another level of memory not illustrated here.

[0046] The memory device may be composed of dynamic random access memories (DRAM), static random access memories (SRAM), magnetic random access memories (MRAM), PRAM, self-selecting memories using Ovonic Threshold Switching (OTS) materials, etc. However, the configuration of the memory device is not limited to these.

[0047] The host device 210 and the memory device 220 correspond to devices that are physically separate from each other. The memory device 220 corresponds to a device independent of the host device 210 that provides storage space to the host device 210.

[0048] The mode manager 221 divides the memory elements 222 into a plurality of groups. The mode manager 221 may divide the memory elements 222 to be controlled into a plurality of groups based on the characteristics and performance of the memory elements 222. The characteristics of the memory elements 222 may specify the type of memory elements (e.g., Double Data Rate (DDR) 4 or DDR5), and the mode manager 221 may divide the memory elements 222 into a first group of a first type (e.g., DDR4) and a second group of a second type (e.g., DDR5). However, the described embodiment is not limited to this. The mode manager 221 may receive a priority among the plurality of groups from the host device 210 via the switch 223. The priority may be set by a user or determined via a predefined policy (e.g., determined by the host device 210).

[0049] The sensor 224 is connected to the mode manager 221 and measures status information of the memory element 222 in the memory device 220. The status information includes at least one of an operating voltage, an operating temperature, an operating time, and an operating count of the memory element 222. The sensor 224 includes a detection device configured to measure at least one of the operating voltage, the operating temperature, the operating time, and the operating count. For example, the sensor 224 includes, but is not limited to, a power monitor, a bandwidth monitor, a latency monitor, a current sensor, a voltage sensor, and a temperature sensor.

[0050] The status information measured by the sensors 224 may be provided as a sum of the individual values, or in the case of temperature, a maximum value, so that the mode manager 221 can determine an overall system performance status based on the status information provided by the sensors 224. For example, the status information may be the total power consumption calculated based on the voltage and current applied to the corresponding system as measured by the sensors 224.

[0051] The mode manager 221 can receive status information from the sensor 224 and dynamically adjust the operation modes of the multiple groups based on the priority and the status information. The mode manager 221 determines the current operation modes of the multiple groups according to the priority, compares the status information with limit resource information corresponding to the status information, and changes the current operation modes of the multiple groups based on the comparison result. The limit resource information means resource information available in the entire memory device 220. For example, the limit resource information includes an overall limit power of the memory device 220, an overall limit temperature of the memory device 220, an overall limit performance of the memory device 220, etc.

[0052] For example, the mode manager 221 may divide the memory elements 222 into two groups, a first group 222-1 and a second group 222-2, and set the high-priority group (e.g., the first group 222-1) as a first operating mode in which the memory elements 222 operate with predetermined performance, and set the low-priority group (e.g., the second group 222-2) as a second operating mode in which the memory elements 222 operate within a range that does not exceed the limit resource information corresponding to the status information.

[0053] Mode manager 221 includes various control means such as controller 221-0 (e.g., one or more processors), which are devices configured to control memory elements 222 included in each group in an operating mode set by mode manager 221, and mode manager 221 may include one or more controllers.

[0054] The mode manager 221 may control the high-priority group (hereinafter, the "high-priority group" is referred to as the "group having priority") through a first controller included in the mode manager 221 so that the high-priority group can operate with a predetermined performance (e.g., a target power consumption), and may control the low-priority group through a second controller included in the mode manager 221. When the total power consumption of the first group 222-1 and the second group 222-2 exceeds the total power limit of the memory device 220, all groups may be controlled through the second controller, and the operation mode of the high-priority group (e.g., the first group 222-1) may be changed to the second operation mode so that the total power consumption of the first group 222-1 and the second group 222-2 falls within the range of the total power limit of the memory device 220. When the total power consumption of the first group 222-1 and the second group 222-2 is less than the total power limit of the memory device 220, the operation mode of the high-priority group (e.g., the first group 222-1) may be changed to the first operation mode again.

[0055] 2B is a diagram illustrating an operation method of a mode manager according to an embodiment of the present invention, and the contents described with reference to FIGS. 1 and 2A may be equally applied to FIG. 2B.

[0056] Referring to FIG. 2B, the mode manager 221 according to one embodiment classifies the memory elements 222 into a first group 222-1 and a second group 222-2, and controls the operation modes of the first group 222-1 and the second group 222-2.

[0057] In FIG. 2B, multiple controllers (first controller 221-1, second-first controller 221-2, second-second controller 221-3, second-third controller 221-4) and multiple multiplexers (first multiplexer 225-1, second multiplexer 225-2) are shown as existing separately from mode manager 221, but mode manager 221 may include multiple controllers and multiple multiplexers.

[0058] The second controllers described with reference to Fig. 2A include the 2-1 controller 221-2, the 2-2 controller 221-3, and the 2-3 controller 221-4. The 2-1 controller 221-2 is a proportional controller, the 2-2 controller 221-3 is an integral controller, and the 2-3 controller 221-4 is a derivative controller. However, the type and number of the second controllers are not limited to those described above.

[0059] The first multiplexer 225-1 may receive a control signal from the mode manager 221 to control the first group 222-1 in a first operation mode, and may determine the first controller 221-1 signal as an output. The first controller 221-1 may control the first group 222-1 to operate with a predetermined performance (e.g., a target power consumption).

[0060] The second multiplexer 225-2 may receive a control signal from the mode manager 221 to control the second group 222-2 in a second operating mode and determine a second controller signal (the sum of the 2-1 controller 221-2, the 2-2 controller 221-3, and the 2-3 controller 221-4) as an output. The second group 222-2 may be controlled in a closed loop by the second controller.

[0061] FIG 2C is a diagram showing a schematic configuration of a host device and a CXL memory device according to an embodiment. The contents described with reference to FIG 1 and FIG 2B may be applied to FIG 2C in the same way. For example, the host device 260 and the CXL switch 270 shown in FIG 2C correspond to the host device 210 and the switch 223 described with reference to FIG 2A, respectively, and the contents of the mode manager 221 and the sensor 224 shown in FIG 2C may be applied to the mode manager 221 and the sensor 224 described with reference to FIG 2A in the same way.

[0062] Referring to FIG. 2C, the host device 260 may be, for example, a CPU. The host device 260 includes one or more cores 261, a cache 262, a memory controller 263, and a home agent 264. The cache 262 may be, for example, a last level cache (LLC). The home agent 264 may be logic that synchronizes data between a cache (for example, LLC) and a remote address to maintain cache coherence. The home agent 264 can perform a function of managing access to an assigned address area to maintain cache coherence. The dual in-line memory module (DIMM) 290 refers to a memory module in which several DRAM chips are mounted on a circuit board, and may be used as a main storage memory of a computer. The DIMM 290 may be controlled by a memory controller 263 of the host device 260.

[0063] The host device 260 is connected to a plurality of CXL endpoints 283-1 to 283-n via the CXL switch 270, and this connection is called a CXL link. Alternatively, the host device 260 may be directly connected to the CXL endpoint 281, and this connection is called a direct connection. The CXL root port 265 is a connection terminal that connects the host device 260 and the CXL switch 270, or connects the host device 260 and the CXL endpoint 281.

[0064] A plurality of CXL memory devices are connected to the host device 260 via the CXL switch 270, and the CXL memory device includes a CXL endpoint, a CXL memory controller, and a collection of memory media, and the collection of memory media may constitute a CXL memory device. For example, n (n is a natural number) memory devices are connected to the host device 260 via the CXL switch 270, and an i-th (i is a natural number between 1 and n) CXL memory device includes a CXL endpoint 283-i, a CXL memory controller 285-i, and one or more memory media collections 287-i. A memory media means a memory package, and is a unit that may be connected to a memory interface. For example, in the case of DRAM, a memory media means a unit that is connected to a DRAM package and a DRAM interface. In the case of DDR, a DIMM is composed of eight DRAM packages, and therefore a memory media collection may be composed of eight memory media.

[0065] The CXL memory device is expanded via CXL switch 270 and includes CXL endpoints 283-1 to 283-n, CXL switch 270, CXL memory controllers 285-1 to 285-n, and memory media collections 287-1 to 287-n, which may constitute a disaggregated memory subsystem.

[0066] 3 is a diagram showing an example of a memory box configured with the same type of memory device according to an embodiment of the present invention. The contents described with reference to FIGS. 1 to 2B may be equally applied to FIG.

[0067] 3, a host device 310 according to an embodiment can access and use a memory device in a memory box 320 using an interface (e.g., a CXL interface). The memory box 320 includes a memory device, a mode manager 321, a switch (e.g., a CXL switch) 323, and sensors (current sensor 324-1, voltage sensor 324-2, and temperature sensor 324-3). The mode manager 321 includes a sensor interface 321-1, a first controller 321-2, and a second controller 321-3. The mode manager 321 receives status information measured by the current sensor 324-1, the voltage sensor 324-2, and the temperature sensor 324-3 via the sensor interface 321-1.

[0068] The memory box 320 may be configured with homogeneous memory devices, for example, the memory box 320 may be configured with homogeneous DDR DRAM.

[0069] The mode manager 321 may classify memory devices into a plurality of groups (e.g., a first group 322-1 and a second group 322-2) according to a specific purpose. For example, the mode manager 321 classifies memory devices into the first group 322-1 and the second group 322-2 according to the operational importance of the DRAM area that the host device 310 provides to the memory box 320. Furthermore, the mode manager 321 may set the first group 322-1 to a high-priority group and the second group 322-2 to a low-priority group according to the operational importance of the DRAM area.

[0070] The mode manager 321 may control the first group 322-1, which has a higher priority, via the first controller 321-2 so that the first group 322-1 operates with a predetermined performance (e.g., a target power consumption), and the second group 322-2, which has a lower priority, may be controlled via the second controller 321-3.

[0071] In FIG. 3, an example in which the memory devices are divided into two memory groups is described, but this is not necessarily limited to this. The number of groups may vary depending on the design. Furthermore, in FIG. 3, an example of a memory box configured with DDR DRAM is described, but various memory devices other than DDR DRAM may be adopted.

[0072] 4 and 5 are diagrams illustrating an example of a memory box configured with different types of memory devices according to an embodiment. The contents described with reference to FIGS. 1 to 2B may be equally applied to FIGS. 4 and 5.

[0073] 4, a host device 410 according to an embodiment may access and use a memory device in a memory box 420 using an interface (e.g., a CXL interface). The memory box 420 includes a memory device, a mode manager 421, a switch (e.g., a CXL switch) 423, and sensors (a current sensor 424-1, a voltage sensor 424-2, and a temperature sensor 424-3). The mode manager 421 includes a sensor interface 421-1, a first controller 421-2, and a second controller 421-3. The mode manager 421 receives status information measured by the current sensor 424-1, the voltage sensor 424-2, and the temperature sensor 424-4 via the sensor interface 421-1.

[0074] The memory box 420 may be composed of heterogeneous memory devices. For example, the memory devices include a double data rate (DDR) DRAM and a low power double data rate (LPDDR) DRAM. The mode manager 421 classifies the memory devices into a first group 422-1 composed of DDR DRAM and a second group 422-2 composed of LPDDR DRAM.

[0075] DDR DRAM has the advantage of superior DRAM latency compared to LPDDR DRAM, but consumes more power. LPDDR has the advantage of providing high bandwidth because of good signal integrity due to short signal distance in package implementation.

[0076] The mode manager 421 may set the first group 422-1 consisting of DDR DRAM as a high priority group and the second group 422-2 consisting of LPDDR DRAM as a low priority group. By setting the priorities as described above, the memory box 420 according to an embodiment may adjust power consumption by flexibly changing the operating speed of the second group 422-2 consisting of LPDDR DRAM and lowering the operating bandwidth while guaranteeing the latency of the first group 422-1 consisting of DDR DRAM. In particular, since the idle power of the LPDDR DRAM is superior to that of the DDR DRAM, the influence of the idle power on the power of the first group 422-1 consisting of the DDR DRAM may be minimized.

[0077] When the mode manager 421 changes the second group 422-2 consisting of LPDDR DRAM to a higher priority group, it can control power consumption by lowering the bandwidth of the first group 422-1 consisting of DDR DRAM while taking advantage of the high bandwidth of LPDDR, thereby allowing performance characteristics to be managed appropriately within limited power limits.

[0078] The mode manager 421 can control the high priority group via a first controller 421-2 and control the low priority group via a second controller 421-3 so that the high priority group can operate with a predetermined performance (e.g., target power consumption).

[0079] 5, a host device 510 according to an embodiment can access and use a memory device in a memory box 520 using an interface (e.g., a CXL interface). The memory box 520 includes a memory device, a mode manager 521, a switch (e.g., a CXL switch) 523, and sensors (current sensor 524-1, voltage sensor 524-2, and temperature sensor 524-5). The mode manager 521 includes a sensor interface 521-1, a first controller 521-2, and a second controller 521-3. The mode manager 521 can receive state information measured by the current sensor 524-1, the voltage sensor 524-2, and the temperature sensor 524-3 via the sensor interface 521-1.

[0080] The memory box 520 may be composed of different types of memory devices. For example, the memory devices include a double data rate (DDR) DRAM and an SSD. The mode manager 521 classifies the memory devices into a first group 522-1 composed of DDR DRAM and a second group 522-2 composed of SSD.

[0081] In the case of SSD, in order to prevent data damage due to sudden power loss, temporary power sources such as batteries, capacitors, and super capacitors can be supported, and they may be provided in various operating forms.

[0082] The mode manager 521 may set the second group 522-2 consisting of SSDs as a high priority group and the first group 522-1 consisting of DDR DRAMs as a low priority group. By setting the priorities as above, the memory box 520 according to an embodiment may guarantee a power budget for the second group 522-2 consisting of SSDs and operate in a stable data management state to guarantee data storage and data integrity.

[0083] When a power loss situation occurs, the mode manager 521 may change the first group 522-1 consisting of DDR DRAM to a high priority group in order to guarantee a power budget for the first group 522-1 consisting of DDR DRAM. By changing the priority as described above, the memory box 520 according to an embodiment can quickly migrate data that needs to be stored from the DDR DRAM to the SSD to guarantee data integrity in the power loss algorithm operation of the SSD.

[0084] In Figures 4 and 5, an example in which the memory devices are divided into two memory groups is described, but this is not necessarily limited to this. The number of groups may be different depending on the design. Furthermore, the memory box composed of different types of memory devices is not necessarily limited to the example described above in Figures 4 and 5, and the memory box may be composed of various types of memory devices (e.g., HBM3, NAND FLASH, etc.).

[0085] 6 is a diagram showing a schematic configuration of a host device and a memory box according to another embodiment of the present invention, and the contents described with reference to FIGS.

[0086] 6, a computing system according to one embodiment includes a host device 610 and a memory box 620. The host device 610 may access and use a memory device in the memory box 620 using an interface (e.g., a CXL interface). The memory box 620 includes a memory device, a switch (e.g., a CXL switch) 623, and a sensor 624.

[0087] The switch 623 according to an embodiment includes a bandwidth limiter 623-2. The switch 623 may further include a mode manager 621. However, if an embedded processor (e.g., an embedded CPU) is present in the switch 623, the switch firmware can be realized via the embedded processor, and the embedded processor can perform an operation of grouping memory devices and dynamically determining an operation mode of the memory devices. In this case, the switch 623 may be configured without the mode manager 621. Even if the mode manager 621 is not present, the switch 623 includes a controller 621-1, and the controller 621-1 is connected to the bandwidth limiter 623-2.

[0088] The upstream port 623-1 may be a connection terminal that connects the host device 610 and the switch 623. The bandwidth limiter 623-2 of the switch 623 may be connected to the host device 610 via the upstream port 623-1.

[0089] The downstream port is a connection terminal that connects the memory device group and the switch 623. The bandwidth limiter 623-2 of the switch 623 is connected to the memory device group through a plurality of downstream ports. For example, a first downstream port 623-3 connects the first group 622-1 and the bandwidth limiter 623-2, and a second downstream port 623-4 connects the second group 622-2 and the bandwidth limiter 623-2.

[0090] The bandwidth limiter 623-2 adjusts the bandwidth of data transmission between the host device 610 and multiple groups (e.g., a first group 622-1 and a second group 622-2), and the controller 621-1 can control the bandwidth limiter 623-2 so that the multiple groups can operate in corresponding operating modes.

[0091] 7 is a diagram showing a schematic configuration of a host device and a memory box according to a further embodiment, in which the contents described with reference to FIGS. 1 to 5 may be equally applied to FIG.

[0092] 7, a computing system according to one embodiment includes a host device 710, a switch 723, and a memory box 720. When configuring the memory box 730, the memory device may be directly connected to the external interface. In this case, the memory device may be directly connected to the host device 710 without a switch. Alternatively, the memory device may be connected to the host device 710 via a switch 723 outside the memory box 720.

[0093] The memory box 720 includes memory devices, a mode manager 721, and a sensor 724. Even in a memory box 730 without an internal switch, the mode manager 721 can classify the memory devices into a plurality of groups (for example, a first group 722-1 and a second group 722-2) and dynamically control the operation mode between the plurality of groups. To this end, the mode manager 721 is connected to all the memory devices via a sideband, and the controller 721-1 is connected to each of the memory devices and can control the operation mode of each of the memory devices.

[0094] Fig. 8 is a diagram showing a schematic configuration of a rack cabinet according to an embodiment. The contents described with reference to Figs. 1 to 7 may be equally applied to Fig. 8, and overlapping contents may be omitted.

[0095] 8, a rack cabinet 800 according to an embodiment includes a mode manager 810, a sensor 820, a plurality of compute servers, and a plurality of memory boxes. The rack cabinet 800 may further include a switch connecting the mode manager 810 to the plurality of compute servers and the plurality of memory boxes. For example, a network connection in the rack cabinet 800 can be configured via a switch (e.g., a CXL switch or an Ethernet switch), thereby connecting the mode manager 810 to the plurality of compute servers and the plurality of memory boxes.

[0096] The sensor 820 monitors status information of the rack cabinet 800 (for example, the overall power of the rack cabinet 800) and transmits the status information to the mode manager 810. The mode manager 810 can control all of the multiple compute servers and multiple memory boxes.

[0097] The mode manager 810 may classify the multiple compute servers and the multiple memory boxes into multiple groups. The mode manager 810 may dynamically adjust the operation modes of the multiple groups based on the priority and the state information. The mode manager 810 may determine the current operation modes of the multiple groups according to the priority, compare the state information with the limit resource information corresponding to the state information, and change the current operation modes of the multiple groups based on the result of the comparison.

[0098] For example, the mode manager 810 may classify multiple compute servers and multiple memory boxes into two groups, a first group 830-1 and a second group 830-2, and set a high-priority group (e.g., first group 830-1) to a first operating mode in which the servers operate at a predetermined performance level, and set a low-priority group (e.g., second group 830-2) to a second operating mode in which the servers operate within a range that does not exceed limit resource information corresponding to the status information.

[0099] 9 is a flowchart illustrating a control method according to an embodiment of the present invention. The contents described with reference to FIGS. 1 to 8 may be equally applied to FIG.

[0100] For ease of explanation, steps S910-S940 are described as steps performed using the memory box shown in Figure 2A (e.g., memory device 220 of Figure 2A), but steps S910-S940 may be used via any other suitable electronic device and in any suitable system.

[0101] Additionally, although the operations shown in Figure 9 may be performed in the order and manner shown, the order of some operations may be changed or some operations may be omitted without departing from the spirit and scope of the illustrated embodiments. Multiple operations shown in Figure 9 may be performed in parallel or simultaneously.

[0102] In step S910, the memory box obtains status information of the memory device. The memory box may include a sensor, which can measure the status information for the entire memory box.

[0103] In step S920, the memory box divides the memory devices into a plurality of groups. The memory box may divide the memory devices into a plurality of groups according to the characteristics of the memory devices. Alternatively, the memory devices may have the same characteristics, and the memory box may divide the memory devices into a plurality of groups according to the operational importance of the memory devices.

[0104] In step S930, the memory box obtains the priority among the groups. The priority may be set by the user or may be determined through a predetermined policy.

[0105] In step S940, the memory box dynamically adjusts the operation modes of the multiple groups according to the priority and the status information. The memory box can determine the current operation modes of the multiple groups according to the priority, compare the status information with the limit resource information corresponding to the status information, and change the current operation modes of the multiple groups according to the comparison result.

[0106] host device, memory device, mode manager, first controller, second-first controller, second-second controller, second-third controller, memory element, first group, second group, switch, sensor, first multiplexer, second multiplexer, core, cache, memory controller, home agent, CXL root port, CXL switch, CXL endpoint, CXL memory media, DIMM, memory box, sensor interface, second controller, current sensor, voltage sensor, temperature sensor, controller, upstream port, bandwidth limiter, first downstream port, second downstream port, rack cabinet, host device 210, memory device 220, mode manager 221, first controller 221-1, second-first controller 221-2, second-second controller 221-3, second-third controller 221-4, memory element 222, first group 222-1, second group 222-2, switch 223, sensor 224, first multiplexer 225-1, second multiplexer 225-2, host device 260, core 261, cache 262, memory Controller 263, home agent 264, CXL root port 265, CXL switch 270, CXL endpoint 281, CXL endpoint 283, CXL memory controller 285, memory media 287, DIMM 290, host device 310, memory box 320, mode manager 321, sensor interface 321-1, first controller 321-2, second controller 321-3, first group 322-1, second group 322-2, switch 323, current sensor 324-1, voltage sensor 324-2, temperature sensor 324-3, 24-3, host device 410, memory box 420, mode manager 421, sensor interface 421-1, first controller 421-2, second controller 421-3, first group 422-1, second group 422-2, switch 423, current sensor 424-1, voltage sensor 424-2, temperature sensor 424-3, host device 510, memory box 520, mode manager 521, sensor interface 521-1, first controller 521-2, second controller 521-3, first group 522-1, second group 522-2,switch 523, current sensor 524-1, voltage sensor 524-2, temperature sensor 524-3, host device 610, memory box 620, mode manager 621, controller 621-1, first group 622-1, second group 622-2, switch 623, upstream port 623-1, bandwidth limiter 623-2, first downstream port 623-3, second downstream port 623-4, sensor 624, host device 710, memory box 720, The mode manager 721, the controller 721-1, the first group 722-1, the second group 722-2, the switch 723, the sensor 724, the rack cabinet 800, the mode manager 810, the sensor 820, the first group 830-1, the second group 830-2, and other devices, apparatuses, units, modules, and components disclosed and described herein in connection with FIGS. 1-1 may be embodied by and are representative of hardware components.

[0107] As mentioned above, or in addition to the above description, examples of hardware components that may be used to perform the operations described in the present application, where appropriate, include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dispensers, integrators, and any other electronic components configured to perform the operations described in the present application. As a different example, one or more of the hardware components performing the operations described in this application may be realized by computing hardware, for example, by one or more processors or computers. A processor or computer may be realized by one or more processing elements, for example, an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices configured to respond to and execute instructions in a defined manner to achieve a desired result. As an example, a processor or computer may include or be connected to one or more memories that store instructions or software executed by the processor or computer. The hardware components embodied by a processor or computer may execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform operations described in the applications. The hardware components may also access, manipulate, process, generate, and store data in response to the execution of the instructions or software. For simplicity, a single term "processor" or "computer" may be used to describe the examples described in this application, although in different examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both.For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or a controller that is different from the other processors. One or more processors, or a processor and a controller, may be implemented by a single hardware component or two or more hardware components. As mentioned above, or in addition to the above description, the exemplary hardware components may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

[0108] Among the methods illustrated in Figures 1-9, the methods for performing the operations described in this application may be performed by computing hardware, e.g., one or more processors or computers, which may be executed to perform the operations described in this application as implementation instructions or software embodied as described above. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or other processors and further controllers. One or more processors, or a processor and a controller may perform a single operation or two or more operations.

[0109] The instructions or software for implementing computing hardware, e.g., one or more processors or computers, hardware components and performing the methods as described above, may be created as computer programs, code segments, instructions, or any combination thereof, which individually or collectively instruct or configure one or more processors or computers to operate as a machine or special purpose computer to perform the operations performed by the hardware components and methods described above. In one example of the components and methods described above, the instructions or software include machine code executed directly by one or more processors or computers, such as machine code generated by a compiler. In another example, the instructions or software include higher level code executed by one or more processors or computers using an interpreter. The instructions or software may be created using any programming language based on the block diagrams and flow charts illustrated in the figures and corresponding descriptions herein, which disclose algorithms for performing the operations performed by the hardware components and methods as described above.

[0110] The instructions or software for controlling computing hardware, e.g., one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, are recorded, stored, or fixed on one or more non-transitory computer-readable storage media, and thus are not signals per se. As mentioned above, or in addition to the above, examples of non-transitory computer-readable storage media include one or more of the following: Read-Only Memory (ROM), Random-Access Programmable Read Only Memory (PROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Random-Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, and non-volatile memory. This may include CD-ROM, CD-RS, CD+Rs, CD-RW, CD+RW, DVD-ROM, DVD-RS, DVD+Rs, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-RS, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drives (HDD), solid state drives (SSD), flash memory, multimedia card micro or card-type memory such as cards (e.g., Secure Digital (SD) or Extreme Digital (XD)), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk, and other devices configured to store instructions or software and any associated data, data files and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files and data structures to one or more processors or computers for execution by the one or more processors or computers.As an example, the instructions or software and any associated data, data files, and data structures may be distributed across a network-coupled computer system, where the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by one or more processors or computers.

[0111] Although the disclosure includes specific examples, it will be apparent after reading the disclosure of this application that various changes in form and details may be made without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered merely in an illustrative sense and not for purposes of limitation. In each example, the description of a feature or aspect should be considered as applicable to the similar feature or aspect in the different examples. Appropriate results can be achieved when the techniques described are performed in different orders, and / or when components in the described systems, architectures, devices or circuits are combined in different ways, and / or when other components or equivalents are substituted or supplemented.

[0112] Therefore, besides the disclosure of the above and all drawings, the scope of the disclosure should be construed to include the claims and their equivalents, i.e., all modifications within the scope of the claims and their equivalents are to be included in the disclosure.

Claims

1. A memory box, the memory box comprising: a memory device including memory cells for storing data; a sensor for measuring state information of the memory device; a mode manager that divides the memory devices into a plurality of groups, receives priorities among the plurality of groups from a host device, receives status information from the sensors, and dynamically adjusts an operating mode of the plurality of groups based on the priorities and the status information. Memory box.

2. 2. The memory box of claim 1, wherein the mode manager determines current operating modes of the multiple groups according to the priority, compares the status information with limit resource information corresponding to the status information, and changes the current operating modes of the multiple groups based on a result of the comparison, in order to dynamically adjust the operating modes.

3. The memory box of claim 1 , wherein the mode manager divides the memory devices into a plurality of groups according to characteristics of the memory devices to divide the memory devices into the plurality of groups.

4. the memory devices have the same characteristics as each other; The memory box according to claim 1 , wherein the mode manager divides the memory devices into the plurality of groups according to operational importance of the memory devices.

5. The memory box of claim 1 , wherein the mode manager includes a controller that controls the groups so that the groups can operate in corresponding operation modes.

6. 2. The memory box of claim 1, wherein the mode manager dynamically adjusts the operating mode by setting the multiple high priority groups to a first operating mode that operates them with a predetermined performance, and setting the multiple low priority groups to a second operating mode that operates them within a range that does not exceed limit resource information corresponding to the status information.

7. The mode manager includes: a first controller that controls the high priority group to operate in the first operation mode; a second controller that controls the low priority group to operate in the second operation mode; 7. The memory box of claim 6, comprising:

8. The memory box of claim 1 , wherein the memory device comprises a Compute Express Link (CXL) memory device.

9. a switch connecting the memory device and the host device; 2. The memory box of claim 1, wherein the mode manager receives priorities among the plurality of groups from the host device via the switch for receiving the priorities.

10. A memory box according to claim 1; A host device; A computing system comprising:

11. The computing system of claim 10 , further comprising a switch configured to connect the host device to the memory box.

12. A switch comprising: a processor that divides memory devices into a plurality of groups, receives priorities among the plurality of groups from a host device, receives status information of the memory devices from a sensor, and dynamically adjusts operating modes of the plurality of groups based on the priorities and the status information.

13. a bandwidth limiter for adjusting a bandwidth of data transmission between the host device and the plurality of groups; a controller for controlling the bandwidth limiter so that the plurality of groups can operate in a corresponding mode of operation; The switch of claim 12 further comprising:

14. 13. The switch of claim 12, wherein the switch is configured to connect the host device and the memory device; the memory device including memory cells for storing data; the sensor configured to measure the status information; Including the memory box.

15. 1. A computing system, comprising: A host device; a plurality of memory boxes each including a memory device including memory cells for storing data; A sensor for measuring state information of the plurality of memory boxes; a mode manager that divides the memory boxes into a plurality of groups, receives status information from the sensors, and dynamically adjusts an operation mode of the plurality of groups based on the status information. Computing system.

16. The computing system of claim 15 , wherein the mode manager divides the memory boxes into the groups according to characteristics of the memory boxes for the division of the memory boxes.

17. The memory boxes have the same characteristics as each other, The computing system of claim 15 , wherein the mode manager divides the memory boxes into the groups according to operational importance of the memory boxes for dividing the memory boxes.

18. A computing system according to claim 15; a plurality of compute servers including the host device; Including, the state information relates to the plurality of compute servers and the plurality of memory boxes; The mode manager divides the plurality of compute servers and the plurality of memory boxes into a plurality of groups, receives priorities among the plurality of groups, and dynamically adjusts operating modes of the plurality of groups based on the priorities and the status information.

19. A control method, the control method comprising: obtaining status information of a memory device; dividing the memory devices into a plurality of groups; obtaining a priority among the groups; and dynamically adjusting an operational mode of the plurality of groups based on the priority and the status information. Control methods.

20. The step of dynamically adjusting the operation mode includes: determining a current operation mode of the plurality of groups according to the priority order; comparing the status information with limit resource information corresponding to the status information; modifying the current operating modes of the plurality of groups based on a result of the comparison; 20. The control method of claim 19, comprising:

21. 20. The method of claim 19, wherein the dividing step comprises dividing the memory devices into the plurality of groups according to characteristics of the memory devices.

22. the memory devices have the same characteristics as each other; 20. The method of claim 19, wherein the dividing step includes dividing the memory devices into the plurality of groups according to operational importance of the memory devices.

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