Integrated circuit element

Abstract

To provide an integrated circuit element of which an integration degree and reliability are improved.SOLUTION: An integrated circuit element 100 contains: a plurality of gap fill insulation films 222 that is arranged so as to be separated each other between adjacent element separation films; a plurality of gate structure materials 162 that is separated each other to a first horizontal direction on a gap fill insulation film; a first source / drain region and a second source / drain regions 130a and b that are arranged to both sides along a first horizontal direction of the first gate structure material selected from the gate structure material, respectively; an insulation block 212 that is arranged to a lower side of the first source / drain region; an insulation barrier 124 that covers a bottom surface of the first source / drain region, and is interposed between the first source / drain region and the insulation block; and a lower part contact 232 that is contacted to the bottom surface of the second source / drain region in the lower side of the second source / drain region, and is separated from the insulation block in a first horizontal direction while nipping the first gap fill insulation film selected from the plurality of gap fill insulation films.SELECTED DRAWING: Figure 2A

Description

[Technical field]

[0001] The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices that include power rails. [Background technology]

[0002] With the development of electronic technology, the downscaling of integrated circuit devices has been rapidly progressing recently. Since semiconductor devices are required to operate at high speeds as well as with high accuracy, various researches are being conducted to optimize the structure of transistors included in the semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-91893 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide an integrated circuit element with improved integration density and reliability. It is another object of the present invention to provide a method for manufacturing an integrated circuit device with improved integration density and reliability. [Means for solving the problem]

[0005] In order to achieve the above object, an integrated circuit device according to one aspect of the present invention includes a plurality of isolation films extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a plurality of gap-fill insulating films arranged along the first horizontal direction between two adjacent isolation films among the plurality of isolation films; a plurality of gate structures extending in the second horizontal direction and spaced apart from each other in the first horizontal direction on the plurality of gap-fill insulating films; a first source / drain region and a second source / drain region respectively arranged on both sides along the first horizontal direction of a first gate structure selected from the plurality of gate structures; an insulating block arranged below the first source / drain region; an insulating barrier covering a bottom surface of the first source / drain region and arranged between the first source / drain region and the insulating block; and a lower contact in contact with a bottom surface of the second source / drain region below the second source / drain region and spaced apart from the insulating block in the first horizontal direction across a first gap-fill insulating film selected from the plurality of gap-fill insulating films.

[0006] In order to achieve the above object, an integrated circuit device according to an exemplary embodiment of the present invention includes a back trench extending long along a first horizontal direction, and a plurality of isolation films spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, in the back trench, a plurality of gap-fill insulating films arranged spaced apart from each other along the first horizontal direction, a plurality of insulating barriers arranged between the plurality of gap-fill insulating films in the back trench, a first source / drain region on a first insulating barrier among the plurality of insulating barriers, a second source / drain region on a second insulating barrier among the plurality of insulating barriers, a gate structure arranged between the first source / drain region and the second source / drain region and on the first gap-fill insulating film among the plurality of gap-fill insulating films, a first insulating block facing a bottom surface of the first source / drain region in a vertical direction across the first insulating barrier, and a lower contact spaced from the first insulating block in the first horizontal direction across the first gap-fill insulating film, and contacting the second source / drain region through the second insulating barrier.

[0007] In order to achieve the above object, an integrated circuit device according to an exemplary embodiment of the present invention includes a plurality of isolation films extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, a plurality of gap-fill insulating films arranged spaced apart from each other along the first horizontal direction between two adjacent isolation films among the plurality of isolation films, a nanosheet stack including at least one nanosheet disposed at a position vertically spaced apart from an upper surface of a first gap-fill insulating film selected from the plurality of gap-fill insulating films and facing an upper surface of the first gap-fill insulating film, and a first gap-fill insulating film stack including at least one nanosheet stack arranged at a position vertically spaced apart from an upper surface of the first gap-fill insulating film, and a second gap-fill insulating film stack including at least one nanosheet stack arranged at a position vertically spaced apart from an upper surface of the first gap-fill insulating film, The gate structure includes a gate structure extending elongately in the second horizontal direction on the film and surrounding the nanosheet stack, a first source / drain region and a second source / drain region respectively arranged on either side of the gate structure along the first horizontal direction, an insulating block arranged below the first source / drain region, an insulating barrier arranged vertically between the first source / drain region and the insulating block and having an upper surface arranged at a vertical level higher than a bottom surface of the gate structure, and a lower contact separated from the insulating block in the first horizontal direction by the first gap-fill insulating film below the second source / drain region. Effect of the Invention

[0008] The integrated circuit element according to the present invention includes an insulating barrier disposed on a bottom surface of a first source / drain region among the plurality of source / drain regions. The insulating barrier includes a sidewall facing the gate electrode. Thus, the semiconductor substrate is removed without damaging the first source / drain region and without remaining in the vicinity of the bottom surface of the first source / drain region. This improves the integration density and reliability of the integrated circuit element. [Brief description of the drawings]

[0009] [Figure 1] 1 is a planar layout diagram of a partial configuration of an integrated circuit element according to an embodiment of the present invention. [Figure 2A] 2 is a cross-sectional view taken along the line X1-X1' in FIG. [Figure 2B] 2 is a cross-sectional view showing the configuration of a cross section taken along line Y1-Y1' and a cross section taken along line Y2-Y2' in FIG. [Figure 2C] FIG. 2B is an enlarged view of the area marked "EX1" in FIG. 2A. [Figure 2D] FIG. 2C is an enlarged view of the area marked "EX2" in FIG. 2B. [Figure 3A] 1. FIG. 4 is a cross-sectional view for explaining an integrated circuit element according to another embodiment, the cross-sectional view corresponding to the cross-section taken along line X1-X1' in FIG. [Figure 3B] FIG. 3B is an enlarged view of the area marked "EX3" in FIG. 3A. [Figure 4A] 1. FIG. 4 is a cross-sectional view for explaining an integrated circuit element according to still another embodiment, the cross-sectional view corresponding to the cross section taken along line X1-X1' in FIG. [Figure 4B] FIG. 4B is an enlarged view of the area marked "EX4" in FIG. 4A. [Figure 5A] 1. FIG. 4 is a cross-sectional view for explaining an integrated circuit element according to still another embodiment, the cross-sectional view corresponding to the cross section taken along line X1-X1' in FIG. [Figure 5B] FIG. 5B is an enlarged view of the area marked "EX5" in FIG. 5A. [Figure 6A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 6B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 7A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 7B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 8A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 8B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 9A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 9B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 10A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 10B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 11A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 11B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 12] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 13] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 14A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 14B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 15A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 15B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 16A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 16B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 17A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 17B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 18A] 1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 18B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. [Figure 19A]1A to 1C are cross-sectional views illustrating a process sequence for explaining a method for manufacturing an integrated circuit device according to an embodiment of the present invention, the cross-sectional views corresponding to the cross section taken along line X1-X1' in FIG. [Figure 19B] 2A to 2C are cross-sectional views of a portion corresponding to the cross sections taken along the lines Y1-Y1' and Y2-Y2' in FIG. 1 in a process sequence. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and duplicated description thereof will be omitted.

[0011] In this specification, the vertical direction is defined as the Z direction, and the horizontal direction is defined as the direction perpendicular to the Z direction. The first horizontal direction and the second horizontal direction are defined as directions intersecting each other. The first horizontal direction is referred to as the X direction, and the second horizontal direction is referred to as the Y direction. The vertical level refers to the height level along the vertical direction (Z direction).

[0012] Fig. 1 is a planar layout diagram showing a partial configuration of an integrated circuit device 100 according to an embodiment of the present invention. Fig. 2A is a cross-sectional view taken along line X1-X1' in Fig. 1, Fig. 2B is a cross-sectional view showing the configuration of a cross section taken along line Y1-Y1' and a cross section taken along line Y2-Y2' in Fig. 1, Fig. 2C is an enlarged view of an area marked "EX1" in Fig. 2A, and Fig. 2D is an enlarged view of an area marked "EX2" in Fig. 2B.

[0013] According to an exemplary embodiment described below with reference to FIGS. 1 and 2A-2D, an integrated circuit device 100 constitutes a logic cell including a gate-all-around FET device including a nanowire- or nanosheet-shaped active region and a gate surrounding the active region. For example, the integrated circuit device includes a multi-bridge channel FET (MBCFET) device. However, the technical idea of ​​the present invention is not limited thereto, and the integrated circuit device 100 may include a planar FET device, a fin FET device, etc.

[0014] 1 and 2A-2D, an integrated circuit device 100 includes a backside structure BSS and a frontside structure FSS on the backside structure BSS. According to an exemplary embodiment, the backside structure BSS includes a plurality of device isolation films 114, a plurality of gap fill insulating films 222, a plurality of insulating blocks 212, a plurality of bottom contacts 232, and a backside power rail. According to an exemplary embodiment, the frontside structure FSS includes a plurality of nanosheet stack NSS, a plurality of gate electrodes 160, a plurality of source / drain regions 130, a plurality of insulating barriers 124, and a plurality of top contacts 172.

[0015] According to an exemplary embodiment, the isolation films 114 extend long in a first horizontal direction (X direction), sandwich a plurality of backside trenches BT, and are spaced apart from each other in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). For example, the isolation films 114 extend parallel to each other along the first horizontal direction (X direction). For example, the backside trenches BT extend long in the first horizontal direction (X direction) and are defined by the isolation films 114.

[0016] In some embodiments, the isolation layer 114 comprises at least one selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0017] According to an exemplary embodiment, a plurality of gap-fill insulating films 222 are arranged in each of the back trenches BT along the first horizontal direction (X direction) at a distance from each other. The gap-fill insulating films 222 extend in the vertical direction (Z direction) in the back trenches BT. According to an exemplary embodiment, both side walls of the gap-fill insulating films 222 in the second horizontal direction (Y direction) contact the isolation film 114.

[0018] In some embodiments, the gap-fill insulating films 222 are made of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof, including but not limited to the above examples. As used herein, the terms "SiN," "SiO," "SiCN," "SiBN," "SiON," "SiOCN," "SiBCN," and "SiOC" refer to materials made of the elements contained therein, and are not intended to represent chemical formulas that indicate stoichiometric relationships.

[0019] According to an exemplary embodiment, an active structure is disposed on each of the plurality of gap-fill insulating films 222. For example, the active structure has a fin shape, a nanowire shape, or a nanosheet shape. In Figures 2A-2C, the active structure is illustrated as being a nanosheet stack NSS, but is not limited thereto.

[0020] According to an exemplary embodiment, the plurality of nanosheet stacks NSS are individually disposed on the plurality of gap-fill insulating films 222, respectively. In this specification, the nanosheet stacks NSS are referred to as nanosheet structures. According to an exemplary embodiment, the plurality of nanosheet stacks NSS each include at least one nanosheet. According to an exemplary embodiment, each of the plurality of nanosheet stacks NSS is disposed at a position spaced apart in the vertical direction (Z direction) from the upper surface of each of the plurality of gap-fill insulating films 222, respectively.

[0021] The multiple nanosheet stack NSS includes multiple nanosheets, such as a first nanosheet N1, a second nanosheet N2, a third nanosheet N3, and a fourth nanosheet N4, each of which is vertically spaced apart from one another (Z direction) and vertically overlapped. The term "nanosheet" as used herein means a conductive structure having a cross section substantially perpendicular to the direction of current flow. Nanosheets should be understood to include nanowires. Also, in this specification, the multiple nanosheets N1, N2, N3, N4, or the nanosheet stack NSS, are referred to as a channel region.

[0022] The first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 are different from each other in distance in the vertical direction (Z direction) from the upper surface of the gap-fill insulating film 222. Each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 included in the nanosheet stack NSS has a channel region. For example, the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 each have a thickness along the vertical direction (Z direction) selected within a range of about 4 nm to 6 nm, but are not limited thereto. In some embodiments, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 have substantially the same thickness along the vertical direction (Z direction). In other embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses along the vertical direction (Z direction).

[0023] In some embodiments, at least some of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 included in one nanosheet stack NSS have different sizes in the first horizontal direction (X direction). In other embodiments, at least some of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 may have the same size in the first horizontal direction (X direction).

[0024] According to an exemplary embodiment, a plurality of gate structures 162 are disposed on the plurality of device isolation films 114, extending long in the second horizontal direction (Y direction) across the plurality of device isolation films 114. According to an exemplary embodiment, a plurality of gap-fill insulating films 222 are disposed in regions where the plurality of gate structures 162 and the plurality of back trenches BT intersect, and the plurality of gate structures 162 cover the plurality of nanosheet stacks NSS on the plurality of gap-fill insulating films 222 to surround each of the plurality of nanosheets N1, N2, N3, and N4. For example, a first group of nanosheet stacks NSS arranged along the second horizontal direction (Y direction) among the plurality of nanosheet stacks NSS is surrounded by the first gate structure 162 among the plurality of gate structures 162. According to an exemplary embodiment, each of the plurality of gate structures 162 contacts the plurality of nanosheet stacks NSS and includes a portion overlapping the plurality of nanosheet stacks NSS.

[0025] According to an exemplary embodiment, a plurality of transistors are formed in the overlapping portions of the plurality of nanosheet stacks NSS and the plurality of gate structures 162. According to an exemplary embodiment, the plurality of transistors may include PMOS transistors and NMOS transistors. For example, each of the plurality of transistors is composed of at least one nanosheet stack NSS, a gate structure 162 surrounding the at least one nanosheet stack NSS, and a source / drain region 130 facing the at least one nanosheet stack NSS in the first horizontal direction (X direction).

[0026] In some embodiments, the nanosheets N1, N2, N3, and N4 are each composed of an undoped Si layer. In other embodiments, the nanosheets N1, N2, N3, and N4 are each composed of a doped Si layer. For example, when the nanosheets N1, N2, N3, and N4 constitute a PMOS transistor, the nanosheets N1, N2, N3, and N4 are each composed of a Si layer doped with a p-type dopant, and when the nanosheets N1, N2, N3, and N4 constitute an NMOS transistor, the nanosheets N1, N2, N3, and N4 are each composed of a Si layer doped with an n-type dopant, but are not limited thereto. The p-type dopant is selected from B (boron) and Ga (gallium). The n-type dopant is selected from P (phosphorus), As (arsenic), and Sb (antimony).

[0027] According to an exemplary embodiment, the gate structures 162 surround the nanosheet stacks NSS on the gap-fill insulating films 222 and extend parallel to each other along the second horizontal direction (Y direction). For example, the gate structures 162 are spaced apart from each other in the first horizontal direction (X direction). According to an exemplary embodiment, each of the gate structures 162 includes a gate electrode 160 and a gate dielectric film 152 disposed between the nanosheet stacks NSS and the gate electrode 160.

[0028] According to an exemplary embodiment, each of the multiple gate electrodes 160 includes a main gate portion 160M and multiple sub-gate portions 160S. The main gate portion 160M covers the upper surface of the nanosheet stack NSS and extends in the second horizontal direction (Y direction). The multiple sub-gate portions 160S are integrally connected to the main gate portion 160M, and are disposed one by one between each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4, and between the first nanosheet N1 and the gap-fill insulating film 222. In the vertical direction (Z direction), the thickness of each of the multiple sub-gate portions 160S is thinner than the thickness of the main gate portion 160M.

[0029] In some embodiments, each of the gate electrodes 160 is made of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal is selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride is selected from TiN and TaN. The metal carbide is TiAlC. However, the materials constituting the gate electrodes 160 are not limited to those exemplified.

[0030] In some embodiments, the gate dielectric layer 152 is a laminated structure of an interface dielectric layer and a high dielectric layer. The interface dielectric layer is a low dielectric material layer having a dielectric constant of about 9 or less, such as a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. In other embodiments, the interface dielectric layer may be omitted. The high dielectric layer is a material having a dielectric constant greater than that of a silicon oxide layer. For example, the high dielectric layer has a dielectric constant of about 10 to 25. The high dielectric layer may be made of, but is not limited to, hafnium oxide.

[0031] According to an exemplary embodiment, the upper surfaces of the gate structures 162 are covered with a capping insulating pattern 168. For example, the upper surfaces of the gate electrode 160 and the gate dielectric layer 152 are each covered with a capping insulating pattern 168. In some embodiments, the capping insulating pattern 168 includes silicon nitride.

[0032] According to an exemplary embodiment, both side walls of the gate structure 162 and the capping insulating pattern 168 are covered with an outer insulating spacer 116. The outer insulating spacer 116 covers both side walls of the main gate portion 160M on the upper surface of the plurality of nanosheet stacks NSS. The outer insulating spacer 116 is separated from the gate electrode 160 with the gate dielectric film 152 interposed therebetween.

[0033] According to an exemplary embodiment, the source / drain regions 130 are repeatedly arranged between the gate structures 162 along the first horizontal direction (X direction) and the second horizontal direction (Y direction). According to an exemplary embodiment, the source / drain regions 130 are spaced apart from one another in the first horizontal direction (X direction) with the respective nanosheet stacks NSS therebetween. For example, the source / drain regions 130 and the nanosheet stacks NSS are alternately arranged with one another along the first horizontal direction (X direction). According to an exemplary embodiment, two source / drain regions 130 adjacent to one another in the second horizontal direction (Y direction) are spaced apart from one another in the second horizontal direction (Y direction) with an inter-gate insulating film 144, which will be described later, therebetween. In some embodiments, the source / drain regions 130 each fill a portion of the back trenches BT.

[0034] According to an exemplary embodiment, both side surfaces in the first horizontal direction (X direction) of each of the multiple nanosheet stacks NSS face the source / drain region 130. According to an exemplary embodiment, the multiple source / drain regions 130 face the multiple nanosheets N1, N2, N3, N4 arranged adjacently and the sub-gate portion 160S of the gate electrode 160 in the first horizontal direction (X direction). For example, each of the multiple source / drain regions 130 contacts one nanosheet stack NSS and one part of the gate structure 162 on both sides in the first horizontal direction (X direction).

[0035] According to an exemplary embodiment, each of the source / drain regions 130 includes a pair of source / drain barriers 132 and a source / drain body 134 between the pair of source / drain barriers 132. According to an exemplary embodiment, the pair of source / drain barriers 132 covers the nanosheets N1, N2, N3, and N4 arranged adjacent to each other on both sides along the first horizontal direction (X direction) and the sub-gate portion 160S of the gate electrode 160. For example, each source / drain barrier 132 contacts one side of the nanosheets N1, N2, N3, and N4 and faces the sub-gate portion 160S of the gate electrode 160 with the gate dielectric film 152 interposed therebetween. According to an exemplary embodiment, the source / drain body 134 is separated from the nanosheets N1, N2, N3, and N4 and the sub-gate portion 160S on both sides along the first horizontal direction (X direction) with the source / drain barriers 132 interposed therebetween.

[0036] In some embodiments, the pair of source / drain barriers 132 are spaced apart from each other in a first horizontal direction (X-direction) with the source / drain body 134 therebetween. In some embodiments, each source / drain barrier 132 is interposed between the source / drain body 134 and the plurality of nanosheets N1, N2, N3, N4 and extends in a vertical direction (Z-direction). In some embodiments, the pair of source / drain barriers 132 are made of a different material from the source / drain body 134, or have different composition ratios from each other even if they contain the same material.

[0037] In some embodiments, the first group of the source / drain regions 130 constitutes a PMOS transistor. In some embodiments, the source / drain barrier 132 and the source / drain body 134 of the first group of source / drain regions 130 are each made of Si doped with a p-type dopant. 1-x Ge xIt consists of a layer (where 0.0 < x ≤ 0.6), and the Ge content ratio of the source / drain body 134 is greater than the Ge content ratio of the source / drain barrier 132. In some embodiments, the Ge content ratio of the source / drain barrier 132 is greater than about 0.0 atomic % and less than or equal to about 20 atomic %, for example, greater than or equal to about 15 atomic % and less than or equal to about 30 atomic %. The Ge content ratio of the source / drain body 134 is greater than or equal to about 30 atomic % and less than or equal to about 60 atomic %, for example, greater than or equal to about 40 atomic % and less than or equal to about 60 atomic %. However, the technical idea of the present invention is not limited to the above-exemplified ones. In some embodiments, the p-type dopant is at least one selected from B (boron) and Ga (gallium), but is not limited thereto. In some embodiments, the source / drain region 130 of the first group may further include a first semiconductor capping layer (not shown) covering the upper surface of the source / drain body 134. The first semiconductor capping layer (not shown) consists of an undoped Si layer, a Si layer doped with a p-type dopant, or a SiGe layer having a Ge content ratio smaller than that of the source / drain body 134.

[0038] In some other embodiments, the second group of the source / drain regions 130 constitutes an NMOS transistor. The source / drain barrier 132 of the second group of source / drain regions 130 is made of an undoped Si layer, and the source / drain body 134 is made of a Si layer doped with an n-type dopant. In some other embodiments, the source / drain barrier 132 and the source / drain body 134 are made of Si layers doped with an n-type dopant, but the content ratio of the n-type dopant in the source / drain body 134 is greater than the content ratio of the n-type dopant in the source / drain barrier 132. The n-type dopant is at least one selected from, but not limited to, P (phosphorus), As (arsenic), and Sb (antimony). In some embodiments, the second group of source / drain regions 130 further includes a second semiconductor capping layer (not shown) covering an upper surface of the source / drain body 134. The second semiconductor capping layer (not shown) is made of an undoped Si layer or a Si layer doped with an n-type dopant. When the second semiconductor capping layer (not shown) is made of a Si layer doped with an n-type dopant, the content ratio of the n-type dopant in the second semiconductor capping layer (not shown) is smaller than the content ratio of the n-type dopant in the source / drain barrier 132.

[0039] 2B, trench-side insulating spacers 119 covering lower portions of sidewalls in the second horizontal direction (Y direction) of the source / drain regions 130 are disposed on the element isolation films 114. For example, the trench-side insulating spacers 119 contact lower sidewalls of the source / drain regions 130.

[0040] In some embodiments, the vertical level of the top of the trench-side insulating spacer 119 is higher than the vertical level of the lowest surface of the source / drain regions 130. In some embodiments, the trench-side insulating spacer 119 together with the device isolation films 114 define the back trenches BT.

[0041] In some embodiments, trench-side insulating spacers 119 are made of silicon nitride (SiN), silicon oxide (SiO), SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. As used herein, the terms "SiN," "SiO," "SiCN," "SiBN," "SiON," "SiOCN," "SiBCN," and "SiOC" refer to materials made of the elements contained therein and not to chemical formulas indicating stoichiometric relationships.

[0042] According to an exemplary embodiment, the plurality of element isolation films 114, the plurality of source / drain regions 130, the trench-side insulating spacer 119, and the outer insulating spacer 116 are covered with an insulating liner 142. According to an exemplary embodiment, an inter-gate insulating film 144 is disposed on the insulating liner 142. According to an exemplary embodiment, the insulating liner 142 and the inter-gate insulating film 144 are disposed between two source / drain regions 130 adjacent to each other in the second horizontal direction (Y direction).

[0043] In some other embodiments, the insulating liner 142 is omitted, in which case the inter-gate insulating film 144 contacts multiple source / drain regions 130.

[0044] In some embodiments, the insulating liner 142 is selected from the group consisting of SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO 2 In some embodiments, inter-gate insulating film 144 is made of silicon nitride, silicon oxide, SiON, SiOCN, or a combination thereof.

[0045] According to an exemplary embodiment, the source / drain regions 130 include a plurality of first source / drain regions 130a and a plurality of second source / drain regions 130b. According to an exemplary embodiment, the first source / drain regions 130a and the second source / drain regions 130b are spaced apart from each other in a first horizontal direction (X direction) with one nanosheet stack NSS in between. For example, the first source / drain region 130a functions as a drain region, and the second source / drain region 130b functions as a source region. In FIG. 1, the first source / drain regions 130a are illustrated as being arranged in a line along the second horizontal direction (Y direction), and the second source / drain regions 130b are illustrated as being spaced apart from the first source / drain regions 130a with one gate structure 162 in between, but are not limited thereto. For example, at least one first source / drain region 130a and at least one second source / drain region 130b are arranged along the second horizontal direction (Y direction) between two adjacent gate structures 162. In some embodiments, the first source / drain regions 130a and the second source / drain regions 130b have the same shape as illustrated in Figures 2A and 2B. In other embodiments, the first source / drain regions 130a and the second source / drain regions 130b have different shapes, for example, different horizontal widths or different vertical thicknesses.

[0046] According to an exemplary embodiment, the integrated circuit element 100 further includes a plurality of upper contacts 172 disposed on the plurality of first source / drain regions 130a. Each of the plurality of upper contacts 172 extends longitudinally in the vertical direction (Z direction) between a pair of adjacent gate structures 162 among the plurality of gate structures 162. A metal silicide film (not shown) is disposed between the first source / drain regions 130a and the upper contacts 172.

[0047] The upper contacts 172 each fill an upper contact hole 172H that penetrates the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (Z direction) and extends to the inside of each of the first source / drain regions 130a. In some embodiments, the upper contacts 172 electrically connect wiring (not shown) on the upper contacts to the first source / drain regions 130a. The first source / drain regions 130a are each separated from the upper contact 172 by a metal silicide film (not shown). The first source / drain regions 130a each surround a bottom of the upper contacts 172 outside the upper contact hole 172H.

[0048] In some embodiments, the metal silicide film (not shown) is made of, but is not limited to, titanium silicide. In other embodiments, the metal silicide film (not shown) can be omitted. In some embodiments, the plurality of top contacts 172 are each made of a metal, a conductive metal nitride, or a combination thereof. For example, the plurality of top contacts 172 are each made of W, Cu, Al, Ti, Ta, TiN, TaN, alloys thereof, or a combination thereof.

[0049] According to an exemplary embodiment, a plurality of insulating blocks 212 are disposed on the bottom surfaces of the plurality of first source / drain regions 130a, respectively. For example, the plurality of insulating blocks 212 overlap the plurality of first source / drain regions 130a in the vertical direction (Z direction). According to an exemplary embodiment, the plurality of insulating blocks 212 extend in the plurality of back trenches BT in the vertical direction (Z direction), and both side walls of the plurality of insulating blocks 212 along the first horizontal direction (X direction) face and contact the gap-fill insulating film 222, and both side walls of the plurality of second insulating blocks 212 in the second horizontal direction (Y direction) face and contact the element isolation film 114.

[0050] According to an exemplary embodiment, a plurality of insulating barriers 124 are disposed between the first source / drain regions 130a and the insulating blocks 212, respectively. The insulating barriers 124 cover bottom surfaces of the first source / drain regions 130a in the back trenches BT. For example, the bottom surfaces of the first source / drain regions 130a face the upper surfaces of the respective insulating blocks 212 with the insulating barriers 124 interposed therebetween.

[0051] According to an exemplary embodiment, the upper surfaces 124U of the insulating barriers 124 are in contact with the bottom surfaces of the pair of source / drain barriers 132 and the bottom surface of one source / drain body 134. According to an exemplary embodiment, the pair of source / drain barriers 132 and the source / drain body 134 of each of the first source / drain regions 130a are separated from the insulating block 212 and the gap-fill insulating films 222 by the insulating barriers 124. For example, the gap-fill insulating films 222 have sidewalls facing the insulating barriers 124 and / or the insulating blocks 212, and entirely cover the bottom surface 162L of the gate structure 162.

[0052] 2C and 2D, the bottom surfaces 162L of the gate structures 162 are disposed at a first vertical level LV1. For example, the gate dielectric film 152 covering the bottom surfaces of the lowest ends of the gate electrodes 160 is disposed at the first vertical level LV1. According to an exemplary embodiment, the top surfaces 124U of the insulating barriers 124 are disposed at a second vertical level LV2 higher than the first vertical level LV1. In some embodiments, the top surfaces 124U of the insulating barriers 124 are disposed at a vertical level higher than the bottom surfaces of the lowest ends of the sub-gate portions 160S of the gate electrodes 160. For example, the top surfaces of the gap-fill insulating films 222 are in contact with the bottom surfaces 162L of the gate structures 162, respectively, and are disposed at a vertical level lower than the top surfaces 124U of the insulating barriers 124.

[0053] According to an exemplary embodiment, both sidewalls of the insulating barriers 124 along the first horizontal direction (X direction) each include a portion facing the gate structure 162. In some embodiments, both sidewalls of the insulating barriers 124 along the first horizontal direction (X direction) are separated from the bottom sub-gate portion 160S of the gate electrode 160 by the gate dielectric film 152.

[0054] In some embodiments, bottom surfaces of the insulating barriers 124 are disposed at a vertical level lower than the first vertical level LV1. In this case, both side walls of the insulating barriers 124 along the first horizontal direction (X direction) include portions that contact and face the gap-fill insulating films 222. In other embodiments, bottom surfaces of the insulating barriers 124 are disposed at the same level as the first vertical level LV1 or at a vertical level higher than the first vertical level LV1. In this case, side walls of the insulating blocks 212 include portions that face the gate structures 162.

[0055] In some embodiments, both side walls of the insulating barriers 124 along the second horizontal direction (Y direction) include a portion in contact with the trench-side insulating spacer 119 and a portion in contact with the element isolation film 114.

[0056] In some embodiments, the insulating barriers 124 and the insulating blocks 212 are each independently made of silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or combinations thereof. As used herein, the terms "SiCN," "SiBN," "SiON," "SiOCN," "SiBCN," and "SiOC" refer to materials made of the elements contained therein and not to chemical formulas indicating stoichiometric relationships.

[0057] In some embodiments, the insulating barriers 124 are made of a different material than the gap-fill dielectrics 222. In some embodiments, the insulating blocks 212 are made of a different material than the gap-fill dielectrics 222.

[0058] According to an exemplary embodiment, the insulating barriers 124 of the integrated circuit device 100 cover the bottom surfaces of the first source / drain regions 130a to prevent them from being exposed. The insulating barriers 124 protect the source / drain regions 130 from being etched during the manufacturing process of the integrated circuit device 100, or prevent surrounding semiconductor material from remaining unremoved and contacting the first source / drain regions 130a to induce leakage current. For example, the insulating barriers 124 are disposed between the first source / drain regions 130a and the gap-fill insulating films 222, and the gap-fill insulating films 222 contact the entire bottom surface 162L of the gate structure 162 and are separated from the first source / drain regions 130a. This prevents power loss in the integrated circuit device 100 and improves electrical reliability.

[0059] According to an exemplary embodiment, a plurality of lower contacts 232 are disposed on the bottom surfaces of the second source / drain regions 130b, respectively, filling a portion of the back trenches BT and extending in the vertical direction (Z direction). For example, each of the lower contacts 232 vertically overlaps with each of the second source / drain regions 130b, respectively, and contacts each of the second source / drain regions 130b. According to an exemplary embodiment, the upper surfaces 232U of the lower contacts 232 contact the bottom surfaces of the pair of source / drain barriers 132 and the bottom surface of one source / drain body 134, respectively.

[0060] According to the exemplary embodiment, both side walls of the plurality of bottom contacts 232 in the first horizontal direction (X direction) include portions facing and in contact with the gap-fill insulating film 222, and both side walls of the plurality of bottom contacts 232 in the second horizontal direction (Y direction) include portions facing and in contact with the element isolation film 114. According to the exemplary embodiment, the plurality of gap-fill insulating films 222 are disposed between the plurality of insulating blocks 212 and the plurality of bottom contacts 232 in the first horizontal direction (X direction).

[0061] Unlike the example of FIG. 1, when two first source / drain regions 130a are arranged adjacent to each other in the first horizontal direction (X direction) with a gate structure 162 interposed therebetween, two insulating blocks 212 respectively arranged under the two first source / drain regions 130a are spaced apart in the first horizontal direction (X direction) with a gap-fill insulating film 222 interposed therebetween. Similarly, unlike the example of FIG. 1, when two second source / drain regions 130b are arranged adjacent to each other in the first horizontal direction (X direction) with a gate structure 162 interposed therebetween, two lower contacts 232 respectively arranged under the two second source / drain regions 130b are spaced apart in the first horizontal direction (X direction) with a gap-fill insulating film 222 interposed therebetween. For example, in each back trench BT, the insulating blocks 212 and the lower contacts 232 are spaced apart from each other with a gap-fill insulating film 222 interposed therebetween and are arranged along the first horizontal direction (X direction).

[0062] According to an exemplary embodiment, the upper surfaces 232U of the lower contacts 232 are disposed at a second vertical level LV2, which is the same vertical level as the upper surfaces 124U of the insulating barriers 124. According to an exemplary embodiment, the upper surfaces 232U of the lower contacts 232 are disposed at a vertical level higher than the bottom surfaces 162L of the gate structures 162. In this case, both side walls of the lower contacts 232 along the first horizontal direction (X direction) include portions facing the gate structures 162. For example, the side walls of the upper portions of the lower contacts 232 along the first horizontal direction (X direction) include portions facing the lowermost sub-gate portion 160S of the gate electrode 160 across the gate dielectric film 152. In some embodiments, the side walls of the lower contacts 232 along the second horizontal direction (Y direction) include portions that contact and face the trench-side insulating spacer 119.

[0063] In some embodiments, the second source / drain regions 130b have a flat bottom profile, and the bottom contacts 232 generally cover the bottom surfaces of the second source / drain regions 130b. For example, the bottom contacts 232 contact the second source / drain regions 130b but do not extend into and through the second source / drain regions 130b.

[0064] In some embodiments, the bottom contacts 232 include a conductive material, such as, but not limited to, doped polysilicon or metal. In some embodiments, the bottom contacts 232 include a metal body extending in a vertical direction (Z direction) and a conductive barrier layer surrounding the metal body. The metal body is made of Ru, Co, W, or a combination thereof. The conductive barrier layer is made of Ti, TiN, Ta, TaN, or a combination thereof.

[0065] 2A to 2D, the upper surfaces 124U of the insulating barriers 124, the upper surfaces 232U of the lower contacts 232, and the upper surfaces of the insulating blocks 212 are all shown to have a flat shape, but are not limited to the above. For example, the upper surfaces 124U of the insulating barriers 124, the upper surfaces 232U of the lower contacts 232, and the upper surfaces of the insulating blocks 212 each independently have an upward convex shape or a downward convex shape.

[0066] According to an exemplary embodiment, the bottom surfaces of the gap-fill insulating films 222, the bottom surfaces of the insulating blocks 212, the bottom surfaces of the bottom contacts 232, and the bottom surfaces of the device isolation films 114 form a first coplanar BSSB.

[0067] According to an exemplary embodiment, in the first horizontal direction (X direction), the insulating barriers 124 have a first horizontal width wx1, the insulating blocks 212 have a second horizontal width wx2, and the bottom contacts 232 have a third horizontal width wx3. In some embodiments, the first horizontal width wx1 is equal to the second horizontal width wx2. For example, the sidewalls of each of the insulating barriers 124 are coplanar with the sidewalls of each of the insulating blocks 212. In some embodiments, the third horizontal width wx3 is equal to the first horizontal width wx1 and the second horizontal width wx2. In some other embodiments, the first horizontal width wx1, the second horizontal width wx2, and the third horizontal width wx3 are each narrower in the vertical direction (Z direction) closer to the first coplanar BSSB. In that case, the first horizontal width wx1 is wider than the second horizontal width wx2. In some embodiments, at the same vertical level, the first horizontal width wx1 of the insulating barriers 124 is the same as the third horizontal width wx3 of the bottom contacts 232. In some embodiments, at the same vertical level, the second horizontal width wx2 of the insulating blocks 212 is the same as the third horizontal width wx3 of the bottom contacts 232.

[0068] According to an exemplary embodiment, in the second horizontal direction (Y direction), the insulating barriers 124 have a fourth horizontal width wy1, the insulating blocks 212 have a fifth horizontal width wy2, and the bottom contacts 232 have a sixth horizontal width wy3. In some embodiments, the back trenches BT have a wider width along the second horizontal direction (Y direction) the further away from the bottom surfaces of the source / drain regions 130 in the vertical direction (Z direction) toward the first coplanar surface BSSB. In some embodiments, the fourth horizontal width wy1, the fifth horizontal width wy2, and the sixth horizontal width wy3 each gradually increase closer to the first coplanar surface BSSB. For example, the insulating blocks 212 are disposed at a lower vertical level than the insulating barriers 124 in the back trenches BT, and the fifth horizontal width wy2 is wider than the fourth horizontal width wy1. In some embodiments, at the same vertical level, the fourth horizontal width wy1 of the insulating barriers 124 is the same as the sixth horizontal width wy3 of the bottom contacts 232. In some embodiments, at the same vertical level, the fifth horizontal width wy2 of the insulating blocks 212 is the same as the sixth horizontal width wy3 of the bottom contacts 232.

[0069] According to an exemplary embodiment, the integrated circuit element 100 includes a metal power rail 254 extending in a first horizontal direction (X-direction) on a portion of the first coplanar BSSB. According to an exemplary embodiment, the metal power rail 254 contacts bottom surfaces of the plurality of bottom contacts 232 and is configured to apply a voltage to the plurality of second source / drain regions 130b. The metal power rail 254 is surrounded by a bottom insulating film 252 covering other regions on the first coplanar BSSB.

[0070] In some embodiments, the plurality of metal power rails 254 includes a metal wiring layer and a conductive barrier layer surrounding the metal wiring layer. Further details regarding the metal wiring layer and the conductive barrier layer that constitute the metal power rails 254 are similar to the description of the metal body and the conductive barrier layer that constitute the bottom contact 232. In some embodiments, the bottom insulating film 252 is a silicon oxide film, a silicon nitride film, a silicon carbide film, a low dielectric film, or a combination thereof.

[0071] Figures 3A and 3B are cross-sectional views for explaining an integrated circuit element 100a according to some other embodiments, where Figure 3A is a cross-sectional view of a portion corresponding to the cross section taken along line X1-X1' in Figure 1, and Figure 3B is an enlarged view of an area indicated as "EX3" in Figure 3A. In Figures 3A and 3B, the same reference symbols as in Figures 1 and 2A to 2D indicate the same members, and redundant description thereof will be omitted here.

[0072] According to an exemplary embodiment, the insulating barriers 124 and the insulating blocks 212 are sequentially disposed one by one on the bottom surfaces of the source / drain regions 130. According to an exemplary embodiment, one insulating barrier 124 and one insulating block 212 constitute one insulating structure, and the insulating structure extends in the vertical direction (Z direction) on the bottom surfaces of the source / drain regions 130. According to an exemplary embodiment, the gap-fill insulating films 222 are arranged in each back trench BT, spaced apart from each other in the first horizontal direction (X direction), with one insulating structure sandwiched therebetween.

[0073] For example, a first group of the insulating barriers 124 covers the bottom surfaces of the first source / drain regions 130a, and a first group of the insulating blocks 212 extends in the vertical direction (Z direction) below the bottom surfaces of the first source / drain regions 130a. For example, a second group of the insulating barriers 124 covers the bottom surfaces of the second source / drain regions 130b, and a second group of the insulating blocks 212 extends in the vertical direction (Z direction) below the bottom surfaces of the second source / drain regions 130b.

[0074] In some embodiments, the bottom contacts 232 penetrate the second group of insulating blocks 212 and the second group of insulating barriers 124 in the vertical direction (Z direction) to contact bottom surfaces of the second source / drain regions 130b. For example, a portion of the bottom contacts 232 extends into the second source / drain regions 130b. In some embodiments, the top surfaces of the bottom contacts 232 are located at a vertical level higher than the bottom surfaces of the source / drain regions 130. For example, the top surfaces of the bottom contacts 232 are located at a vertical level higher than the second vertical level LV2.

[0075] In some embodiments, a metal silicide film (not shown) is disposed between the second source / drain regions 130b and the bottom contact 232. Each of the second source / drain regions 130b is separated from the bottom contact 232 by a metal silicide film (not shown).

[0076] In some embodiments, the bottom contacts 232 have a narrower width along the first horizontal direction (X direction) the further they are from the first coplanar surface BSSB in the vertical direction (Z direction). For example, the width along the first horizontal direction (X direction) of the upper portions of the bottom contacts 232 is narrower than the width along the first horizontal direction (X direction) of the lower portions of the bottom contacts 232. For example, the third horizontal width wx3 of the bottom contacts 232 is wider the closer they are to the first coplanar surface BSSB.

[0077] In some embodiments, the third horizontal width wx3 of the bottom contacts 232 is narrower than the first horizontal width wx1 of the insulating barriers 124 and narrower than the second horizontal width wx2 of the insulating blocks 212. In some embodiments, the bottom contacts 232 are separated from the gap-fill insulating films 222 by the insulating barriers 124 and the insulating blocks 212. In some embodiments, the bottom contacts 232 are separated from the gate structures 162 by the second group of insulating barriers 124.

[0078] Figures 4A and 4B are cross-sectional views for explaining an integrated circuit element 100b according to still another embodiment. Figure 4A is a cross-sectional view of a portion corresponding to the cross section taken along line X1-X1' in Figure 1, and Figure 4B is an enlarged view of an area indicated as "EX4" in Figure 4A. In Figures 4A and 4B, the same reference symbols as in Figures 1 and 2A to 2D indicate the same members, and redundant description thereof will be omitted here.

[0079] According to an exemplary embodiment, the insulating barriers 124 cover bottom surfaces of the source / drain regions 130. According to an exemplary embodiment, a first group of the insulating barriers 124 covers bottom surfaces of the first source / drain regions 130a, and a second group of the insulating barriers 124 covers bottom surfaces of the second source / drain regions 130b.

[0080] According to an exemplary embodiment, the multiple lower contacts 232 include a first portion 232a extending vertically (Z direction) between two gap-fill insulating films 222 adjacent to each other in a first horizontal direction (X direction), and a second portion 232b extending from the first portion 232a and penetrating a second group of insulating barriers 124 in the vertical direction (Z direction) to contact the multiple second source / drain regions 130b.

[0081] In some embodiments, the top surfaces of the first portions 232a of the bottom contacts 232 contact the bottom surfaces of the second group of insulating barriers 124. In some embodiments, the second portions 232b of the bottom contacts 232 include portions that extend into the second source / drain regions 130b. In some embodiments, the top surfaces of the second portions 232b are disposed at a vertical level higher than the second vertical level LV2.

[0082] In some embodiments, the second portions 232b of the bottom contacts 232 are spaced apart from the gate structures 162 in the first horizontal direction (X-direction) across the second group of insulating barriers 124. For example, the bottom contacts 232 are spaced apart from the gate electrodes 160 across the second group of insulating barriers 124 to ensure electrical reliability of the integrated circuit device 100b.

[0083] In some embodiments, a seventh horizontal width wx31, which is a width of the first portion 232a along the first horizontal direction (X direction), is wider than an eighth horizontal width wx32, which is a width of the second portion 232b along the first horizontal direction (X direction). In some embodiments, the seventh horizontal width wx31 of the first portion 232a is equal to the first horizontal width wx1 of the insulating barriers 124 and equal to the second horizontal width wx2 of the insulating blocks 212. In some embodiments, the seventh horizontal width wx31 of the first portion 232a is constant regardless of the vertical level. In some embodiments, the eighth horizontal width wx32 of the second portion 232b becomes narrower as it moves away from the first coplanar BSSB in the vertical direction (Z direction).

[0084] 5A and 5B are cross-sectional views for explaining an integrated circuit device 100c according to still another embodiment. FIG. 5A is a cross-sectional view of a portion corresponding to the cross section taken along line X1-X1' in FIG. 1, and FIG. 5B is an enlarged view of an area indicated by "EX5" in FIG. 5A. Specifically, the difference between the integrated circuit device 100c and the integrated circuit device 100b described with reference to FIGS. 5A and 5B is whether a lower insulating liner 230 is disposed between the first portions 232a of the plurality of lower contacts 232 and the adjacent gap-fill insulating film 222. In FIGS. 5A and 5B, the same reference numerals as those in FIGS. 1, 2A to 2D, and 4A and 4B indicate the same members, and redundant description thereof will be omitted here.

[0085] According to an exemplary embodiment, a lower insulating liner 230 covering sidewalls of the first portions 232a of the lower contacts 232 is disposed on bottom surfaces of the second group of insulating barriers 124. According to an exemplary embodiment, the lower insulating liner 230 is disposed between the first portions 232a of the lower contacts 232 and the adjacent gap-fill insulating film 222. For example, the first portions 232a of the lower contacts 232 are spaced apart in the first horizontal direction (X-direction) from the gap-fill insulating film 222 with the lower insulating liner 230 interposed therebetween.

[0086] According to an exemplary embodiment, the first and second portions 232a, 232b of the plurality of bottom contacts 232 overlap in the vertical direction (Z direction). In some embodiments, the sidewalls of the first and second portions 232a, 232b extend coplanar. In some embodiments, the bottom insulating liner 230 vertically overlaps the second group of insulating barriers 124. For example, the first portions 232a do not vertically overlap the second group of insulating barriers 124.

[0087] In some embodiments, a seventh horizontal width wx31 of the first portion 232a of the bottom contacts 232 is narrower than the first horizontal width wx1 of the insulating barriers 124 and narrower than the second horizontal width wx2 of the insulating blocks 212. In some embodiments, the seventh horizontal width wx31 of the first portion 232a is constant regardless of the vertical level. In some embodiments, an eighth horizontal width wx32 of the second portion 232b is narrower in the vertical direction (Z direction) from the first coplanar BSSB.

[0088] 6A to 19B are cross-sectional views illustrating a process sequence for explaining a manufacturing method of an integrated circuit device according to an embodiment of the present invention, in which Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12, Fig. 13, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, and Fig. 19A are cross-sectional views illustrating a process sequence of a portion corresponding to a cross section taken along line X1-X1' in Fig. 1, and Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, and Fig. 19B are cross-sectional views illustrating a portion corresponding to a cross section taken along line Y1-Y1' and a cross section taken along line Y2-Y2' in Fig. 1. In Fig. 6A to Fig. 19B, the same reference numerals as Fig. 1 and Fig. 2A to Fig. 2D indicate the same members, and redundant description thereof will be omitted here.

[0089] 6A and 6B, a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS are alternately laminated one by one on the substrate 102, and then the plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and a portion of the substrate 102 are etched to define a plurality of fin-type structures FA on the substrate 102. The plurality of fin-type structures FA protrude in a vertical direction (Z direction) from the main surface 102M of the substrate 102. Then, an element isolation film 114 is formed to cover each sidewall of the plurality of fin-type structures FA. A laminated structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS remains on the fin upper surface FT of each of the plurality of fin-type structures FA.

[0090] In some embodiments, the substrate 102 comprises a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. As used herein, the terms "SiGe," "SiC," "GaAs," "InAs," "InGaAs," and "InP" refer to materials composed of the elements contained therein and not to chemical formulas indicating stoichiometric relationships. For example, the substrate 102 is a bulk Si substrate.

[0091] The sacrificial semiconductor layers 104 and the nanosheet semiconductor layers NS are made of semiconductor materials having different etching selectivity. In some embodiments, the nanosheet semiconductor layers NS are made of Si layers, and the sacrificial semiconductor layers 104 are made of SiGe layers. In some embodiments, the Ge content is constant in the sacrificial semiconductor layers 104. The SiGe layers constituting the sacrificial semiconductor layers 104 have a constant Ge content selected within a range of about 5 atomic % to 60 atomic %, for example, about 10 atomic % to 40 atomic %. The Ge content in the SiGe layers constituting the sacrificial semiconductor layers 104 may be variously selected as required.

[0092] 7A and 7B, a plurality of dummy gate structures DGS are formed on a stacked structure of a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS. The plurality of dummy gate structures DGS are each elongated in a second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS has a structure in which an oxide film D122, a dummy gate layer D124, and a capping layer D126 are stacked in order. In some embodiments, the dummy gate layer D124 is made of polysilicon, and the capping layer D126 is made of a silicon nitride film.

[0093] Then, an inner gate insulating spacer 118 is formed to cover both side walls of the dummy gate structure DGS, and then a spacer 119 is formed to cover the fin-type structure FA, the dummy gate structure DGS, and the inner gate insulating spacer 118. For example, the inner gate insulating spacer 118 is made of SiN. For example, the spacer 119 includes SiOCN, SiCN, or a combination thereof. In some embodiments, the spacer 119 is made of a single film made of SiOCN. In other embodiments, the spacer 119 includes a SiOCN film covering the inner gate insulating spacer 118 and an oxide film covering the SiOCN film.

[0094] 8A and 8B, the spacer 119 is partially etched to form an inner gate insulating spacer 118 and an outer insulating spacer 116 covering both side walls of the dummy gate structure DGS from the spacer 119. While forming the outer insulating spacer 116, the spacer 119 is etched to expose the fin-type structure FA. The exposed fin-type structure FA is also etched together with the spacer 119 to form a first recess R1 on the fin-type structure FA. To form the first recess R1, an etching process using dry etching, wet etching, or a combination thereof is performed. In some embodiments, the bottom surface of the first recess R1 is disposed at a vertical level lower than the upper surfaces of the plurality of device isolation films 114 and higher than the main surface 102M of the substrate 102.

[0095] During the etching process for forming the first recess R1, a first recess side insulating spacer 119 is formed to cover both side walls of the fin structure FA in a region adjacent to the first recess R1.

[0096] After the first recess R1 is formed in the fin structure FA, the nanosheet semiconductor layers NS (see FIGS. 7A and 7B) are divided into a plurality of nanosheet stacks NSS, each of which includes a first nanosheet N1, a second nanosheet N2, a third nanosheet N3, and a fourth nanosheet N4.

[0097] 9A and 9B, a plurality of sacrificial semiconductor blocks 122 are formed to fill a portion of the first recess R1 in the resultant structure of FIGS. 8A and 8B by selectively epitaxially growing a semiconductor material from the fin-type structure FA exposed through the first recess R1. In some embodiments, the plurality of sacrificial semiconductor blocks 122 are epitaxially grown Si layers, epitaxially grown SiC layers, or epitaxially grown SiGe layers.

[0098] In some embodiments, the top surfaces of the plurality of sacrificial semiconductor blocks 122 are disposed at a vertical level lower than the bottom surface of the lowest sacrificial semiconductor layer 104 among the plurality of sacrificial semiconductor layers 104 stacked in the vertical direction (Z direction). In some embodiments, the top surface profile of the plurality of sacrificial semiconductor blocks 122 is formed to be flat by adjusting the epitaxial growth temperature.

[0099] 10A and 10B, in the resultant structure of FIGS. 9A and 9B, a plurality of insulating barriers 124 are formed to fill a portion of the first recess R1 on each of the plurality of sacrificial semiconductor blocks 122. In some embodiments, the vertical level of the upper surfaces of the plurality of insulating barriers 124 is disposed at a vertical level higher than the bottom surface of the lowest sacrificial semiconductor layer 104 among the plurality of sacrificial semiconductor layers 104 stacked in the vertical direction (Z direction).

[0100] 11A and 11B, in the resultant structure of FIGs. 10A and 10B, a semiconductor material is selectively epitaxially grown in the first recess R1 to form a plurality of source / drain regions 130. For example, a source / drain barrier 132 and a source / drain body 134 are sequentially formed in the first recess R1.

[0101] In some embodiments, a semiconductor material is epitaxially grown from the sidewalls of each of the nanosheets N1, N2, N3, N4 and the sidewalls of each of the sacrificial semiconductor layers 104 exposed through the first recesses R1 to form the source / drain barrier 132. In some embodiments, the source / drain barrier 132 covers the sidewalls of each of the nanosheets N1, N2, N3, N4 and the sidewalls of each of the sacrificial semiconductor layers 104. For example, as a portion of the top surface of each of the insulating barriers 124, the sidewalls of each of the nanosheets N1, N2, N3, N4 and the portions adjacent to the sidewalls of each of the sacrificial semiconductor layers 104 are covered by the source / drain barrier 132, while the remaining top surface is exposed.

[0102] In some embodiments, a low-pressure chemical vapor deposition (LPCVD), selective epitaxial growth (SEG), or cyclic deposition and etching (CDE) process is performed using source materials including elemental semiconductor precursors to form the source / drain barriers 132. The elemental semiconductor precursors include elements such as Si and Ge.

[0103] For example, a Si source and a Ge source are used to form the source / drain barrier 132. Silane (SiH 4 ), disilane (Si 2 H 6 ), trisilane (Si 3 H 8 ), dichlorosilane (SiH 2 Cl 2 ) can be used as a Ge source, but is not limited thereto. 4 ), Gegelman 2 H 6 ), trigermane (Ge 3 H 8 ), tetragermane (Ge 4 H 10 ), dichlorogermane (Ge 2 H 2 Cl 2 ), but is not limited thereto. When the source / drain barrier 132 is made of a SiGe layer doped with B (boron), a B source can be used in addition to the Si source and Ge source to form the B-doped SiGe layer. Diborane (B 2 H 6 ), triborane, tetraborane, pentaborane, etc., can be used, but are not limited to them. In an exemplary embodiment, during the epitaxial growth process for forming the source / drain barrier 132, an ion implantation process of B dopant using a B source is performed in-situ.

[0104] In some embodiments, a source / drain body 134 is formed on the insulating barriers 124 to cover the source / drain barriers 132 and portions of the upper surfaces of the insulating barriers 124 that are not covered by the source / drain barriers 132. To form the source / drain body 134, a process similar to that described for forming the source / drain barriers 132 is performed. In some embodiments, the process of forming the source / drain body 134 is performed in-situ with the process of forming the source / drain barriers 132.

[0105] Then, an insulating liner 142 is formed to cover the multiple source / drain regions 130, an inter-gate insulating film 144 is formed on the insulating liner 142, and the insulating liner 142 and the inter-gate insulating film 144 are planarized to expose the upper surface of the capping layer D126.

[0106] Referring to FIG. 12, the capping layer D126 is removed from the resultant structure of FIGS. 11A and 11B to expose the top surface of the dummy gate layer D124, and the insulating liner 142 and the inter-gate insulating film 144 are partially removed so that the top surface of the inter-gate insulating film 144 and the top surface of the dummy gate layer D124 are approximately at the same level.

[0107] 13, the dummy gate layer D124 and the oxide film D122 thereunder are removed from the resultant structure of FIG. 12 to provide a gate space GS, and the nanosheet stacks NSS are exposed through the gate space GS. Then, the sacrificial semiconductor layers 104 remaining on the fin structure FA are removed through the gate space GS, and the gate space GS is expanded to the spaces between the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4, and between the first nanosheet N1 and the fin top surface FT of the fin structure FA.

[0108] In some embodiments, the etching selectivity difference between the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 and the plurality of sacrificial semiconductor layers 104 is utilized to selectively remove the plurality of sacrificial semiconductor layers 104. A liquid or gas phase etchant is used to selectively remove the plurality of sacrificial semiconductor layers 104. In an exemplary embodiment, CH 3 Etching solution for COOH-based materials, e.g. CH 3 COOH, HNO 3 , and HF mixture, or CH 3 COOH, H 2 O 2 An etching solution consisting of a mixture of SiO 2 and HF can be used, but is not limited to the example.

[0109] Thereafter, a gate dielectric film 152 is formed to cover the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fourth nanosheet N4 and the exposed surfaces of the fin-type structure FA. In order to form the gate dielectric film 152, an atomic layer deposition (ALD) process may be used.

[0110] 14A and 14B, a gate forming conductive layer (not shown) is formed on the gate dielectric layer 152 to fill the gate space GS (see FIG. 13) and cover the upper surface of the inter-gate insulating layer 144. The gate forming conductive layer (not shown) is made of a metal, a metal nitride, a metal carbide, or a combination thereof. An ALD process or a CVD process is used to form the gate forming conductive layer (not shown). Then, the gate forming conductive layer (not shown), the gate dielectric layer 152, and the outer insulating spacer 116 are partially removed from their respective upper surfaces so that the upper surface of the inter-gate insulating layer 144 is exposed and an upper portion of the gate space GS is again left empty, thereby forming a gate structure 162. Then, a capping insulating pattern 168 is formed on the gate structure 162 to fill the gate space GS.

[0111] 15A and 15B, in the result of FIG. 14A and FIG. 14B, a part of the insulating liner 142 and a part of the inter-gate insulating film 144 are removed to form a plurality of upper contact holes 172H exposing the plurality of first source / drain regions 130a, and then a part of the plurality of first source / drain regions 130a is removed through the plurality of upper contact holes 172H by an anisotropic etching process, so that the plurality of contact holes 172H extend long toward the substrate 102 side. Then, a metal silicide film (not shown) is formed on the plurality of first source / drain regions 130a exposed at the bottom side of the plurality of upper contact holes 172H. In an exemplary embodiment, the method for forming the metal silicide film (not shown) includes forming a metal liner (not shown) conformally covering the exposed surface of the plurality of first source / drain regions 130a, and performing a heat treatment to induce a reaction between the plurality of first source / drain regions 130a and a metal constituting the metal liner. Then, a plurality of upper contacts 172 are formed on the metal silicide film. Thereafter, a plurality of front wiring layers (not shown) are formed to cover the upper surfaces of the inter-gate insulating film 144, the upper contacts 172, and the capping insulating patterns 168, thereby forming the front structure FSS of FIG.

[0112] 16A and 16B, after a carrier substrate (not shown) is attached on the front structure FSS, the back surface of the substrate 102 is polished until the sacrificial semiconductor blocks 122 are exposed. In this process, parts of the isolation films 114, parts of the substrate 102, and parts of the sacrificial semiconductor blocks 122 are removed. For example, the sacrificial semiconductor blocks 122 are used as an etch stop film, and the source / drain regions 130 are self-aligned through the exposed sacrificial semiconductor blocks 122.

[0113] In some embodiments, during the polishing process, the substrate 102 disposed at a vertical level lower than the first recess R1 illustrated in Figures 16A and 16B is removed, thereby forming a plurality of back trenches BT that define the boundaries of the fin-type structure FA. For example, the plurality of back trenches BT extend parallel to each other along the first horizontal direction (X direction), and a plurality of residual blocks 103 and a plurality of sacrificial semiconductor blocks 122 that are parts of the substrate 102 that are not removed are disposed in the plurality of back trenches BT.

[0114] 17A and 17B, the sacrificial semiconductor blocks 122 exposed through the back surface of the resultant structure of FIG. 16A and FIG. 16B are removed to form a first hole pattern HP1. For example, the sacrificial semiconductor blocks 122 are removed by dry etching or wet etching, but are not limited to the above examples. For example, the first hole pattern HP1 is defined by the residual blocks 103, the isolation films 114, and the insulating barriers 124.

[0115] Thereafter, the insulating blocks 212 are formed to fill the first hole pattern HP1. For example, the insulating blocks 212 are formed by forming a spin-coated film to fill the first hole pattern HP1, and then polishing the back surface until the residual blocks 103 are exposed.

[0116] 18A and 18B, the remaining blocks 103 exposed through the back surface in the resultant structure of FIGS. 17A and 17B are removed to form a second hole pattern HP2. In some embodiments, the remaining blocks 103 are removed by wet etching, which may easily remove even the remaining blocks 103 at the corners of the second hole pattern HP2 while preventing damage to the gate structures 162.

[0117] In some embodiments, the second hole pattern HP2 is defined by the insulating blocks 212, the device isolation films 114, the insulating barriers 124, and the gate structures 162. In some embodiments, the second hole pattern HP2 exposes the bottom surfaces of the gate structures 162 as a whole. For example, the width of the second hole pattern HP2 in the first horizontal direction (X direction) is equal to the sum of the widths of the gate dielectric film 152 covering the lowermost sub-gate portion 160S and both side walls thereof in the first horizontal direction (X direction). Even in such a case, the lower portions of the source / drain regions 130 are protected by the insulating barrier 124 and are prevented from being damaged by etching. As a result, it is not necessary to leave some of the residual blocks 103 adjacent to the lower portions of the source / drain regions 130 unremoved in order to prevent the lower portions of the source / drain regions 130 from being exposed and removed together with the residual blocks 103. In addition, it is possible to prevent power loss in the integrated circuit device due to the remaining parts of the residual blocks 103.

[0118] Thereafter, a plurality of gap-fill insulating layers 222 are formed to fill the second hole pattern HP2. For example, the plurality of gap-fill insulating layers 222 are formed by forming a spin-coated layer to fill the second hole pattern HP2, and then polishing the back surface until the plurality of residual blocks 103 are exposed.

[0119] 19A and 19B, in the resultant structure of FIGS. 18A and 18B, an etching mask (not shown) is formed on the back surface to expose the insulating blocks 212 vertically overlapping with the second source / drain regions 130b, and then the insulating barriers 124 and the insulating blocks 212 under the second source / drain regions 130b are removed to form lower contact holes 232H to expose the bottom surfaces of the second source / drain regions 130b. In some embodiments, the gap-fill insulating layers 222 have an etch selectivity with the insulating barriers 124 and the insulating blocks 212. In some embodiments, the source / drain barriers 132 and the source / drain bodies 134 of the second source / drain regions 130b are exposed through the lower contact holes 232H. Thereafter, the lower contact holes 232H are filled with a conductive material, and the back surface is polished to form the lower contacts 232. As a result, the bottom surfaces of the multiple lower contacts 232, the bottom surfaces of the multiple gap-fill insulating films 222, the bottom surfaces of the multiple insulating barriers 124, the bottom surfaces of the multiple insulating blocks 212, and the bottom surfaces of the multiple element isolation films 114 form a first coplanar surface BSSB.

[0120] 2A to 2D, in the resultant structure of FIGS. 19A and 19B, an insulating material layer (not shown) is formed on the first coplanar BSSB, and then a portion of the insulating material layer is removed to form a hole pattern (not shown) and a conductive material is filled into the hole pattern (not shown) to form a metal power rail 254 and a lower insulating film 252.

[0121] An exemplary method for manufacturing the integrated circuit element 100 illustrated in FIGS. 1 and 2A to 2D has been described above with reference to FIGS. 6A to 19B. However, it will be understood by those skilled in the art that various modifications and changes can be made within the scope of the technical concept of the present invention to manufacture the integrated circuit elements illustrated in FIGS. 3A to 5B and integrated circuit elements having various structures modified and altered therefrom, based on what has been described with reference to FIGS. 6A to 19B. [Explanation of symbols]

[0122] 100 Integrated circuit element 102 Substrate 114 Element isolation film 116 Outer insulating spacer 124 Insulation Barrier 130 Source / Drain Region 132 Source / Drain Barrier 134 Source / Drain Body 142 Insulating Liner 144 Inter-gate insulating film 152 Gate dielectric film 160 Gate electrode 160M Main Gate Area 160S Subgate section 162 Gate Structure 172 Upper Contact 212 Insulation Block 222 Gap-fill insulating film 232 Lower Contact 254 Metal Power Rail NSS Nanosheet Stack N1, N2, N3, N4 nanosheets

Claims

1. a plurality of isolation layers extending in a first horizontal direction and spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction; a plurality of gap-fill insulating layers arranged spaced apart from each other along the first horizontal direction between two adjacent isolation layers among the plurality of isolation layers; a plurality of gate structures extending in the second horizontal direction and spaced apart from one another in the first horizontal direction on the plurality of gap-fill insulating layers; a first source / drain region and a second source / drain region disposed on both sides of a first gate structure selected from the plurality of gate structures along the first horizontal direction; an insulating block disposed below the first source / drain region; an insulating barrier covering a bottom surface of the first source / drain region and disposed between the first source / drain region and the insulating block; a lower contact below the second source / drain region and in contact with a bottom surface of the second source / drain region, the lower contact being spaced apart from the insulating block in the first horizontal direction across a first gap-fill insulating film selected from the plurality of gap-fill insulating films.

2. 2. The integrated circuit device of claim 1, wherein the first source / drain region is separated from the first gap-fill insulating film by the insulating barrier.

3. The insulating barrier has a side wall along the first horizontal direction, 2. The integrated circuit device of claim 1 including a portion in contact with said first gate structure.

4. 2. The integrated circuit device of claim 1, wherein at the same vertical level, the width of the insulating block along the first horizontal direction is the same as the width of the bottom contact along the first horizontal direction.

5. 2. The integrated circuit device of claim 1, wherein the first gap-fill insulating layer covers an entire bottom surface of the first gate structure.

6. The first gap-fill insulating film further includes a nanosheet stack including at least one nanosheet that is disposed at a position vertically spaced apart from the upper surface of the first gap-fill insulating film and faces the upper surface of the first gap-fill insulating film; The integrated circuit device of claim 1 , wherein the first gate structure surrounds the nanosheet stack on the first gap-fill insulating film.

7. The first source / drain region is a source / drain barrier covering a side surface of the nanosheet stack and a portion of a side surface of the first gate structure; a source / drain body facing the first gate structure in a first horizontal direction across the source / drain barrier; 7. The integrated circuit device of claim 6, wherein a bottom surface of the source / drain body contacts the insulating barrier.

8. 2. The integrated circuit device of claim 1, wherein a bottom surface of the isolation layer, a bottom surface of the plurality of gap-fill insulating layers, a bottom surface of the insulating block, and a bottom surface of the bottom contact form a first coplanar surface.

9. 9. The integrated circuit device of claim 8, further comprising a backside power rail disposed on said first coplanar surface and contacting said bottom contact.

10. 2. The integrated circuit device of claim 1, wherein the vertical level of the upper surface of the insulating barrier is the same as the vertical level of the upper surface of the bottom contact.

Images