Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide: a semiconductor device having a stable structure and improved reliability; and a manufacturing method thereof.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a buffer film 310 on a substrate 300; forming a polishing stop film 320 on the buffer film 310; forming a stack 330 on the polishing stop film 320; forming a channel structure 340 having different heights extending through the stack 330 and the polishing stop film 320; polishing the substrate 300 and the buffer layer 310 to expose the polishing stop film 320; and removing the polishing stop film 320 to expose a sidewall of the channel structure 340.SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] The present invention relates to an electronic device and a method for manufacturing an electronic device, and more particularly to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] The integration density of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, the integration density of a semiconductor device in which memory cells are formed in a single layer on a substrate has reached its limit, so that a three-dimensional semiconductor device in which memory cells are stacked on a substrate has been proposed. In addition, various structures and manufacturing methods have been developed to improve the operational reliability of such semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0003] One embodiment of the present invention provides a semiconductor device and a method for manufacturing the semiconductor device having a stable structure and improved characteristics. [Means for solving the problem]

[0004] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include forming a polishing stop film on a substrate, forming a stack on the polishing stop film, forming channel structures extending through the stack and the polishing stop film and having different heights, polishing the substrate and the channel structure to expose the polishing stop film, and removing the polishing stop film.

[0005] A method for manufacturing a semiconductor device according to one embodiment of the present invention may include the steps of forming a substrate including a first region and a second region, forming a polishing stop film having a first type of stress in the first region of the substrate, forming a gap-fill film having a second type of stress different from the first type in the second region of the substrate, forming a stack on the polishing stop film and the gap-fill film, forming channel structures extending through the stack and the polishing stop film and having different heights, and polishing the substrate and the channel structure to expose the polishing stop film.

[0006] A method for manufacturing a semiconductor device according to an embodiment of the present invention may include the steps of forming a buffer film, forming a polishing stop film on the buffer film, forming a stack on the polishing stop film, forming a channel structure extending into the buffer film through the stack and the polishing stop film, polishing the buffer film and the channel structure to expose the polishing stop film, and removing the polishing stop film. Effect of the Invention

[0007] According to the present technology, it is possible to provide a semiconductor device having a stable structure and improved reliability.

[0008] According to the present technology, since the channel structures can be formed to substantially the same height, the memory cells can have uniform characteristics in subsequent processes. [Brief description of the drawings]

[0009] [Figure 1A] 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention; [Figure 1B] 1 is a diagram for explaining a semiconductor device according to an embodiment of the present invention; [Figure 2A] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2B]1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2C] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3A] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3B] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3C] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 3D] 1A to 1C are diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the accompanying drawings.

[0011] 1A and 1B are diagrams for explaining a semiconductor device according to an embodiment of the present invention, in which Fig. 1B is an enlarged view of A in Fig. 1A.

[0012] 1A and 1B, the semiconductor device may include at least one of a substrate 100, a gate structure 140, a channel structure 150, and a source structure 160. The semiconductor device may further include at least one of an isolation insulating film ISO, a peripheral circuit PC, an interconnection structure 120, a bonding structure 130, a first interlayer insulating film IL1, and a second interlayer insulating film IL2.

[0013] The substrate 100 may be a semiconductor substrate such as a silicon wafer, a SiGe wafer, or an SOI wafer. A peripheral circuit PC may be located on the substrate 100, and an isolation insulating film ISO may be located in the substrate 100. An active region may be defined by the isolation insulating film ISO. The peripheral circuit PC may include a transistor 110, a capacitor, a resistor, or the like. For example, the transistor 110 may include a first junction 110A, a second junction 110B, a gate insulating film 110C, or a gate electrode 110D. The gate insulating film 110C may be located between the gate electrode 110D and the substrate 100. The gate insulating film 110C and the isolation insulating film ISO may include an insulating material such as an oxide or a nitride.

[0014] An interconnection structure 120 may be located on the substrate 100. Here, the interconnection structure 120 may include a first contact via 120A, a first wiring 120B, a second wiring 120C, and a second contact via 120D. The first contact via 120A and the first wiring 120B may be located in a first interlayer insulating film IL1. Here, the first interlayer insulating film IL1 may be located on the substrate 100. At least one of the first contact vias 120A may be connected to the transistor 110. The first wiring 120B may be connected to each of the first contact vias 120A.

[0015] The gate structure 140 may be located on the peripheral circuit PC. The gate structure 140 may include an insulating film 140A and a conductive film 140B that are alternately stacked. The insulating film 140A may include an insulating material such as an oxide, and the conductive film 140B may include a conductive material such as tungsten, molybdenum, or polysilicon. The conductive film 140B may be a word line, a bit line, a drain select line, or a source select line.

[0016] The source structure 160 may be located on the gate structure 140. The channel structure 150 may extend into the source structure 160 through the gate structure 140. The channel structure 150 may be connectable to the source structure 160. The channel structure 150 may have a tapered cross section, with a narrower width at the top than at the bottom. Each of the channel structures 150 may include at least one of a channel membrane 150A, a memory membrane 150B surrounding the channel membrane 150A, and an insulating core 150C within the channel membrane 150A. Here, the channel membrane 150A may be connectable to the source structure 160.

[0017] If the channel structures 150 have different heights, the heights of the channel structures 150 protruding from the gate structures 140 may be different, and thus the positions of the junctions formed in the channel structures 150 during fabrication may be different.

[0018] According to an embodiment of the present invention, the heights H of the channel structures 150 may be substantially the same. This is because the upper surfaces of the channel structures 150 having different heights can be polished and partially removed during the manufacturing process. That is, the channel structures 150 can be polished so that the upper surfaces of the channel films 150A and the insulating cores 150C of the channel structures 150 are located at substantially the same level. Thus, the channel structures 150 may include junctions J located at substantially the same level. Here, the junctions J may be located within the channel films 150A of the channel structures 150. The junctions J may refer to regions in the channel films 150A where impurities are doped. According to the present invention, the junctions J of the channel structures 150 can be located at substantially the same level, so that the memory cells can have uniform characteristics.

[0019] The top surface of the memory film 150B may be located at a lower level than the top surfaces of the channel film 150A and the insulating core 150C because, during the manufacturing process, a portion of the memory film 150B may be removed to form a junction J in the channel film 150A located at a level corresponding to the conductive film 140B. Here, the conductive film 140B may be a source selection line.

[0020] The second wiring 120C and the second contact via 120D of the interconnection structure 120 may be located below the gate structure 140. The second contact via 120D may be connected to the channel structure 150. The second wiring 120C may be located below the second contact via 120D. The second wiring 120C may be connected to the second contact via 120D. The second contact via 120D and the second wiring 120C may be located in the second interlayer insulating film IL2.

[0021] The bonding structure 130 may be located between the gate structure 140 and the peripheral circuit PC. The bonding structure 130 may include a first bonding pad 130A and a second bonding pad 130B. The first bonding pad 130A may be located in a first interlayer insulating film IL1, and the second bonding pad 130B may be located in a second interlayer insulating film IL2. The first bonding pad 130A may be connected to at least one of the first wirings 120B, and the second bonding pad 130B may be connected to at least one of the second wirings 120C. The first bonding pad 130A and the second bonding pad 130B may be bonded to each other.

[0022] According to the above-mentioned structure, the channel structures 150 may have substantially the same height, and the junctions J formed in the channel films 150A of the channel structures 150 may also be located at substantially the same level.

[0023] A structure including a memory cell array including the channel structure 150 and the like can be configured as a separate structure and bonded to a peripheral circuit PC related to the operation of the memory cell array. By configuring the peripheral circuit PC related to the operation of the memory cell array as a separate structure, more memory cells can be located in the structure including the memory cell array, and therefore more data can be stored.

[0024] 2A to 2C are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the following, the description will be omitted to avoid overlapping with the description given above.

[0025] 2A, a pre-polishing stop film 210A may be formed on a substrate 200. The pre-polishing stop film 210A may be formed to cover the substrate 200. The pre-polishing stop film 210A may include a material having a selectivity to oxide. Alternatively, the pre-polishing stop film 210A may include at least one of nitride, tungsten, cobalt silicide, aluminum oxide, and titanium silicide.

[0026] 2B, the substrate 200 may include chip regions CHR and scribe lane regions SR. The chip regions CHR may be regions in which semiconductor chips are formed. Semiconductor chips may be repeatedly formed on the substrate 200, and the chip regions CHR may be arranged in a first direction I and a second direction II intersecting the first direction I. The scribe lane regions SR may be located between the chip regions CHR. The scribe lane regions SR may be a portion that is cut out in a dicing process for separating the semiconductor chips. The substrate 200 may be cut along the scribe lane regions SR to separate the chip regions CHR from each other.

[0027] The chip region CHR may include a first region AR1 and a second region AR2. However, without being limited thereto, the second region AR2 of the chip region CHR may partially overlap the scribe lane region SR. Here, the first region AR1 may be a cell region CER, and the second region AR2 may be a peripheral circuit region PR. The peripheral circuit region PR may surround the cell region CER. The cell region CER may be a region in which a memory cell array such as a channel structure is formed, and the peripheral circuit region PR may be a region in which structures related to the operation of the memory cell array such as a decoder, a logic circuit, and a ROM (Read Only Memory) are formed.

[0028] The pre-polishing-stop layer 210A may be patterned to form a polishing-stop layer 210. The polishing-stop layer 210 may be formed on the chip region CHR of the substrate 200. For example, the polishing-stop layer 210 may be formed in the first region AR1 of the substrate 200. The polishing-stop layer 210 may be arranged in a first direction I and a second direction II.

[0029] 2C, a gap-fill layer 220 may be formed in the scribe lane region SR of the substrate 200. First, a preliminary gap-fill layer (not shown) may be formed in an opening formed by patterning the preliminary polishing-stop layer 210A. Next, the preliminary gap-fill layer may be polished to expose the polishing-stop layer 210, thereby forming the gap-fill layer 220. Here, the gap-fill layer 220 may be formed in a second region AR2 of the chip region CHR. For example, the gap-fill layer 220 may be formed in the second region AR2 located between the first regions AR1. Here, the gap-fill layer 220 may include an insulating material such as an oxide.

[0030] The polish-stop layer 210 may have a first type of stress. The gap-fill layer 220 may have a second type of stress different from the first type. For example, the first type of stress may be a tensile stress, and the second type of stress may be a compressive stress. Thus, the polish-stop layer 210 and the gap-fill layer 220 may generate different types of stress in the substrate 200, so that the stresses can be offset. Therefore, warping of the substrate 200 can be prevented or reduced.

[0031] According to the above-described manufacturing method, the polishing stop layer 210 and the gap-fill layer 220 having different types of stresses can be formed on the substrate 200. For example, the polishing stop layer 210 having a tensile stress can be formed in the first region AR1 of the substrate 200, and the gap-fill layer 220 having a compressive stress can be formed in the second region AR2 of the substrate 200. Therefore, warping of the substrate 200 can be prevented or reduced.

[0032] 3A to 3D are diagrams for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the following, the description will be omitted to avoid overlapping with the description above.

[0033] Referring to FIG. 3A, a first wafer W1 may be formed. First, a polishing stop layer 320 may be formed on a substrate 300. For example, referring to FIGS. 2A to 2C again, a polishing stop layer 320 may be formed on a first region AR1 of the substrate 300. Here, the polishing stop layer 320 may not be present on a second region AR2. The first region AR1 may be a cell region CER, and the second region AR2 may be a peripheral circuit region PR. The polishing stop layer 320 may include a material having a selectivity with respect to an oxide. Alternatively, the polishing stop layer 320 may include at least one of a nitride, tungsten, cobalt silicide, aluminum oxide, and titanium silicide. For example, the polishing stop layer 320 may include a nitride.

[0034] Before forming the polishing stop layer 320, the buffer layer 310 may be formed. For example, referring again to FIGS. 2A to 2C, a preliminary buffer layer may be formed before forming the preliminary polishing stop layer. Then, when patterning the preliminary polishing stop layer, the buffer layer may be formed by patterning the preliminary buffer layer. The buffer layer 310 may be for preventing the substrate 300 from being damaged during the process of forming the channel structure 340 in a subsequent process. Here, the buffer layer 310 may include an insulating material such as an oxide.

[0035] Next, a stack 330 may be formed on the polishing stop layer 320. For example, referring again to FIGS. 2A to 2C, a stack may be formed on the polishing stop layer and the gap-fill layer. Here, the stack 330 may include a first material film 330A and a second material film 330B that are alternately stacked. Here, the first material film 330A may include an insulating material such as an oxide, and the second material film 330B may include a sacrificial material such as a nitride. Alternatively, the second material film 330B may include a conductive material such as tungsten, molybdenum, or polysilicon.

[0036] Channel structures 340 may then be formed extending through the stack 330 and the polish-stop film 320. Here, the channel structures 340 may penetrate the polish-stop film 320. At least one of the channel structures 340 may extend into the buffer film 310. Alternatively, at least one of the channel structures 340 may extend into the substrate 300. Each of the channel structures 340 may include at least one of a channel film 340A, a memory film 340B surrounding the channel film 340A, and an insulating core 340C within the channel film 340A.

[0037] The channel structure 340 may be formed in the first region AR1, but may not be formed in the second region AR2. For example, the channel structure 340 may be formed in the cell region CER. To form the channel structure 340, an opening extending through the stack 330 must be formed, but the depth of the opening may vary due to process limitations, and this problem may become more severe as the aspect ratio of the stack 330 increases. Thus, the channel structure 340 may have different heights.

[0038] Next, the second material film 330B may be replaced with a third material film 330C through a slit (not shown). As a result, a gate structure 330G including the first material film 330A and the third material film 330C alternately stacked may be formed. The third material film 330C may include a conductive material such as tungsten, molybdenum, or polysilicon. Here, the third material film 330C may be a word line, a bit line, a drain selection line, or a source selection line. For reference, if the second material film 330B includes a conductive material, the replacement process may be omitted. In this case, the stack 330 may be used as the gate structure 330G. Next, a slit structure (not shown) may be formed in the slit. Here, the slit structure may include an insulating material, a conductive material, or a semiconductor material.

[0039] Next, a first contact via 350, a first wiring 360, and a first bonding pad 380 may be formed on the gate structure 330G. The first contact via 350 may be connected to the channel structure 340. The first wiring 360 may be connected to the first contact via 350. At least one of the first bonding pads 380 may be connected to the first wiring 360. The first contact via 350, the first wiring 360, and the first bonding pad 380 may be formed in the first interlayer insulating film 370. Thus, a first wafer W1 may be formed, including at least one of the substrate 300, the buffer film 310, the polishing stop film 320, the gate structure 330, the channel structure 340, the first contact via 350, the first wiring 360, the first interlayer insulating film 370, and the first bonding pad 380.

[0040] A second wafer W2 may be formed. First, a peripheral circuit PC may be formed. The peripheral circuit PC may be formed on a substrate 400. The peripheral circuit PC may include a transistor 410. The transistor 410 may include at least one of a junction 410A, 410B, a gate insulating film 410C, and a gate electrode 410D. An isolation insulating film ISO may be formed in the substrate 400, and an active region of the transistor 410 may be defined by the isolation insulating film ISO. Next, a second contact via 420 and a second wiring 430 may be formed on the peripheral circuit PC. At least one of the second contact vias 420 may be connected to the transistor 410. The second wiring 430 may be connected to the second contact via 420, respectively. Next, a second bonding pad 450 may be formed. The second bonding pad 450 may be connected to at least one of the second wiring 430. The second contact via 420 , the second wiring 430 , and the second bonding pad 450 may be formed in the second interlayer insulating film 440 .

[0041] Next, the first wafer W1 and the second wafer W2 may be bonded together. For example, the top surface of the first wafer W1 may be bonded to the top surface of the second wafer W2. The first bonding pad 380 of the first wafer W1 may be bonded to the second bonding pad 450 of the second wafer W2. The first wafer W1 may be rotated and bonded to the second wafer W2.

[0042] 3B, the substrate 300 and the buffer film 310 may be polished to expose the polishing stop film 320. For example, the substrate 300 and the channel structure 340 may be polished to expose the polishing stop film 320. For reference, the polishing stop film 320 may be partially removed. Since the channel structure 340 may extend through the polishing stop film 320 into the buffer film 310 or the substrate 300, polishing the channel structure 340 may result in the top surface of the polishing stop film 320 and the top surface of the channel structure 340 being located at substantially the same level. In other words, the channel structure 340 may be polished to have substantially the same height.

[0043] Referring to FIG. 3C, the polishing stop film 320 may be removed. In this case, the sidewall of the channel structure 340 may be exposed. For example, the memory film 340B of the channel structure 340 may be exposed. Then, a part of the memory film 340B may be removed to expose the sidewall of the channel film 340A. Then, a junction J may be formed in the channel film 340A located at a level corresponding to the third material film 330C. For example, the junction J may be formed in the channel film 340A by doping with impurities. Since the channel structure 340 has substantially the same height, the junction J may also be formed at substantially the same level. Therefore, the memory cells may have uniform characteristics. Here, the third material film 330C may be a source selection line.

[0044] 3D, a source structure 390 may be formed on the gate structure 330G. For example, the source structure 390 may be formed to be coupled to the channel structure 340. Here, the channel film 340A may be coupled to the source structure 390.

[0045] According to the above-described manufacturing method, even if the channel structures 340 are formed to have different heights before bonding, the channel structures 340 can be polished to substantially the same height after bonding using the polishing stop layer 320. Therefore, the junctions J can be formed at substantially the same level in the channel structures 340, and the memory cells can have uniform characteristics.

[0046] The first wafer W1 configured with the memory cell array including the channel structure 340 and the like can be bonded to a separate second wafer W2 configured with peripheral circuits PC related to the operation of the memory cell array. Therefore, by configuring the peripheral circuits PC related to the operation of the memory cell array as a separate second wafer W2, more memory cells can be positioned on the first wafer W1 including the memory cell array, and therefore more data can be stored.

[0047] Although the embodiments according to the technical idea of ​​the present invention have been described above with reference to the attached drawings, this is merely for the purpose of describing the embodiments according to the concept of the present invention, and the present invention is not limited to the above embodiments. Various substitutions, modifications and changes to the embodiments are possible by a person having ordinary skill in the art to which the present invention pertains, within the scope of the technical idea of ​​the present invention described in the claims, and these also belong to the scope of the present invention. [Explanation of symbols]

[0048] 100, 200, 300, 400: substrate, 110, 410: transistor, 110A, 110B, 410A, 410B: junction, 110C, 410C: gate insulating film, 110D, 410D: gate electrode, 120: interconnection structure, 120A, 120D, 350, 420: contact via, 120B, 120C, 360, 430: wiring, 130: bonding structure, 130A, 130B, 380, 450: bonding pad, 140, 330G: gate structure, 140A: insulating film, 140B: conductive film, 150, 340: channel structure, 150A, 3 40A: channel film, 150B, 340B: memory film, 150C, 340C: insulating core, 160, 390: source structure, 210A: pre-polishing stop film, 210, 320: polishing stop film, 220: gap fill film, 310: buffer film, 330: laminate, 330A: first material film, 330B: second material film, 330C: third material film, 340: channel structure, W: wafer, CHR: chip region, CER: cell region, SR: scribe lane region, PR: peripheral circuit region, AR: region, J: junction, IL, 370, 440: interlayer insulating film, ISO: isolation insulating film, PC: peripheral circuit

Claims

1. forming a polishing stop film on the substrate; forming a laminate on the polish stop film; forming channel structures extending through the stack and the polish stop film into the substrate and having different heights; polishing the substrate and the channel structure to expose the polish stop layer; removing the polishing stop film; A method for manufacturing a semiconductor device comprising the steps of:

2. The step of polishing the substrate and the channel structure includes: polishing the channel structures so that the channel structures have substantially the same height; The method for manufacturing a semiconductor device according to claim 1 .

3. forming a source structure connected to the channel structure on the stack after removing the polishing stop layer; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

4. the substrate includes a first region and a second region, the polishing stop film is formed in the first region, and a gap fill film is formed in the second region; The method for manufacturing a semiconductor device according to claim 1 .

5. the polish stop film has a first type of stress and the gap-fill film has a second type of stress different from the first type. The method for manufacturing a semiconductor device according to claim 4 .

6. the first type of stress is a tensile stress and the second type of stress is a compressive stress; The method for manufacturing a semiconductor device according to claim 5 .

7. The first region is a cell region, and the second region is a peripheral circuit region. The method for manufacturing a semiconductor device according to claim 4 .

8. The channel structure is formed in the cell region. The method for manufacturing a semiconductor device according to claim 7 .

9. the polishing stop layer includes a material having a selectivity to oxide, and the gap fill layer includes an oxide; The method for manufacturing a semiconductor device according to claim 4 .

10. The polishing stop film includes at least one of nitride, tungsten, cobalt silicide, aluminum oxide, and titanium silicide. The method for manufacturing a semiconductor device according to claim 1 .

11. forming a buffer film before forming the polishing stop film; The method for manufacturing a semiconductor device according to claim 1 , further comprising:

12. providing a substrate including a first region and a second region; forming a polish stop layer having a first type of stress in the first region of the substrate; forming a gap-fill film having a second type of stress different from the first type in the second region of the substrate; forming a laminate on the polish stop film and the gap fill film; forming channel structures extending through the stack and the polish stop film and having different heights; polishing the substrate and the channel structure so that the polish stop layer is exposed; A method for manufacturing a semiconductor device comprising the steps of:

13. the first type of stress is a tensile stress and the second type of stress is a compressive stress; The method for manufacturing a semiconductor device according to claim 12 .

14. removing the polishing stop film; forming a source structure on the laminate, the source structure being coupled to the channel structure; The method for manufacturing a semiconductor device according to claim 12, further comprising:

15. The step of polishing the substrate and the channel structure includes: polishing the channel structures so that the channel structures have substantially the same height; The method for manufacturing a semiconductor device according to claim 12 .

16. The first region is a cell region, and the second region is a peripheral circuit region. The method for manufacturing a semiconductor device according to claim 12 .

17. The channel structure is formed in the cell region. The method for manufacturing a semiconductor device according to claim 16.

18. the polishing stop layer includes a material having a selectivity to oxide, and the gap fill layer includes an oxide; The method for manufacturing a semiconductor device according to claim 12 .

19. The polishing stop film includes at least one of nitride, tungsten, cobalt silicide, aluminum oxide, and titanium silicide. The method for manufacturing a semiconductor device according to claim 12 .

20. forming a buffer film before forming the polishing stop film; The method for manufacturing a semiconductor device according to claim 12, further comprising:

21. forming a buffer film; forming a polishing stop film on the buffer film; forming a laminate on the polish stop film; forming a channel structure extending through the stack and the polish stop film into the buffer film; polishing the buffer film and the channel structure so as to expose the polish stop film; removing the polishing stop film; A method for manufacturing a semiconductor device comprising the steps of:

22. forming a source structure connected to the channel structure on the stack after removing the polishing stop layer; The method for manufacturing a semiconductor device according to claim 21 , further comprising:

23. The step of polishing the buffer film and the channel structure includes: polishing the channel structures so that the channel structures have substantially the same height; The method for manufacturing a semiconductor device according to claim 21 .

24. The polishing stop film includes a material having a selectivity to oxide. The method for manufacturing a semiconductor device according to claim 21 .

25. The polishing stop film includes at least one of nitride, tungsten, cobalt silicide, aluminum oxide, and titanium silicide. The method for manufacturing a semiconductor device according to claim 21 .

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