Semiconductor device

Abstract

To provide a semiconductor device capable of improving an element performance and reliability.SOLUTION: A semiconductor device includes: a first channel pattern CH1 that contains a lower pattern BP1 extended to a first direction D1 and a plurality of first sheet patterns NS1 that is arranged thereon and is separated to a second direction D2; a second channel pattern CH2 that contains a plurality of second sheet patterns NS2 that is arranged onto the lower pattern and is separated to a second direction, and is separated to the first direction with the first channel pattern; a first gate structure body GS1 that surrounds the first sheet pattern, and contains a first gate electrode 120 and a first gate insulation film 130; a second gate structure body GS2 that surrounds the second sheet pattern, and contains a second gate electrode 220 and a second gate insulation film 230; a first gate capping pattern 145 on the first gate structure body; and a second gate capping pattern 245 on the second gate structure body. The number of the first and second sheet patterns is different, and a thickness of the first and second capping patterns to the second direction are different.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an MBCFET (registered trademark) (Multi-Bridge Channel Field Effect Transistor). [Background technology]

[0002] As one of the scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.

[0003] Such multi-gate transistors are easy to scale because they use a three-dimensional channel. Furthermore, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, it is possible to effectively suppress the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage.

[0004] However, in a multi-gate transistor in which a gate is formed on the surface of a multi-channel active pattern, the performance of the gate electrode may be deteriorated due to the size of the nanosheet (NS). Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned problems with the conventional multi-gate transistors, and an object of the present invention is to provide a semiconductor device capable of improving element performance and reliability. [Means for solving the problem]

[0006] In order to achieve the above object, a semiconductor device according to the present invention includes a lower pattern extending in a first direction, a first channel pattern including a plurality of first sheet patterns disposed on the lower pattern and spaced apart in a second direction different from the first direction, and a plurality of second sheet patterns disposed on the lower pattern and spaced apart in the second direction, the first channel pattern and the second channel pattern spaced apart in the first direction, a first gate structure surrounding the first sheet pattern and including a first gate electrode and a first gate insulating film, a second gate structure surrounding the second sheet pattern and including a second gate electrode and a second gate insulating film, a first gate capping pattern on the first gate structure, and a second gate capping pattern on the second gate structure, wherein a number of the first sheet patterns is different from a number of the second sheet patterns, and a thickness of the first gate capping pattern in the second direction is different from a thickness of the second gate capping pattern in the second direction.

[0007] In order to achieve the above object, a semiconductor device according to the present invention includes a lower pattern extending in a first direction, a first channel pattern including a plurality of first sheet patterns disposed on the lower pattern and spaced apart in a second direction different from the first direction, and a plurality of second sheet patterns disposed on the lower pattern and spaced apart in the second direction, the first channel pattern and the second channel pattern spaced apart in the first direction, a first gate electrode surrounding the first sheet pattern, a second gate electrode surrounding the second sheet pattern, a first gate capping pattern on the first gate electrode, a second gate capping pattern on the second gate electrode, and a gate electrode extending into the first gate capping pattern. the first gate contact electrically connected to the first gate electrode and the second gate contact extended into the second gate capping pattern and electrically connected to the second gate electrode, a number of the first sheet patterns is different from a number of the second sheet patterns, the first gate electrode includes a first portion of the first gate electrode overlapping the first channel pattern in the second direction, the second gate electrode includes a first portion of the second gate electrode overlapping the second channel pattern in the second direction, and a distance from an upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is different from a distance from an upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode.

[0008] In addition, a semiconductor device according to the present invention, which has been made to achieve the above-mentioned object, includes a lower pattern, a first channel pattern disposed on the lower pattern and including a plurality of first sheet patterns, a second channel pattern disposed on the lower pattern and including a plurality of second sheet patterns, wherein the number of the second sheet patterns included in the second channel pattern is less than the number of the first sheet patterns included in the first channel pattern, a source / drain pattern disposed on the lower pattern and electrically connected to the first channel pattern and the second channel pattern, a first gate electrode surrounding the first sheet pattern in a cross-sectional view, a second gate electrode surrounding the second sheet pattern in a cross-sectional view, a first gate capping pattern on the first gate electrode, and a second gate capping pattern on the second gate electrode, wherein in the cross-sectional view, a distance from an upper surface of the lower pattern to an upper surface of the first gate electrode is greater than a distance from an upper surface of the lower pattern to an upper surface of the second gate electrode. Effect of the Invention

[0009] According to the semiconductor device of the present invention, by changing the number of nanosheets (NS) rather than the width of the nanosheets, process defects that may occur during the manufacturing process can be eliminated, and further, by reducing the volume of the outer gate, the capacitance between the metal gate and the contact can be reduced. [Brief description of the drawings]

[0010] [Figure 1] 1 is an exemplary plan view for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 2 is a cross-sectional view taken along lines BB, CC, and DD in FIG. 1. [Figure 4] 2 is a cross-sectional view taken along lines EE, FF, and GG in FIG. 1. [Diagram 5]4 is an enlarged cross-sectional view of a region P in FIG. 3. [Figure 6] 4 is an enlarged cross-sectional view showing a region Q in FIG. 3. [Figure 7] 4 is an enlarged cross-sectional view of a region R in FIG. 3. [Figure 8] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 9] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 10] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 12] FIG. 13 is a diagram for explaining a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 13] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 14] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 15] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 16] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention [Figure 18] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention [Figure 19] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention [Figure 20] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention [Figure 21]1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 25] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 27] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 30] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 31] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 32] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 33] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 34] 1A to 1C are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Next, specific examples of embodiments for carrying out the semiconductor device according to the present invention will be described with reference to the drawings.

[0012] In this specification, although terms such as first, second, etc. are used to describe various elements or components, it should be understood that these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, it goes without saying that a first element or component referred to below may be a second element or component within the technical concept of the present invention.

[0013] Semiconductor devices according to embodiments of the present invention may include tunneling transistors (FETs), three-dimensional (3D) transistors, or two-dimensional material based transistors (2D material based FETs), and heterostructures thereof. Additionally, the semiconductor device according to the embodiment of the present invention may include a bipolar junction transistor, a lateral double-diffused transistor (LDMOS), and the like.

[0014] A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an illustrative plan view for explaining the schematic configuration of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, FIG. 3 is a cross-sectional view taken along lines BB, CC, and DD in FIG. 1, FIG. 4 is a cross-sectional view taken along lines EE, FF, and GG in FIG. 1, and FIGS. 5 to 7 are cross-sectional views respectively showing enlarged P region, Q region, and R region in FIG. 3. For reference, FIG. 1 is simplified and does not include the gate insulating film (130, 230, 330), the gate contact (175, 275, 375), the source / drain via 195, etc.

[0015] 1 to 7, a semiconductor device according to an embodiment of the present invention includes a first lower pattern BP1, first to third channel patterns (CH1, CH2, CH3), first to third gate structures (GS1, GS2, GS3), first to third gate capping patterns (145, 245, 345), first to fourth source / drain patterns (150, 250, 350, 450), and first to third gate contacts (175, 275, 375).

[0016] The substrate 100 is bulk silicon or silicon-on-insulator (SOI). In some embodiments, the substrate 100 may be a silicon substrate or may include other materials such as, but not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0017] The first lower pattern BP1 protrudes from the substrate 100 in a third direction D3. The first lower pattern BP1 extends long in the first direction D1. The first lower pattern BP1 is a fin-shaped pattern. As an example, the first lower pattern BP1 is disposed in a region in which a PMOS is formed. As another example, the first lower pattern BP1 may be disposed in a region where an NMOS is formed. The first lower pattern BP1 is formed by etching a portion of the substrate 100 and includes an epitaxial layer grown on the substrate 100. The first lower pattern BP1 includes an elemental semiconductor material, silicon or germanium. Also, the first lower pattern BP1 may include a compound semiconductor, for example, a IV-IV compound semiconductor or a III-V compound semiconductor.

[0018] The IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a Group IV element. The III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a group V element.

[0019] A field dielectric 105 is disposed on the substrate 100 . The field insulating film 105 is disposed on the sidewalls of the first lower pattern BP1. The field insulating film 105 is not disposed on the upper surface (BP1_US) of the first lower pattern. The field insulating film 105 entirely covers the sidewalls of the first lower pattern BP1. Unlike the drawing, the field insulating film 105 may cover a portion of the sidewall of the first lower pattern BP1. In this case, a portion of the first lower pattern BP1 protrudes from the upper surface of the field insulating film 105 in the third direction D3. Although the upper surface of the field insulating film 105 is shown as being flat, the present invention is not limited to this. Unlike the figure, the top surface of the field insulating film 105 may have a concave shape. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film 105 is shown as a single film, this is for convenience of explanation and is not intended to be limiting.

[0020] At least one first channel pattern CH1 is disposed on the first lower pattern BP1. At least one second channel pattern CH2 is disposed on the first lower pattern BP1. At least one third channel pattern CH3 is disposed on the first lower pattern BP1. The first channel pattern CH1, the second channel pattern CH2, and the third channel pattern CH3 are each disposed on the upper surface (BP1_US) of the first lower pattern. The first channel pattern CH1, the second channel pattern CH2, and the third channel pattern CH3 each overlap the first lower pattern BP1 in the third direction D3. The first channel pattern CH1, the second channel pattern CH2, and the third channel pattern CH3 are each spaced apart from the first lower pattern BP1 in a third direction D3.

[0021] The first channel pattern CH1 is spaced apart from the second channel pattern CH2 and the third channel pattern CH3 in a first direction D1. The first channel patterns CH1 are spaced apart from each other in a first direction D1. The second channel pattern CH2 is spaced apart from the third channel pattern CH3 in the first direction D1. The second channel patterns CH2 are spaced apart from each other in the first direction D1. The third channel patterns CH3 are spaced apart from each other in the first direction D1. The first channel pattern CH1 includes a plurality of first sheet patterns NS1. A plurality of first sheet patterns NS1 are disposed on the upper surface (BP1_US) of the first lower pattern. The multiple first sheet patterns NS1 are arranged in the third direction D3 on the first lower pattern BP1. The first sheet patterns NS1 are spaced apart from each other in the third direction D3.

[0022] The second channel pattern CH2 includes a plurality of second sheet patterns NS2. A plurality of second sheet patterns NS2 are disposed on the upper surface (BP1_US) of the first lower pattern. The plurality of second sheet patterns NS2 are arranged in the third direction D3 on the first lower pattern BP1. The second sheet patterns NS2 are spaced apart from each other in the third direction D3. The third channel pattern CH3 includes a plurality of third sheet patterns NS3. A plurality of third sheet patterns NS3 are disposed on the upper surface (BP1_US) of the first lower pattern. The plurality of third sheet patterns NS3 are arranged in a third direction D3 on the first lower pattern BP1. The third sheet patterns NS3 are spaced apart from each other in the third direction D3. The third direction D3 intersects with the first direction D1 and the second direction D2. For example, the third direction D3 is the thickness direction of the substrate 100. The first direction D1 intersects with the second direction D2.

[0023] The number of the first sheet patterns NS1 is different from the number of the second sheet patterns NS2 and the number of the third sheet patterns NS3. The number of the second sheet patterns NS2 is different from the number of the third sheet patterns NS3. For example, the number of first sheet patterns NS1 included in the first channel pattern CH1 is greater than the number of second sheet patterns NS2 included in the second channel pattern CH2. The number of first sheet patterns NS1 included in the first channel pattern CH1 is greater than the number of third sheet patterns NS3 included in the third channel pattern CH3. The number of second sheet patterns NS2 included in the second channel pattern CH2 is greater than the number of third sheet patterns NS3 included in the third channel pattern CH3. Although the first to third channel patterns (CH1, CH2, CH3) each include a plurality of sheet patterns, the present invention is not limited to this. Unlike the drawing, the number of third sheet patterns NS3 included in the third channel pattern CH3 may be one.

[0024] The first channel pattern CH1 includes one more sheet pattern than the second channel pattern CH2, but is not limited to this. The second channel pattern CH2 includes one more sheet pattern than the third channel pattern CH3, but is not limited to this. Although a case where the second channel pattern CH2 is arranged between the first channel pattern CH1 and the third channel pattern CH3 is shown, this is for convenience of explanation and is not limited thereto. Of course, the first channel pattern CH1 can be disposed between the second channel pattern CH2 and the third channel pattern CH3.

[0025] The first to third sheet patterns (NS1, NS2, NS3) each include an upper surface and a lower surface. Taking the first sheet pattern NS1 as an example, the upper surface of the first sheet pattern NS1 is opposite to the lower surface of the first sheet pattern NS1 in the third direction D3. The lower surface of the first sheet pattern NS1 faces the upper surface (BP1_US) of the first lower pattern. The upper surface (CH1_US) of the first channel pattern is the upper surface of the first sheet pattern NS1 located at the top of the first sheet pattern NS1 included in the first channel pattern CH1. The upper surface (CH2_US) of the second channel pattern is the upper surface of the second sheet pattern NS2 located at the top of the second sheet pattern NS2 included in the second channel pattern CH2. The upper surface (CH3_US) of the third channel pattern is the upper surface of the third sheet pattern NS3 located at the top of the third sheet pattern NS3 included in the third channel pattern CH3. The height or distance from the top surface (BP1_US) of the first lower pattern to the top surface (CH2_US) of the second channel pattern is smaller than the height or distance from the top surface (BP1_US) of the first lower pattern to the top surface (CH1_US) of the first channel pattern. The height or distance from the top surface (BP1_US) of the first lower pattern to the top surface (CH2_US) of the second channel pattern is greater than the height or distance from the top surface (BP1_US) of the first lower pattern to the top surface (CH3_US) of the third channel pattern.

[0026] The first to third sheet patterns (NS1, NS2, NS3) each include one of elemental semiconductor materials, silicon or germanium, a IV-IV compound semiconductor, or a III-V compound semiconductor. The first sheet pattern NS1 contains the same material as the second sheet pattern NS2. The first sheet pattern NS1 contains the same material as the third sheet pattern NS3. The first sheet pattern NS1 may include the same material as the first lower pattern BP1, or may include a different material than the first lower pattern BP1. In some embodiments of the semiconductor device, the first lower pattern BP1 is a silicon lower pattern including silicon. The first to third sheet patterns (NS1, NS2, NS3) are silicon sheet patterns that contain silicon.

[0027] The width of the first sheet pattern NS1 in the second direction D2 becomes larger or smaller in proportion to the width of the upper surface (BP1_US) of the first lower pattern in the second direction D2. Although a case is shown in which the widths in the second direction D2 of the first sheet patterns NS1 stacked in the third direction D3 are uniform, this is for convenience of explanation and is not limiting. Unlike the figure, the width in the second direction D2 of the first sheet pattern NS1 stacked in the third direction D3 may become smaller as it becomes farther away from the first lower pattern BP1. Needless to say, the above description can also be applied to the second sheet pattern NS2 and the third sheet pattern NS3. Although the above description has been given of a case in which three channel patterns (CH1, CH2, CH3) including different numbers of sheet patterns are disposed on the first lower pattern BP1, the present invention is not limited thereto. Contrary to the description, for example, two channel patterns including different numbers of sheet patterns may be disposed on the first lower pattern BP1. As another example, four or more channel patterns including different numbers of sheet patterns may be disposed on the first lower pattern BP1.

[0028] The first to third gate structures (GS1, GS2, GS3) are each disposed on the first lower pattern BP1. The first to third gate structures (GS1, GS2, GS3) each intersect with the first lower pattern BP1. The first to third gate structures (GS1, GS2, GS3) each contact the upper surface (BP1_US) of the first lower pattern. The first gate structure GS1 is spaced apart from the second gate structure GS2 and the third gate structure GS3 in a first direction D1. The second gate structure GS2 is spaced apart from the third gate structure GS3 in the first direction D1. The first gate structure GS1 surrounds the first channel pattern CH1 in cross sections in the first direction D1 and the second direction D2. The term "surround" as used herein may be construed as extending along the periphery, but not necessarily completely surrounding. The first gate structure GS1 surrounds each of the first sheet patterns NS1 in a cross section intersecting the first direction D1 and the second direction D2.

[0029] The first gate structure GS1 includes a first inner gate structure (GS1_I) and a first outer gate structure (GS1_O). The first inner gate structure (GS1_I) is disposed between the first sheet patterns NS1 adjacent to each other in the third direction D3 and between the first lower pattern BP1 and the first sheet pattern NS1. A first outer gate structure (GS1_O) is disposed on an upper surface (CH1_US) of the first channel pattern. For example, the first inner gate structure (GS1_I) and the first outer gate structure (GS1_O) may be defined from a cross-sectional perspective as in FIG.

[0030] The second gate structure GS2 surrounds the second channel pattern CH2 in cross sections in the first direction D1 and the second direction D2. The second gate structure GS2 surrounds each of the second sheet patterns NS2 in a cross section intersecting the first direction D1 and the second direction D2. The second gate structure GS2 includes a second inner gate structure (GS2_I) and a second outer gate structure (GS2_O). The second inner gate structure (GS2_I) is disposed between the second sheet patterns NS2 adjacent to each other in the third direction D3 and between the first lower pattern BP1 and the second sheet pattern NS2. A second outer gate structure (GS2_O) is disposed on the upper surface (CH2_US) of the second channel pattern.

[0031] The third gate structure GS3 surrounds the third channel pattern CH3. A third gate structure GS3 surrounds each of the third sheet patterns NS3. The third gate structure GS3 includes a third inner gate structure (GS3_I) and a third outer gate structure (GS3_O). The third inner gate structure (GS3_I) is disposed between the third sheet patterns NS3 adjacent to each other in the third direction D3 and between the first lower pattern BP1 and the third sheet pattern NS3. A third outer gate structure (GS3_O) is disposed on an upper surface (CH3_US) of the third channel pattern.

[0032] The first gate structure GS1 includes a first gate electrode 120 and a first gate insulating film . The first inner gate structure (GS1_I) and the first outer gate structure (GS1_O) each include a first gate electrode 120 and a first gate insulating film 130. The first gate electrode 120 is disposed on the first lower pattern BP1. When viewed in cross section, the first gate electrodes 120 surround each of the first sheet patterns NS1. The first gate insulating film 130 is disposed between the first gate electrode 120 and the first channel pattern CH1. The first gate insulating film 130 is disposed between the first gate electrode 120 and the first sheet pattern NS1.

[0033] The second gate structure GS2 includes a second gate electrode 220 and a second gate insulating film 230. The second inner gate structure (GS2_I) and the second outer gate structure (GS2_O) each include a second gate electrode 220 and a second gate insulating film 230. The second gate electrode 220 is disposed on the first lower pattern BP1. When viewed in cross section, the second gate electrodes 220 surround each of the second sheet patterns NS2. The second gate insulating film 230 is disposed between the second gate electrode 220 and the second sheet pattern NS2.

[0034] The third gate structure GS3 includes a third gate electrode 320 and a third gate insulating film 330. The third inner gate structure (GS3_I) and the third outer gate structure (GS3_O) each include a third gate electrode 320 and a third gate insulating film 330. The third gate electrode 320 is disposed on the first lower pattern BP1. When viewed in cross section, the third gate electrodes 320 surround each of the third sheet patterns NS3. The third gate insulating film 330 is disposed between the third gate electrode 320 and the third sheet pattern NS3.

[0035] The first to third gate insulating films (130, 230, 330) extend along the upper surface of the field insulating film 105 and the upper surface (BP1_US) of the first lower pattern, respectively. The first to third gate insulating films (130, 230, 330) are in contact with the upper surface of the field insulating film 105 and the upper surface of the first lower pattern (BP1_US), respectively. In the cross-sectional view of FIG. 2, the upper surface 120US of the first gate electrode, the upper surface 220US of the second gate electrode, and the upper surface 320US of the third gate electrode are shown as recessed curved surfaces, but the present invention is not limited to this. Of course, the top surface 120US of the first gate electrode, the top surface 220US of the second gate electrode, and the top surface 320US of the third gate electrode may be flat.

[0036] 3 and 5, the first gate electrode 120 includes a first portion 120R1 and a second portion 120R2. The first portion 120R1 of the first gate electrode is directly connected to the second portion 120R2 of the first gate electrode. The second portions 120R2 of the first gate electrode are located on both sides of the first portion 120R1 of the first gate electrode. Unlike the top surface 220US of the second gate electrode and the top surface 320US of the third gate electrode, the top surface 120US of the first gate electrode is flat. In this case, the first portion 120R1 of the first gate electrode overlaps the first channel pattern CH1 in the third direction D3. For example, the first portion 120R1 of the first gate electrode is a portion of the first gate electrode 120 that overlaps with the upper surface (CH1_US) of the first channel pattern in the third direction D3. The second portion 120R2 of the first gate electrode does not overlap the first channel pattern CH1 in the third direction D3.

[0037] 3 and 6, the second gate electrode 220 includes a first portion 220R1 and a second portion 220R2. The first portion 220R1 of the second gate electrode is directly connected to the second portion 220R2 of the second gate electrode. The second portions 220R2 of the second gate electrode are located on both sides of the first portion 220R1 of the second gate electrode. The upper surface 220US of the second gate electrode includes a region recessed toward the second channel pattern CH2. The first portion 220R1 of the second gate electrode is a region where a part of the second gate electrode 220 is recessed. The first portion 220R1 of the second gate electrode overlaps the second channel pattern CH2 in the third direction D3. The first portion 220R1 of the second gate electrode overlaps with an upper surface (CH2_US) of the second channel pattern in the third direction D3. The second portion 220R2 of the second gate electrode does not overlap the second channel pattern CH2 in the third direction D3.

[0038] 3 and 7, the third gate electrode 320 includes a first portion 320R1 and a second portion 320R2. The first portion 320R1 of the third gate electrode is directly connected to the second portion 320R2 of the third gate electrode. The second portions 320R2 of the third gate electrode are located on both sides of the first portion 320R1 of the third gate electrode. The upper surface 320US of the third gate electrode includes a region recessed toward the third channel pattern CH3. The first portion 320R1 of the third gate electrode is a region where a part of the third gate electrode 320 is recessed. The first portion 320R1 of the third gate electrode overlaps the third channel pattern CH3 in the third direction D3. The first portion 320R1 of the third gate electrode overlaps an upper surface (CH3_US) of the third channel pattern in the third direction D3. The second portion 320R2 of the third gate electrode does not overlap the third channel pattern CH3 in the third direction D3.

[0039] A height H11 from the upper surface (BP1_US) of the first lower pattern to an upper surface 120US of the first portion 120R1 of the first gate electrode is different from a height H21 from the upper surface (BP1_US) of the first lower pattern to an upper surface 220US of the first portion 220R1 of the second gate electrode. For example, a height H11 from the upper surface (BP1_US) of the first lower pattern to an upper surface 120US of the first portion 120R1 of the first gate electrode is greater than a height H21 from the upper surface (BP1_US) of the first lower pattern to an upper surface 220US of the first portion 220R1 of the second gate electrode. A height H21 from the upper surface (BP1_US) of the first lower pattern to an upper surface 220US of the first portion 220R1 of the second gate electrode is greater than a height H31 from the upper surface (BP1_US) of the first lower pattern to an upper surface 320US of the first portion 320R1 of the third gate electrode.

[0040] The second gate electrode 220 will be taken as an example for explanation. A height H21 from the top surface (BP1_US) of the first lower pattern to the top surface 220US of the first portion 220R1 of the second gate electrode is measured on a line passing through the center of the top surface (CH2_US) of the second channel pattern. For example, the height H21 from the upper surface (BP1_US) of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode is the height from the upper surface (BP1_US) of the first lower pattern to the upper surface 220US of the second gate electrode in FIG. A height H13 from the upper surface (BP1_US) of the first lower pattern to an upper surface 120US of the second portion 120R2 of the first gate electrode is the same as a height H23 from the upper surface (BP1_US) of the first lower pattern to an upper surface 220US of the second portion 220R2 of the second gate electrode. A height H23 from the upper surface (BP1_US) of the first lower pattern to an upper surface 220US of the second portion 220R2 of the second gate electrode is the same as a height H33 from the upper surface (BP1_US) of the first lower pattern to an upper surface 320US of the second portion 320R2 of the third gate electrode. Here, the term "same height" refers not only to the heights being completely the same at the two positions being compared, but also to a slight difference in height that may occur due to margins in the process.

[0041] When the upper surface 120US of the first gate electrode is flat as shown in FIG. 3, the height H11 from the upper surface (BP1_US) of the first lower pattern to the upper surface 120US of the first portion 120R1 of the first gate electrode is the same as the height H13 from the upper surface (BP1_US) of the first lower pattern to the upper surface 120US of the second portion 120R2 of the first gate electrode. Unlike the figure, when the upper surface 120US of the first gate electrode has a concave shape, the height H11 from the upper surface (BP1_US) of the first lower pattern to the upper surface 120US of the first portion 120R1 of the first gate electrode may be smaller than the height H13 from the upper surface (BP1_US) of the first lower pattern to the upper surface 120US of the second portion 120R2 of the first gate electrode.

[0042] In Figures 3, 6, and 7, the height H21 from the upper surface (BP1_US) of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode is smaller than the height H23 from the upper surface (BP1_US) of the first lower pattern to the upper surface 220US of the second portion 220R2 of the second gate electrode. A height H31 from the upper surface (BP1_US) of the first lower pattern to an upper surface 320US of the first portion 320R1 of the third gate electrode is smaller than a height H33 from the upper surface (BP1_US) of the first lower pattern to an upper surface 320US of the second portion 320R2 of the third gate electrode.

[0043] The first gate structure GS1 and the second gate structure GS2 will be taken as an example for explanation. When viewed in cross section as in FIG. 2, when the upper surface 220US of the second gate electrode is located at the same height level as the upper surface 120US of the first gate electrode, the area where the second source / drain contact 270 and the second outer gate structure (GS2_O) face each other is larger than the area where the first source / drain contact 170 and the first outer gate structure (GS1_O) face each other.

[0044] As a result, the capacitance between the second source / drain contact 270 and the second outer gate structure (GS2_O) is greater than the capacitance between the first source / drain contact 170 and the first outer gate structure (GS1_O). A large capacitance between the outer gate structure and the source / drain contacts hinders the operation of semiconductor devices that require high speed operation. This can result in a decrease in the performance and reliability of the semiconductor device. On the other hand, the capacitance between the second source / drain contact 270 and the second outer gate structure (GS2_O) is reduced by making the upper surface 220US of the second gate electrode lower than the upper surface 120US of the first gate electrode. That is, the performance and reliability of the semiconductor device are improved.

[0045] The first to third gate electrodes (120, 220, 320) may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first to third gate electrodes (120, 220, 320) may be made of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten nitride (WN), tungsten nitride (Tb ... The metal oxide may include, but is not limited to, at least one of tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the above-mentioned materials.

[0046] The first to third gate insulating films (130, 230, 330) may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0047] Although the first to third gate insulating films (130, 230, 330) are each shown as a single film, this is for convenience of explanation and is not intended to be limiting. Each of the first to third gate insulating films (130, 230, 330) includes a plurality of films. Taking the first gate insulating film 130 as an example, the first gate insulating film 130 may include an interfacial layer disposed between the first channel pattern CH1 and the first gate electrode 120, and an insulating film having a high dielectric constant. For example, the interface film does not have to be formed along the profile of the upper surface of the field insulating film 105 .

[0048] A semiconductor device according to some embodiments includes an NC (Negative Capacitance) FET that uses a negative capacitor. For example, the first to third gate insulating films (130, 230, 330) each include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties. The ferroelectric material film has a negative capacitance, and the paraelectric material film has a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance has a positive value and is greater than the absolute value of each individual capacitance. When a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the overall capacitance value of the ferroelectric material film and the paraelectric material film connected in series increases. With the increased overall capacitance, transistors including ferroelectric material films have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0049] The ferroelectric material film has ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide is a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0050] The ferroelectric material film further includes a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant contained in the ferroelectric material film varies depending on which ferroelectric material the ferroelectric material film contains. When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0051] When the dopant is aluminum (Al), the ferroelectric material film contains 3 to 8 at % (atomic %) of aluminum. Here, the ratio of the dopant is the ratio of aluminum to the sum of hafnium and aluminum. When the dopant is silicon (Si), the ferroelectric material film contains 2 to 10 at % of silicon. When the dopant is yttrium (Y), the ferroelectric material film contains 2 to 10 at % of yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film contains 1 to 7 at % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film contains 50 to 80 at % of zirconium.

[0052] The paraelectric material film has paraelectric properties. The paraelectric material film includes, for example, at least one of silicon oxide and metal oxide having a high dielectric constant. The metal oxide contained in the paraelectric material film may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The ferroelectric material film and the paraelectric material film may comprise the same material. A ferroelectric material film has ferroelectric properties, but a paraelectric material film does not necessarily have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material layer may be different from the crystal structure of the hafnium oxide contained in the paraelectric material layer.

[0053] The ferroelectric material film has a thickness that provides ferroelectric properties. The thickness of the ferroelectric material film is, for example, 0.5 to 10 nm, but is not limited to this. Since each ferroelectric material has a different critical thickness at which the ferroelectric properties are exhibited, the thickness of the ferroelectric material film varies depending on the ferroelectric material. As an example, each of the first to third gate insulating layers 130, 230, and 330 includes a ferroelectric material layer. As another example, each of the first to third gate insulating layers 130, 230, and 330 may include a plurality of ferroelectric material layers spaced apart from one another. Each of the first to third gate insulating films (130, 230, 330) may have a laminated film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately laminated.

[0054] A first gate spacer 140 is disposed on the sidewall of the first gate structure GS1. A second gate spacer 240 is disposed on the sidewall of the second gate structure GS2. A third gate spacer 340 is disposed on the sidewalls of the third gate structure GS3. In a cross-sectional view such as FIG. 2, the first gate structure GS1 does not indent between the first gate spacer 140 and the first channel pattern CH1. The first outer gate structure (GS1_O) is disposed between the first gate spacers 140. In some embodiments of the semiconductor device, a portion of the second gate structure GS2 is recessed between the second gate spacer 240 and the second channel pattern CH2. A portion of the third gate structure GS3 is recessed between the third gate spacer 340 and the third channel pattern CH3. In a cross-sectional view such as FIG. 2, the second gate spacer 240 is shaped to rest on the second outer gate structure (GS2_O). A portion of the second outer gate structure (GS2_O) is recessed between the second gate spacer 240 and the second channel pattern CH2. The third gate spacer 340 is shaped to rest on the third outer gate structure (GS3_O). A portion of the third outer gate structure (GS3_O) is indented between the third gate spacer 340 and the third channel pattern CH3.

[0055] The first to third gate spacers (140, 240, 340) are made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the first to third gate spacers (140, 240, 340) are shown as being single films, this is for convenience of explanation and is not intended to be limiting.

[0056] The first gate capping pattern 145 is disposed on the first gate structure GS1. The first gate capping pattern 145 is disposed on the upper surface 120US of the first gate electrode. The first gate capping pattern 145 includes a bottom surface 145BS and a top surface 145US that are opposite to each other in the third direction D3. The bottom surface 145BS of the first gate capping pattern faces the first gate electrode 120. A lower surface 145BS of the first gate capping pattern contacts an upper surface 120US of the first gate electrode.

[0057] The second gate capping pattern 245 is disposed on the second gate structure GS2. The second gate capping pattern 245 is disposed on the upper surface 220US of the second gate electrode. The second gate capping pattern 245 includes a bottom surface 245BS and a top surface 245US that are opposite to each other in the third direction D3. The bottom surface 245BS of the second gate capping pattern faces the second gate electrode 220. The lower surface 245BS of the second gate capping pattern contacts the upper surface 220US of the second gate electrode.

[0058] A third gate capping pattern 345 is disposed on the third gate structure GS3. The third gate capping pattern 345 is disposed on an upper surface 320US of the third gate electrode. The third gate capping pattern 345 includes a bottom surface 345BS and a top surface 345US that are opposite to each other in the third direction D3. The bottom surface 345BS of the third gate capping pattern faces the third gate electrode 320. A lower surface 345BS of the third gate capping pattern contacts an upper surface 320US of the third gate electrode.

[0059] An upper surface 145US of the first gate capping pattern is disposed in the same plane as an upper surface 245US of the second gate capping pattern. An upper surface 145US of the first gate capping pattern is disposed in the same plane as an upper surface 345US of the third gate capping pattern. A height H12 from the upper surface (BP1_US) of the first lower pattern to an upper surface 145US of the first gate capping pattern is the same as a height H22 from the upper surface (BP1_US) of the first lower pattern to an upper surface 245US of the second gate capping pattern. A height H12 from the upper surface (BP1_US) of the first lower pattern to an upper surface 145US of the first gate capping pattern is the same as a height H32 from the upper surface (BP1_US) of the first lower pattern to an upper surface 345US of the third gate capping pattern. For example, a height H21 from the upper surface (BP1_US) of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode is the height from the upper surface (BP1_US) of the first lower pattern to the lower surface 245BS of the second gate capping pattern.

[0060] The second gate capping pattern 245 will be taken as an example for explanation. The thickness t2 of the second gate capping pattern 245 is the thickness of the second gate capping pattern 245 at a portion where the second gate capping pattern 245 overlaps the second channel pattern CH2 in the third direction D3. For example, the thickness t2 of the second gate capping pattern 245 is measured on a line passing through the center of the upper surface (CH2_US) of the second channel pattern. The first gate capping pattern 145 has a thickness t 1 different from a thickness t 2 of the second gate capping pattern 245 and a thickness t 3 of the third gate capping pattern 345 . The thickness t 2 of the second gate capping pattern 245 is different from the thickness t 3 of the third gate capping pattern 345 . For example, the thickness t 3 of the third gate capping pattern 345 is greater than the thickness t 1 of the first gate capping pattern 145 and the thickness t 2 of the second gate capping pattern 245 .

[0061] The thickness t 2 of the second gate capping pattern 245 is greater than the thickness t 1 of the first gate capping pattern 145 . A thickness t1 of the first gate capping pattern 145 at a portion overlapping the first channel pattern CH1 in the third direction D3 is smaller than a thickness t2 of the second gate capping pattern 245 at a portion overlapping the second channel pattern CH2 in the third direction D3. A thickness t2 of the second gate capping pattern 245 at a portion overlapping the second channel pattern CH2 in the third direction D3 is smaller than a thickness t3 of the third gate capping pattern 345 at a portion overlapping the third channel pattern CH3 in the third direction D3. Taking the first gate spacer 140 and the first gate capping pattern 145 as an example, the first gate capping pattern 145 is disposed on an upper surface of the first gate spacer 140 . Contrary to the illustration, the upper surface of the first gate spacer 140 may be flush with the upper surface 145US of the first gate capping pattern.

[0062] The first to third gate capping patterns (145, 245, 345) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0063] The gate isolation structure GCS is disposed on a substrate 100 . The gate isolation structure GCS is disposed on the field insulating film 105 . The gate isolation structure GCS is in contact with the field insulating film 105 . The gate isolation structure GCS protrudes beyond the upper surface of the field insulating film 105 in the third direction D3. For example, a portion of the gate isolation structure GCS indents into the field insulating film 105. The first gate structure GS1 is disposed between adjacent gate isolation structures GCS in the second direction D2. The second gate structure GS2 is disposed between adjacent gate isolation structures GCS in the second direction D2. The third gate structure GS3 is disposed between adjacent gate isolation structures GCS in the second direction D2.

[0064] The first to third gate insulating films (130, 230, 330) do not extend along the sidewalls of the gate isolation structure GCS in the third direction D3. Taking the first gate insulating layer 130 as an example, the first gate insulating layer 130 does not extend from the top surface of the field insulating layer 105 to the bottom surface 145BS of the first gate capping pattern. The first gate insulating film 130 does not contact the first gate capping pattern 145 . The first to third gate electrodes (120, 220, 320) are in contact with the sidewalls of the gate isolation structure GCS. An upper surface of the gate isolation structure GCS is flush with an upper surface 145US of the first gate capping pattern, an upper surface 245US of the second gate capping pattern, and an upper surface 345US of the third gate capping pattern.

[0065] The gate isolation structure GCS includes an insulating material. The gate isolation structure GCS may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the gate isolation structure GCS is shown as being a single film, this is for convenience of explanation and is not intended to be limiting.

[0066] Although the gate isolation structure GCS is illustrated as being separated from the first to third gate spacers (140, 240, 340) for the sake of convenience of explanation, the present invention is not limited to this. Although the first to third gate structures (GS1, GS2, GS3) separated by the gate isolation structure GCS are shown to cross one lower pattern, this is for convenience of explanation and is not limiting. Unlike the figure, at least one of the first to third gate structures (GS1, GS2, GS3) separated by the gate isolation structure GCS intersects with a plurality of lower patterns.

[0067] The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 are disposed on the first lower pattern BP1. The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 contact the first lower pattern BP1.

[0068] The first source / drain patterns 150 are disposed between the first gate structures GS1 adjacent to each other in the first direction D1. The first source / drain patterns 150 are connected to the first channel patterns CH1 disposed on both sides. The first source / drain patterns 150 contact the respective first sheet patterns NS1. The second source / drain patterns 250 are disposed between the second gate structures GS2 adjacent to each other in the first direction D1. The second source / drain patterns 250 are connected to the second channel patterns CH2 disposed on both sides. The second source / drain patterns 250 contact the respective second sheet patterns NS2.

[0069] The third source / drain patterns 350 are disposed between the third gate structures GS3 adjacent to each other in the first direction D1. The third source / drain patterns 350 are connected to the third channel patterns CH3 arranged on both sides. The third source / drain patterns 350 contact the respective third sheet patterns NS3. The fourth source / drain pattern 450 is disposed between the first gate structure GS1 and the second gate structure GS2 adjacent to each other in the first direction D1. The fourth source / drain pattern 450 is connected to the first channel pattern CH1 and the second channel pattern CH2. The fourth source / drain patterns 450 contact the respective first sheet patterns NS1 and the respective second sheet patterns NS2.

[0070] In some embodiments, the fourth source / drain pattern 450 is disposed between the second gate structure GS2 and the third gate structure GS3 adjacent in the first direction D1. The fourth source / drain pattern 450 is connected to the second channel pattern CH2 and the third channel pattern CH3. The fourth source / drain patterns 450 contact the respective second sheet patterns NS2 and the respective third sheet patterns NS3. Although not shown in the figure, the fourth source / drain pattern 450 is disposed between the first gate structure GS1 and the third gate structure GS3 adjacent to each other in the first direction D1.

[0071] For example, the number of the second sheet patterns NS2 arranged on one side of the fourth source / drain pattern 450 is greater than the number of the third sheet patterns NS3 arranged on the other side of the fourth source / drain pattern 450. 2, the top of one side of the fourth source / drain pattern 450 is higher than the top of the other side of the fourth source / drain pattern 450. As shown in FIG. That is, the upper surface of the fourth source / drain pattern 450 has an inclined surface. When the fourth contact silicide film 455 is disposed on the fourth source / drain pattern 450 , the upper surface of the fourth source / drain pattern 450 having an inclined surface is inferred through the upper surface of the fourth contact silicide film 455 . An upper surface of the fourth contact silicide film 455 contacts the fourth source / drain contact 470 .

[0072] The first inner gate structure (GS1_I) contacts the first source / drain pattern 150. The first inner gate structure (GS1_I) contacts the fourth source / drain pattern 450. The first gate insulating film 130 of the first inner gate structure GS1_I contacts the first source / drain pattern 150 and / or the fourth source / drain pattern 450. The first outer gate structure (GS1_O) does not contact the first source / drain pattern 150. The first outer gate structure (GS1_O) does not contact the fourth source / drain pattern 450.

[0073] The second inner gate structure (GS2_I) and the second outer gate structure (GS2_O) contact the second source / drain pattern 250. The second inner gate structure (GS2_I) and the second outer gate structure (GS2_O) contact the fourth source / drain pattern 450. The second gate insulating film 230 of the second inner gate structure (GS2_I) and the second gate insulating film 230 of the second outer gate structure (GS2_O) contact the second source / drain pattern 250 and / or the fourth source / drain pattern 450.

[0074] The third inner gate structure (GS3_I) and the third outer gate structure (GS3_O) contact the third source / drain pattern 350. The third inner gate structure (GS3_I) and the third outer gate structure (GS3_O) contact the fourth source / drain pattern 450. The third gate insulating film 330 of the third inner gate structure (GS3_I) and the third gate insulating film 330 of the third outer gate structure (GS3_O) contact the third source / drain pattern 350 and / or the fourth source / drain pattern 450.

[0075] The top surface of the second source / drain pattern 250 is lower than the top surface of the first source / drain pattern 150 and higher than the top surface of the third source / drain pattern 350 . The first to fourth source / drain patterns (150, 250, 350, 450) each include an epitaxial pattern. The first to fourth source / drain patterns (150, 250, 350, 450) each include a semiconductor material. The first to fourth source / drain patterns (150, 250, 350, 450) contain dopants of the same conductivity type. The first to fourth source / drain patterns (150, 250, 350, 450) include a p-type dopant or an n-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0076] The source / drain etch stop layer 185 extends along the outer sidewalls of the first to third gate spacers (140, 240, 340) and the sidewalls of the first to third source / drain patterns (150, 250, 350). Although not shown, the source / drain etch stop layer 185 extends along the sidewalls of the fourth source / drain pattern 450 . The source / drain etch stop layer 185 extends along the top surface of the field insulating layer 105 . For example, the source / drain etch stop layer 185 contacts the sidewalls of the first to third source / drain patterns (150, 250, 350). Although not shown, the source / drain etch stop layer 185 contacts the sidewalls of the fourth source / drain pattern 450 .

[0077] The source / drain etch stop layer 185 does not extend along the sidewalls of the first gate capping pattern 145 , the second gate capping pattern 245 , and the third gate capping pattern 345 . Unlike the drawings, the source / drain etch stop layer 185 may extend along the sidewalls of the first to third gate capping patterns (145, 245, 345). The source / drain etch stop film 185 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0078] The first upper interlayer insulating film 190 is disposed on the substrate 100 . A first upper interlayer insulating film 190 is disposed on the source / drain etch stop layer 185 . The first upper interlayer insulating layer 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low-k material may have a value less than 3.9, which is the dielectric constant of silicon oxide.

[0079] The contact isolation structure CSS is disposed in the first upper interlayer insulating film 190 . The contact isolation structure CSS does not extend to the field insulating film 105 . The contact isolation structures CSS do not separate the source / drain etch stop layers 185 . A portion of the first upper interlayer insulating film 190 is disposed between the contact isolation structure CSS and the field insulating film 105 . The width of the contact isolation structure CSS in the second direction D2 increases with increasing distance from the field insulating film 105. The contact isolation structures CSS are disposed on both sides of the first to fourth source / drain patterns (150, 250, 350, 450). In other words, the first to fourth source / drain patterns (150, 250, 350, 450) are respectively disposed between the contact isolation structures CSS adjacent to each other in the second direction D2.

[0080] The contact isolation structure CSS comprises an insulating material. The contact isolation structure CSS may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the contact isolation structure CSS is shown as being a single film, this is for convenience of explanation and is not intended to be limiting.

[0081] A first source / drain contact 170 is disposed on the first source / drain pattern 150 . The first source / drain contact 170 is electrically connected to the first source / drain pattern 150 . The first source / drain contacts 170 are disposed on the first upper interlayer insulating film 190 . A second source / drain contact 270 is disposed on the second source / drain pattern 250 . The second source / drain contact 270 is electrically connected to the second source / drain pattern 250 . The second source / drain contacts 270 are disposed on the first upper interlayer insulating film 190 .

[0082] A third source / drain contact 370 is disposed on the third source / drain pattern 350 . The third source / drain contact 370 is electrically connected to the third source / drain pattern 350 . The third source / drain contact 370 is disposed on the first upper interlayer insulating film 190 . A fourth source / drain contact 470 is disposed on the fourth source / drain pattern 450 . The fourth source / drain contact 470 is electrically connected to the fourth source / drain pattern 450 . The first to third source / drain contacts (170, 270, 370) are disposed between the contact isolation structures CSS. The first to third source / drain contacts (170, 270, 370) are in contact with the contact isolation structure CSS. Although not shown, the fourth source / drain contact 470 contacts the contact isolation structure CSS.

[0083] The height from the upper surface of the field insulating film 105 to the lower surface of the first source / drain pattern 150 is the same as the height from the upper surface of the field insulating film 105 to the lower surface of the second source / drain pattern 250 . The height from the upper surface of the field insulating film 105 to the lower surface of the first source / drain pattern 150 is the same as the height from the upper surface of the field insulating film 105 to the lower surface of the third source / drain pattern 350 . In a cross-sectional view such as FIG. 2, the lower surface of the fourth source / drain contact 470 connected to the upper surface of the fourth source / drain pattern 450 having an inclined surface has an inclined surface.

[0084] The first contact silicide layer 155 is disposed between the first source / drain contact 170 and the first source / drain pattern 150 . The second contact silicide layer 255 is disposed between the second source / drain contact 270 and the second source / drain pattern 250 . The third contact silicide film 355 is disposed between the third source / drain contact 370 and the third source / drain pattern 350 . The fourth contact silicide layer 455 is disposed between the fourth source / drain contact 470 and the fourth source / drain pattern 450 .

[0085] Although the first to fourth source / drain contacts (170, 270, 370, 470) are shown to have a single conductive film structure, the present invention is not limited to this. Unlike the figures, the first to fourth source / drain contacts (170, 270, 370, 470) may have a multi-conductive film structure including a barrier film and a plug film. The first through fourth source / drain contacts (170, 270, 370, 470) may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The first to fourth contact silicide films (155, 255, 355, 455) may include a metal silicide material. The 2D material may include a 2D allotrope or compound, such as, but not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. That is, the above-mentioned two-dimensional materials are merely listed as examples, and the two-dimensional materials that can be included in the semiconductor device of the present invention are not limited to the above-mentioned materials.

[0086] The second upper interlayer insulating film 191 is disposed on the first to third gate capping patterns (145, 245, 345) and the first to fourth source / drain contacts (170, 270, 370, 470). The second upper interlayer insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low-k material may have a value less than 3.9, which is the dielectric constant of silicon oxide.

[0087] The first gate contact 175 is disposed within the second upper interlayer insulating film 191 and the first gate capping pattern 145 . The first gate contact 175 penetrates the second upper interlayer insulating film 191 and the first gate capping pattern 145 . The first gate contact 175 is connected to the first gate electrode 120 . The second gate contact 275 is disposed within the second upper interlayer insulating film 191 and the second gate capping pattern 245 . The second gate contact 275 penetrates the second upper interlayer insulating film 191 and the second gate capping pattern 245 . The second gate contact 275 is connected to the second gate electrode 220 . The third gate contact 375 is disposed within the second upper interlayer insulating film 191 and the third gate capping pattern 345 . The third gate contact 375 penetrates the second upper interlayer insulating film 191 and the third gate capping pattern 345 . The third gate contact 375 is connected to the third gate electrode 320 .

[0088] A height H14 from the upper surface (BP1_US) of the first lower pattern to the bottom surface of the first gate contact 175 is the same as a height H24 from the upper surface (BP1_US) of the first lower pattern to the bottom surface of the second gate contact 275. A height H14 from the upper surface (BP1_US) of the first lower pattern to the bottom surface of the first gate contact 175 is the same as a height H34 from the upper surface (BP1_US) of the first lower pattern to the bottom surface of the third gate contact 375. For example, the second gate contact 275 is connected to the second portion 220R2 of the second gate electrode. The second gate contact 275 contacts the top surface 220US of the second portion 220R2 of the second gate electrode. The third gate contact 375 is connected to the second portion 320R2 of the third gate electrode. The third gate contact 375 contacts the top surface 320US of the second portion 320R2 of the third gate electrode.

[0089] Although the first gate contact 175 is shown to be connected to the second portion 120R2 of the first gate electrode, the present invention is not limited to this. Of course, the first gate contact 175 may be connected to the first portion 120R1 of the first gate electrode. Although the first to third gate contacts (175, 275, 375) are shown to have a single conductive film structure, the present invention is not limited to this. Unlike the figures, the first to third gate contacts (175, 275, 375) may have a multi-layer conductive film structure including a barrier film and a plug film. The first, second, and third gate contacts (175, 275, 375) may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0090] The source / drain vias 195 are disposed in the second upper interlayer insulating film 191 . The source / drain vias 195 are disposed on the first to third source / drain contacts (170, 270, 370). The source / drain via 195 is connected to the first to third source / drain contacts (170, 270, 370). Although not shown, the source / drain via 195 is connected to a fourth source / drain contact 470 . Although the source / drain via 195 is shown having a single conductive film structure, it is not limited thereto. Unlike the figure, the source / drain via 195 may have a multi-layer conductive film structure including a barrier film and a plug film. The source / drain vias 195 can include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0091] 8 to 11 are diagrams illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. For convenience of explanation, the following will mainly explain the points that are different from the contents explained using FIGS. For reference, FIGS. 8 to 10 are cross-sectional views taken along line AA in FIG. 1, and FIG. 11 is a cross-sectional view taken along lines BB, CC, and DD in FIG. 8, in a semiconductor device according to another embodiment of the present invention, the second outer gate structure (GS2_O) does not contact the second source / drain pattern 250 and / or the fourth source / drain pattern 450. In the semiconductor device according to the embodiment of the present invention, as shown in FIG.

[0092] The third outer gate structure (GS3_O) does not contact the third source / drain pattern 350 and / or the fourth source / drain pattern 450. When viewed in cross section, the second gate spacer 240 does not rest on the second outer gate structure (GS2_O). The second outer gate structure (GS2_O) does not indent between the second gate spacer 240 and the second channel pattern CH2. The third gate spacer 340 does not rest on the third outer gate structure (GS3_O). A portion of the third outer gate structure (GS3_O) does not indent between the third gate spacer 340 and the third channel pattern CH3.

[0093] Referring to FIG. 9, a semiconductor device according to another embodiment of the present invention further includes a first inner spacer 140IN, a second inner spacer 240IN, and a third inner spacer 340IN. The first inner spacer 140IN is disposed between the first inner gate structure GS1_I and the first source / drain pattern 150. The first inner spacer 140IN is disposed between the first inner gate structure GS1_I and the fourth source / drain pattern 450. When viewed in cross section, the first inner spacer 140IN is not disposed on the upper surface (CH1_US) of the first channel pattern. The first inner spacer 140IN contacts the first inner gate structure GS1_I, the first source / drain pattern 150, and the fourth source / drain pattern 450.

[0094] The second inner spacer 240IN is disposed between the second inner gate structure GS2_I and the second source / drain pattern 250. The second inner spacer 240IN is disposed between the second inner gate structure GS2_I and the fourth source / drain pattern 450. The second inner spacer 240IN contacts the second inner gate structure (GS2_I), the second source / drain pattern 250, and the fourth source / drain pattern 450. The second inner spacer 240IN is disposed between the second outer gate structure GS2_O and the second source / drain pattern 250. The second inner spacer 240IN is disposed between the second outer gate structure GS2_O and the fourth source / drain pattern 450. When viewed in cross section, the second inner spacer 240IN is disposed on the upper surface (CH2_US) of the second channel pattern.

[0095] The third inner spacer 340IN is disposed between the third inner gate structure GS3_I and the third source / drain pattern 350. The third inner spacer 340IN is disposed between the third inner gate structure GS3_I and the fourth source / drain pattern 450. The third inner spacer 340IN contacts the third inner gate structure GS3_I, the third source / drain pattern 350, and the fourth source / drain pattern 450. The third inner spacer 340IN is disposed between the third outer gate structure GS3_O and the third source / drain pattern 350. The third inner spacer 340IN is disposed between the third outer gate structure GS3_O and the fourth source / drain pattern 450. When viewed in cross section, the third inner spacer 340IN is disposed on the upper surface (CH2_US) of the second channel pattern. The first inner spacer 140IN, the second inner spacer 240IN, and the third inner spacer 340IN each include an insulating material.

[0096] Referring to FIG. 10, a semiconductor device according to another embodiment of the present invention further includes a rear source / drain contact 470_BC and a rear wiring line 50. The first lower pattern BP1 is disposed on an insulating substrate 290. The insulating substrate 290 is disposed on the lower surface of the first lower pattern BP1. The bottom surface of the first lower pattern BP1 is opposite to the top surface (BP1_US) of the first lower pattern in the third direction D3. The insulating substrate 290 comprises an insulating material and may include at least one of silicon oxide, silicon nitride, and combinations thereof. The insulating substrate 290 may be a substrate formed, such as by a deposition process, after the substrate 100 of FIGS. 2-4 is removed during the manufacturing process.

[0097] The rear wiring line 50 is disposed within the insulating substrate 290 . The rear wiring line 50 includes a line portion and a via portion. Although the line portion of the rear wiring line 50 is illustrated as extending in the first direction D1, this is for convenience of explanation and is not intended to be limiting. The via portion of the rear wiring line 50 protrudes from the line portion of the rear wiring line 50 in the third direction D3. Unlike the illustration, the rear wiring line 50 does not have to include a via portion. The rear source / drain contact 470_BC is disposed between the fourth source / drain pattern 450 and the rear wiring line 50 . The rear source / drain contact (470_BC) electrically connects the fourth source / drain contact 470 and the rear wiring line 50. Although the rear source / drain contact 470_BC is shown connected to a portion of the fourth source / drain pattern 450 for convenience of explanation, the present invention is not limited thereto. Although the rear wiring line 50 is shown connected to the fourth source / drain pattern 450, the present invention is not limited thereto. The rear wiring line 50 is connected to at least one of the first to third source / drain patterns (150, 250, 350).

[0098] A rear contact silicide layer (455_BC) is disposed between the rear source / drain contact (470_BC) and the fourth source / drain pattern 450. The rear contact silicide film (455_BC) includes a metal silicide material. Although the rear source / drain contacts 470_BC and the rear wiring lines 50 are each shown as being made of a single conductive film, the present invention is not limited thereto. Unlike the figure, at least one of the rear source / drain contacts 470_BC and the rear wiring line 50 may have a multi-layer conductive film structure including a barrier film and a filling film. The rear contact silicide film (455_BC) and the rear wiring line 50 may each include at least one of, for example, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0099] Referring to FIG. 11, in a semiconductor device according to another embodiment of the present invention, the first to third gate insulating films 130, 230, and 330 each extend in a third direction D3 along a sidewall of a gate isolation structure GCS. Taking the first gate insulating layer 130 as an example, the first gate insulating layer 130 extends from the upper surface of the field insulating layer 105 to the bottom surface 145BS of the first gate capping pattern. The first gate insulating layer 130 contacts the first gate capping pattern 145 . When viewed in cross section, the first to third gate electrodes (120, 220, 320) do not contact the sidewalls of the gate isolation structure GCS.

[0100] 12 to 14 are diagrams illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. For reference, FIG. 12 is an illustrative plan view for explaining a semiconductor device according to another embodiment of the present invention, FIG. 13 is a cross-sectional view taken along lines HH and JJ in FIG. 12, and FIG. 14 is a cross-sectional view taken along lines KK and LL in FIG. 12. The following description of the lower pattern, channel pattern, gate structure, gate capping pattern, gate contact, etc. is similar to that described with reference to FIGS. 1 to 11, so the description thereof will be simplified or omitted.

[0101] 12 to 14, a semiconductor device according to another embodiment of the present invention includes a second lower pattern BP2, a third lower pattern BP3, a fifth channel pattern CH5, a sixth channel pattern CH6, a fifth gate structure GS5, a sixth gate structure GS6, a fifth gate capping pattern 545, a sixth gate capping pattern 645, a fifth source / drain pattern 550, a sixth source / drain pattern 650, a fifth gate contact 575, and a sixth gate contact 675.

[0102] The substrate 100 includes a first region I and a second region II. The first region I and the second region II may each be one of a logic region, an SRAM region, and an I / O region. As an example, the first region I and the second region II may be regions performing the same function. As another example, the first region I and the second region II may be regions that perform different functions from each other. As an example, the first region I and the second region II may be regions in which transistors of the same conductivity type are formed. As another example, the first region I and the second region II may be regions in which transistors of different conductivity types are formed.

[0103] The second lower pattern BP2 and the third lower pattern BP3 each protrude from the substrate 100 in a third direction D3. The second lower pattern BP2 and the third lower pattern BP3 each extend in a first direction D1. The field insulating film 105 covers or overlaps at least a portion of the sidewall of the second lower pattern BP2. The field insulating film 105 covers or overlaps at least a portion of the sidewall of the third lower pattern BP3. The fifth channel pattern CH5 is disposed on the second lower pattern BP2. The fifth channel pattern CH5 is disposed on the upper surface (BP2_US) of the second lower pattern. The sixth channel pattern CH6 is disposed on the third lower pattern BP3. The sixth channel pattern CH6 is disposed on the upper surface (BP3_US) of the third lower pattern.

[0104] The fifth channel pattern CH5 includes a plurality of fifth sheet patterns NS5. The fifth sheet patterns NS5 are disposed on the upper surface (BP2_US) of the second lower pattern at a distance from each other in the third direction D3. The sixth channel pattern CH6 includes a plurality of sixth sheet patterns NS6. The sixth sheet patterns NS6 are disposed on the upper surface (BP3_US) of the third lower pattern at a distance from each other in the third direction D3. In some embodiments of the semiconductor device, the number of the fifth sheet patterns NS5 is different from the number of the sixth sheet patterns NS6. For example, the number of fifth sheet patterns NS5 included in the fifth channel pattern CH5 is greater than the number of sixth sheet patterns NS6 included in the sixth channel pattern CH6.

[0105] The upper surface (CH5_US) of the fifth channel pattern is the upper surface of the fifth sheet pattern NS5 located at the top of the fifth sheet pattern NS5 included in the fifth channel pattern CH5. The upper surface (CH6_US) of the sixth channel pattern is the upper surface of the sixth sheet pattern NS6 located at the top of the sixth sheet pattern NS6 included in the sixth channel pattern CH6. The height from the top surface (BP2_US) of the second lower pattern to the top surface (CH5_US) of the fifth channel pattern is greater than the height from the top surface (BP3_US) of the third lower pattern to the top surface (CH6_US) of the sixth channel pattern.

[0106] The fifth gate structure GS5 is disposed on the second lower pattern BP2. The fifth gate structure GS5 intersects with the second lower pattern BP2. The sixth gate structure GS6 is disposed on the third lower pattern BP3. The sixth gate structure GS6 intersects with the third lower pattern BP3. The fifth gate structure GS5 surrounds the fifth channel pattern CH5. A fifth gate structure GS5 surrounds each of the fifth sheet patterns NS5.

[0107] The fifth gate structure GS5 includes a fifth inner gate structure (GS5_I) and a fifth outer gate structure (GS5_O). The fifth gate structure GS5 includes a fifth gate electrode 520 and a fifth gate insulating film 530. The sixth gate structure GS6 surrounds the sixth channel pattern CH6. A sixth gate structure GS6 surrounds each of the sixth sheet patterns NS6. The sixth gate structure GS6 includes a sixth inner gate structure (GS6_I) and a sixth outer gate structure (GS6_O). The sixth gate structure GS6 includes a sixth gate electrode 620 and a sixth gate insulating film 630.

[0108] The fifth gate electrode 520 includes a first portion and a second portion. The second portion of the fifth gate electrode 520 is located on both sides of the first portion of the fifth gate electrode 520 . In a cross-sectional view such as FIG. 14, the upper surface 520US of the fifth gate electrode is flat. A first portion of the fifth gate electrode 520 overlaps the fifth channel pattern CH5 in the third direction D3. The second portion of the fifth gate electrode 520 does not overlap the fifth channel pattern CH5 in the third direction D3. The sixth gate electrode 620 includes a first portion and a second portion. The second portions of the sixth gate electrode 620 are located on both sides of the first portion of the sixth gate electrode 620 . In a cross-sectional view such as FIG. 14, the upper surface 620US of the sixth gate electrode includes a region recessed toward the sixth channel pattern CH6. The first portion of the sixth gate electrode 620 is a region in which a portion of the sixth gate electrode 620 is recessed. A first portion of the sixth gate electrode 620 overlaps with the sixth channel pattern CH6 in the third direction D3. The second portion of the sixth gate electrode 620 does not overlap the sixth channel pattern CH6 in the third direction D3.

[0109] For example, a height H51 from the upper surface (BP2_US) of the second lower pattern to an upper surface 520US of the first portion of the fifth gate electrode 520 is greater than a height H61 from the upper surface (BP3_US) of the third lower pattern to an upper surface 620US of the first portion of the sixth gate electrode 620. A height H53 from the upper surface (BP2_US) of the second lower pattern to an upper surface 520US of the second portion of the fifth gate electrode 520 is the same as a height H63 from the upper surface (BP3_US) of the third lower pattern to an upper surface 620US of the second portion of the sixth gate electrode 620. Unlike the figures, the shape of the fifth gate electrode 520 may be similar to the shape of the second gate electrode 220 in FIGS. 2 and 3, and the shape of the sixth gate electrode 620 may be similar to the shape of the third gate electrode 320 in FIGS. In such a case, the description of the cross sections of the second gate electrode 220 and the third gate electrode 320 described with reference to FIG. 3 can be applied to the description of the cross sections of the fifth gate electrode 520 and the sixth gate electrode 620.

[0110] A fifth gate spacer 540 is disposed on the sidewall of the fifth gate structure GS5. A sixth gate spacer 640 is disposed on the sidewall of the sixth gate structure GS6. For example, in a cross-sectional view such as FIG. 13, the fifth outer gate structure (GS5_O) does not indent between the fifth gate spacer 540 and the fifth channel pattern CH5. A portion of the sixth outer gate structure (GS6_O) is recessed between the sixth gate spacer 640 and the sixth channel pattern CH6. Contrary to the figure, if the shape of the fifth gate structure GS5 is similar to the shapes of the second gate structure GS2 and the third gate structure GS3 in FIG. 2, the fifth gate spacer 540 may be shaped to rest on the fifth outer gate structure (GS5_O).

[0111] The fifth gate capping pattern 545 is disposed on an upper surface 520US of the fifth gate electrode. A lower surface 545BS of the fifth gate capping pattern contacts an upper surface 520US of the fifth gate electrode. The sixth gate capping pattern 645 is disposed on an upper surface 620US of the sixth gate electrode. A lower surface 645BS of the sixth gate capping pattern contacts an upper surface 620US of the sixth gate electrode. An upper surface 545US of the fifth gate capping pattern is flush with an upper surface 645US of the sixth gate capping pattern. A height H52 from the upper surface (BP2_US) of the second lower pattern to the upper surface (545US) of the fifth gate capping pattern is the same as a height H62 from the upper surface (BP3_US) of the third lower pattern to the upper surface (645US) of the sixth gate capping pattern. The fifth gate capping pattern 545 has a thickness t 5 different from a thickness t 6 of the sixth gate capping pattern 645 . The thickness t 5 of the fifth gate capping pattern 545 is smaller than the thickness t 6 of the sixth gate capping pattern 645 .

[0112] The fifth gate structure GS5 and / or the sixth gate structure GS6 are disposed between adjacent gate isolation structures GCS in the second direction D2. The fifth source / drain pattern 550 is disposed on the second lower pattern BP2. The fifth source / drain patterns 550 are disposed on both sides of the fifth gate structure GS5. The fifth source / drain pattern 550 is connected to the fifth channel pattern CH5. The sixth source / drain pattern 650 is disposed on the third lower pattern BP3. The sixth source / drain patterns 650 are disposed on both sides of the sixth gate structure GS6. The sixth source / drain pattern 650 is connected to the sixth channel pattern CH6.

[0113] The fifth inner gate structure (GS5_I) contacts the fifth source / drain pattern 550. The fifth outer gate structure (GS5_O) does not contact the fifth source / drain pattern 550. The sixth inner gate structure (GS6_I) contacts the sixth source / drain pattern 650. The sixth outer gate structure (GS6_O) contacts the sixth source / drain pattern 650. The fifth and sixth source / drain patterns (550, 650) each include an epitaxial pattern. The fifth and sixth source / drain patterns (550, 650) each include a semiconductor material. The fifth and sixth source / drain patterns (550, 650) are respectively disposed between adjacent contact isolation structures CSS in the second direction D2.

[0114] A fifth source / drain contact 570 is disposed on the fifth source / drain pattern 550 . The fifth source / drain contact 570 is electrically connected to the fifth source / drain pattern 550 . A sixth source / drain contact 670 is disposed on the sixth source / drain pattern 650 . The sixth source / drain contact 670 is electrically connected to the sixth source / drain pattern 650 . The fifth contact silicide film 555 is disposed between the fifth source / drain contact 570 and the fifth source / drain pattern 550 . The sixth contact silicide film 655 is disposed between the sixth source / drain contact 670 and the sixth source / drain pattern 650 .

[0115] The fifth gate contact 575 penetrates the second upper interlayer insulating film 191 and the fifth gate capping pattern 545 . The fifth gate contact 575 is connected to the fifth gate electrode 520 . The sixth gate contact 675 penetrates the second upper interlayer insulating film 191 and the sixth gate capping pattern 645 . The sixth gate contact 675 is connected to the sixth gate electrode 620 . A height H54 from the upper surface (BP2_US) of the second lower pattern to the bottom surface of the fifth gate contact 575 is the same as a height H64 from the upper surface (BP3_US) of the third lower pattern to the bottom surface of the sixth gate contact 675. For example, the sixth gate contact 675 is connected to a second portion of the sixth gate electrode 620 . The source / drain via 195 is disposed over the fifth and sixth source / drain contacts (570, 670). The source / drain via 195 is connected to the fifth and sixth source / drain contacts (570, 670).

[0116] 15 and 16 are diagrams illustrating a schematic configuration of a semiconductor device according to another embodiment of the present invention. For the sake of convenience, the following description will focus on the points that are different from those described using FIGS. 15 and 16, in a semiconductor device according to another embodiment of the present invention, the number of fifth sheet patterns NS5 included in the fifth channel pattern CH5 is the same as the number of sixth sheet patterns NS6 included in the sixth channel pattern CH6. The height from the top surface (BP2_US) of the second lower pattern to the top surface (CH5_US) of the fifth channel pattern is the same as the height from the top surface (BP3_US) of the third lower pattern to the top surface (CH6_US) of the sixth channel pattern.

[0117] In FIG. 15, the height from the upper surface (CH5_US) of the fifth channel pattern to the upper surface 520US of the fifth gate electrode is greater than the height from the upper surface (CH6_US) of the sixth channel pattern to the upper surface 620US of the sixth gate electrode. The fifth outer gate structure (GS5_O) is recessed between the fifth gate spacer 540 and the fifth channel pattern CH5. The fifth gate spacer 540 is shaped to rest on the fifth outer gate structure (GS5_O).

[0118] 17 to 34 are cross-sectional views illustrating intermediate stages in a method for manufacturing a semiconductor device according to an embodiment of the present invention. 17 and 18, a mold fin-like pattern FMS is formed on a substrate 100. The mold fin-like pattern FMS extends in a first direction D1. The mold fin-like pattern FMS includes a first lower pattern BP1 and an upper pattern structure UP1.

[0119] An upper pattern structure UP1 is formed on the first lower pattern BP1. The upper pattern structure UP1 includes a plurality of sacrificial patterns (SC_L) and a plurality of active patterns (ACT_L) that are alternately stacked. For example, the active pattern (ACT_L) includes a silicon film. The sacrificial pattern (SC_L) includes a silicon-germanium film. In the upper pattern structure UP1, the active pattern (ACT_L) is disposed on the top.

[0120] A mold hard mask pattern (F_HM) is placed on the mold fin-shaped pattern FMS. The mold hard mask pattern (F_HM) is used as a mask for forming the mold fin-like pattern FMS. For example, the mold hard mask pattern (F_HM) may include, but is not limited to, silicon nitride.

[0121] Next, a pre-field insulating film 105P is formed on the substrate 100. The pre-field insulating film 105P covers or overlaps the sidewalls of the mold fin-shaped pattern FMS and the sidewalls of the mold hard mask pattern (F_HM). The pre-field insulating film 105P does not cover or overlap the upper surface of the mold hard mask pattern (F_HM).

[0122] 19 and 20, a pattern mask PT_M is formed on the pre-field insulating film 105P and the mold hard mask pattern F_HM. The patterned mask (PT_M) includes a first opening that exposes a portion of the mold hard mask pattern (F_HM). A first etching step is performed using a pattern mask (PT_M) including a first opening. During the first etching process, the mold hard mask pattern (F_HM) overlapping the first opening is removed.

[0123] During the first etching process, at least one active pattern ACT_L is removed from a portion overlapping the first opening. For example, the first etching process removes a part of one active pattern (ACT_L). For example, the first etching step ends when the topmost sacrificial pattern (SC_L) is exposed. A first etching step forms a first etching trench.

[0124] 19 to 22, the first etching trenches formed during the first etching process are filled with a pattern mask (PT_M). Next, a second opening is formed in the pattern mask (PT_M) to expose another portion of the mold hard mask pattern (F_HM). A second etching step is performed using a pattern mask (PT_M) that includes a second opening. During the second etching process, the mold hard mask pattern (F_HM) overlapping the second opening is removed.

[0125] During the second etching process, at least one active pattern ACT_L is removed from a portion overlapping with the second opening. For example, the second etching process removes a portion of the two active patterns (ACT_L). For example, during the second etching process, a portion of the uppermost disposed sacrificial pattern (SC_L) is also removed. The second etching step is completed when the sacrificial pattern (SC_L) located directly underneath the top is exposed. By the first etching step and the second etching step, a plurality of steps having a staircase shape are formed in the mold fin-like pattern FMS.

[0126] With reference to FIGS. 21 to 24, the pattern mask (PT_M) is removed. Next, the mold hard mask pattern (F_HM) is removed. A part of the pre-field insulating film 105P is removed, and a field insulating film 105 is formed on the substrate 100. The field insulating film 105 covers the sidewalls of the first lower pattern BP1. Next, a plurality of dummy gate electrodes 120D are formed on the mold fin-like pattern FMS. The multiple dummy gate electrodes 120D are not formed in the step portions of the mold fin-like pattern FMS. In some embodiments, the dummy gate electrode 120D does not overlap the step portion of the mold fin-like pattern FMS in the third direction D3. Each dummy gate electrode 120D intersects with a mold fin-like pattern FMS. Each of the dummy gate electrodes 120D extends in a second direction D2. The dummy gate electrodes 120D are spaced apart from each other in the first direction D1.

[0127] A dummy gate insulating film 130D is formed between the dummy gate electrode 120D and the mold fin-like pattern FMS. The dummy gate insulating film 130D is formed along the profile of the mold fin-like pattern FMS. A dummy gate capping film 120HM is formed on the dummy gate electrode 120D. Using the dummy gate capping film 120HM as a mask, a dummy gate electrode 120D is formed. The dummy gate electrode 120D includes, but is not limited to, polysilicon, for example. The dummy gate insulating film 130D includes, but is not limited to, silicon oxide. The dummy gate capping film 120HM includes, but is not limited to, silicon nitride, for example.

[0128] 23 to 26, a dummy gate spacer 140D is formed on the sidewall of the dummy gate electrode 120D. During the formation of the dummy gate spacers 140D, source / drain recesses are formed in the mold fin-like pattern FMS. The source / drain recess is formed between the dummy gate electrodes 120D adjacent to each other in the first direction D1.

[0129] First to fourth source / drain patterns (150, 250, 350, 450) are formed in the mold fin-like pattern FMS. The first to fourth source / drain patterns (150, 250, 350, 450) fill the source / drain recesses. The first to fourth source / drain patterns (150, 250, 350, 450) are formed on the first lower pattern BP1. The first to fourth source / drain patterns (150, 250, 350, 450) are formed between the dummy gate electrodes 120D adjacent to each other in the first direction D1. The fourth source / drain pattern 450 formed in the step portion of the mold fin-like pattern FMS has an inclined upper surface.

[0130] Next, a source / drain etch stop film 185 is formed on the first to fourth source / drain patterns (150, 250, 350, 450). The source / drain etch stop film 185 is formed along the profiles of the first to fourth source / drain patterns (150, 250, 350, 450).

[0131] 25 to 28, a first upper interlayer insulating film 190 is formed on the source / drain etch stop film 185. As shown in FIG. A portion of the first upper interlayer insulating film 190 and the dummy gate capping film 120HM are removed to expose the upper surface of the dummy gate electrode 120D. While exposing the upper surface of the dummy gate electrode 120D, the first pre-gate spacer 140P is formed. Next, the dummy gate insulating film 130D and the dummy gate electrode 120D are removed to expose the upper pattern structure UP1 between the first pre-gate spacers 140P.

[0132] Next, the sacrificial pattern (SC_L) is removed to form a first channel pattern CH1 including a first sheet pattern NS1, a second channel pattern CH2 including a second sheet pattern NS2, and a third channel pattern CH3 including a third sheet pattern NS3. As a result, a gate trench is formed between the first pre-gate spacers 140P. Next, a first pre-gate insulating film 130P and a first pre-gate electrode 120P are formed in the gate trench. The first pre-gate insulating film 130P and the first pre-gate electrode 120P surround the first sheet pattern NS1, the second sheet pattern NS2, and the third sheet pattern NS3 in the cross section in the first direction D1 and the third direction D3.

[0133] 27 to 30, a part of the first pre-gate insulating film 130P and a part of the first pre-gate electrode 120P are removed to form a first gate structure GS1 surrounding the first sheet pattern NS1. During the formation of the first gate structure GS1, a portion of the first pre-gate spacer 140P is etched. This forms a first gate spacer 140 on the sidewall of the first gate structure GS1. A part of the first pre-gate insulating film 130P and a part of the first pre-gate electrode 120P are removed to form a second pre-gate insulating film 130P1 and a second pre-gate electrode 120P1 surrounding the second sheet pattern NS2 and the third sheet pattern NS3. A portion of the first pre-gate spacer 140P is etched to form a second pre-gate spacer 140P1 on the sidewall of the second pre-gate electrode 120P1.

[0134] 29 to 32, a gate recess mask (RC_M) is formed on the first gate structure GS1, the second pre-gate insulating film 130P1, and the second pre-gate electrode 120P1. The gate recess mask (RC_M) includes a first recess opening. The first recess opening overlaps the second channel pattern CH2 in the third direction D3. A first gate recess step is performed using a gate recess mask (RC_M) that includes a first recess opening. During the first gate recess process, a portion of the second pre-gate insulating film 130P1 and a portion of the second pre-gate electrode 120P1 are etched. As a result, a second gate structure GS2 surrounding the second sheet pattern NS2 is formed. During the formation of the second gate structure GS2, a portion of the second pre-gate spacer 140P1 is etched. This forms second gate spacers 240 on the sidewalls of the second gate structure GS2.

[0135] 31-34, after forming the second gate structure GS2, the gate recess mask (RC_M) partially or entirely fills the space above the second gate structure GS2 using additional recess mask material. Next, a gate recess mask (RC_M) including a second recess opening is formed. The second recess opening overlaps the third channel pattern CH3 in the third direction D3. A second gate recess step is performed using a gate recess mask (RC_M) that includes a second recess opening. During the second gate recess process, a portion of the second pre-gate insulating film 130P1 and a portion of the second pre-gate electrode 120P1 are etched. As a result, a third gate structure GS3 surrounding the third sheet pattern NS3 is formed.

[0136] While the third gate structure GS3 is being formed, a portion of the second pre-gate spacer 140P1 is etched. This forms a third gate spacer 340 on the sidewall of the third gate structure GS3. Next, the gate recess mask (RC_M) including the second recess opening is removed. Next, referring to FIGS. 2 and 3, first, second, and third gate capping patterns (145, 245, 345) are formed on the first, second, and third gate structures (GS1, GS2, GS3).

[0137] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0138] 100 Substrates 105 Field Insulation Film 120, 220, 320 (first to third) gate electrodes 130, 230, 330 (first to third) gate insulating films 140, 240, 340 (1st to 3rd) Gate spacers 145, 245, 345 (1st to 3rd) Gate capping pattern 150, 250, 350, 450 (1st to 4th) source / drain patterns 155, 255, 355, 455 (1st to 4th) Contact silicide film 170, 270, 370, 470 (1st to 4th) source / drain contacts 185 Source / Drain Etching Stop Film 190 First upper interlayer insulating film 191 Second upper interlayer insulating film 195 Source / Drain Via BP1~BP3 (1st~3rd) Lower Pattern CH1~CH3 (1st~3rd) channel pattern CSS Contact Isolation Structure GCS Gate isolation structure GS1~GS3 (1st~3rd) gate structure GS1_I~GS3_I (1st~3rd) Inner Gate Structure GS1_O~GS3_O (1st~3rd) Outer Gate Structure NS1~NS3 (1st~3rd) sheet patterns UP1 Upper pattern structure

Claims

1. a lower pattern extending in a first direction; a first channel pattern including a plurality of first sheet patterns disposed on the lower pattern and spaced apart in a second direction different from the first direction; a second sheet pattern disposed on the lower pattern and spaced apart from the first channel pattern in the second direction; a first gate structure surrounding the first sheet pattern and including a first gate electrode and a first gate insulating film; a second gate structure surrounding the second sheet pattern and including a second gate electrode and a second gate insulating film; a first gate capping pattern on the first gate structure; a second gate capping pattern on the second gate structure; the number of the first sheet patterns is different from the number of the second sheet patterns; a thickness of the first gate capping pattern in the second direction is different from a thickness of the second gate capping pattern in the second direction.

2. the number of the first sheet patterns is greater than the number of the second sheet patterns; The semiconductor device of claim 1 , wherein the first gate capping pattern has a thickness smaller than a thickness of the second gate capping pattern.

3. 2. The semiconductor device of claim 1, wherein a thickness of the first gate capping pattern in a portion overlapping the first channel pattern in the second direction is different from a thickness of the second gate capping pattern in a portion overlapping the second channel pattern in the second direction.

4. a source / drain pattern disposed on the lower pattern and electrically connected to the first channel pattern and the second channel pattern; 2. The semiconductor device according to claim 1, wherein the source / drain pattern contacts each of the first sheet patterns and each of the second sheet patterns.

5. the first gate structure includes a first outer gate structure disposed on an upper surface of the first channel pattern; the second gate structure includes a second outer gate structure disposed on an upper surface of the second channel pattern; the first gate insulating film of the first outer gate structure is spaced apart from the source / drain pattern; 5. The semiconductor device of claim 4, wherein the second gate insulating film of the second outer gate structure contacts the source / drain pattern.

6. a lower pattern extending in a first direction; a first channel pattern including a plurality of first sheet patterns disposed on the lower pattern and spaced apart in a second direction different from the first direction; a second sheet pattern disposed on the lower pattern and spaced apart from the first channel pattern in the second direction; a first gate electrode surrounding the first sheet pattern; a second gate electrode surrounding the second sheet pattern; a first gate capping pattern on the first gate electrode; a second gate capping pattern on the second gate electrode; a first gate contact extending into the first gate capping pattern and electrically connected to the first gate electrode; a second gate contact extending into the second gate capping pattern and electrically connected to the second gate electrode; the number of the first sheet patterns is different from the number of the second sheet patterns; the first gate electrode includes a first portion of the first gate electrode overlapping the first channel pattern in the second direction; the second gate electrode includes a first portion of the second gate electrode overlapping the second channel pattern in the second direction; a distance from an upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is different from a distance from the upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode.

7. the number of the first sheet patterns is greater than the number of the second sheet patterns; 7. The semiconductor device of claim 6, wherein a distance from an upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is greater than a distance from an upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode.

8. 7. The semiconductor device of claim 6, wherein a distance from an upper surface of the lower pattern to a bottom surface of the first gate contact is the same as a distance from an upper surface of the lower pattern to a bottom surface of the second gate contact.

9. the first gate electrode includes a second portion of the first gate electrode that is electrically connected to the first portion of the first gate electrode and does not overlap the first channel pattern in the second direction; 7. The semiconductor device of claim 6, wherein a distance from a top surface of the lower pattern to a top surface of the first portion of the first gate electrode is smaller than a distance from a top surface of the lower pattern to a top surface of the second portion of the first gate electrode.

10. The lower pattern and a first channel pattern disposed on the lower pattern and including a plurality of first sheet patterns; a second channel pattern disposed on the lower pattern and including a plurality of second sheet patterns; Here, the number of the second sheet patterns included in the second channel pattern is less than the number of the first sheet patterns included in the first channel pattern, a source / drain pattern disposed on the lower pattern and electrically connected to the first channel pattern and the second channel pattern; In a cross-sectional view, a first gate electrode surrounding the first sheet pattern; In a cross-sectional view, a second gate electrode surrounding the second sheet pattern; a first gate capping pattern on the first gate electrode; a second gate capping pattern on the second gate electrode; 4. A semiconductor device comprising: a first gate electrode and a second gate electrode; a first insulating layer formed on the first insulating layer and a second insulating layer formed on the second gate electrode;

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