Memory controller including row hammer tracking device

Abstract

To efficiently detect a row hammer address.SOLUTION: A memory controller includes: a command / address generation module; and a row-hammer tracking module 150 configured to track a row-hammer address on the basis of an active command received from the command / address generation module, and addresses for a target bank of the active command and a row. The row-hammer tracking module includes: a plurality of storage devices each of which stores a candidate address of the corresponding bank and an access counting value for the candidate address in each field F1 corresponding to the bank; and at least one search controller configured to search for the fields of the plurality of storage devices each of which corresponds to a different bank during one clock on the basis of active commands each of which is subject to a different bank, while sequentially searching for the fields of the plurality of storage devices each of which corresponds to the target bank when receiving the active command.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to semiconductor design technology, and in particular, the present invention relates to a memory controller and a memory system with a Row Hammer tracking device. [Background technology]

[0002] In addition to the normal refresh operation, which sequentially refreshes multiple word lines, the memory device also performs an additional refresh operation (hereinafter referred to as a "target refresh operation") on memory cells of specific word lines that are likely to lose data due to the row hammer phenomenon.

[0003] The row hammer phenomenon refers to a phenomenon in which data in memory cells connected to adjacent word lines is damaged due to a high number of activations of a particular word line. To prevent this row hammer phenomenon, a target refresh operation is performed on adjacent word lines of a word line that is activated a preset number of times or more.

[0004] Meanwhile, in order to detect an attacking word line and select an address to be targeted for refresh (hereinafter, referred to as a "row hammer address") during a target refresh operation, a memory device or a memory controller needs to detect a word line that is activated a preset number of times or more. Recently, various methods have been researched for detecting a row hammer address by tracking a row address input together with an active command. Summary of the Invention [Problem to be solved by the invention]

[0005] The technical problem to be solved by the embodiments of the present invention is to provide a memory controller having a row hammer tracking device capable of efficiently detecting a row hammer address. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a memory controller includes a command / address generation module and a row hammer tracking module that tracks a row hammer address based on an active command received from the command / address generation module and an address for a target bank and row of the active command. The row hammer tracking module includes a plurality of storage devices each having a field corresponding to a bank, each field storing a candidate address of the corresponding bank and an access counting value for the candidate address. When the active command is received, the field of the plurality of storage devices corresponding to the target bank is sequentially searched by a clock, but the field of the plurality of storage devices corresponding to the different banks is searched for one clock based on active commands targeting different banks.

[0007] According to one embodiment of the present invention, the row hammer tracking device includes a spillover counter that stores a miscounting value, a plurality of storage devices each having a field corresponding to a bank, in which a candidate address of a corresponding bank and an access counting value for the candidate address are stored, a plurality of search controllers that are cascaded with each other corresponding to each of the plurality of storage devices, and when a bank address and a row address are input along with an active command, compare the candidate address and access counting value read from the field corresponding to the bank address with the row address and the miscounting value, respectively, to generate an address hit signal, a count hit signal, and field information, and an update controller that updates the access counting value or the miscounting value of a target field designated by the field information in response to the address hit signal and the count hit signal. Effect of the Invention

[0008] In the memory system according to the proposed embodiment, the row hammer tracking device is realized by using a static random access memory (SRAM) as a storage device instead of a content addressable memory (CAM) that is known in the art, thereby minimizing the area occupied by the row hammer tracking device. In addition, the data of the storage device can be read in a pipeline manner to detect the row hammer address in a short time, thereby effectively mitigating the row hammer risk. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 1 is a block diagram of a known memory system. [Figure 1B] FIG. 1 is a block diagram of a known memory system. [Diagram 2] 1 is a block diagram of a memory system according to an embodiment of the present invention; [Diagram 3] FIG. 2 is a detailed configuration diagram of a memory controller according to an embodiment of the present invention. [Figure 4] FIG. 2 is a detailed configuration diagram of a row hammer tracking module according to an embodiment of the present invention. [Diagram 5] FIG. 5 is a detailed configuration diagram of the spillover counter in FIG. 4. [Figure 6] FIG. 2 is a timing diagram for explaining a known first active interval tRC and a known second active interval tRRD. [Figure 7] 2 is a detailed configuration diagram of a storage device group according to the first embodiment of the present invention. FIG. [Figure 8A] 8 is an example for explaining a method for reading the storage device group in FIG. 7; [Figure 8B] 8 is an example for explaining a method for reading the storage device group in FIG. 7; [Figure 8C] 8 is an example for explaining a method for reading the storage device group in FIG. 7; [Figure 9A]8 is yet another example for explaining the method of reading the storage device group of FIG. 7; [Figure 9B] 8 is yet another example for explaining the method of reading the storage device group of FIG. 7; [Figure 9C] 8 is yet another example for explaining the method of reading the storage device group of FIG. 7; [Figure 9D] 8 is yet another example for explaining the method of reading the storage device group of FIG. 7; [Figure 10] FIG. 11 is a detailed configuration diagram of a storage device group according to the second embodiment of the present invention. [Figure 11A] 11 is an example for explaining a method for reading the storage device group of FIG. 10; [Figure 11B] 11 is an example for explaining a method for reading the storage device group of FIG. 10; [Figure 12A] 11 is yet another example for explaining the method of reading the storage device group of FIG. 10; [Figure 12B] 11 is yet another example for explaining the method of reading the storage device group of FIG. 10; [Figure 12C] 11 is yet another example for explaining the method of reading the storage device group of FIG. 10; [Figure 13A] 2 is a block diagram and a flowchart illustrating the operation of any one of the search controllers according to an embodiment of the present invention. FIG. [Figure 13B] 2 is a block diagram and a flowchart illustrating the operation of any one of the search controllers according to an embodiment of the present invention. FIG. [Figure 14] 4 is a flowchart illustrating an operation of an update controller according to an embodiment of the present invention. [Figure 15A] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15B] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15C]1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15D] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15E] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15F] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15G] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15H] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15I] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15J] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15K] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15L] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. [Figure 15M] 1 is an example for explaining a row hammer tracking method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to enable those skilled in the art to easily carry out the technical concept of the present invention.

[0011] In addition, when a part is described as being "connected" to another part throughout the specification, this includes not only the case where the part is "directly connected" to another part, but also the case where the part is "electrically connected" to another part via another circuit in between. In addition, when a part is described as "including" or "comprising" a certain component, this does not mean that the other component is excluded, but means that the part can further include or comprise the other component, unless otherwise specified to the contrary. In addition, even if some components are described in the singular form throughout the specification, it will be understood that the present invention is not limited thereto, and that the component may be composed of a plurality of components.

[0012] 1A and 1B are block diagrams of a known memory system 1.

[0013] As shown in FIGS. 1A and 1B, a memory system 1 may include a memory controller 2 and a memory module 3.

[0014] The memory controller 2 can control the operation of the memory module 3 in response to a request from the host 5. The memory module 3 can include a plurality of memory devices 4. The memory devices 4 can commonly receive commands and addresses from the memory controller 2 and can individually exchange data with the memory controller 2.

[0015] The memory device 4 may include a plurality of memory cells connected between a plurality of word lines (hereinafter referred to as "rows") and a plurality of bit lines (hereinafter referred to as "columns"). The memory controller 2 provides the memory device 4 with a row address for specifying a row of the memory device 4 and a column address for specifying a column, and can select a preset number of memory cells. The rows of the memory devices 4 included in one memory module 3 may be specified by the same row address.

[0016] As shown in FIG. 1A, each memory device 4 may include a counting circuit 4A for counting the number of accesses of a row. The counting circuit 4A of each memory device 4 may have the same configuration and may be realized by a plurality of row counters each corresponding to a row. Each row counter may count the number of row addresses that specify the corresponding row to generate a counting value. The memory controller 2 may select a row address having a maximum value among the counting values ​​provided by the memory device 4 as a row hammer address. The memory controller 2 may provide a refresh command (e.g., a refresh management command) together with the row hammer address to the memory device 4, thereby allowing the memory device 4 to perform a target refresh operation on an adjacent row of the row corresponding to the row hammer address.

[0017] However, when counting circuits 4A are provided in each memory device 4 as in FIG. 1A, the area of ​​the memory device (or module) increases unnecessarily due to the counting circuits performing duplicated counting operations.

[0018] As shown in FIG. 1B, the memory controller 2 may include a counting circuit 2A for counting the number of times a row is active (or the number of times it is accessed, hereinafter referred to as the number of times it is accessed). The counting circuit 2A may be realized by a plurality of row counters each corresponding to a row, and each row counter may count the number of row addresses specifying the corresponding row to generate a counting value. The memory controller 2 may calculate a row hammer address according to the counting value of the counting circuit 2A. The memory controller 2 may provide a refresh command (e.g., a refresh management command) together with the row hammer address to the memory device 4, so that the memory device 4 may perform a target refresh operation on an adjacent row of the row corresponding to the row hammer address.

[0019] When the counting circuit 2A is arranged in the memory controller 2 as in FIG. 1B, the area of ​​the memory device 4 can be reduced. However, the memory controller 2 needs a counting capacity of (number of rows)×(number of bits of each row counter). For example, if 512 rows are arranged and a 16-bit row counter is required to count each row, a counting capacity of 8192 bits is required. This may degrade the performance of the memory controller 2.

[0020] Meanwhile, a method has been proposed in which, without counting the number of accesses to all rows, the candidate addresses and the number of inputs of the candidate addresses are stored in the entries of a content addressable memory (CAM), and then the row hammer address is tracked using the data stored in each entry. However, as the chip area is reduced due to process miniaturization, the minimum number of activations that can cause the row hammer phenomenon (hereinafter referred to as the "row hammer threshold") is also decreasing, and as a result, the number of CAM entries that must be tracked is increasing, making it difficult to actually perform row hammer tracking using a CAM.

[0021] In the following embodiment of the present invention, a method for preventing performance degradation of a memory controller and reducing the risk of row hammer by implementing a row hammer tracking device using a static random access memory (SRAM) instead of a conventional CAM will be described.

[0022] FIG. 2 is a block diagram of a memory system 10 according to an embodiment of the present invention.

[0023] 2, the memory system 10 can store data or read stored data in response to a request REQ provided from the host 20. The memory system 10 can be used as a primary or secondary storage device of the host 20. The memory system 10 can be used as a device that stores data under the control of the host 20, such as a mobile phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0024] The memory system 10 may include a memory controller 100 and at least one memory module 200 .

[0025] The memory controller 100 may generate a command / address signal C / A in response to a request REQ from the host 20 and provide it to the memory module 200 to control the operation of the memory module 200. The memory controller 100 may provide a clock to the memory module 200 along with the command / address signal C / A. For example, the memory controller 100 may provide data DQ to the memory module 200 during a write operation. The memory controller 100 may provide data DQ read from the memory module 200 to the host 20 during a read operation.

[0026] The memory module 200 may operate as a buffer memory, a working memory, or a main memory for the host 20 including the memory controller 100. The memory module 200 may operate in response to a command / address signal C / A issued by the memory controller 100. The memory module 200 may store data DQ transmitted from the memory controller 100 or transmit data DQ to the memory controller 100. Depending on the embodiment, the memory module 200 may further include a module controller or a register clock driver, and a data buffer. Depending on the embodiment, the memory controller 100 may include a configuration corresponding to the module controller or the register clock driver, and a data buffer.

[0027] The memory module 200 may include one or more memory devices 200A. Each of the memory devices 200A may include a plurality of banks BKs. Each of the banks BKs may include a plurality of memory cells coupled between a plurality of rows and a plurality of columns. The memory controller 100 may provide the memory device 200A with a bank address for specifying the bank BKs of the memory device 200A, a row address for specifying the row, and a column address for specifying the column, and may select a preset number of memory cells.

[0028] Each memory device 100 may perform an active operation, a precharge operation, a refresh operation, a read operation, or a write operation on a memory cell according to a command / address signal C / A and / or data DQ provided from the memory controller 100. Each memory device 100 may be referred to as a memory chip. The memory devices 200A included in the same memory module 200 may have different data input / output paths while commonly receiving the command / address signal C / A. According to an embodiment, each memory device 100 may be a dynamic random access memory (DRAM) such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), or the like. According to an embodiment, the memory device 200A may be configured with different types of memories. Hereinafter, it is assumed that the memory device 200A is a DRAM device supporting a double data rate (DDR) interface.

[0029] FIG. 3 is a detailed configuration diagram of the memory controller 100 according to the embodiment of the present invention.

[0030] As shown in FIG. 3, the memory controller 100 may include a data transfer module 110, a command / address generation module 130, and a row hammer tracking module 150.

[0031] The data transfer module 110 can transfer data DQ corresponding to a request REQ from the host 20 to the memory module 200 during a write operation, or transfer data DQ read from the memory module 200 to the host 20 during a read operation.

[0032] The command / address generation module 130 can generate a command / address signal C / A corresponding to a request REQ from the host 20 and provide the command / address signal C / A to the memory module 200 .

[0033] The command / address generation module 130 may provide a bank address BKADD, a row address RADD, and a column address for specifying a bank, row, and column to be read together with a read command for a read operation as a command / address signal C / A, and may provide a bank address BKADD, a row address RADD, and a column address for specifying a bank, row, and column to be written together with a write command for a write operation as a command / address signal C / A. The command / address generation module 130 may provide a preset number of normal refresh commands as the command / address signal C / A during a refresh time ("Refresh Interval", tREF) that is a time for all rows defined in the specification to be normally (sequentially) refreshed.

[0034] The command / address generation module 130 may generate a bank address BKADD and a row address RADD for specifying a bank and row to be activated together with an active command ACT for an active operation, and provide them as a command / address signal C / A. In an embodiment of the present invention, if the active command ACT is generated, the command / address generation module 130 may provide the active command ACT, the bank address BKADD, and the row address RADD to the row hammer tracking module 150. In addition, if the row hammer address RH_ADD is transmitted from the row hammer tracking module 150 together with an alert signal ALERT_S, the command / address generation module 130 may provide the row hammer address RH_ADD for specifying a bank and row to be targeted for refresh together with a refresh management command as a command / address signal C / A based on the row hammer address RH_ADD. In the following embodiment, it will be described that the row hammer address RH_ADD provided from the row hammer tracking module 150 includes all information related to the bank address and the row address.

[0035] The row hammer tracking module 150 may collect information on banks and rows that have been subjected to a row hammer attack in the memory device 200A based on the active command ACT, the bank address BKADD, and the row address RADD. The row hammer tracking module 150 may generate an alert signal ALERT_S and a row hammer address RH_ADD based on the collected information (i.e., the bank address and the row address) and transmit them to the command / address generation module 130. 4 is a detailed block diagram of the Row Hammer tracking module 150 according to an embodiment of the present invention. FIG. 5 is a detailed block diagram of the spillover counter 410 of FIG.

[0036] 4, the row hammer tracking module 150 may include a spillover counter 410, a storage device group 420 including a plurality of storage devices 421-424, a plurality of search controllers 431-434, an update controller 440, and a reset circuit 450. The plurality of storage devices 421-424 and the plurality of search controllers 431-434 may correspond one-to-one, and the following description will be given of an example in which four storage devices 421-424 and four search controllers 431-434 are provided.

[0037] The spillover counter 410 may include a field corresponding to each of a plurality of banks. In each field, a miscounting value SP_CNT of the corresponding bank may be stored. For example, as shown in FIG. 5, when the first to fourth banks BK0 to BK3 are arranged in the memory device, the spillover counter 410 may include first to fourth fields that store miscounting values ​​1, 4, 3, and 6 for the first to fourth banks BK0 to BK3, respectively.

[0038] The first to fourth storage devices 421-424 may have fields corresponding to the banks. For example, the first to fourth storage devices 421-424 may have a first field F1 corresponding to the first bank BK0. Similarly, the first to fourth storage devices 421-424 may have a second field corresponding to the second bank BK1, a third field corresponding to the third bank BK2, and a fourth field corresponding to the fourth bank BK3. In each field, a candidate address (A_ADD in FIG. 7 and FIG. 10) of the corresponding bank and an access counting value (A_CNT in FIG. 7 and FIG. 10) for the candidate address may be stored. One candidate address and its corresponding access counting value may constitute an entry, and one field may include multiple entries. The fields at the same level (for example, the kth (k is a positive integer) field) of the first to fourth storage devices 421 to 424 can store the candidate address A_ADD and the access counting value A_CNT for the same bank. The first to fourth storage devices 421 to 424 can each be configured with an SRAM (static random access memory). The detailed configurations of the first to fourth storage devices 421 to 424 will be described in detail with reference to Figs. 7 to 11B.

[0039] The first to fourth search controllers 431 to 434 may be cascaded to each other. That is, the input terminal of each of the first to fourth search controllers 431 to 434 may be connected to the output terminal of the previous stage search controller, and the output terminal may be connected to the input terminal of the next stage search controller. Among the first to fourth search controllers 431 to 434, the output of the fourth search controller 434 arranged at the last stage may be provided to the update controller 440. The first to fourth search controllers 431 to 434 may sequentially read out the candidate addresses and the access counting values ​​stored in the fields of the same level by the clock CK. Meanwhile, the first to fourth search controllers 431 to 434 may operate in a pipeline manner in which the candidate addresses and the access counting values ​​stored in the fields of different levels are simultaneously read out.

[0040] The first to fourth search controllers 431 to 434 can receive a bank address BKADD and a row address RADD together with an active command ACT from the command / address generating module 130. The first to fourth search controllers 431 to 434 can read a candidate address and an access counting value from a field selected by the bank address BKADD among the fields of the first to fourth storage devices 421 to 424, and can read a miscounting value SP_CNT from a field selected by the bank address BKADD among the fields of the spillover counter 410. The first to fourth search controllers 431 to 434 can compare the read candidate address and access counting value with the row address RADD and the read miscounting value, respectively, and generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE, S_PTR. The first to fourth search controllers 431 to 434 can transmit the active command ACT, the bank address BKADD, the row address RADD, the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR to the next stage search controller. In particular, the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR generated from the fourth search controller 434 can be provided to the update controller 440.

[0041] For example, the first to fourth search controllers 431 to 434 can compare the read candidate addresses with the row address RADD. When any one of the read candidate addresses matches (hits) the row address RADD, the first to fourth search controllers 431 to 434 can activate an address hit signal R_HIT. When the read candidate address and the row address RADD do not match, the first to fourth search controllers 431 to 434 can compare the read access counting value with the read miscounting value. When any one of the read access counting values ​​matches (hits) the read miscounting value, the first to fourth search controllers 431 to 434 can activate a count hit signal C_HIT. When the address hit signal R_HIT or the count hit signal C_HIT is activated, the first to fourth search controllers 431 to 434 can generate field information S_LINE, S_PTR for a field having a hit candidate address or a hit access counting value (hereinafter referred to as a "target field"). The field information S_LINE, S_PTR can include a position pointer S_PTR that designates a stage of a storage device including the target field and a hit entry of the target field, and shifting line data S_LINE that stores field data of the target field. The detailed configurations and operations of the first to fourth search controllers 431 to 434 will be described in detail with reference to FIG. 13A and FIG. 13B.

[0042] The update controller 440 may receive an active command ACT, a bank address BKADD, a row address RADD, an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE, S_PTR from the fourth search controller 434 among the first to fourth search controllers 431 to 434. According to an embodiment, the update controller 440 may receive the bank address BKADD and the row address RADD together with the active command ACT from the command / address generation module 130.

[0043] When the address hit signal R_HIT is activated, the update controller 440 may increase the access counting value of the hit entry of the target field based on the field information S_LINE and S_PTR, or generate a row hammer address RH_ADD along with the alert signal ALERT_S. For example, the update controller 440 may compare the access counting value of the hit entry of the shifting line data S_LINE with a preset row hammer threshold. If the access counting value is smaller than the row hammer threshold, the update controller 440 may increase the access counting value of the hit entry of the target field according to the position pointer S_PTR, and if the access counting value is equal to or greater than the row hammer threshold, the update controller 440 may generate a row hammer address RH_ADD using the candidate address of the shifting line data S_LINE and the bank address BKADD, and provide the row hammer address RH_ADD along with the alert signal ALERT_S to the command / address generation module 130. The update controller 440 may also initialize the access counting value of the hit entry of the target field.

[0044] When the address hit signal R_HIT is inactivated and the count hit signal C_HIT is activated, the update controller 440 may replace the row address RADD with a candidate address of the hit entry in the target field and increment the access counting value of the hit entry. When both the address hit signal R_HIT and the count hit signal C_HIT are inactivated, the update controller 440 may increment the miscounting value SP_CNT of the field selected by the bank address BKADD among the fields of the spillover counter 410.

[0045] Meanwhile, the update controller 440 can initialize all fields of the first to fourth storage devices 421 to 424 in response to the reset signal RST. The update controller 440 can initialize all miscounting values ​​of the spillover counter 410 in response to the reset signal RST. The detailed operation of the update controller 440 will be described in detail with reference to FIG.

[0046] The reset circuit 450 can generate the reset signal RST at intervals of a refresh time tREF defined in the specifications as the time for all rows to be normally refreshed. For example, if the refresh period tREF is set to 64 ms, the reset circuit 450 can activate the reset signal RST every 64 ms.

[0047] Hereinafter, a configuration of a storage device according to an embodiment of the present invention will be described with reference to the drawings.

[0048] FIG. 6 is a timing diagram for explaining the known first active interval tRC and second active interval tRRD.

[0049] As shown in Fig. 6, in the memory device specifications, the minimum interval between active commands for the same bank is defined as a first active interval (RAS cycle time, tRC), and the minimum interval between active commands for different banks is defined as a second active interval (row-to-row delay time, tRRD). For example, the first active interval tRC can be set to several tens of ns, and the second active interval tRRD can be set to several ns.

[0050] In the following embodiments, for convenience of explanation, the first active interval tRC and the second active interval tRRD are converted from time units to clock units. For this purpose, the first active interval tRC and the second active interval tRRD are actually defined in time units, and are divided by the unit time tCK and processed by a floor function, and are described as the first active interval tRC and the second active interval tRRD. That is, as shown in FIG. 6, the active command ACT for the second bank BK1 may be inputted with a second active interval tRRD of 2CK from the input of the active command ACT for the first bank BK0. Also, the active command ACT for the first bank BK0 may be inputted again with a first active interval tRC of 8CK from the input of the active command ACT for the first bank BK0.

[0051] FIG. 7 is a detailed configuration diagram of the storage device group 420 according to the first embodiment of the present invention.

[0052] As shown in FIG 7, the number of storage devices in the storage device group 420 may be set according to a first active interval tRC. For example, if the first active interval tRC is set to 8CK, eight storage devices may be provided. In this case, the depth of each storage device may be set according to the number of banks. For example, if four banks BK0 to BK3 are arranged in each memory device, the depth of each storage device may be set to 4, and each storage device may be composed of four fields.

[0053] As described above, one field may include multiple entries, and each entry may store one candidate address and its corresponding access counting value. The number of entries included in one field may be set to a value obtained by dividing the number of candidate addresses to be tracked by the number of storage devices. For example, if the number of candidate addresses to be tracked is 5000 and the number of storage devices is 8, the number of entries included in one field may be set to 5000 / 8=625.

[0054] 8A to 8C are examples for explaining a read method of the storage device group 420 of FIG. 7. In FIG. 8A to 8C, four banks BK0 to BK3 are arranged, the first active interval tRC is set to 8CK, and the second active interval tRRD is set to 1CK. In this case, first to eighth storage devices 810 to 880 are arranged, and each storage device may be composed of first to fourth fields. Although not shown in the drawings, first to eighth search controllers corresponding to the first to eighth storage devices 810 to 880, respectively, may be arranged.

[0055] 8A(A), an active command ACT for the first bank BK0 is input during the first clock 1CK period. The first search controller can read field data including a candidate address and an access counting value stored in the first field of the first storage device 810.

[0056] 8A(B), during the second clock 2CK period, an active command ACT for the second bank BK1 is input at a second active interval tRRD. The first search controller can read the field data stored in the second field of the first storage device 810, and the second search controller can read the field data stored in the first field of the second storage device 820.

[0057] 8A(C), during the third clock 3CK period, an active command ACT for the third bank BK2 is input at the second active interval tRRD. The first search controller can read the field data stored in the third field of the first storage device 810, the second search controller can read the field data stored in the second field of the second storage device 820, and the third search controller can read the field data stored in the first field of the third storage device 830.

[0058] As shown in (D) of FIG. 8A, during the fourth clock 4CK period, an active command ACT for the fourth bank BK3 is input at the second active interval tRRD. The first search controller can read the field data stored in the fourth field of the first storage device 810, the second search controller can read the field data stored in the third field of the second storage device 820, the third search controller can read the field data stored in the second field of the third storage device 830, and the fourth search controller can read the field data stored in the first field of the fourth storage device 840. That is, the search controllers can read the field data of the storage devices 810 to 880 in a pipeline manner.

[0059] As shown in (E), (F), (G), and (H) of Figure 8B, during the fifth clock 5CK cycle to the eighth clock 8CK cycle, the search controller can read out field data from storage devices 810 to 880 in the above-mentioned pipeline manner. As shown in (I) of Fig. 8C, after the first active interval tRC of 8CK has elapsed, all fields for the first bank BK0 have been read out, so the next read can proceed even if an active command ACT is input to the first bank BK0. As shown in (I), (J), and (K) of Fig. 8C, during the ninth clock 9CK cycle to the eleventh clock 11CK cycle, the search controller can read out all field data from the storage devices 810 to 880 in the above-mentioned pipeline manner.

[0060] 9A to 9D are further examples for explaining a read method of the storage device group 420 of FIG. 7. In FIG. 9A to 9D, four banks BK0 to BK3 are arranged, the first active interval tRC is set to 8CK, and the second active interval tRRD is set to 2CK. In this case, first to eighth storage devices 910 to 980 are arranged, and each storage device may be composed of first to fourth fields. Although not shown in the drawings, first to eighth search controllers corresponding to the first to eighth storage devices 910 to 980, respectively, may be arranged.

[0061] As shown in (A) of FIG. 9A, during the first clock 1CK period, an active command ACT for the first bank BK0 is input. The first search controller can read the field data stored in the first field of the first storage device 910. As shown in (B) of FIG. 9A, during the second clock 2CK period, the second search controller can read the field data stored in the first field of the second storage device 920.

[0062] As shown in (C) of FIG. 9A, during the third clock 3CK period, an active command ACT for the second bank BK1 is input at the second active interval tRRD. The first search controller can read the field data stored in the second field of the first storage device 910, and the third search controller can read the field data stored in the first field of the third storage device 930. As shown in (D) of FIG. 9A, during the fourth clock 4CK period, the second search controller can read the field data stored in the second field of the second storage device 920, and the fourth search controller can read the field data stored in the first field of the fourth storage device 940.

[0063] As shown in FIG. 9B (E), during the fifth clock 5CK period, an active command ACT for the third bank BK2 is input at the second active interval tRRD. The first search controller can read the field data stored in the third field of the first storage device 910, the third search controller can read the field data stored in the second field of the third storage device 930, and the fifth search controller can read the field data stored in the first field of the fifth storage device 950. As shown in FIG. 9B (F), during the sixth clock 6CK period, the second search controller can read the field data stored in the third field of the second storage device 920, the fourth search controller can read the field data stored in the second field of the fourth storage device 940, and the sixth search controller can read the field data stored in the first field of the sixth storage device 960.

[0064] 9B(G), during the seventh clock 7CK period, an active command ACT for the fourth bank BK3 is input at the second active interval tRRD. The first search controller can read the field data stored in the fourth field of the first storage device 910, the third search controller can read the field data stored in the third field of the third storage device 930, the fifth search controller can read the field data stored in the second field of the fifth storage device 950, and the seventh search controller can read the field data stored in the first field of the seventh storage device 970. 9B(H), during the eighth clock 8CK period, the second search controller can read the field data stored in the fourth field of the second storage device 920, the fourth search controller can read the field data stored in the third field of the fourth storage device 940, the sixth search controller can read the field data stored in the second field of the sixth storage device 960, and the eighth search controller can read the field data stored in the first field of the eighth storage device 980. That is, the search controllers can read the field data of the storage devices 910-980 in a pipelined manner.

[0065] As shown in (I) of Fig. 9C, after the first active interval tRC of 8CK has elapsed, all fields for the first bank BK0 have been read out, so even if an active command ACT is input to the first bank BK0, the next read can proceed. As shown in (I), (J), (K), (L), (M), and (N) of Fig. 9C and Fig. 9D, during the ninth clock 9CK cycle to the fourteenth clock 14CK cycle, the search controller can read out all field data of the storage devices 910 to 980 in the above-mentioned pipeline manner.

[0066] As shown in Figures 8A to 9D, the search controller of the first embodiment may read a candidate address and an access counting value stored in an m-th field (m is a positive integer different from x) of an (x+y)-th storage device while reading a candidate address and an access counting value stored in a k-th field (k is a positive integer greater than 2) of an x-th storage device (x is a positive integer), where y may be set based on a second active interval tRRD. For reference, in the example described in Figures 8A to 9D, if a specific search controller determines that any one of the read candidate addresses matches (hits) with a row address RADD, the search controller of the next stage may suspend an additional read operation for the same bank.

[0067] Meanwhile, in the examples described in Figures 8A to 9D, the active command ACT is input to the first to fourth banks BK0 to BK3 in sequence, but the proposed invention is not limited thereto. The active command ACT can be input regardless of the order of the banks. For example, the active command ACT can be input to the second bank BK1 first, and after the second active interval tRRD, the active command ACT can be input to the fourth bank BK3.

[0068] FIG. 10 is a detailed configuration diagram of a storage device group 420 according to the second embodiment of the present invention.

[0069] As shown in FIG. 10, the number of storage devices in the storage device group 420 may be set according to a ratio between a first active interval tRC and a second active interval tRRD. For example, if the first active interval tRC is set to 8CK and the second active interval tRRD is set to 2CK, four storage devices may be provided. In this case, the depth of each storage device may be set according to the product of the number of banks and the second active interval tRRD. For example, if four banks BK0 to BK3 are arranged in each memory device, the depth of each storage device may be set to 4×2=8, and each storage device may be configured with two fields for each bank, i.e., eight fields.

[0070] 11A and 11B are examples for explaining a read method of the storage device group 420 of FIG. 10. In FIG. 11A and 11B, four banks BK0 to BK3 are arranged, the first active interval tRC is set to 8CK, and the second active interval tRRD is set to 2CK. In this case, first to fourth storage devices 1110 to 1140 are arranged, and each storage device may be composed of first to eighth fields. Although not shown in the drawings, first to fourth search controllers corresponding to the first to fourth storage devices 1110 to 1140, respectively, may be arranged.

[0071] As shown in (A) of FIG. 11A, during the first clock 1CK cycle, an active command ACT for the first bank BK0 is input. The first search controller can read the field data stored in the first field of the first storage device 1110. As shown in (B) of FIG. 11A, during the second clock 2CK cycle, the first search controller can read the field data stored in the second field of the first storage device 1110.

[0072] As shown in (C) of FIG. 11A, during the third clock 3CK period, an active command ACT for the second bank BK1 is input at the second active interval tRRD. The first search controller can read the field data stored in the third field of the first storage device 1110, and the second search controller can read the field data stored in the first field of the second storage device 1120. As shown in (D) of FIG. 11A, during the fourth clock 4CK period, the first search controller can read the field data stored in the fourth field of the first storage device 1110, and the second search controller can read the field data stored in the second field of the second storage device 1120.

[0073] As shown in (E) of FIG. 11A, during the fifth clock 5CK period, an active command ACT for the third bank BK2 is input at the second active interval tRRD. The first search controller can read the field data stored in the fifth field of the first storage device 1110, the second search controller can read the field data stored in the third field of the second storage device 1120, and the third search controller can read the field data stored in the first field of the third storage device 1130. As shown in (F) of FIG. 11A, during the sixth clock 6CK period, the first search controller can read the field data stored in the sixth field of the first storage device 1110, the second search controller can read the field data stored in the fourth field of the second storage device 1120, and the third search controller can read the field data stored in the second field of the third storage device 1130.

[0074] 11B(G), during the seventh clock 7CK period, an active command ACT for the fourth bank BK3 is input at the second active interval tRRD. The first search controller can read the field data stored in the seventh field of the first storage device 1110, the second search controller can read the field data stored in the fifth field of the second storage device 1120, the third search controller can read the field data stored in the third field of the third storage device 1130, and the fourth search controller can read the field data stored in the first field of the fourth storage device 1140. 11B(H), during the eighth clock 8CK, the first search controller can read the field data stored in the eighth field of the first storage device 1110, the second search controller can read the field data stored in the sixth field of the second storage device 1120, the third search controller can read the field data stored in the fourth field of the third storage device 1130, and the fourth search controller can read the field data stored in the second field of the fourth storage device 1140. That is, the search controllers can read the field data of the storage devices 1110-1140 in a pipeline manner.

[0075] As shown in (I) of Fig. 11B, after the first active interval tRC of 8CK has elapsed, all fields for the first bank BK0 have been read out, so the next read can proceed even if an active command ACT is input to the first bank BK0. As shown in (I), (J), and (K) of Fig. 11B, during the ninth clock 9CK cycle to the fourteenth clock 14CK cycle, the search controller can read out all field data from the storage devices 1110 to 1140 in the above-mentioned pipeline manner.

[0076] Figures 12A to 12C are further examples for explaining a method for reading the storage device group 420 of Figure 10. Figures 12A to 12C illustrate a case where an active command ACT is input regardless of the order of the first to fourth banks BK0 to BK3 under the same conditions as Figures 11A and 11B.

[0077] As shown in (A) of FIG. 12A, an active command ACT for the third bank BK2 is input during the first clock 1CK period. The first search controller can read the field data stored in the fifth field of the first storage device 1210. As shown in (B) of FIG. 12A, during the second clock 2CK period, the first search controller can read the field data stored in the sixth field of the first storage device 1210. As shown in (C) of FIG. 12A, the second active interval tRRD has passed but no additional active command ACT has been input, so during the third clock 3CK period, the second search controller can read the field data stored in the fifth field of the second storage device 1220.

[0078] Thereafter, as shown in (D) of FIG. 12A, during the fourth clock 4CK period, an active command ACT for the first bank BK0 is input. The first search controller can read the field data stored in the first field of the first storage device 1210, and the second search controller can read the field data stored in the sixth field of the second storage device 1220. As shown in (E) of FIG. 12A, during the fifth clock 5CK period, the first search controller can read the field data stored in the second field of the first storage device 1210, and the third search controller can read the field data stored in the fifth field of the third storage device 1230. As shown in (F) of FIG. 12A, during the sixth clock 6CK period, the second search controller can read the field data stored in the first field of the second storage device 1220, and the third search controller can read the field data stored in the sixth field of the third storage device 1230. As shown in (G) of FIG. 12B, during the seventh clock 7CK period, the second search controller can read the field data stored in the second field of the second storage device 1220, and the fourth search controller can read the field data stored in the fifth field of the fourth storage device 1240.

[0079] Then, as shown in (H) of FIG. 12B, during the eighth clock 8CK period, an active command ACT for the second bank BK1 is input. The first search controller can read the field data stored in the third field of the first storage device 1210, the third search controller can read the field data stored in the first field of the third storage device 1230, and the fourth search controller can read the field data stored in the sixth field of the fourth storage device 1240. As shown in (I) of FIG. 12B, during the ninth clock 9CK period, the first search controller can read the field data stored in the fourth field of the first storage device 1210, and the third search controller can read the field data stored in the second field of the third storage device 1230.

[0080] As shown in (J) of FIG. 12B, during the 10th clock 10CK cycle, an active command ACT for the fourth bank BK3 is input. The first search controller reads the field data stored in the 7th field of the first storage device 1210, the second search controller reads the field data stored in the 3rd field of the second storage device 1220, and the fourth search controller reads the field data stored in the 1st field of the fourth storage device 1240. In this manner, as shown in (K), (L) of FIG. 12B and (M), (N), (O), and (P) of FIG. 12C, during the 11th clock 11CK cycle to the 17th clock 17CK cycle, the search controller can read all the field data of the storage devices 1210 to 1240 in the above-mentioned pipeline manner. 11A to 12B, the search controller of the second embodiment may read the candidate address and access counting value stored in the (ky)th field of the zth (z is a positive integer different from x) storage device while reading the candidate address and access counting value stored in the kth (k is a positive integer) field of the xth (x is a positive integer) storage device, where y may be set based on the second active interval tRRD and the order of the bank to which the active command is input. For reference, in the example described in FIGS. 8A to 9D, if a specific search controller determines that any one of the read candidate addresses matches (hits) with the row address RADD, the search controller of the next stage may suspend additional read operations for the same bank.

[0081] Meanwhile, in the memory device specifications, a time window in which four active commands can be applied is defined as a third active window (tFAW). According to an embodiment, the row hammer tracking module 150 may arrange a buffer for storing four consecutive active commands at the front end of the storage device group 420. The storage device group 420 may receive the output of the buffer. In this case, the number of storage devices in the storage device group 420 may be set by multiplying the ratio of the first active interval tRC and the third active interval tFAW by 4. For example, if the first active interval tRC is set to 8CK and the third active interval tFAW is set to 8CK, 8 / 8×4=4 storage devices may be provided. Also, the depth of each storage device may be set by dividing the product of the number of banks and the third active interval tFAW by 4. For example, if four banks BK0 to BK3 are arranged in each memory device, the depth of each storage device is set to 4×8 / 4=8, and each storage device can be configured with two fields for each bank, i.e., eight fields.

[0082] 13A and 13B are a block diagram and a flowchart illustrating the operation of any one of the search controllers according to an embodiment of the present invention.

[0083] As shown in FIG. 13A, input / output signals of one of search controllers 1300 among first to fourth search controllers 431 to 434 shown in FIG. 4 are shown.

[0084] The search controller 1300 can read the candidate address A_ADD and the access counting value A_CNT from the field of the storage device by the bank address BKADD, and can read the miscounting value SP_CNT from the field of the spillover counter 410. The search controller 1300 can compare the read candidate address A_ADD and the access counting value A_CNT with the row address RADD and the read miscounting value SP_CNT, respectively, to generate an address hit signal R_HIT, a count hit signal 1300_HIT, and field information S_LINE, S_PTR. The search controller 1300 can transmit the active command ACT, the bank address BKADD, the row address RADD, the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR to the next stage search controller.

[0085] For reference, among the cascaded search controllers, the frontmost search controller may receive a bank address BKADD and a row address RADD together with an active command ACT from the command / address generation module 130. The frontmost search controller may receive an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR, which are set to initial values ​​(e.g., 0).

[0086] Referring now to FIG. 13B, the operation of the search controller 1300 is illustrated.

[0087] The active command ACT is input along with the bank address BKADD and row address RADD (S110).

[0088] When the address hit signal R_HIT transmitted from the previous search controller is activated (YES in S120), the search controller 1300 can transmit the signal transmitted from the previous search controller to the next search controller (S180). On the other hand, when the address hit signal R_HIT is inactivated (NO in S120), the search controller 1300 can select one of the fields of the storage device and one of the fields of the spillover counter 410 according to the bank address BKADD. As a result, the candidate address A_ADD and the access counting value A_CNT can be read from the storage device, and the miscounting value SP_CNT can be read from the spillover counter 410 (S130).

[0089] The search controller 1300 may compare the row address RADD with the candidate addresses A_ADD (S140). If at least one of the candidate addresses A_ADD matches the row address RADD (YES in S140), the search controller 1300 may activate an address hit signal R_HIT and generate (or update) field information S_LINE, S_PTR for the field of the selected storage device (i.e., the target field) (S150). At this time, the field information S_LINE, S_PTR may include a position pointer S_PTR that designates the stage of the storage device including the target field and a hit entry of the target field, and shifting line data S_LINE in which the field data of the target field is stored. Thereafter, the search controller 1300 can transmit the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR along with the active command ACT, the bank address BKADD, and the row address RADD to the next stage search controller (S180).

[0090] If all the candidate addresses A_ADD do not match the row address RADD (NO in S140), the search controller 1300 can compare the miscounting value SP_CNT with the access counting value A_CNT (S160). If at least one of the access counting values ​​A_CNT matches the miscounting value SP_CNT (YES in S160), the search controller 1300 can activate the count hit signal C_HIT and generate (or update) field information S_LINE, S_PTR for the target field (S170). Thereafter, the search controller 1300 can transmit the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR along with the active command ACT, the bank address BKADD, and the row address RADD to the next stage search controller (S180).

[0091] Meanwhile, in a storage device configuration arranged as described in the second embodiment, the operation described in FIG. 13B may be repeated a number of times corresponding to the second active interval tRRD.

[0092] FIG. 14 is a flowchart illustrating an operation of the update controller 440 according to an embodiment of the present invention.

[0093] As shown in FIG. 14, when the reset signal RST is activated (YES in S210), the update controller 440 can initialize all the field data of the storage devices 421-424 and the miscounting value of the spillover counter 410 (S220). For example, since the reset signal RST is activated at a constant period, the storage devices 421-424 and the spillover counter 410 can be initialized at a constant period. For reference, in order to initialize all the field data of the storage devices 421-424, a clock period corresponding to the number of fields of each storage device may be required. For example, if four fields are arranged in each storage device, at least four clock periods are required.

[0094] When a bank address BKADD and a row address RADD are input along with an active command ACT (S230), the update controller 440 can receive the active command ACT, the bank address BKADD, the row address RADD, the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE and S_PTR from the fourth search controller 434.

[0095] If the address hit signal R_HIT is activated (YES in S240), the update controller 440 may compare the access counting value A_CNT of the shifting line data S_LINE with a preset row hammer threshold RH_T (S250). At this time, the hit entry is selected by the position pointer S_PTR, and the access counting value A_CNT of the hit entry may be compared with the row hammer threshold RH_T. If the access counting value A_CNT of the hit entry is smaller than the row hammer threshold RH_T (NO in S250), the update controller 440 may increment the access counting value A_CNT of the hit entry by "+1" (S252). Thereafter, the update controller 440 may write (or update) the shifting line data S_LINE to the target field according to the position pointer S_PTR and the bank address BKADD (S258). As a result, the access counting value of the hit entry in the target field may be incremented.

[0096] On the other hand, if the access counting value A_CNT of the hit entry is equal to or greater than the row hammer threshold RH_T (YES in S250), the update controller 440 generates a row hammer address RH_ADD using the candidate address A_ADD of the hit entry of the shifting line data S_LINE and the bank address BKADD, and outputs the row hammer address RH_ADD together with an alert signal ALERT_S indicating that a row hammer situation has occurred (S254). In addition, the update controller 440 may set the access counting value A_CNT of the hit entry to a specific value (e.g., 0) (S256). Thereafter, the update controller 440 may write (or update) the shifting line data S_LINE to the target field using the position pointer S_PTR and the bank address BKADD (S258). This may initialize the access counting value of the hit entry of the target field.

[0097] On the other hand, if the address hit signal R_HIT is inactivated (NO in S240) and the count hit signal C_HIT is activated (YES in S260), the update controller 440 can replace the row address RADD with the candidate address A_ADD of the hit entry of the shifting line data S_LINE and increment the access counting value A_CNT of the hit entry of the shifting line data S_LINE by "+1" (S264). Then, the update controller 440 can write (or update) the shifting line data S_LINE to the target field using the position pointer S_PTR and the bank address BKADD (S258). As a result, the candidate address and the access counting value of the hit entry of the target field can all be updated.

[0098] On the other hand, if the count hit signal C_HIT is inactivated (NO in S260), the update controller 440 can increment the miscounting value SP_CNT of the field selected by the bank address BKADD among the fields of the spillover counter 410 (S262).

[0099] Hereinafter, a row hammer tracking method according to an embodiment of the present invention will be described with reference to a specific example.

[0100] 15A to 15M are diagrams illustrating an example of a row hammer tracking method according to an embodiment of the present invention.

[0101] As shown in FIG. 15A, the first to fifth banks BK0 to BK4 are arranged, the first active interval tRC is set to 4CK, and the second active interval tRRD is set to 1CK. In this case, the first to fourth storage devices are arranged, and each storage device can be composed of the first to fifth fields corresponding to the first to fifth banks BK0 to BK4. In FIG. 15A, it is assumed that the first to fifth entries are arranged in each field, and the row hammer threshold RH_T is set to 5000-1=4999.

[0102] As shown in FIG. 15B, during the first clock 1CK period, the bank address BKADD designating the first bank BK0 and the row address RADD designating the 16th row are input together with the active command ACT (BKADD:0, RADD:16). The first search controller can read field data (i.e., candidate addresses and access counting values) (1, 3), (2, 2), (3, 4000), (4, 2000), and (5, 30) from the first field corresponding to the first bank BK0 among the fields of the first storage device, and can read the miscounting value 2 from the spillover counter. At this time, since all the candidate addresses do not match the row address (RADD) 16 and the access counting value 2 of the second entry matches the miscounting value 2, the first search controller can activate the count hit signal C_HIT and generate field information S_LINE, S_PTR for the first field and transmit them to the second search controller. At this time, the shifting line data S_LINE of the field information S_LINE, S_PTR is updated to the field data (1, 3) (2, 2) (3, 4000) (4, 2000) (5, 30) read from the first field, and the position pointer S_PTR can be set to a value (i.e., stage1, entry2) specifying the position (stage) of the first storage device and the second entry (entry) that was hit.

[0103] As shown in FIG. 15C, during the second clock 2CK period, the bank address BKADD designating the second bank BK1 and the row address RADD designating the 13th row are input together with the active command ACT (BKADD:1, RADD:13). The first search controller can read the field data (0,0)(0,0)(0,0)(0,0)(0,0) from the second field corresponding to the second bank BK1 and read the miscounting value 0 from the spillover counter. At this time, since the access counting value 0 of the first entry matches the miscounting value 0 first, the first search controller can generate field information S_LINE, S_PTR for the second field and transmit it to the second search controller. At this time, the shifting line data S_LINE is updated to the field data (0,0)(0,0)(0,0)(0,0)(0,0) read from the second field, and the position pointer S_PTR can be set to a value specifying the position (stage) of the first storage device and the first entry (entry) that was hit (i.e., stage1, entry1).

[0104] Also, the second search controller can read the field data (6, 2), (7, 3), (8, 4000), (9, 2000), (10, 30) from the first field corresponding to the first bank BK0 by the bank address BKADD transmitted from the first search controller, and can read the miscounting value 2 from the spillover counter. At this time, since the access counting value 2 of the first entry matches the miscounting value 2, the second search controller can update the shifting line data S_LINE to the field data (6, 2), (7, 3), (8, 4000), (9, 2000), (10, 30) read from the first field, and set the position pointer S_PTR to (stage2, entry1).

[0105] As shown in FIG. 15D, during the third clock 3CK period, the bank address BKADD designating the third bank BK2 and the row address RADD designating the 23rd row are input together with the active command ACT (BKADD:2, RADD:23). Since the access counting value 5 of the first entry of the third field matches the miscounting value 5 first, the first search controller can update the shifting line data S_LINE to the field data read from the third field and set the position pointer S_PTR to (stage1, entry1). Since the access counting value 0 of the first entry of the second field matches the miscounting value 0 first, the second search controller can update the shifting line data S_LINE to the field data read from the second field and set the position pointer S_PTR to (stage2, entry1). Also, since the comparison results are all mismatch, the third search controller can directly transfer the signal transferred from the second search controller to the fourth search controller.

[0106] As shown in FIG. 15E, during the fourth clock 4CK period, the bank address BKADD designating the fourth bank BK3 and the row address RADD designating the 9th row are input together with the active command ACT (BKADD:3, RADD:9). Since the access counting value 6 of the first entry of the fourth field matches the miscounting value 6 first, the first search controller can update the shifting line data S_LINE to the field data read from the fourth field and set the position pointer S_PTR to (stage1, entry1). Since the comparison results are all mismatches, the second search controller can transmit the signal transmitted from the first search controller to the third search controller as it is. Since the access counting value 0 of the first entry of the second field matches the miscounting value 0 first, the third search controller can update the shifting line data S_LINE to the field data read from the second field and set the position pointer S_PTR to (stage3, entry1). On the other hand, since the candidate address 16 of the first entry in the first field matches the row address RADD16, the fourth search controller can activate the address hit signal R_HIT, update the shifting line data S_LINE to the field data read from the first field, and set the position pointer S_PTR to (stage4, entry1).

[0107] Thereafter, during the fifth clock 5CK period, the update controller can check the signal transmitted from the fourth search controller. The update controller can increase the access counting value 7 of the first entry of the shifting line data S_LINE designated by the position pointer S_PTR by "+1" since the address hit signal R_HIT is activated and the access counting value 7 of the first entry of the shifting line data S_LINE designated by the position pointer S_PTR is smaller than the row hammer threshold RH_T. As shown in FIG. 15F, the update controller can write the shifting line data S_LINE to the first field of the fourth storage device designated by the position pointer S_PTR. As a result, the first entry of the first field can be updated to (16, 8). At this time, since the update controller knows the bank address BKADD, it can select the first field.

[0108] Meanwhile, during the fifth clock 5CK period, the bank address BKADD specifying the fifth bank BK4 and the row address RADD specifying the 30th row are input together with the active command ACT. (BKADD:4, RADD:30). The first search controller can transmit the signal set to the initial value to the second search controller as it is. Since the candidate address 9 of the fourth entry in the fourth field matches the row address RADD9, the second search controller can activate the address hit signal R_HIT, update the shifting line data S_LINE to the field data read from the fourth field, and set the position pointer S_PTR to (stage2, entry4). The third search controller can transmit the signal transmitted from the second search controller to the fourth search controller as it is. Since the access counting value 0 of the first entry in the second field matches the miss counting value 0 first, the fourth search controller can update the shifting line data S_LINE to the field data read from the second field and set the position pointer S_PTR to (stage4, entry1).

[0109] Thereafter, during the sixth clock 6CK period, the update controller can check the signal transmitted from the fourth search controller. Since the count hit signal C_HIT is activated, the update controller can substitute the row address (RADD) 13 for the candidate address of the first entry of the shifting line data S_LINE and increase the access counting value 0 of the first entry of the shifting line data S_LINE by "+1". As shown in FIG. 15G, the update controller can write the shifting line data S_LINE to the second field of the fourth storage device designated by the position pointer S_PTR. As a result, the first entry of the second field can be updated to (13, 1). Meanwhile, during the sixth clock 6CK period, the bank address BKADD designating the first bank BK0 and the row address RADD designating the fourth row are input again together with the active command ACT. (BKADD:0, RADD:4). As described above, each search controller can generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE, S_PTR.

[0110] Thereafter, during the seventh clock 7CK period, the update controller can substitute the row address (RADD) 23 for the candidate address of the first entry of the shifting line data S_LINE by the count hit signal C_HIT, and increase the access counting value 5 of the first entry of the shifting line data S_LINE by "+1". As shown in FIG. 15H, the update controller can write the shifting line data S_LINE to the third field of the first storage device designated by the position pointer S_PTR. This allows the first entry of the third field to be updated to (23, 6). Meanwhile, during the seventh clock 7CK period, the bank address BKADD designating the third bank BK2 and the row address RADD designating the 23rd row are input again together with the active command ACT. (BKADD: 2, RADD: 23). As described above, each search controller can generate the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR.

[0111] Meanwhile, according to an embodiment, when a write operation of the update controller and a read operation of the search controller for the same field are requested at the same time, an additional circuit for preventing collision may be disposed. For example, as shown in FIG. 15I, a comparison circuit 1510 and a multiplexer 1520 may be disposed at the front end of each search controller. The comparison circuit 1510 may compare a bank address BKADD input to the search controller with a bank address BKADD provided from the update controller for each clock to generate a match signal HIT. The multiplexer 1520 may select one of field data read from a field of the storage device corresponding to the bank address BKADD and shifting line data S_LINE provided from the update controller in response to the match signal HIT and provide it to the search controller. For example, as shown in FIG. 15I, during the seventh clock 7CK period, the comparison circuit 1510 may generate a match signal HIT of a logic high level when the bank address BKADD input to the search controller and the bank address BKADD provided from the update controller are the same as the address for the third bank BK2. The multiplexer 1520 may select the shifting line data S_LINE provided from the update controller in response to the match signal HIT of a logic high level, and provide the same to the search controller. Finally, the search controller generates the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE, S_PTR using the bank address BKADD, the row address RADD, the selected data provided from the multiplexer 1520, and the miscounting value provided from the spillover counter, and the update controller may perform a write operation. Meanwhile, in FIG. 15I, the comparison circuit 1510 and the multiplexer 1520 are described as being disposed at the front end of the search controller, but the proposed invention is not limited thereto. According to an embodiment, the comparison circuit 1510 and the multiplexer 1520 may be included inside each search controller.

[0112] Thereafter, during the eighth clock 8CK period, the update controller may confirm that the address hit signal R_HIT is activated and the access counting value 4999 of the fourth entry of the shifting line data S_LINE designated by the position pointer S_PTR is equal to or greater than the row hammer threshold RH_T. Thus, the update controller may generate a row hammer address RH_ADD having a candidate address (or row address RADD) and a bank address BKADD of the fourth entry of the shifting line data S_LINE, and set the access counting value of the fourth entry of the shifting line data S_LINE to 0. As shown in FIG. 15J, the update controller may output the row hammer address RH_ADD together with an alert signal ALERT_S. Also, the update controller may write the shifting line data S_LINE to the fourth field of the second storage device designated by the position pointer S_PTR. This may update the fourth entry of the fourth field to (9, 0) and initialize the access counting value.

[0113] Then, during the ninth clock 9CK period, the address hit signals R_HIT and the count hit signals C_HIT are all inactivated, so that the update controller can increment the miscounting value 3 of the fifth field of the spillover counter by “+1” using the bank address BKADD, as shown in FIG. 15K.

[0114] Thereafter, during the tenth clock 10CK period, the address hit signal R_HIT is activated, and the access counting value 2000 of the fourth entry of the shifting line data S_LINE designated by the position pointer S_PTR is smaller than the row hammer threshold RH_T, so the update controller can increase the access counting value 2000 of the fourth entry of the shifting line data S_LINE by "+1". As shown in FIG. 15L, the update controller can write the shifting line data S_LINE to the first field of the first storage device designated by the position pointer S_PTR. This allows the fourth entry of the first field to be updated to (4, 2001).

[0115] Thereafter, during the 11th clock 11CK period, the address hit signal R_HIT is activated, and the access counting value 6 of the first entry of the shifting line data S_LINE designated by the position pointer S_PTR is smaller than the row hammer threshold RH_T, so the update controller can increase the access counting value 6 of the first entry of the shifting line data S_LINE by "+1". As shown in FIG. 15M, the update controller can write the shifting line data S_LINE to the third field of the first storage device designated by the position pointer S_PTR. This allows the first entry of the third field to be updated to (23, 7).

[0116] For reference, CAM is a memory with a relatively complex structure that can search memory according to data contents, and when a data pattern is input, it can search for data that matches the pattern. As a result, CAM is used very efficiently in database searches, etc., but due to its complex structure, it occupies a large amount of space and becomes more difficult to implement as the number of objects to be searched increases. In contrast, SRAM is a memory with a relatively simple structure that can directly access data by address to read or write it. As a result, SRAM is characterized by high speed and low access latency, and can improve the operating speed of a processor.

[0117] As described above, the memory controller 100 according to the embodiment of the present invention uses SRAM as a storage device instead of a conventionally known CAM to store the candidate addresses and their access counting values. When implementing a row hammer tracking module using CAM, the number of CAMs corresponding to the banks must be provided, and as the row hammer threshold becomes lower, the number of objects to be searched increases, making it practically difficult to implement. In contrast, in the embodiment of the present invention, the area occupied by the row hammer tracking device can be minimized by using SRAM as a storage device to store the candidate addresses and their access counting values. In addition, a plurality of SRAMs and corresponding search controllers are arranged one-to-one, and the search controller reads data from the SRAM in a pipeline manner, making it possible to detect row hammer addresses in a short time, thereby efficiently reducing the risk of row hammer.

[0118] Meanwhile, in the above embodiment, the row hammer tracking module 150 is described as being disposed inside the memory controller 100, but the proposed invention is not limited thereto. Depending on the embodiment, the row hammer tracking module 150 may be disposed in the module controller or resist clock driver of the memory module 200, and may be disposed in each memory device 200A.

[0119] Although the technical concept of the present invention has been specifically recorded in the above-mentioned preferred embodiment, it should be noted that the above-mentioned embodiment is for the purpose of explanation and not for the purpose of limiting the present invention. In addition, a person skilled in the art of the present invention will understand that various embodiments are possible within the scope of the technical concept of the present invention.

[0120] For example, the logic gates and transistors exemplified in the above-mentioned embodiments should be implemented so that their positions and types differ depending on the polarity of the input signal.

Claims

1. A command / address generation module; a row hammer tracking module that tracks a row hammer address based on an active command received from the command / address generation module and an address for a target bank and row of the active command; Equipped with The Row Hammer tracking module includes: a plurality of storage devices each including a field corresponding to a bank, each field storing a candidate address of the corresponding bank and an access counting value for the candidate address; at least one search controller that sequentially searches the fields of the storage devices corresponding to the target bank by a clock when the active command is received, and searches the fields of the storage devices corresponding to the different banks for one clock based on active commands targeted to different banks; A memory controller comprising:

2. 2. The memory controller of claim 1, wherein fields at the same level of the plurality of storage devices store candidate addresses and access counting values ​​for the same bank.

3. The number of the plurality of storage devices is 2. The memory controller of claim 1, wherein the first active interval is set to be a minimum interval between active commands to the same bank.

4. The depth of each of the plurality of storage devices is:

4. The memory controller according to claim 3, which is set according to the number of said banks.

5. The Row Hammer tracking module includes: During one clock to read the candidate address and the access counting value stored in the k-th (k is a positive integer) field of the x-th (x is a positive integer) storage device, Read the candidate address and the access counting value stored in the m-th field (m is a positive integer different from k) of the (x+y)-th storage device; 4. The memory controller of claim 3, wherein y is set based on a second active interval that is a minimum interval between active commands to different banks.

6. The number of the plurality of storage devices is 2. The memory controller of claim 1, wherein the active interval is set by a ratio of a first active interval, which is a minimum interval between active commands to the same bank, and a second active interval, which is a minimum interval between active commands to different banks.

7. The depth of each of the plurality of storage devices is:

7. The memory controller of claim 6, wherein the second active interval is set by a product of the number of banks and the second active interval.

8. The Row Hammer tracking module includes: During one clock to read the candidate address and the access counting value stored in the k-th (k is a positive integer) field of the x-th (x is a positive integer) storage device, Read the candidate address and the access counting value stored in the (k−y)-th field of the z-th storage device (z is a positive integer different from x); The memory controller of claim 6 , wherein y is set based on the second active interval and an order of banks to which the active command is input.

9. a spillover counter that stores a miscounting value; a plurality of storage devices each including a field corresponding to a bank, each field storing a candidate address of the corresponding bank and an access counting value for the candidate address; a plurality of search controllers, each corresponding to each of the plurality of storage devices and cascaded to each other, for comparing a candidate address and an access counting value read from a field corresponding to the bank address with the row address and the miscounting value when a bank address and a row address are input together with an active command, to generate an address hit signal, a count hit signal, and field information; an update controller for updating an access counting value or a miss counting value of a target field designated by the field information in response to the address hit signal and the count hit signal; A row hammer tracking device comprising:

10. Each of the plurality of storage devices includes:

10. The row hammer tracking device of claim 9, which is constructed using static random access memory (SRAM).

11. 10. The Row Hammer tracking device of claim 9, wherein the kth field of the plurality of storage devices (k is a positive integer) stores a candidate address and an access counting value for the same bank.

12. The plurality of search controllers include:

10. The Row Hammer tracking device according to claim 9, wherein the candidate addresses and the access counting values ​​stored in the fields at the same level are read out sequentially by a clock.

13. The plurality of search controllers include:

13. The Rowhammer tracking device of claim 12, wherein the candidate addresses and the access counting values ​​stored in fields at different levels are simultaneously read out.

14. The number n of the plurality of storage devices is 10. The row hammer tracking apparatus of claim 9, wherein the row hammer tracking apparatus is set by a first active interval which is the minimum interval between active commands to the same bank.

15. The depth of each of the plurality of storage devices is: The row hammer tracking device of claim 14, set by the number of said banks.

16. The number n of the plurality of storage devices is 10. The row hammer tracking apparatus of claim 9, wherein the row hammer tracking apparatus is set by a ratio of a first active interval, which is the minimum interval between active commands to the same bank, and a second active interval, which is the minimum interval between active commands to different banks.

17. The depth of each of the plurality of storage devices is:

17. The row hammer tracking apparatus of claim 16, wherein the second active interval is set by the product of the number of banks and the second active interval.

18. The update controller includes: When the address hit signal is activated, if the access counting value of the target field is less than the Row Hammer threshold, incrementing the access counting value of the target field; 10. The row hammer tracking device of claim 9, wherein if the access counting value of the target field is equal to or greater than a row hammer threshold, the candidate address of the target field is selected as a row hammer address, and the access counting value of the target field is initialized.

19. The update controller includes: When the count hit signal is activated, Substituting the row address with a candidate address of the target field and incrementing an access counting value of the target field; 10. The row hammer tracking apparatus of claim 9, further comprising: a step of incrementing the miscounting value of the spillover counter when the count hit signal is deactivated.

20. The spillover counter comprises: a miscounting value corresponding to each of the banks is stored; The update controller 10. The row hammer tracking device of claim 9, further comprising: a miscounting value corresponding to the bank address being read.

21. A reset circuit that generates a reset signal set according to a refresh period is further provided, 10. The row hammer tracking device of claim 9, wherein the update controller initializes the miscounting value of the spillover counter and all fields of the plurality of storage devices in response to the reset signal.

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