Semiconductor unit

Abstract

To provide a semiconductor unit supporting high integration.SOLUTION: A semiconductor unit includes a first transistor and a second transistor. The first transistor includes a semiconductor layer, a pair of first conductive layers, and a pair of second conductive layers on the pair of first conductive layer. The pair of first conductive layers and the pair of second conductive layers serve as a source electrode or a drain electrode of the first transistor. A third conductive layer, which serves as a gate electrode of the second transistor, is in contact with one of the pair of first conductive layer. In cross-sectional view of the first transistor in a channel width direction, the height of the semiconductor layer is larger than the width of the semiconductor layer. The semiconductor unit can includes a capacitative element. In the case, the third conductive layer also serves as one of a pair of electrodes of the capacitative element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs, CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (including at least transistors and capacitive elements) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of transistors using oxide semiconductors. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with high operation speed.Another object of one embodiment of the present invention is to provide a memory device with low power consumption.Another object of one embodiment of the present invention is to provide a novel memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first semiconductor layer, first to fifth conductive layers, and a second insulating layer. The second transistor includes a second semiconductor layer, a sixth conductive layer, and a third insulating layer. The first semiconductor layer and the second semiconductor layer are disposed separately over a substrate. The first conductive layer and the second conductive layer are disposed over the first semiconductor layer. The third conductive layer is disposed over the first conductive layer. The fourth conductive layer is disposed over the second conductive layer. The first insulating layer is disposed over the third conductive layer, the fourth conductive layer, and the second semiconductor layer and has a first opening and a second opening. The first opening is provided to overlap with a region between the third conductive layer and the fourth conductive layer. The second opening is provided to overlap at least a portion of the second conductive layer and at least a portion of the second semiconductor layer. The second insulating layer is disposed in the first opening, overlapping the first semiconductor layer. The fifth conductive layer is disposed on the second insulating layer in the first opening. The third insulating layer is disposed in the second opening, overlapping the second semiconductor layer, and has a third opening overlapping at least a portion of the second conductive layer. The sixth conductive layer has a region that overlaps with the second semiconductor layer via the third insulating layer in the second opening, and a region that contacts at least a portion of the second conductive layer in the third opening. In a cross-sectional view in the channel width direction, the height of the first semiconductor layer is greater than the width of the first semiconductor layer.

[0013] In the above semiconductor device, the first semiconductor layer preferably has a region facing the second semiconductor layer in a cross section in a channel width direction of the second transistor.

[0014] In the above semiconductor device, the shortest distance between the first conductive layer and the second conductive layer is preferably shorter than the shortest distance between the third conductive layer and the fourth conductive layer.

[0015] In the above semiconductor device, the fifth conductive layer and the sixth conductive layer preferably have the same material.

[0016] It is preferable that the semiconductor device has a fourth insulating layer, and the fourth insulating layer has, in the first opening, a region in contact with at least a portion of the upper surface of the first conductive layer, a region in contact with at least a portion of the upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region in contact with a side surface of the fourth conductive layer.

[0017] In the above semiconductor device, it is preferable that the second transistor has seventh to tenth conductive layers, the seventh conductive layer and the eighth conductive layer are disposed on the second semiconductor layer, the ninth conductive layer is disposed on the seventh conductive layer, the tenth conductive layer is disposed on the eighth conductive layer, and the second opening is provided to overlap with a region between the ninth conductive layer and the tenth conductive layer.

[0018] Preferably, the semiconductor device has a fifth insulating layer, and the fifth insulating layer has, in the second opening, a region in contact with at least a portion of the upper surface of the seventh conductive layer, a region in contact with at least a portion of the upper surface of the eighth conductive layer, a region in contact with a side surface of the ninth conductive layer, a region in contact with a side surface of the tenth conductive layer, a side surface of the fourth conductive layer, and a region in contact with at least a portion of the upper surface of the second conductive layer.

[0019] In the above semiconductor device, each of the first conductive layer, the second conductive layer, the seventh conductive layer, and the eighth conductive layer preferably contains titanium and nitrogen.

[0020] In the above semiconductor device, the third conductive layer, the fourth conductive layer, the ninth conductive layer, and the tenth conductive layer preferably contain tungsten.

[0021] One embodiment of the present invention is a semiconductor device including a first transistor including a first semiconductor layer, a second transistor including a second semiconductor layer, a capacitor, a third semiconductor layer, and a first insulating layer. The first transistor includes first to fifth conductive layers and a second insulating layer. The second transistor includes a sixth conductive layer and a third insulating layer. The capacitor includes a seventh conductive layer, a third insulating layer, and a sixth conductive layer. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are disposed separately from each other over a substrate. The first conductive layer and the second conductive layer are disposed over the first semiconductor layer. The third conductive layer is disposed over the first conductive layer. The fourth conductive layer is disposed over the second conductive layer. The seventh conductive layer is disposed over the third semiconductor layer. The first insulating layer is disposed on the third conductive layer, the fourth conductive layer, the second semiconductor layer, and the seventh conductive layer, and has a first opening and a second opening. The first opening is disposed to overlap a region between the third conductive layer and the fourth conductive layer. The second opening is disposed to overlap at least a portion of the second conductive layer, at least a portion of the seventh conductive layer, and at least a portion of the second semiconductor layer. The second insulating layer is disposed in the first opening, overlapping the first semiconductor layer. The fifth conductive layer is disposed on the second insulating layer in the first opening. The third insulating layer is disposed in the second opening, overlapping the second semiconductor layer, and has a third opening, overlapping at least a portion of the second conductive layer. The sixth conductive layer has a region that overlaps with the second semiconductor layer through the third insulating layer in the second opening, a region that overlaps with the seventh conductive layer through the third insulating layer in the second opening, and a region that contacts at least a portion of the second conductive layer in the third opening. In a cross-sectional view in the channel width direction, the height of the first semiconductor layer is greater than the width of the first semiconductor layer.

[0022] In the above semiconductor device, in a cross-sectional view of the second transistor in the channel width direction, it is preferable that the first semiconductor layer has a region facing the second semiconductor layer, and the second semiconductor layer has a region facing the third semiconductor layer.

[0023] In the above semiconductor device, the shortest distance between the first conductive layer and the second conductive layer is preferably shorter than the shortest distance between the third conductive layer and the fourth conductive layer.

[0024] In the above semiconductor device, the fifth conductive layer and the sixth conductive layer preferably have the same material.

[0025] It is preferable that the semiconductor device has a fourth insulating layer, and the fourth insulating layer has, in the first opening, a region in contact with at least a portion of the upper surface of the first conductive layer, a region in contact with at least a portion of the upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region in contact with a side surface of the fourth conductive layer.

[0026] In the above semiconductor device, it is preferable that the second transistor has eighth to eleventh conductive layers, the eighth and ninth conductive layers are arranged on the second semiconductor layer, the tenth and eleventh conductive layers are arranged on the eighth and ninth conductive layers, respectively, and the second opening is provided so as to overlap with a region between the tenth and eleventh conductive layers.

[0027] Preferably, the semiconductor device has a fifth insulating layer, and the fifth insulating layer has, in the second opening, a region in contact with at least a portion of the upper surface of the eighth conductive layer, a region in contact with at least a portion of the upper surface of the ninth conductive layer, a region in contact with a side surface of the tenth conductive layer, a region in contact with a side surface of the eleventh conductive layer, a region in contact with a side surface of the fourth conductive layer, and a region in contact with at least a portion of the upper surface of the second conductive layer, and a region located between the sixth conductive layer and the seventh conductive layer.

[0028] In the above semiconductor device, each of the first conductive layer, the second conductive layer, the seventh conductive layer, the eighth conductive layer, and the ninth conductive layer preferably contains titanium and nitrogen.

[0029] In the above semiconductor device, the third conductive layer, the fourth conductive layer, the tenth conductive layer, and the eleventh conductive layer preferably contain tungsten.

[0030] In the above semiconductor device, it is preferable that the first semiconductor layer contains indium, is formed perpendicular or approximately perpendicular to the surface of the substrate, and when a cross-section of the first semiconductor layer is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed.

[0031] In the above semiconductor device, it is preferable that the first semiconductor layer contains indium, is formed perpendicular or approximately perpendicular to the surface of the substrate, has a first region, a second region in contact with the first region, and a third region in contact with the second region, and when a cross-section of the first semiconductor layer is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in each of the first region, the second region, and the third region.

[0032] In the above semiconductor device, it is preferable that the second region contains zinc, the second region contains crystals, and the c-axis of the crystals is approximately parallel to the normal direction to the side surface of the first semiconductor layer.

[0033] In the above semiconductor device, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region.

[0034] Another embodiment of the present invention is a semiconductor device including a first memory cell and a second memory cell. Each of the first memory cell and the second memory cell includes a first transistor, a second transistor, and a capacitor. In each of the first memory cell and the second memory cell, a gate electrode of the second transistor includes a region in contact with one of a source electrode and a drain electrode of the first transistor and a region overlapping with a lower electrode of the capacitor through a gate insulating layer of the second transistor. A semiconductor layer of the second transistor of the first memory cell extends in a channel length direction of the second transistor of the first memory cell and includes a region overlapping with a gate electrode of the second transistor of the second memory cell through a gate insulating layer of the second transistor of the second memory cell. In a cross-sectional view of the second transistor in the channel width direction, the height of the semiconductor layer is greater than the width of the semiconductor layer.

[0035] In the above-mentioned semiconductor device, in each of the first memory cell and the second memory cell, one of the source electrode and the drain electrode of the first transistor preferably has a first conductive layer and a second conductive layer on the first conductive layer, and the other of the source electrode and the drain electrode of the first transistor preferably has a third conductive layer and a fourth conductive layer on the third conductive layer, and the shortest distance between the first conductive layer and the third conductive layer is preferably shorter than the shortest distance between the second conductive layer and the fourth conductive layer.

[0036] In the semiconductor device, in each of the first memory cell and the second memory cell, the gate electrode of the second transistor preferably has a region in contact with an upper surface of the first conductive layer of the first transistor.

[0037] In the above semiconductor device, it is preferable that the semiconductor layer contains indium, the semiconductor layer is formed perpendicular or approximately perpendicular to the surface of the substrate, and when a cross-sectional view of the semiconductor layer is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed.

[0038] In the above semiconductor device, it is preferable that the semiconductor layer contains indium, is formed perpendicular or approximately perpendicular to the surface of the substrate, has a first region, a second region in contact with the first region, and a third region in contact with the second region, and when a cross-section of the semiconductor layer is observed using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in each of the first region, the second region, and the third region.

[0039] In the above semiconductor device, it is preferable that the second region contains zinc, the second region contains crystals, and the c-axes of the crystals are approximately parallel to the normal direction to the side surface of the semiconductor layer.

[0040] In the above semiconductor device, it is preferable that the indium content in the first region is higher than the indium content in the second region, and the indium content in the third region is higher than the indium content in the second region. [Effects of the Invention]

[0041] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to another embodiment of the present invention, a highly reliable semiconductor device can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to another embodiment of the present invention, a novel semiconductor device can be provided. According to another embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to another embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0042] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with high operation speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0043] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief explanation of the drawings]

[0044] [Figure 1] Fig. 1A is a plan view showing a configuration example of a semiconductor device, and Figs. 1B to 1D are cross-sectional views showing the configuration example of the semiconductor device. [Figure 2] Fig. 2A is a plan view showing an example of the configuration of a semiconductor device, and Figs. 2B to 2D are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 3] 3A to 3C are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 4] 4A to 4C are plan views showing configuration examples of semiconductor devices. [Figure 5] 5A to 5C are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 7] 7A to 7D are cross-sectional views illustrating an example of a method for forming an oxide semiconductor layer. [Figure 8] 8A to 8D are cross-sectional views illustrating examples of oxide semiconductor layers. [Figure 9] 9A to 9C are cross-sectional views showing examples of semiconductor layers. [Figure 10]10A to 10C are cross-sectional views showing examples of the configuration of a semiconductor device. [Figure 11] 11A is a plan view showing an example of the configuration of a semiconductor device, and FIG. 11B is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 12] Fig. 12(A) is a plan view showing a configuration example of a semiconductor device, and Fig. 12(B) to Fig. 12(D) are cross-sectional views showing a configuration example of a semiconductor device. [Figure 13] Fig. 13(A) is a plan view showing an example of the configuration of a semiconductor device, and Fig. 13(B) and Fig. 13(C) are cross-sectional views showing an example of the configuration of a semiconductor device. [Figure 14] 14(A) and 14(B) are perspective views showing configuration examples of a semiconductor device. [Figure 15] Fig. 15(A) is a plan view showing a configuration example of a semiconductor device, and Fig. 15(B) to Fig. 15(D) are cross-sectional views showing a configuration example of a semiconductor device. [Figure 16] 16A is a plan view showing an example of the configuration of a semiconductor device, and FIG. 16B is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 17] 17A is a plan view showing an example of the configuration of a semiconductor device, and FIG. 17B is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 18] 18A and 18B are plan and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 19] 19A and 19B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 20] 20A and 20B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 21] 21A and 21B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 22]22A and 22B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 23] 23A and 23B are plan and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 24] 24A and 24B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 25] 25A and 25B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 26] 26A and 26B are plan and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 27] 27A and 27B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 28] 28A and 28B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 29] 29A and 29B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 30] 30A and 30B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 31] 31A and 31B are plan views and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 32] Fig. 32A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 32B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. [Figure 33]Fig. 33A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 33B is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. [Figure 34] 34A and 34B are plan and cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 35] FIG. 35 is a plan view showing a configuration example of a semiconductor device. [Figure 36] 36(A) is a plan view showing an example of the configuration of a semiconductor device, and FIG. 36(B) is a cross-sectional view showing an example of the configuration of a semiconductor device. [Figure 37] FIG. 37 is a plan view showing a configuration example of a semiconductor device. [Figure 38] FIG. 38 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 39] 39A to 39H are diagrams illustrating examples of circuit configurations of memory cells. [Figure 40] FIG. 40 is a diagram illustrating an example of a circuit configuration of a semiconductor device. [Figure 41] FIG. 41 is a timing chart showing an example of a method for driving a semiconductor device. [Figure 42] 42A and 42B are perspective views illustrating a configuration example of a semiconductor device. [Figure 43] FIG. 43 is a block diagram illustrating the CPU. [Figure 44] FIG. 44 is a block diagram illustrating the CPU. [Figure 45] 45(A) and 45(B) are perspective views of the semiconductor device. [Figure 46] 46(A) and 46(B) are perspective views of the semiconductor device. [Figure 47] 47(A) and 47(B) are diagrams illustrating the hierarchy of memory devices in a semiconductor device. [Figure 48] 48(A) and 48(B) are diagrams showing an example of electronic equipment, and FIGS. 48(C) to 48(E) are diagrams showing an example of a mainframe computer. [Figure 49] FIG. 49 is a diagram showing an example of space equipment. [Figure 50] FIG. 50 is a diagram illustrating an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE INVENTION

[0045] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0046] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0047] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0048] In order to facilitate understanding of the invention, particularly in plan views or perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0049] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers attached to components in one part of this specification may not match the ordinal numbers attached to the same components in other parts of this specification or in the claims.

[0050] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0051] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0052] Although the drawings used in the embodiments in this specification show the case where the sidewall of the insulating layer in the opening portion of the insulating layer is perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulating layer is formed, the sidewall may have a tapered shape.

[0053] In this specification and the like, the opening also includes, for example, a groove, a slit, and the like.

[0054] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0055] In this specification, "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in the manufacturing process of a memory device, a planarization process (typically a CMP (Chemical Mechanical Polishing) process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, in the case of two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, and this is also referred to as "having the same or approximately the same height."

[0056] In this specification, "side edges that coincide or approximately coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or approximately coincide" is also used.

[0057] (Embodiment 1) In this embodiment, a semiconductor device including an oxide semiconductor layer and a manufacturing method of the semiconductor device will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, a memory cell of a memory device described later.

[0058] <Configuration Example 1 of Semiconductor Device> A structural example of a semiconductor device will be described with reference to Fig. 1 and Fig. 2. Fig. 1A to Fig. 1D and Fig. 2A to Fig. 2D are plan views and cross-sectional views of a semiconductor device including a transistor.

[0059] FIG. 1(A) is a plan view of a semiconductor device. FIGS. 1(B) to 1(D) are cross-sectional views of the semiconductor device. FIG. 1(B) is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 1(A). FIG. 1(C) is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 1(A). FIG. 1(D) is a cross-sectional view of a portion indicated by the dashed-dotted line B1-B2 in FIG. 1(A). The dashed-dotted line B1-B2 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. In the plan view of FIG. 1(A), some elements are omitted for clarity, and some elements are shown transparently.

[0060] Figures 2(A) to 2(D) correspond to Figures 1(A) to 1(D), respectively, and show the positions of openings provided in the insulating layer.

[0061] 1 includes an insulating layer 215 over a substrate (not shown), an insulating layer 216 over the insulating layer 215, an insulating layer 221 over the insulating layer 216, an insulating layer 222 over the insulating layer 221, a transistor 200a and a transistor 200b over the insulating layer 222, an insulating layer 275, and an insulating layer 280. An insulating layer 282 is provided over the transistor 200a and the transistor 200b, an insulating layer 283 is provided over the insulating layer 282, and an insulating layer 285 is provided over the insulating layer 283.

[0062] The transistor 200a includes a semiconductor layer 230a over the insulating layer 222, conductive layers 242a and 242b over the semiconductor layer 230a and the insulating layer 222, an insulating layer 255a over the conductive layer 242a and the conductive layer 242b, an insulating layer 250a over the semiconductor layer 230a and the insulating layer 255a, and a conductive layer 260a over the insulating layer 250a. The conductive layer 242a includes a conductive layer 242a1 and a conductive layer 242a2 over the conductive layer 242a1. The conductive layer 242b includes a conductive layer 242b1 and a conductive layer 242b2 over the conductive layer 242b1. In FIG. 1B, the conductive layer 260a has a two-layer structure.

[0063] The transistor 200b includes a semiconductor layer 230b over the insulating layer 222, conductive layers 242c and 242d over the semiconductor layer 230b and the insulating layer 222, an insulating layer 255b over the conductive layer 242c and the conductive layer 242d, an insulating layer 250b over the semiconductor layer 230b and the insulating layer 255b, and a conductive layer 260b over the insulating layer 250b. The conductive layer 242c includes a conductive layer 242c1 and a conductive layer 242c2 over the conductive layer 242c1. The conductive layer 242d includes a conductive layer 242d1 and a conductive layer 242d2 over the conductive layer 242d1. In FIGS. 1C and 1D, the conductive layer 260b has a two-layer structure.

[0064] An insulating layer 275 is provided over the conductive layers 242a to 242d, and an insulating layer 280 is provided over the insulating layer 275. An opening 291a and an opening 291b are formed in the insulating layer 280 and the insulating layer 275 (see FIGS. 2A to 2D). The opening 291a overlaps with a region between the conductive layer 242a2 and the conductive layer 242b2. The opening 291a overlaps with at least a part of the semiconductor layer 230a. The opening 291b overlaps with a region between the conductive layer 242c2 and the conductive layer 242d2. The opening 291b overlaps with at least a part of the conductive layer 242b1 and at least a part of the semiconductor layer 230b.

[0065] Insulating layer 255a is disposed in opening 291a. Insulating layer 255a has, in opening 291a, a region in contact with a side surface of insulating layer 280, a region in contact with a side surface of insulating layer 275, a region in contact with a side surface of conductive layer 242a2, a region in contact with a side surface of conductive layer 242b2, a region in contact with the top surface of conductive layer 242a1, and a region in contact with the top surface of conductive layer 242b1.

[0066] An opening 292a reaching the semiconductor layer 230a is formed in the insulating layer 255a (see FIGS. 2A and 2B). The opening 292a is provided so as to overlap with a region between the conductive layer 242a1 and the conductive layer 242b1. Note that the opening 292a is provided in a region overlapping with the opening 291a. Therefore, the opening 291a and the opening 292a can be regarded as one opening. Thus, the opening (the opening including the opening 291a and the opening 292a) may be referred to as an opening 290a.

[0067] The insulating layer 250a and the conductive layer 260a are disposed in the opening 290a. The insulating layer 250a contacts the semiconductor layer 230a in the opening 290a. In the opening 290a, the insulating layer 250a has a region in contact with a side surface of the insulating layer 255a, a region in contact with a side surface of the conductive layer 242a1, and a region in contact with a side surface of the conductive layer 242b1.

[0068] The insulating layer 255b is disposed in the opening 291b. In the opening 291b, the insulating layer 255b has a region in contact with a side surface of the insulating layer 280, a region in contact with a side surface of the insulating layer 275, a region in contact with a side surface of the conductive layer 242c2, a region in contact with a side surface of the conductive layer 242d2, a region in contact with the top surface of the conductive layer 242c1, and a region in contact with the top surface of the conductive layer 242d1. In addition, in the opening 291b, the insulating layer 255b has a region in contact with a side surface of the insulating layer 280, a region in contact with a side surface of the insulating layer 275, a region in contact with a side surface of the conductive layer 242b2, and a region in contact with a portion of the top surface of the conductive layer 242b1.

[0069] An opening 292b reaching the semiconductor layer 230b is formed in the insulating layer 255b (see FIGS. 2A, 2C, and 2D). The opening 292b is provided so as to overlap with a region between the conductive layer 242c1 and the conductive layer 242d1.

[0070] The insulating layer 250b is disposed in the openings 291b and 292b. The insulating layer 250b contacts the semiconductor layer 230b at the openings 291b and 292b. The insulating layer 250b has a region in contact with a side surface of the insulating layer 255b, a region in contact with a side surface of the conductive layer 242c1, and a region in contact with a side surface of the conductive layer 242d1 at the openings 291b and 292b.

[0071] An opening 293 reaching the conductive layer 242b1 is formed in the insulating layer 255b and the insulating layer 250b (see FIGS. 2A, 2B, and 2D). Note that the opening 292b and the opening 293 are provided in a region overlapping with the opening 291b. Therefore, the opening 291b, the opening 292b, and the opening 293 can be regarded as one opening. Therefore, the opening (the opening including the opening 291b, the opening 292b, and the opening 293) may be referred to as an opening 290b.

[0072] The conductive layer 260b is disposed in the opening 290b. The conductive layer 260b has a region in contact with the side surface of the insulating layer 250b and a region in contact with the top surface of the conductive layer 242b1 in the opening 290b.

[0073] The semiconductor layer 230a has a region that functions as a channel formation region of the transistor 200a. The conductive layer 260a has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200a. The insulating layer 250a has a region that functions as a first gate insulating layer of the transistor 200a. The conductive layer 242a has a region that functions as one of a source electrode and a drain electrode of the transistor 200a. The conductive layer 242b has a region that functions as the other of the source electrode and the drain electrode of the transistor 200a. Note that FIG. 1B can also be said to be a cross-sectional view of the transistor 200a in the channel length direction.

[0074] The semiconductor layer 230b has a region that functions as a channel formation region of the transistor 200b. The conductive layer 260b has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200b. The insulating layer 250b has a region that functions as a first gate insulating layer of the transistor 200b. The conductive layer 242c has a region that functions as one of a source electrode and a drain electrode of the transistor 200b. The conductive layer 242d has a region that functions as the other of the source electrode and the drain electrode of the transistor 200b. Note that FIG. 1C can also be said to be a cross-sectional view of the transistor 200b in the channel length direction. FIG. 1D can also be said to be a cross-sectional view of the transistor 200b in the channel width direction.

[0075] The conductive layer 260b is in contact with the conductive layer 242b1. That is, the other of the source electrode and the drain electrode of the transistor 200a is electrically connected to the gate electrode of the transistor 200b. With this structure, it is not necessary to provide an electrode for connecting the other of the source electrode and the drain electrode of the transistor 200a to the gate electrode of the transistor 200b, and the semiconductor device can be formed without reducing the transistor density. Therefore, the integration degree of the semiconductor device can be increased, and the memory capacity can be increased. Furthermore, the number of steps in the manufacturing process of the semiconductor device can be reduced.

[0076] With the above structure, the other of the source and the drain of the transistor 200a can be electrically connected to the gate of the transistor 200b, thereby forming a memory cell including two transistors (also referred to as a 2T0C memory cell).

[0077] An insulating layer 282 is provided on the insulating layer 280, the insulating layer 255a, the insulating layer 250a, the conductive layer 260a, the insulating layer 255b, the insulating layer 250b, and the conductive layer 260b.

[0078] An insulating layer 241a is provided in contact with the inner walls of the openings formed in the insulating layers 285, 283, 282, 280, and 275, and a conductive layer 240a is provided in contact with the side surfaces of the insulating layer 241a. The lower surface of the conductive layer 240a is in contact with the upper surface of the conductive layer 242a2. An insulating layer 241b is provided in contact with the inner walls of the openings formed in the insulating layers 285, 283, 282, 280, and 275, and a conductive layer 240b is provided in contact with the side surfaces of the insulating layer 241b. The lower surface of the conductive layer 240b is in contact with the upper surface of the conductive layer 242c2. Furthermore, an insulating layer 241c is provided in contact with the inner walls of the openings formed in the insulating layer 285, the insulating layer 283, the insulating layer 282, the insulating layer 280, and the insulating layer 275, and a conductive layer 240c is provided in contact with the side surface of the insulating layer 241c. The lower surface of the conductive layer 240c is in contact with the upper surface of the conductive layer 242d2.

[0079] The conductive layer 240a functions as a plug connecting to the conductive layer 242a. The conductive layer 240b functions as a plug connecting to the conductive layer 242c. The conductive layer 240c functions as a plug connecting to the conductive layer 242d.

[0080] [Transistor 200a] Here, a structural example of the transistor 200a will be described. FIG. 3A shows an enlarged view of the conductive layer 260a and its vicinity in FIG. 1B. FIG. 3B shows an enlarged cross-sectional view of the transistor 200a in the channel width direction, showing the semiconductor layer 230a and its vicinity. Note that since the transistor 200a has a similar structure to the transistor 200b, FIG. 1D can be referred to for the cross-sectional view of the transistor 200a in the channel width direction.

[0081] The semiconductor layer 230a is formed on and in contact with the insulating layer 222. As shown in Fig. 3(B), the semiconductor layer 230a has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. For this reason, the semiconductor layer 230a can also be said to have a fin-like shape.

[0082] Here, the aspect ratio of the semiconductor layer 230a in a cross-sectional view in the channel width direction refers to the ratio of the length L of the semiconductor layer 230a in the B3-B4 direction (which can also be referred to as the width L of the semiconductor layer 230a) to the length H of the semiconductor layer 230a in a direction perpendicular to the surface on which the semiconductor layer 230a is to be formed (e.g., the insulating layer 222) (which can also be referred to as the height H of the semiconductor layer 230a). The aspect ratio of the semiconductor layer 230a is preferably as large as possible without causing the semiconductor layer 230a to collapse during the manufacturing process of the transistor 200a. In the semiconductor layer 230a, the height H of the semiconductor layer 230a is at least longer than the width L of the semiconductor layer 230a. The height H of the semiconductor layer 230a is set to be greater than 1 time and less than 400 times, preferably between 2 times and 100 times, more preferably between 5 times and 40 times, and even more preferably between 10 times and 20 times. For example, the height H can be between 2 times and 10 times the width L. For example, the width L can be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 30 nm. Furthermore, for example, the height H can be 50 nm to 2000 nm, and preferably 100 nm to 1000 nm. Furthermore, for example, the height H may be 50 nm to 100 nm. By setting the aspect ratio of the semiconductor layer 230a within the above range, the insulating layer 255a, the insulating layer 250a, the conductive layer 260a, the conductive layer 242a, the conductive layer 242b, the conductive layer 240a, and the like can be provided so as to cover the semiconductor layer 230a with good coverage.

[0083] 3(B), in a cross-sectional view in the channel width direction, the angle θ between the side surface of the semiconductor layer 230a and the top surface of the insulating layer 222 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, and more preferably 85° to 95°.

[0084] An insulating layer 250a, a conductive layer 260a, a conductive layer 242a, and a conductive layer 242b are provided to cover the semiconductor layer 230a having such a high aspect ratio. In the transistor 200a, as shown in FIG. 3B, the insulating layer 250a and a portion of the conductive layer 260a are provided so as to sandwich the semiconductor layer 230a in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 230a and the conductive layer 260a are provided facing each other with the insulating layer 250a sandwiched between the upper portion, the side surface on the B3 side, and the side surface on the B4 side of the semiconductor layer 230a. In other words, the upper portion, the side surface on the B3 side, and the side surface on the B4 side of the semiconductor layer 230a each function as a channel formation region. Therefore, compared to when the semiconductor layer 230a is formed in a flat plate shape, the channel width of the transistor 200a is increased by the height H of the side surface on the B3 side and the height H of the side surface on the B4 side of the semiconductor layer 230a.

[0085] The increased channel width as described above can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200a. This allows a semiconductor device with high operating speed to be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the semiconductor layer 230a, the channel width can be increased without increasing the area occupied by the transistor 200a. This allows for miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by increasing the area where the side surfaces of the conductive layer 260a and the semiconductor layer 230a face each other, the threshold voltage can be easily controlled, and the transistor 200a can be normally off.

[0086] Furthermore, as shown in FIG. 3B and other figures, the upper portion of the semiconductor layer 230a may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulating layer 250a, the conductive layer 242a, and the conductive layer 242b near the upper portion of the semiconductor layer 230a. Note that in FIG. 3B, a symmetrical structure is shown in which curved shapes are provided on both the B3 side and the B4 side of the upper portion of the semiconductor layer 230a, but the present invention is not limited to this. For example, an asymmetrical structure may also be used in which a curved shape is provided on one of the B3 side and the B4 side of the upper portion of the semiconductor layer 230a.

[0087] Because the semiconductor layer 230a has a high aspect ratio, it is preferably formed in the shape of a sidewall on the side surface of the pillar (the insulating layer 223a described later). Therefore, it is preferable to form the semiconductor layer 230a using the atomic layer deposition (ALD) method, which has good coverage. Furthermore, when the semiconductor layer 230a has a laminated structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0088] Since the semiconductor layer 230a is formed in a sidewall shape in contact with the pillar, as shown in FIG. 1A, the top surface shape of the semiconductor layer 230a is a circumferential shape (which can also be called a frame shape, annular shape, doughnut shape, or closed curve shape) with both ends coinciding. The semiconductor layer 230a can also be said to have a shape with an opening in the center. Note that in FIG. 1A, the top surface shape of the semiconductor layer 230a is symmetrical about the dashed dotted line B3-B4, but the present invention is not limited to this. For example, the top surface shape of the semiconductor layer 230a may be asymmetrical.

[0089] Although the above description has been given of a configuration in which the transistor 200a has one circumferential semiconductor layer 230a, the present invention is not limited to this. For example, the transistor 200a may have two or more circumferential semiconductor layers 230a. For example, as shown in FIG. 4A, two pillars may be arranged in the B3-B4 direction, and the circumferential semiconductor layer 230a may be formed in contact with the side surface of each pillar. Note that the transistor 200b is omitted from FIG. 4A.

[0090] 1A and 4A, the semiconductor layer 230a preferably overlaps with the conductive layer 260a at two or more locations in a plan view. That is, the transistor 200a preferably has two or more regions where the semiconductor layer 230a and the conductive layer 260a overlap. With such a structure, a plurality of fin-shaped semiconductor layers 230a are formed in a cross-sectional view in the channel width direction. Each of the plurality of fin-shaped semiconductor layers 230a functions as a channel formation region. That is, the transistor 200a functions as a multi-channel transistor. Therefore, the channel width of the transistor 200a can be further increased.

[0091] Furthermore, by forming the semiconductor layers 230a in a sidewall shape in contact with the side surfaces of the pillars, the semiconductor layers 230a can be formed simultaneously, as shown in FIG. 4A. By forming the semiconductor layers 230a in this manner, the distance between the semiconductor layers 230a can be set according to the size and shape of the pillars. Therefore, the distance between the semiconductor layers 230a can be reduced, the area occupied by the transistor 200a can be reduced, and the semiconductor device can be highly integrated.

[0092] Furthermore, the semiconductor layer 230a may be formed into a shape having multiple openings by combining the circumferential semiconductor layers 230a. For example, as shown in FIG. 4(B), the semiconductor layer 230a may have a shape in which three openings are arranged in the B3-B4 direction in a plan view. In this case, three pillars may be formed adjacent to each other at a short distance, and the semiconductor layer 230a may be formed in a sidewall shape in contact with the three pillars. In this case, a portion of the semiconductor layer 230a is provided between the pillars. Furthermore, as shown in FIG. 4(C), the semiconductor layer 230a may have a lattice shape in a plan view. In this case, lattice-shaped trenches may be formed in the pillars, and the semiconductor layer 230a may be formed to fill the trenches. Note that the number of semiconductor layers 230a is not limited to one, and two or more may be provided. In this way, it is preferable that the semiconductor layer 230a has a structure having a plurality of portions extending in the channel width direction (B3-B4 direction) and a plurality of portions extending in the channel length direction (A1-A2 direction). This makes it possible to prevent the semiconductor layer 230a from collapsing during the transistor fabrication process when the semiconductor layer 230a has a high aspect ratio structure.

[0093] The conductive layer 242a and the conductive layer 242b are spaced apart from each other and are provided in contact with the semiconductor layer 230a. As shown in FIG. 3C and other figures, the conductive layer 242a and the conductive layer 242b are provided so as to cover the semiconductor layer 230a, which has a high aspect ratio. Preferably, each of the conductive layer 242a and the conductive layer 242b is in contact with two or more fin-shaped semiconductor layers 230 in a cross-sectional view, as shown in FIG. 1D and other figures.

[0094] Here, as shown in FIG. 3C, near the source or drain of the transistor 200a, the conductive layer 242a is provided so as to be folded in half with the semiconductor layer 230a sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductive layer 242a contacts the semiconductor layer 230a at the top, the side surface on the B3 side, and the side surface on the B4 side of the semiconductor layer 230a. Therefore, compared to when the semiconductor layer 230a is formed in a flat plate shape, the contact area between the conductive layer 242a and the semiconductor layer 230a is increased by the height H of the side surface on the B3 side and the height H of the side surface on the B4 side of the semiconductor layer 230a. Furthermore, by using a structure in which the semiconductor layer 230a and the conductive layer 242a are in contact with multiple fin-shaped semiconductor layers 230a as shown in FIG. 1A, the contact area can be further increased. Note that while FIGS. 3C and 1A show the vicinity of the conductive layer 242a, the same applies to the conductive layer 242b. That is, similar to the above-described conductive layer 242a and semiconductor layer 230a, the contact area between the conductive layer 242b and semiconductor layer 230a is large.

[0095] As described above, by increasing the contact area between the conductive layer 242a and the semiconductor layer 230a and the contact area between the conductive layer 242b and the semiconductor layer 230a, the on-state current, frequency characteristics, and the like of the transistor 200a can be improved without increasing the area occupied by the transistor 200a. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0096] As shown in FIG. 1B, the conductive layer 242a has a stacked structure of a conductive layer 242a1 and a conductive layer 242a2 on the conductive layer 242a1, and the conductive layer 242b has a stacked structure of a conductive layer 242b1 and a conductive layer 242b2 on the conductive layer 242b1. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as the layers in contact with the semiconductor layer 230a (the conductive layers 242a1 and 242b1). This can suppress a decrease in the conductivity of the conductive layers 242a and 242b. Furthermore, it can suppress the extraction of oxygen from the semiconductor layer 230a, thereby suppressing the formation of excessive oxygen vacancies. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen as the layers in contact with the semiconductor layer 230a (the conductive layers 242a1 and 242b1), because this can reduce the hydrogen concentration in the semiconductor layer 230a.

[0097] For the conductive layer 242a1 and the conductive layer 242b1, a metal nitride is preferably used, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or that maintain conductivity even when absorbing oxygen.

[0098] The conductive layers 242a2 and 242b2 preferably have higher conductivity than the conductive layers 242a1 and 242b1. For example, the thicknesses of the conductive layers 242a2 and 242b2 are preferably larger than the thicknesses of the conductive layers 242a1 and 242b1. A conductor that can be used for the conductive layer 260b (described later) may be used for the conductive layers 242a2 and 242b2. The above structure can reduce the resistance of the conductive layers 242a2 and 242b2. This can increase the on-state current of the transistor 200a and improve the operating speed of the semiconductor device according to this embodiment.

[0099] For example, the conductive layers 242a1 and 242b1 can be formed using tantalum nitride or titanium nitride, and the conductive layers 242a2 and 242b2 can be formed using tungsten.

[0100] 1B, in a cross-sectional view of the transistor 200a in the channel length direction, the conductive layers 242a1 and 242b1 protrude toward the opening 292a beyond the conductive layers 242a2 and 242b2, respectively. The protruding portions of the conductive layers 242a1 and 242b1 are covered with the insulating layer 250a. The shortest distance between the conductive layers 242a1 and 242b1 is shorter than the shortest distance between the conductive layers 242a2 and 242b2. This structure enables the source-drain distance to be shortened, thereby shortening the channel length.

[0101] The shortest distance between the conductive layer 242a1 and the conductive layer 242b1 is preferably small because it affects the channel length of the transistor 200a. For example, the shortest distance is preferably 1 nm to 60 nm, more preferably 1 nm to 50 nm, even more preferably 2 nm to 50 nm, even more preferably 2 nm to 30 nm, and even more preferably 2 nm to 20 nm. This configuration allows the distance between the source and drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200a. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0102] In the transistor 200a shown in FIG. 3A, the opposing side surfaces of the conductive layer 242a1 and the conductive layer 242b1 are substantially perpendicular to the top surface of the semiconductor layer 230a, but the present invention is not limited to this. For example, as shown in FIG. 5A, the opposing side surfaces of the conductive layer 242a1 and the conductive layer 242b1 may have a tapered shape. With such a shape, the distance between the conductive layer 260a and the semiconductor layer 230a is reduced near the side ends of the conductive layer 242a1 and the conductive layer 242b1, thereby reducing the influence of the Loff region.

[0103] As shown in FIG. 5B, the opposing side surfaces of the conductive layers 242a1 and 242b1 may be tapered, and the opposing side surfaces of the conductive layers 242a2 and 242b2 may also be tapered.

[0104] 5(C), the taper angle of the conductive layer 242a1 may be made more acute than the taper angle of the conductive layer 242a2, and the taper angle of the conductive layer 242b1 may be made more acute than the taper angle of the conductive layer 242b2. With this shape, the distance between the conductive layer 260a and the semiconductor layer 230a becomes smaller near the side ends of the conductive layer 242a1 and the conductive layer 242b1, thereby reducing the influence of the Loff region.

[0105] 1B, the conductive layer 260a is disposed in the opening 290a. In the opening 290a, the conductive layer 260a is provided so as to cover the top surface of the insulating layer 222, the side surface of the semiconductor layer 230a, and the top surface of the semiconductor layer 230a via the insulating layers 255a and 250a. The top surface of the conductive layer 260a is disposed so as to be flush or approximately flush with the top of the insulating layer 255a, the top of the insulating layer 250a, and the top surface of the insulating layer 280.

[0106] The sidewalls of the opening 290a may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may be tapered. Tapering the sidewalls improves the coverage of the insulating layer 250a and the like provided in the opening 290a, and reduces defects such as voids.

[0107] The conductive layer 260a can be provided to extend in the channel width direction. With this structure, when a plurality of transistors 200a are provided, the conductive layer 260a functions as a wiring.

[0108] A portion of the conductive layer 260a is provided so as to be folded in half, sandwiching the fin-shaped semiconductor layer 230a. As a result, as shown in FIG. 3B, in a cross-sectional view in the channel width direction, the semiconductor layer 230a and the conductive layer 260a are provided facing each other across the insulating layer 250a at the top, the side surface on the B3 side, and the side surface on the B4 side of the semiconductor layer 230a. In other words, the top, the side surface on the B3 side, and the side surface on the B4 side of the semiconductor layer 230a each function as a channel formation region. Therefore, compared to when the semiconductor layer 230a is formed in a flat plate shape, the channel width of the transistor 200a is increased by the height H of the side surface on the B3 side and the height H of the side surface on the B4 side of the semiconductor layer 230a.

[0109] 1B and the like, the conductive layer 260a is shown as having a two-layer structure. Here, the conductive layer 260a preferably includes a conductive layer 260a1 and a conductive layer 260a2 disposed over the conductive layer 260a1. For example, the conductive layer 260a1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260a2. In this case, the conductive layer 260a1 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion.

[0110] The conductive layer 260a1 is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0111] Furthermore, since the conductive layer 260a1 has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 260a2 caused by oxygen contained in the insulating layer 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0112] The conductive layer 260a2 is preferably made of a conductor with high conductivity. For example, the conductive layer 260a2 can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 260a2 may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0113] In the transistor 200a, the conductive layer 260a is formed in a self-aligned manner to fill the opening 290a. Here, the side surfaces of the insulating layer 280 in the opening 290a coincide or substantially coincide with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. Therefore, the conductive layer 260a can be arranged to overlap the region between the conductive layer 242a and the conductive layer 242b without alignment.

[0114] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. O H) may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and V O It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in an oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0115] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor may decrease. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, and the conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0116] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type.O It is preferable to reduce H in the source and drain regions. O It is preferable to prevent the amount of H from being excessively reduced. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 260a, the conductive layer 242a, the conductive layer 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 260a, the conductive layer 242a, the conductive layer 242b, and the like. Note that hydrogen in the oxide semiconductor is V O H can be formed, so V O To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0117] Therefore, in this embodiment, the semiconductor device has a structure in which the hydrogen concentration in the channel formation region is reduced, the oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260a is suppressed, and the reduction in the hydrogen concentration in the source region and the drain region is suppressed.

[0118] The insulating layer 255a is formed in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2. The insulating layer 255a preferably has a barrier property against oxygen. The insulating layer 255a is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 255a having a barrier property against oxygen can prevent the side surfaces of the conductive layer 242a2 and the conductive layer 242b2 from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200a.

[0119] Furthermore, the insulating layer 255a is formed in contact with the side surfaces of the conductive layer 242a2 and the conductive layer 242b2, and functions to protect the conductive layer 242a2 and the conductive layer 242b2. Therefore, after the conductive layer 242a2 and the conductive layer 242b2 are formed and before the insulating film (insulating film 250P described later) that will become the insulating layer 250a and the insulating layer 250b is formed, heat treatment may be performed in an atmosphere containing oxygen. At this time, excessive oxidation of the conductive layer 242a2 and the conductive layer 242b2 can be prevented.

[0120] Silicon nitride has a barrier property against oxygen and can therefore be suitably used as the insulating layer 255a.

[0121] Furthermore, in this embodiment, an insulating layer 255a is provided between the insulating layer 250a and the conductive layer 242a2 and between the insulating layer 250a and the conductive layer 242b2. This allows the distance between the conductive layer 260a and the conductive layer 242a2 and the distance between the conductive layer 260a and the conductive layer 242b2 to be increased by the thickness of the insulating layer 255a. Therefore, the thickness of the insulating layer 250a can be reduced to reduce the Loff region while reducing the parasitic capacitance generated between the conductive layer 260a and the conductive layer 242a2 and the parasitic capacitance generated between the conductive layer 260a and the conductive layer 242b2.

[0122] The thickness of the insulating layer 255a is preferably thicker than any one of the insulating layers 250a1 to 250a4 described below. The thickness of the insulating layer 255a is preferably 1 nm to 20 nm, more preferably 1 nm to 15 nm, and even more preferably 3 nm to 10 nm. For example, the thickness can be approximately 5 nm. By setting the insulating layer 255a to the above thickness, the distance between the conductive layer 260a and the conductive layer 242a2 or the conductive layer 242b2 can be increased, and parasitic capacitance can be reduced. Note that it is sufficient that at least a portion of the insulating layer 255a has a region with the above thickness. Furthermore, since the insulating layer 255a is provided in the opening 290a, it is preferable to form the insulating layer 255a by using an ALD method or the like, which has good coverage.

[0123] The insulating layer 250a in contact with the channel formation region of the semiconductor layer 230a preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 230a. Therefore, the V O By reducing H, the channel forming region can be made i-type or substantially i-type.

[0124] 3A, the insulating layer 250a preferably has a stacked structure of an insulating layer 250a1 in contact with the semiconductor layer 230a, an insulating layer 250a2 on the insulating layer 250a1, an insulating layer 250a3 on the insulating layer 250a2, and an insulating layer 250a4 on the insulating layer 250a3. In this case, the insulating layer 250a1 and the insulating layer 250a3 preferably have a function of capturing or fixing hydrogen.

[0125] Examples of insulators capable of capturing or fixing hydrogen include metal oxides with an amorphous structure. For the insulating layer 250a1 and the insulating layer 250a3, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, which may have the property of capturing or fixing hydrogen through the dangling bonds. In other words, metal oxides with an amorphous structure have a high ability to capture or fix hydrogen.

[0126] Furthermore, it is preferable to use a high-dielectric-constant (high-k) material for the insulating layer 250a1 and the insulating layer 250a3. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulating layer 250a1 and the insulating layer 250a3, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0127] For the insulating layer 250a1 and the insulating layer 250a3, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0128] In this embodiment, an aluminum oxide film is used as the insulating layer 250a1. The aluminum oxide film preferably has an amorphous structure. By providing the insulating layer 250a1 in contact with the semiconductor layer 230a, hydrogen contained in the semiconductor layer 230a and the like can be more effectively captured and fixed.

[0129] In the present embodiment, hafnium oxide is used as insulating layer 250a3. By providing insulating layer 250a3 between insulating layer 250a2 and insulating layer 250a4, hydrogen contained in insulating layer 250a2 and the like can be more effectively captured and fixed.

[0130] Next, insulating layer 250a2 is preferably made of a thermally stable insulator such as silicon oxide or silicon oxynitride. In this specification, oxynitride refers to a material whose composition contains more oxygen than nitrogen, and nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0131] The silicon oxide film used as the insulating layer 250a2 is preferably formed using the PEALD (Plasma Enhanced ALD) method.

[0132] In order to suppress oxidation of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260a, an insulating layer using an oxygen barrier insulator is preferably provided near each of the conductive layer 242a, the conductive layer 242b, and the conductive layer 260a. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 250a1, the insulating layer 250a4, the insulating layer 250a3, and the insulating layer 275.

[0133] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties means having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0134] Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulating layer 250a1, the insulating layer 250a3, the insulating layer 250a4, and the insulating layer 275 each preferably have a single-layer structure or a multilayer structure of the above-mentioned oxygen barrier insulators.

[0135] The insulating layer 250a1 preferably has a barrier property against oxygen. The insulating layer 250a1 is preferably at least less permeable to oxygen than the insulating layer 280. The insulating layer 250a1 has a region in contact with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. The insulating layer 250a1 has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200a.

[0136] The insulating layer 250a1 is provided in contact with the upper surface and side surfaces of the semiconductor layer 230a and the upper surface of the insulating layer 222. The insulating layer 250a1 has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the semiconductor layer 230a when heat treatment or the like is performed. This can reduce the formation of oxygen vacancies in the semiconductor layer 230a.

[0137] Furthermore, by providing the insulating layer 250a1, it is possible to prevent an excessive amount of oxygen from being supplied from the insulating layer 280 to the semiconductor layer 230a, and to supply an appropriate amount of oxygen to the semiconductor layer 230a. Therefore, it is possible to prevent the source and drain regions from being excessively oxidized, which would result in a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200a.

[0138] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen, and therefore can be suitably used as the insulating layer 250a1.

[0139] The insulating layer 250a4 also preferably has a barrier property against oxygen. The insulating layer 250a4 is provided between the channel formation region of the semiconductor layer 230a and the conductive layer 260a, and between the insulating layer 280 and the conductive layer 260a. This structure can prevent oxygen contained in the channel formation region of the semiconductor layer 230a from diffusing into the conductive layer 260a and forming oxygen vacancies in the channel formation region of the semiconductor layer 230a. Furthermore, it can prevent oxygen contained in the semiconductor layer 230a and oxygen contained in the insulating layer 280 from diffusing into the conductive layer 260a and oxidizing the conductive layer 260a. The insulating layer 250a4 is preferably at least less permeable to oxygen than the insulating layer 280. For example, a silicon nitride film is preferably used as the insulating layer 250a4. In this case, the insulating layer 250a4 contains at least nitrogen and silicon.

[0140] Furthermore, the insulating layer 250a4 preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 260a from diffusing into the semiconductor layer 230a.

[0141] The insulating layer 275 also preferably has a barrier property against oxygen. The insulating layer 275 is provided between the insulating layer 280 and the conductive layer 242a and between the insulating layer 280 and the conductive layer 242b. The insulating layer 275 is provided in contact with the side surface of the conductive layer 242a and the top surface of the insulating layer 222. This structure can prevent oxygen contained in the insulating layer 280 from diffusing into the conductive layer 242a and the conductive layer 242b. Therefore, it is possible to prevent the conductive layer 242a and the conductive layer 242b from being oxidized by the oxygen contained in the insulating layer 280 and thereby prevent an increase in resistivity. The insulating layer 275 is preferably at least less permeable to oxygen than the insulating layer 280. For example, silicon nitride is preferably used as the insulating layer 275. In this case, the insulating layer 275 contains at least nitrogen and silicon.

[0142] In order to prevent the hydrogen concentration in the source and drain regions of the semiconductor layer 230a from decreasing, an insulating layer using a barrier insulator against hydrogen is preferably provided near each of the source and drain regions. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 275.

[0143] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulating layer 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0144] By providing the insulating layer 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0145] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200a can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0146] The insulating layers 250a1 to 250a4 function as part of the gate insulator. The insulating layers 250a1 to 250a4, together with the insulating layer 255a and the conductive layer 260a, are provided in the opening 290a. To miniaturize the transistor 200a, the insulating layers 250a1 to 250a4 are preferably thin. The thicknesses of the insulating layers 250a1 to 250a4 are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulating layers 250a1 to 250a4 may have a region with the above-described thickness at least in part.

[0147] Furthermore, the thickness of the silicon oxide film used as the insulating layer 250a2 is preferably 0.7 nm or more and 3 nm or less.

[0148] In order to thin the insulating layers 250a1 to 250a4 as described above, it is preferable to form the insulating layers 250a1 to 250a4 by the ALD method. Furthermore, in order to provide the insulating layers 250a1 to 250a4 in the opening 290a, it is preferable to form the insulating layers by the ALD method. Examples of the ALD method include a thermal ALD method, in which a precursor and a reactant are reacted using only thermal energy, and a PEALD method, in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which allows film formation at a lower temperature.

[0149] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling extremely thin films, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulating layer 250a can be formed with good coverage on the side surfaces of the insulating layer 255a, the conductive layer 242a1, and the conductive layer 242b1 in the opening 290, and with the thin film thickness as described above.

[0150] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0151] Although the insulating layer 250a has been described above as having a four-layer structure of insulating layers 250a1 to 250a4, the present invention is not limited to this. The insulating layer 250a may have a structure including at least one of the insulating layers 250a1 to 250a4. By configuring the insulating layer 250a as one, two, or three of the insulating layers 250a1 to 250a4, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0152] For example, as shown in Fig. 6, insulating layer 250a may have a three-layer structure. In this case, insulating layer 250 preferably has a stacked structure of insulating layer 250a1, insulating layer 250a2 on insulating layer 250a1, and insulating layer 250a3 on insulating layer 250a2. In other words, this is the same as the structure shown in Fig. 3(A) except that insulating layer 250a4 is removed.

[0153] In forming the insulating layer 250a, it is preferable to use the ALD process two or more times. For example, the insulating layer 250a preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250a. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0154] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200a and the like. For example, it is preferable to provide an insulating layer having an insulator that has a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200a and the like. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 283, the insulating layer 282, the insulating layer 222, or the insulating layer 221. Furthermore, the insulating layer 215 provided under the transistor 200a may have a structure similar to one or both of the insulating layers 282 and 283. In this case, the insulating layer 215 may have a stacked structure of the insulating layer 282 and the insulating layer 283. Alternatively, the insulating layer 282 may be on the bottom and the insulating layer 283 on the top, or the insulating layer 282 may be on the top and the insulating layer 283 on the bottom.

[0155] One or more of the insulating layers 283, 282, 222, and 221 preferably have a function of suppressing the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200a, etc. to the transistor 200a, etc. Therefore, one or more of the insulating layers 283, 282, 222, and 221 preferably include an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, one or more of the insulating layers 283, 282, 222, and 221 preferably include an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules, etc.) (i.e., through which the oxygen is less likely to permeate).

[0156] The insulating layers 283, 282, 222, and 221 each preferably have an insulator that suppresses the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulating layers 283 and 221 preferably use silicon nitride, which has a high hydrogen barrier property. For example, the insulating layer 282 preferably uses aluminum oxide, which has a high ability to capture or fix hydrogen. For example, the insulating layer 222 preferably uses hafnium oxide, which is a high-dielectric-constant (high-k) material and has a high ability to capture or fix hydrogen.

[0157] At least one of the insulating layers 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulating layer 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulating layer 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0158] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed above the insulating layer 283 to the transistor 200a and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film disposed below the insulating layer 221 to the transistor 200a and the like. Furthermore, hydrogen contained in the insulating layer 280, the insulating layer 250, and the like can be captured and fixed to the insulating layer 282 or the insulating layer 222. Furthermore, the insulating layer 282 and the insulating layer 283 can prevent oxygen contained in the insulating layer 280 and the like from diffusing upward from the transistor 200a and the like. Furthermore, the insulating layer 222 and the insulating layer 221 can prevent oxygen contained in the semiconductor layer 230a and the like from diffusing downward from the transistor 200a and the like. Thus, the structure in which the transistor 200a is surrounded from above and below by insulating layers that have a function of preventing impurities such as water and hydrogen and oxygen diffusion can reduce the diffusion of excess oxygen and hydrogen into the oxide semiconductor. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0159] Furthermore, it is preferable to use silicon nitride or the like, which has a high hydrogen barrier property, for insulating layer 275 and insulating layer 250a4. It is also preferable to use aluminum oxide or the like, which has a high ability to capture or fix hydrogen, for insulating layer 250a1. It is also preferable to use hafnium oxide or the like, which has a high ability to capture or fix hydrogen, for insulating layer 250a3.

[0160] The insulating layer 216 and the insulating layer 280 preferably have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0161] For example, the insulating layer 216 and the insulating layer 280 each preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies.

[0162] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0163] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be planarized.

[0164] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0165] [Oxide semiconductor layer] Here, a description will be given of an oxide semiconductor layer that can be used for the semiconductor layer 230. The oxide semiconductor layer includes a metal oxide.

[0166] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids.

[0167] By using a crystalline metal oxide for an oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystalline (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure.

[0168] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Furthermore, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0169] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having a crystal structure different from either a single-crystal structure or a polycrystalline structure. In particular, the oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having a CAAC structure.

[0170] The CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the ab-plane without any clear grain boundaries. Observing a cross section of an oxide semiconductor layer having the CAAC structure using a high-resolution transmission electron microscope (TEM) image reveals that metal atoms are arranged in layers in the crystal parts. Therefore, an oxide semiconductor layer having the CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in layers can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0171] In addition, a structure in which metal atoms in each of a plurality of microcrystals are arranged in layers parallel or approximately parallel to the surface on which the metal atoms are formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the metal atoms are formed, is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the plurality of microcrystals may have a crystal structure other than a hexagonal system (e.g., a cubic system crystal structure).

[0172] For example, the CAAC structure is formed so that the c-axis is perpendicular or nearly perpendicular to the surface on which the film is formed. In the CAAC structure, metal atoms are arranged in layers parallel or nearly parallel to the surface on which the film is formed. In the region of the CAAC structure, the c-axis is preferably within 90°±20° (70° to 110°), more preferably within 90°±15° (75° to 105°), more preferably within 90°±10° (80° to 100°), and even more preferably within 90°±5° (85° to 95°) relative to the surface on which the film is formed.

[0173] A polycrystalline structure has grain boundaries. Furthermore, when a polycrystalline oxide semiconductor layer is formed and then heat treatment is performed, tiny gaps (also called nanocracks or microcracks) or tiny spaces (also called nanospaces or microspaces) can be formed between crystalline portions. The formation of tiny gaps or tiny spaces in an oxide semiconductor layer increases the electrical resistance of the oxide semiconductor layer. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source and drain electrodes increases. This adversely affects the initial characteristics and reliability of the transistor. In contrast, with a CAAC structure, grain boundaries are not clearly observed in the ab plane, enabling the realization of a highly reliable semiconductor device. Furthermore, the small number of grain boundaries reduces the energy barrier against carrier conduction in the transistor channel, which is expected to improve the on-state current. Furthermore, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using an oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, making the transistor suitable for high-speed operation.

[0174] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the carrier mobility of the metal oxide used in the transistor. To increase the carrier mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0175] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of these techniques may be used for analysis.

[0176] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor layer is formed or the normal vector of the surface of the oxide semiconductor layer.

[0177] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) on a TEM image reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0178] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT pattern is created by performing FFT processing on each region in the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots with high brightness and located at approximately equal distances from the center is defined as the crystal axis direction. Regions whose crystal axis direction calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0179] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image of an oxide semiconductor layer having a CAAC structure viewed in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, with hexagonal Voronoi regions being the most common. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0180] We will now explain how to create a Voronoi diagram. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of the line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal region enclosed by the lines connecting the Voronoi points is defined as the Voronoi region. This allows the creation of a Voronoi diagram.

[0181] As an example of the observation range of the TEM in creating a Voronoi diagram, it is preferable to observe a rectangular region of 50 nm in length and 50 nm in width, although the observation range is not limited to this.

[0182] Furthermore, when the distribution of hexagonal lattice orientations was analyzed using lattice points extracted by image analysis of planar TEM images, the difference in hexagonal lattice orientation at the boundary between two structures with different hexagonal lattice orientations was small, and the boundary was observed to be blurred, with the two structures appearing to interdigitate. In other words, no clear boundary was observed in the CAAC structure.

[0183] The orientation of the hexagonal lattice can be calculated by calculating the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0184] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0185] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and may further contain the element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, the element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and may further contain the element M. Note that the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that, in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the term "metal element" as used herein and the like may also include metalloid elements.

[0186] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0187] In a cross section of an oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed. In the TEM image, the metal atoms arranged in layers are observed as a row of bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0188] Examples of metal oxides according to an embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), and indium aluminum. Examples of usable metal oxides include indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include silicon-containing indium tin oxide (ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide). Indium oxide can be used as a metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as a metal oxide according to one embodiment of the present invention.

[0189] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0190] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0191] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies is suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0192] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements with higher period numbers in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0193] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0194] [Method for producing oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0195] In one embodiment of the present invention, a metal oxide having a CAAC structure is formed as a film in order to form an oxide semiconductor layer. A sputtering method can be used to form a metal oxide having high crystallinity. Alternatively, a pulsed laser deposition (PLD) method or another method may be used.

[0196] When a metal oxide is formed using the above-described film formation method (hereinafter referred to as the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface on which the metal oxide is to be formed. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide. By first forming a metal oxide as a first layer on the surface on which the metal oxide is to be formed using a film formation method (hereinafter referred to as the second film formation method) that causes less damage than the sputtering method, PLD method, and the like, which are described as the first film formation methods, and then providing a metal oxide as a second layer using the first film formation method, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface on which the metal oxide is to be formed can be suppressed. Furthermore, impurities contained in the surface on which the metal oxide is to be formed can be prevented from being mixed into the second layer. These features further enhance the crystallinity of the second layer.

[0197] The ALD method and the chemical vapor deposition (CVD) method are suitable as the second film formation method because they can reduce damage to the surface to be formed compared to the sputtering method. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma-enhanced CVD (PECVD), thermal CVD (TCVD), photo-CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and is one of the film formation methods that causes less damage to the surface to be formed. The wet method is one of the film formation methods that causes less damage to the surface to be formed. Examples of wet methods include spray coating.

[0198] A third layer can also be formed on the second layer, and the third layer can be formed using, for example, the second film formation method.

[0199] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0200] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first and third layers) can be increased by using the second layer (i.e., CAAC) having high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor layer. In other words, the second layer serves as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming oxide semiconductor layers with high crystallinity. An oxide semiconductor layer formed by such a deposition method, specifically an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0201] Even when a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. In addition, heat treatment has a function of assisting in increasing the crystallinity of the first layer and the third layer.

[0202] An example of a method for manufacturing the oxide semiconductor layer 30 will be described below with reference to FIGS.

[0203] First, layer 29 is formed. Layer 29 corresponds to an insulating film or conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as layer 29. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as layer 29. Layer 29 does not need to be crystalline. In other words, layer 29 may have an amorphous structure. Furthermore, when layer 29 is crystalline, it may have a crystal structure that has low lattice matching with the metal oxide included in oxide semiconductor layer 30.

[0204] Next, an oxide semiconductor layer 30a is formed on the layer 29 (FIG. 7(A)).

[0205] In a manufacturing method of one embodiment of the present invention, the oxide semiconductor layer 30b is formed by a sputtering method, as described below. When a metal oxide film is formed by a sputtering method, a mixed layer (also called alloying) of components of the metal oxide film to be formed and components of a layer on which the film is to be formed may be formed due to sputtering particles emitted from a target or energy applied to a substrate by the sputtering particles. The alloying may hinder the crystallization of the oxide semiconductor layer thereover. Furthermore, when the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. The use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0206] Therefore, before forming the oxide semiconductor layer 30b, the oxide semiconductor layer 30a is formed in advance using a film formation method that causes minimal damage to the surface on which it is formed. This suppresses alloying of the components contained in the oxide semiconductor layer 30 with the components contained in the layer 29, and makes the thickness of the alloyed region thin, or makes the alloyed region thin enough that it cannot be observed. Here, the oxide semiconductor layer 30a is formed using the ALD method.

[0207] Examples of the ALD method include a thermal ALD method and a PEALD method.

[0208] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Because the ALD method deposits atoms layer by layer, it has the following advantages: it can form ultrathin films; it can form films on surfaces with high aspect ratios or large steps; it can form films with few defects such as pinholes; it can form films with excellent coverage; and it can form films at low temperatures. By using the ALD method to form the oxide semiconductor layer 30a and the oxide semiconductor layer 30c (described later), the coverage of the entire oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, and the like with high aspect ratios.

[0209] Furthermore, the PEALD method may be preferable because it uses plasma, allowing for film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0210] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor layer 30a by the ALD method will be described.

[0211] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 29. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined.

[0212] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0213] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer of combined element M and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer of combined zinc and oxygen.

[0214] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor layer 30a on the layer 29 by the ALD method.

[0215] The substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0216] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge excess precursor, reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the chamber, and then discharge excess reactant, reaction products, etc. from the chamber.

[0217] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0218] When the oxide semiconductor layer 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed.

[0219] Next, an In-M-Zn oxide is formed as the oxide semiconductor layer 30b on the oxide semiconductor layer 30a by sputtering (FIG. 7B). The oxide semiconductor layer 30b preferably has a composition suitable for forming a CAAC structure.

[0220] When the oxide semiconductor layer 30b is formed by sputtering, a mixed layer 31 is formed on or near the surface of the oxide semiconductor layer 30a. During the formation of the oxide semiconductor layer 30b, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 31. In a subsequent heat treatment step, the mixed layer 31 or the minute crystalline regions formed in the mixed layer 31 may act as nuclei, causing at least a portion of the oxide semiconductor layer 30a to crystallize.

[0221] Sputtering methods include RF sputtering, which uses a high-frequency power supply as a sputtering power supply; DC sputtering, which uses a direct-current power supply; and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used to form metal conductive films and can improve productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used to form metal conductive films and semiconductor films. RF sputtering can be suitably used to form insulating films. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used for the oxide semiconductor layer of one embodiment of the present invention can be formed by a method appropriately selected from these methods depending on the conductivity of the sputtering target and the like.

[0222] In-M-Zn oxide can be used as a target for sputtering. When forming metal oxides by sputtering, oxygen or a mixture of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film can be increased.

[0223] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed may be.

[0224] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0225] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that of the sputtering target.

[0226] When forming the oxide semiconductor layer 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, increasing the substrate temperature (stage temperature) during metal oxide formation may result in the formation of a metal oxide with high crystallinity. When forming the oxide semiconductor layer 30b by sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0227] Here, we will explain the formation model of the CAAC structure using the sputtering method. First, microcrystals are formed during sputtering deposition. These microcrystals may be formed by energy imparted to the substrate by sputtering particles (sometimes called atomic particles) or gas particles. Alternatively, planar or pellet-shaped sputtering particles (sometimes called nanoclusters) that peel off from the sputtering target and deposit on the substrate surface may become the microcrystals. Subsequently, sputtering particles are adsorbed onto the edges of the microcrystals, causing the microcrystals to grow laterally (in a direction substantially parallel to the substrate surface). As the microcrystals grow laterally, adjacent microcrystals connect with each other, eliminating the edges of the microcrystals. Once the edges of the microcrystals are eliminated, sputtering particles are adsorbed onto the microcrystals, causing the microcrystals to grow vertically (in a direction substantially perpendicular to the substrate surface). Sputtering particles are adsorbed onto the edges of the vertically grown microcrystals, causing the microcrystals to grow laterally. In this way, the CAAC structure is formed by the microcrystals repeatedly growing laterally and vertically. That is, the CAAC structure is formed by the growth of microcrystals contained in an oxide semiconductor, using the microcrystals as nuclei or seeds.

[0228] Note that the CAAC structure is difficult to form in an oxide semiconductor containing impurities such as silicon, carbon, or water. Therefore, it is preferable to form the oxide semiconductor layer 30b using a film formation method that is less likely to introduce the impurities. The sputtering method is suitable for forming the oxide semiconductor layer 30b because it can form an oxide semiconductor with a low impurity concentration by using a sputtering target with a reduced impurity concentration and a film formation gas with a reduced amount of impurities.

[0229] Next, the oxide semiconductor layer 30c is formed on the oxide semiconductor layer 30b (FIG. 7C). Here, the oxide semiconductor layer 30c is formed by the ALD method. For the formation of the oxide semiconductor layer 30c by the ALD method, the method for forming the oxide semiconductor layer 30a can be referred to.

[0230] When an oxide semiconductor layer 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor layer 30b having the CAAC structure by ALD, the oxide semiconductor layer 30c may grow epitaxially around the oxide semiconductor layer 30b. Therefore, when the oxide semiconductor layer 30c is formed, the oxide semiconductor layer 30c may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed throughout the entire oxide semiconductor layer 30c.

[0231] The oxide semiconductor layer 30c can be used, for example, as a layer in contact with a gate insulating layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on-state.

[0232] Furthermore, by forming the oxide semiconductor layer 30c using the ALD method, damage to the oxide semiconductor layer 30b is reduced, and the entire oxide semiconductor layer 30 can have high crystallinity.

[0233] By using the ALD method, which has high coverage, as a film formation method for the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, the oxide semiconductor layer as a whole can have high coverage. In addition, by forming the oxide semiconductor layer 30b with high crystallinity using a sputtering method, the crystallinity of the oxide semiconductor layers above and below (the oxide semiconductor layer 30a and the oxide semiconductor layer 30c) can also be improved by epitaxial growth from this layer, so that the crystallinity of the oxide semiconductor layer 30 can be improved throughout the entire layer. Therefore, the oxide semiconductor layer 30 can have both high coverage and high crystallinity.

[0234] Next, a heat treatment step may be carried out.

[0235] The heat treatment temperature may be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. A typical temperature is 400°C ± 25°C (375°C to 425°C). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the oxide semiconductor layer 30b with the oxide semiconductor layer 30c (in other words, with the crystal molecules formed by the ALD method).

[0236] The heating device used for heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device performs heat treatment using high-temperature gas.

[0237] The heat treatment may enhance the crystallinity of the region having the CAAC structure in the oxide semiconductor layer 30c. Furthermore, if the region having the CAAC structure is formed only below the oxide semiconductor layer 30c after the ALD process, the heat treatment may cause the region having the CAAC structure to expand upward (FIG. 7D). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire oxide semiconductor layer 30c.

[0238] Furthermore, the heat treatment step may further repair the oxide semiconductor layer 30b by the oxide semiconductor layer 30c filling gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor layer 30b.

[0239] Furthermore, it is preferable that at least a portion of the oxide semiconductor layer 30a is converted into CAAC by the heat treatment process (FIG. 7(D)). It is expected that the CAAC is easily generated because the mixed layer 31 formed in the oxide semiconductor layer 30a during the formation of the oxide semiconductor layer 30b acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor layer 30a that is converted into CAAC is wide, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 29.

[0240] Furthermore, because the CAAC process occurs from the top to the bottom of the oxide semiconductor layer 30a, the CAAC process can be performed up to the vicinity of the layer 29 regardless of the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, the oxide semiconductor layer 30a can be formed with high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0241] After the oxide semiconductor layer 30c is formed, a microwave plasma treatment may be performed.

[0242] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device with a power source that generates high-density plasma using microwaves. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0243] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 30 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the oxide semiconductor layer.

[0244] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. Furthermore, the microwave plasma treatment is preferably carried out while the substrate is heated. The substrate temperature can be set to between room temperature (e.g., 25°C) and 500°C, more preferably between 200°C and 500°C, even more preferably between 300°C and 500°C, and even more preferably between 400°C and 500°C. For example, it can be set to between 400°C and 450°C.

[0245] Alternatively, microwave plasma treatment may be followed by heat treatment without exposure to the atmosphere. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0246] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave plasma treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can act on the oxide semiconductor layer. The V in the oxide semiconductor layer can be formed by the action of the plasma, microwaves, or the like. O By splitting H into oxygen vacancies and hydrogen, the impurity hydrogen can be removed from the oxide semiconductor layer. OH can be reduced. In addition, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon and hydrogen can be reduced by performing microwave plasma treatment. Furthermore, oxygen vacancies formed in the oxide semiconductor layer can be further reduced by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the oxide semiconductor layer.

[0247] Oxygen to be implanted into the oxide semiconductor layer may take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also called O radicals). The oxygen to be implanted into the oxide semiconductor layer may take one or more of the above forms, and is particularly preferably an oxygen radical.

[0248] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0249] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0250] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness, or both, than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0251] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods in a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0252] In the oxide semiconductor layer 30, it is preferable that the region having the CAAC structure is widely present throughout the entire layer including the oxide semiconductor layer 30a and the oxide semiconductor layer 30c. FIG. 8A shows the crystallized states of the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c. The crystals in the region having the CAAC structure in the oxide semiconductor layer 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor layer 30b. The crystals in the region having the CAAC structure in the oxide semiconductor layer 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor layer 30b. The oxide semiconductor layer 30 can sometimes be expressed as a single layer with no clearly observable interface. The oxide semiconductor layer 30 can sometimes be expressed as a single layer.

[0253] The regions having the CAAC structure in the oxide semiconductor layers 30a, 30b, and 30c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axes of the CAAC structures in the oxide semiconductor layers 30a, 30b, and 30c are each approximately parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0254] Furthermore, a portion of the oxide semiconductor layer 30a or 30c may not be crystallized. Furthermore, a region with lower crystallinity than the CAAC structure may remain in a portion of the oxide semiconductor layer 30a or 30c. The example shown in FIG. 8B illustrates a state in which the oxide semiconductor layer 30a is not crystallized near the interface with the layer 29, or a region with lower crystallinity than the CAAC structure remains near the interface. FIG. 8C illustrates a state in which the oxide semiconductor layer 30c is not crystallized near the surface, or a region with lower crystallinity than the CAAC structure remains near the surface. FIG. 8D illustrates a state in which the oxide semiconductor layer 30a is not crystallized near the interface with the layer 29 and near the surface of the oxide semiconductor layer 30c, or a region with lower crystallinity than the CAAC structure remains near the interface with the layer 29 and near the surface of the oxide semiconductor layer 30c.

[0255] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 30, the boundaries between the stacked oxide semiconductor layers 30a, 30b, and 30c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0256] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor layer 30b and the crystals of the oxide semiconductor layer 30a or the oxide semiconductor layer 30c is small. This allows the oxide semiconductor layer 30a or the oxide semiconductor layer 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor layer 30b. In this case, for example, in cross-sectional observation of the oxide semiconductor layer 30 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor layer 30a or the oxide semiconductor layer 30c.

[0257] As long as the lattice mismatch between the crystals of the oxide semiconductor layer 30b and the crystals of the oxide semiconductor layer 30a or 30c is small, the crystal structure of the oxide semiconductor layer 30a or 30c is not particularly limited. The crystal structure of the oxide semiconductor layer 30a or 30c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0258] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0259] When the oxide semiconductor layer 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the film thickness of the oxide semiconductor layer 30 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0260] The thickness of the oxide semiconductor layer 30b is preferably, for example, 200 nm or less. When the oxide semiconductor layer 30b is layered, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0261] Alternatively, if the oxide semiconductor layer 30b can function as a crystal nucleus, the oxide semiconductor layer 30b may not exist as a layer but may be a collection of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor layer 30b exist discretely.

[0262] The thickness of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c is, for example, preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm.

[0263] The thickness of the region where the component contained in the oxide semiconductor layer 30 and the component contained in the layer 29 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 7(A) and 7(B) show an example in which no alloy region is formed between the layer 29 and the oxide semiconductor layer 30a.

[0264] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0265] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor layer 30a to be formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (In, if the oxide semiconductor layer 30a contains In) that is the main component of the oxide semiconductor layer 30a but is not the main component of the layer that will become the surface to be formed (here, layer 29) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor layer 30a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface to be formed but is not the main component of the oxide semiconductor layer 30a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0266] For example, when a silicon oxide layer is used as the layer 29 and SIMS analysis is performed on the oxide semiconductor layer 30 formed on the layer 29, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 29 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0 × 10 20 atoms / cm 3 The distance between the depth at which the thickness decreases and the interface is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0267] By reducing the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, the vicinity of the surface to be formed refers to, for example, a region from more than 0 nm to 3 nm, preferably more than 0 nm to 2 nm, more preferably 1 nm to 2 nm, approximately perpendicularly from the surface to be formed of the oxide semiconductor layer 30.

[0268] The oxide semiconductor layer 30a has a region located, for example, at a distance of 0 to 3 nm from the top surface of the layer 29. The oxide semiconductor layer 30c is located, for example, at a distance of 0 to 3 nm from the top surface of the oxide semiconductor layer 30b. The oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c have, for example, approximately the same thickness. Alternatively, the oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c may have different thicknesses.

[0269] Although the oxide semiconductor layer 30 has been described above as having a three-layer structure of the oxide semiconductor layers 30a to 30c, the present invention is not limited to this. The oxide semiconductor layer 30 may have a two-layer structure or a stacked structure of four or more layers.

[0270] When the oxide semiconductor layer 30 has a two-layer structure, the oxide semiconductor layer 30 can have a configuration in which an oxide semiconductor layer 30a and an oxide semiconductor layer 30b are laminated in this order. By using such a configuration, alloying of the components contained in the oxide semiconductor layer 30 and the components contained in the layer 29 can be suppressed, and the thickness of the alloyed region can be reduced, or the thickness can be made so thin that the alloyed region cannot be observed.

[0271] Alternatively, when the oxide semiconductor layer 30 has a five-layer structure, the oxide semiconductor layer 30 can have a structure in which a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a fourth oxide semiconductor, and a fifth oxide semiconductor are stacked in this order. For example, the first oxide semiconductor, the third oxide semiconductor, and the fifth oxide semiconductor are preferably formed by the second film formation method, more preferably by an ALD method. The second oxide semiconductor and the fourth oxide semiconductor are preferably formed by the first film formation method, more preferably by a sputtering method. With this structure, even if the third oxide semiconductor has a composition that makes it difficult to form a CAAC structure, crystal growth is promoted from one or both of the second oxide semiconductor and the fourth oxide semiconductor, and the crystallinity of the third oxide semiconductor can be improved.

[0272] When the oxide semiconductor layer 30 has a stacked structure of two or more layers, typically a stacked structure of two to five layers, it is preferable to deposit each layer successively without exposing it to the atmosphere. For example, it is preferable to deposit each layer successively using a multi-chamber film deposition apparatus. This allows the oxide semiconductor layer 30 to be deposited while suppressing impurities that may be mixed into each layer.

[0273] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0274] The CAAC structure of an oxide semiconductor layer can sometimes be evaluated from a map showing crystal orientation. For example, in a region having the CAAC structure, the c-axis orientation of crystals is observed.

[0275] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing FFT processing on each region within the cross-sectional TEM image to create an FFT pattern, and then calculating the crystal axis direction of each region. Specifically, for example, two spots of high intensity are observed in the FFT pattern of a region having layered crystals. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0276] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing the crystal orientation.

[0277] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0278] Furthermore, when performing analysis using a cross-sectional TEM image, it is preferable that the observation range of the cross-sectional TEM image is, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0279] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation rate is calculated as the percentage of regions whose orientation is within 20° of the c-axis, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0280] The c-axis orientation rates of the region formed as the oxide semiconductor layer 30a, the region formed as the oxide semiconductor layer 30b, and the region formed as the oxide semiconductor layer 30c are defined as Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation rate is calculated as the percentage of regions whose orientation is within a 20° difference from the c-axis. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. It is preferable that Rc3 / Rc1 be greater than 1. It is also preferable that Rc2 / Rc1 be greater than 1.

[0281] [Composition of oxide semiconductor layer] The oxide semiconductor layer 30a preferably has a different composition from the oxide semiconductor layer 30b. The oxide semiconductor layer 30c preferably has a different composition from the oxide semiconductor layer 30b. The oxide semiconductor layer 30a may have the same composition as the oxide semiconductor layer 30c. Alternatively, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may have different compositions.

[0282] The oxide semiconductor layer 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor layer 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor layer 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor layer 30b preferably contains, in addition to zinc, the element M. By containing the element M in the oxide semiconductor layer 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor layer 30b may be made of a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, an atomic ratio of In:M:Zn=1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn=1:1:2 or a similar composition, an atomic ratio of In:M:Zn=4:2:3 or a similar composition, an atomic ratio of In:M:Zn=1:3:2 or a similar composition, or an atomic ratio of In:M:Zn=1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Preferably, the element M is one or more of gallium, tin, yttrium, and aluminum.

[0283] The oxide semiconductor layer 30b may be configured without the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. It may also be configured with a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0284] The oxide semiconductor layer 30a and the oxide semiconductor layer 30c can be made of a metal oxide having a high proportion of In. It is particularly preferable that the oxide semiconductor layer 30a and the oxide semiconductor layer 30c be made of a metal oxide having a higher proportion of In than the oxide semiconductor layer 30b. The oxide semiconductor layer 30a and the oxide semiconductor layer 30c can be formed by, for example, an ALD method. It is particularly preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, it is possible to increase the on-current and improve the frequency characteristics when the oxide semiconductor layer is applied to a transistor.

[0285] Oxide semiconductors with a high In content tend to be polycrystalline. Using a polycrystalline metal oxide in a transistor adversely affects the initial characteristics or reliability of the transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor layer 30b can be reflected in the oxide semiconductor layer 30a and the oxide semiconductor layer 30c with a high In content. Therefore, even when a metal oxide with a high In content is used for the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, polycrystallization can be suppressed.

[0286] Alternatively, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be configured to not contain the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, In:Zn=2:1 (atomic ratio) or a composition thereabout, or In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be configured to contain a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0287] Alternatively, a metal oxide with a high Ga content may be used for the oxide semiconductor layer 30a and the oxide semiconductor layer 30c. For example, a metal oxide with a higher Ga content than that of the oxide semiconductor layer 30b may be used for the oxide semiconductor layer 30a and the oxide semiconductor layer 30c. For example, a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition similar thereto, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition similar thereto, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition similar thereto may be used for the oxide semiconductor layer 30a and the oxide semiconductor layer 30c, respectively. Increasing the Ga content may result in the band gaps of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c being larger than that of the oxide semiconductor layer 30b. As a result, the oxide semiconductor layer 30b is sandwiched between the oxide semiconductor layers 30a and 30c, which have larger band gaps, allowing the oxide semiconductor layer 30b to function primarily as a current path (channel). Furthermore, the trap levels at and near the interface of the oxide semiconductor layer 30b can be reduced. This allows for a buried channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving the reliability of the transistor.

[0288] Alternatively, one of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor layer 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor layer 30b.

[0289] The oxide semiconductor layer 30a, the oxide semiconductor layer 30b, and the oxide semiconductor layer 30c may each have a structure in which a plurality of layers having the above-described compositions are stacked. For example, the oxide semiconductor layer 30c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0290] The oxide semiconductor layer 30a and the oxide semiconductor layer 30c may be made of a metal oxide having the same composition as the oxide semiconductor layer 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0291] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductor layers 30a and 30c have compositions that make it difficult to form a CAAC structure when formed as a single layer, crystal growth occurs using the oxide semiconductor layer 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductor layers 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor layer 30a and the oxide semiconductor layer 30c and in a region including the oxide semiconductor layer 30b.

[0292] The composition of the metal oxide used in the oxide semiconductor layer 30 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0293] [Impurities in oxide semiconductors] The influence of each impurity in an oxide semiconductor will now be described. The impurities contained in an oxide semiconductor can be quantified using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0294] It is preferable that the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. O ) and impurities, the electrical characteristics may be easily changed and reliability may be reduced. O H may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region, V O It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0295] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, elements with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as impurities.

[0296] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3or less, more preferably 1 × 10 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 The following applies.

[0297] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5 × 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0298] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than 1×10 17 atoms / cm 3 Less than.

[0299] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0300] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0301] The average film thickness of the oxide semiconductor layer 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and even more preferably 10 nm or less.

[0302] The oxide semiconductor layer 30a is an oxide semiconductor layer formed on a surface to be formed on, and the thickness of the oxide semiconductor layer 30a is preferably 0.5 nm or more and 3 nm or less.

[0303] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the semiconductor layer 230 is observed, it may be possible to see that metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure. In this case, for example, the metal atoms are arranged perpendicular or approximately perpendicular to the substrate surface.

[0304] The metal atoms arranged in layers in the region having the CAAC structure can be observed as an array of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. Therefore, in the semiconductor device of one embodiment of the present invention, when a cross section of the semiconductor layer 230 is observed, it may be possible to confirm that the bright spots are arranged in a direction perpendicular or approximately perpendicular to the substrate surface.

[0305] The oxide semiconductor layer 30, which is an AG CAAC, can be used for the semiconductor layer 230a of the transistor 200a. For example, as shown in FIG. 3B, the semiconductor layer 230a can have a configuration including a semiconductor layer 230a1, a semiconductor layer 230a2 in contact with the semiconductor layer 230a1, and a semiconductor layer 230a3 in contact with the semiconductor layer 230a2. Here, the semiconductor layer 230a1 corresponds to the oxide semiconductor layer 30a, the semiconductor layer 230a2 corresponds to the oxide semiconductor layer 30b, and the semiconductor layer 230a3 corresponds to the oxide semiconductor layer 30c.

[0306] Here, the pillars (insulating layer 223a described later) correspond to layer 29. That is, the surface on which semiconductor layer 230a is formed is the pillar, and in transistor 200a, the pillars have been removed. During the manufacturing process, one side of semiconductor layer 230a1 contacts the pillar, and the other side of semiconductor layer 230a2 contacts the semiconductor layer 230a2. After the pillars are removed, one side of semiconductor layer 230a1 contacts the insulating layer 250a. One side of semiconductor layer 230a2 contacts the semiconductor layer 230a1, and the other side of semiconductor layer 230a3 contacts the semiconductor layer 230a2, and the other side of semiconductor layer 230a3 contacts the insulating layer 250a. Here, since the side surfaces of the pillars are formed perpendicular or approximately perpendicular to the substrate surface (which can also be referred to as the surface of the insulating layer 222), the side surfaces of the semiconductor layer 230a (semiconductor layers 230a1 to 230a3) are also perpendicular or approximately perpendicular to the substrate surface.

[0307] As described above, in a cross section of the semiconductor layer 230a (semiconductor layers 230a1 to 230a3) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which they are formed. In other words, in a cross section of the semiconductor layer 230a (semiconductor layers 230a1 to 230a3) observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction perpendicular or approximately perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is approximately parallel to the normal direction to the side surface of the semiconductor layer 230a.

[0308] In this manner, by using the semiconductor layer 230a made of AG CAAC in the channel formation region of the transistor 200a, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0309] Furthermore, when the semiconductor layer 230a has a three-layer structure of semiconductor layers 230a1 to 230a3 as described above, the semiconductor layer 230a is formed in the order of semiconductor layer 230a1, semiconductor layer 230a2, and semiconductor layer 230a3, centered on the region where the pillars were formed. Therefore, as shown in FIG. 9A, in a cross-sectional view in the channel width direction, the semiconductor layers are arranged symmetrically in the order of semiconductor layer 230a3, semiconductor layer 230a2, semiconductor layer 230a1, semiconductor layer 230a1, semiconductor layer 230a2, and semiconductor layer 230a3. That is, in order to make the semiconductor layer 230a have a symmetric structure in a cross-sectional view, it is preferable that the semiconductor layer 230a1 and the semiconductor layer 230a3 have approximately the same composition. It is also preferable that the semiconductor layer 230a1 and the semiconductor layer 230a3 have approximately the same film thickness. Furthermore, when the angle θ in FIG. 3(B) is greater than or equal to 80° and less than 90°, that is, when the side surface of the semiconductor layer 230a is slightly tilted, the slope of the semiconductor layer 230a is arranged symmetrically as shown in FIG. 9(B). When the semiconductor layer 230a is formed with an inclination, the upper portion of the semiconductor layer 230a may be narrower than the lower portion of the semiconductor layer 230a, as shown in FIG. 9(B). When the angle θ in FIG. 3(B) is greater than 90° and less than or equal to 100°, that is, when the side surface of the semiconductor layer 230a is slightly tilted, the slope of the semiconductor layer 230a is arranged symmetrically as shown in FIG. 9(C). When the semiconductor layer 230a is formed with an inclination, the upper portion of the semiconductor layer 230a may be narrower than the lower portion of the semiconductor layer 230a, as shown in FIG. 9(C).

[0310] In the semiconductor layer 230a, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed. At least a part of the channel formation region overlaps with the conductive layer 260a. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged.

[0311] The channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0312] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0313] The carrier concentration in the channel formation region is 1×10 18 cm -3 Below, 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Less than or equal to 1 x 10 10 cm -3 The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 -9 cm -3 It can be said that:

[0314] In addition, when the carrier concentration of the semiconductor layer 230a is reduced, the impurity concentration in the semiconductor layer 230a is reduced to reduce the defect state density. In this specification and the like, a low impurity concentration and a low defect state density are referred to as high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor (or metal oxide) with a low carrier concentration may also be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0315] In order to stabilize the electrical characteristics of the transistor 200a, it is effective to reduce the impurity concentration in the channel formation region in the semiconductor layer 230a. Furthermore, in order to reduce the impurity concentration in the semiconductor layer 230a, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 230a refer to, for example, any elements other than the main components constituting the semiconductor layer 230a.

[0316] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 230a. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0317] Conductive layer 240a is formed in openings in insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, and insulating layer 285. The lower surface of conductive layer 240a is in contact with the upper surface of conductive layer 242a2. Here, the height of the upper surface of conductive layer 240a and the height of the upper surface of insulating layer 285 are approximately the same.

[0318] The conductive layer 240a is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 240a may also have a layered structure in which a first conductive layer is provided in contact with the side surface of the insulating layer 241 and a second conductive layer is further provided inside. In this case, the above-mentioned conductive material can be used as the second conductive layer.

[0319] Furthermore, when the conductive layer 240a has a stacked structure, the insulating layers 285, 283, 282, 280, and the first conductive layer disposed near the insulating layer 275 are preferably made of a conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulating layer 283 can be prevented from entering the semiconductor layer 230a through the conductive layer 240a.

[0320] Although the conductive layer 240a has a two-layer structure in the above description, the present invention is not limited to this. For example, the conductive layer 240a may have a single layer structure or a stacked structure of three or more layers.

[0321] The insulating layer 241a is formed in contact with the inner walls of the openings of the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285. The inner side surface of the insulating layer 241a is in contact with the conductive layer 240a.

[0322] The insulating layer 241a may be a barrier insulating film that can be used for the insulating layer 275, etc. For example, the insulating layer 241a may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulating layer 241a can prevent impurities such as water and hydrogen contained in the insulating layer 280, etc., from entering the semiconductor layer 230a through the conductive layer 240a. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layer 240a.

[0323] Although the insulating layer 241a has a single layer structure in the above description, the present invention is not limited to this. For example, the insulating layer 241a may have a stacked structure of two or more layers.

[0324] For example, when the insulating layer 241a has a two-layer laminated structure, it is preferable that the first insulating layer in contact with the inner wall of the opening such as the insulating layer 280 and the second insulating layer inside it are made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0325] For example, the first insulating layer may be made of aluminum oxide deposited by a thermal ALD method, and the second insulating layer may be made of silicon nitride deposited by a PEALD method. This structure can suppress oxidation of the conductive layer 240a and reduce hydrogen contamination of the conductive layer 240a.

[0326] For example, as shown in FIG. 3C, a structure may be used in which the conductive layer 240a covers the semiconductor layer 230a and the conductive layer 242a, which is folded in half with the semiconductor layer 230a sandwiched between them. As a result, in a cross-sectional view in the channel width direction, the conductive layer 240a contacts the conductive layer 242a at the top, the side surface on the B3 side, and the side surface on the B4 side of the conductive layer 242a. Therefore, compared to when the semiconductor layer 230a is formed in a flat plate shape, the contact area between the conductive layer 240a and the conductive layer 242a is increased by the height H of the side surface on the B3 side and the height H of the side surface on the B4 side of the semiconductor layer 230a. Furthermore, by using a structure in which the conductive layer 240a covers multiple fin-shaped semiconductor layers 230a as shown in FIG. 1A, the contact area between the conductive layer 240a and the conductive layer 242a can be further increased.

[0327] As described above, the contact area between the conductive layer 240a and the conductive layer 242a is increased, thereby reducing the contact resistance between the conductive layer 240a and the conductive layer 242a. This improves the on-state current, frequency characteristics, and the like of the transistor 200a without significantly increasing the area occupied by the transistor 200a. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0328] In the above description, as shown in FIG. 1A, the shape of the opening through which the conductive layer 240a and the insulating layer 241a are provided is rectangular in top view. However, this is not limiting. For example, the opening may be circular, approximately circular, such as elliptical, polygonal, such as rectangular, or polygonal, such as rectangular, with rounded corners. As shown in FIG. 1C, the opening is formed to overlap multiple fin-shaped semiconductor layers 230a. However, this is not limiting and the opening may be formed to overlap at least the conductive layer 242a. For example, as shown in FIG. 10A, a portion of the opening (which may also be referred to as a portion of the conductive layer 240a) may overlap the semiconductor layer 230a, while another portion of the opening (which may also be referred to as the other portion of the conductive layer 240a) may not overlap the semiconductor layer 230a. By configuring the conductive layer 240a so that a portion of the conductive layer 240a overlaps the semiconductor layer 230a, the margin for arranging the conductive layer 240a can be increased. Alternatively, for example, as shown in FIG. 10B, the opening and the conductive layer 240a can be provided in a region that does not overlap with the semiconductor layer 230a.

[0329] [Transistor 200b] The transistor 200b can have a structure similar to that of the transistor 200a described above. For a description of the structure of the transistor 200b, the description of the structure of the transistor 200a can be referred to by replacing the transistor 200a, the semiconductor layer 230a, the conductive layer 242a (the conductive layer 242a1 and the conductive layer 242a2), the conductive layer 242b (the conductive layer 242b1 and the conductive layer 242b2), the insulating layer 255a, the insulating layer 250a, the conductive layer 260a, the opening 291a, and the opening 292a with the transistor 200b, the semiconductor layer 230b, the conductive layer 242c (the conductive layer 242c1 and the conductive layer 242c2), the conductive layer 242d (the conductive layer 242d1 and the conductive layer 242d2), the insulating layer 255b, the insulating layer 250b, the conductive layer 260b, the opening 291b, and the opening 292b, respectively, and making appropriate necessary modifications.

[0330] For an explanation of the configuration of the conductive layer 240b and the insulating layer 241b, the explanation of the configuration of the conductive layer 240a and the insulating layer 241a can be referred to by replacing the conductive layer 240a, the insulating layer 241a, the semiconductor layer 230a, and the conductive layer 242a (conductive layer 242a1 and conductive layer 242a2) with the conductive layer 240b, the insulating layer 241b, the semiconductor layer 230b, and the conductive layer 242c (conductive layer 242c1 and conductive layer 242c2), respectively, and making appropriate necessary modifications. Similarly, the description of the configuration of the conductive layer 240c and the insulating layer 241c can be made by referring to the description of the configuration of the conductive layer 240a and the insulating layer 241a, by replacing the conductive layer 240a, the insulating layer 241a, the semiconductor layer 230a, and the conductive layer 242a (conductive layer 242a1 and conductive layer 242a2) with the conductive layer 240c, the insulating layer 241c, the semiconductor layer 230b, and the conductive layer 242d (conductive layer 242d1 and conductive layer 242d2), respectively, and making appropriate and necessary modifications.

[0331] 1C, the conductive layers 240b and 240c are arranged symmetrically with respect to the conductive layer 260b, but the present invention is not limited to this. For example, as shown in FIG. 10C, in a cross-sectional view in the channel length direction, the conductive layer 240b may be arranged so that a part of the conductive layer 240b overlaps with the semiconductor layer 230b, and the conductive layer 240c does not overlap with the semiconductor layer 230b.

[0332] This concludes the description of the configuration example of the transistor 200b.

[0333] 1 shows a configuration in which the channel length direction of the transistor 200a and the channel length direction of the transistor 200b are parallel or approximately parallel, but the present invention is not limited to this. For example, the channel length direction of the transistor 200a and the channel length direction of the transistor 200b may intersect. Specifically, the channel length direction of the transistor 200a and the channel length direction of the transistor 200b may be perpendicular or approximately perpendicular, or may intersect obliquely.

[0334] For example, as shown in Figures 11A and 11B, the transistors 200a and 200b can be arranged so that the channel length direction of the transistor 200a and the channel length direction of the transistor 200b are perpendicular to each other. This configuration allows the conductive layer 260a to be extended and function as a wiring. This allows for higher integration of the semiconductor device. Furthermore, the design flexibility of the semiconductor device can be increased.

[0335] As shown in FIGS. 12A to 12D, the semiconductor device of this embodiment may have a structure in which a conductive layer 205a and a conductive layer 205b are provided under an insulating layer 221. The conductive layer 205a has a region functioning as a second gate electrode (lower gate electrode) of the transistor 200a, and the conductive layer 205b has a region functioning as a second gate electrode (lower gate electrode) of the transistor 200b. The insulating layer 222 and the insulating layer 221 each have a region functioning as a second gate insulating layer of the transistor 200a and a region functioning as a second gate insulating layer of the transistor 200b. Note that the structure above the insulating layer 221 of the semiconductor device shown in FIGS. 12A to 12D corresponds to that of the semiconductor device shown in FIGS. 1A to 1D; therefore, the above description can be referred to for the detailed structure.

[0336] In the transistor 200a, the conductive layer 205a is arranged to overlap with the semiconductor layer 230a and the conductive layer 260a. Here, the conductive layer 205a is preferably provided to be embedded in an opening formed in the insulating layer 216. The conductive layer 205a can be provided to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 205a functions as a wiring.

[0337] 12(B), the conductive layer 205a preferably includes a conductive layer 205a1 and a conductive layer 205a2. The conductive layer 205a1 is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 205a2 is provided so as to fill a recess in the conductive layer 205a1 formed along the opening. Here, the height of the upper surface of the conductive layer 205a is the same as or approximately the same as the height of the upper surface of the insulating layer 216.

[0338] Here, the conductive layer 205a1 preferably includes a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it preferably includes a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0339] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205a1, impurities such as hydrogen contained in the conductive layer 205a2 can be prevented from diffusing into the semiconductor layer 230a via the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205a1, oxidation of the conductive layer 205a2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205a1 can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductive layer 205a1 preferably contains titanium nitride.

[0340] The conductive layer 205a2 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0341] The conductive layer 205a can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200a can be controlled by changing the potential applied to the conductive layer 205a independently of the potential applied to the conductive layer 260a. In particular, applying a negative potential (a potential lower than the source potential) to the conductive layer 205a can increase the Vth of the transistor 200a and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 205a can reduce the drain current when the potential applied to the conductive layer 260a is 0 V compared to not applying a negative potential.

[0342] The electrical resistivity of the conductive layer 205a is designed taking into consideration the potential applied to the conductive layer 205a, and the film thickness of the conductive layer 205a is set to match the electrical resistivity. The film thickness of the insulating layer 216 is approximately the same as that of the conductive layer 205a. Here, it is preferable to make the film thicknesses of the conductive layer 205a and the insulating layer 216 thin within the range permitted by the design of the conductive layer 205a. By making the film thickness of the insulating layer 216 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 216 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 230a can be suppressed.

[0343] Although the above describes a stacked structure of conductive layer 205a1 and conductive layer 205a2, the present invention is not limited thereto. Conductive layer 205a may have a single-layer structure or a stacked structure of three or more layers. For example, when conductive layer 205a has a three-layer stacked structure, a conductor made of the same material as conductive layer 205a1 may be provided on conductive layer 205a2 in the stacked structure of conductive layer 205a1 and conductive layer 205a2. In this case, the conductor may be formed so that the top surface of conductive layer 205a2 is lower than the top of conductive layer 205a1, and the recess formed by conductive layer 205a1 and conductive layer 205a2 is filled.

[0344] For an explanation of the configuration of the conductive layer 205b, the explanation of the configuration of the conductive layer 205a can be referred to by replacing the conductive layer 205a (conductive layer 205a1 and conductive layer 205a2), the semiconductor layer 230a, and the conductive layer 260a with the conductive layer 205b (conductive layer 205b1 and conductive layer 205b2), the semiconductor layer 230b, and the conductive layer 260b, respectively, and making appropriate necessary modifications.

[0345] <Configuration Example 2 of Semiconductor Device> Another example of the structure of a semiconductor device will be described with reference to Figures 13 and 14. Figures 13A to 13C are plan views and cross-sectional views of a semiconductor device having a transistor over a substrate (not shown).

[0346] FIG. 13(A) is a plan view of a semiconductor device. Also, FIGS. 13(B) and 13(C) are cross-sectional views of the semiconductor device. Here, FIG. 13(B) is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 13(A). Also, FIG. 13(C) is a cross-sectional view of a portion indicated by the dashed-dotted line B1-B2 in FIG. 13(A). Here, the dashed-dotted line B1-B2 is perpendicular to the dashed-dotted line A1-A2. Note that in the plan view of FIG. 13(A), some elements are omitted for clarity, and some elements are shown transparently.

[0347] 14(A) and 14(B) show perspective views of the semiconductor device shown in FIG. 13. Note that some elements are omitted from the perspective views shown in FIGS. 14(A) and 14(B) for clarity. The X direction shown in FIG. 14 is parallel to the A1-A2 direction shown in FIG. 13, and the Y direction shown in FIG. 14 is parallel to the B1-B2 direction shown in FIG. 13. In FIG. 14(B), the conductive layer 260a, the conductive layer 260b, the insulating layer 250a, the insulating layer 250b, the insulating layer 255a, and the insulating layer 255b are indicated by dashed lines.

[0348] 13 includes a capacitor 100 in addition to a transistor 200a and a transistor 200b. The semiconductor device shown in FIG. 13 differs from the semiconductor device shown in FIG. 1 mainly in that it includes a capacitor 100. Hereinafter, differences from the contents explained using FIG. 1 and the like will be mainly explained, and overlapping parts will be referred to and explanations thereof may be omitted.

[0349] 13 includes an insulating layer 216 over a substrate (not shown), an insulating layer 221 over the insulating layer 216, an insulating layer 222 over the insulating layer 221, a transistor 200a, a transistor 200b, and a semiconductor layer 230c over the insulating layer 222, a capacitor 100 over the semiconductor layer 230c, an insulating layer 275, and an insulating layer 280. For the transistor 200a and the transistor 200b, the description of the transistor 200a and the transistor 200b shown in FIG. 1 can be referred to.

[0350] The capacitor 100 includes a conductive layer 242e1 covering the semiconductor layer 230c, an insulating layer 255b on the conductive layer 242e1, an insulating layer 250b on the insulating layer 255b, and a conductive layer 260b on the insulating layer 250b. As shown in FIGS. 13A and 13B, the semiconductor layer 230c has a structure similar to that of the semiconductor layers 230a and 230b and can be formed in the same process. The conductive layer 242e1 has a structure similar to that of the conductive layer 242a1 and the conductive layer 242b1 (conductive layer 242Q1 described later) and the conductive layer 242c1 and the conductive layer 242d1 (conductive layer 242R1 described later), and can be formed in the same process. The insulating layer 255b and the insulating layer 250b are shared with the transistor 200b, and the conductive layer 260b is shared with the transistors 200a and 200b.

[0351] Here, the capacitor 100 includes a conductive layer 242e1 functioning as a first electrode (also referred to as a lower electrode), a conductive layer 260b functioning as a second electrode (also referred to as an upper electrode), and insulating layers 255b and 250b functioning as dielectrics. That is, the capacitor 100 configures a metal-insulator-metal (MIM) capacitor.

[0352] The capacitor 100 has a structure similar to that of the transistor 200b and can be fabricated in parallel in the same layer as the transistor 200b.

[0353] As shown in FIG. 13B, the semiconductor layer 230c has a high aspect ratio, similar to the semiconductor layers 230a and 230b, and multiple semiconductor layers can be provided. Therefore, similar to the semiconductor layers 230a and 230b, the height of the semiconductor layer 230c is greater than the width of the semiconductor layer 230c in a cross-sectional view in the channel width direction. Also, similar to the semiconductor layers 230a and 230b, the semiconductor layer 230c has two or more regions where the semiconductor layer 230c and the conductive layer 260b overlap in a top view. Therefore, the area where the conductive layer 242e1 and the conductive layer 260b, which are provided along the top surface and side surface of the semiconductor layer 230c, face each other with the insulating layer 255b and the insulating layer 250b interposed therebetween, can be increased. This allows for an increase in capacitance without significantly increasing the area occupied by the capacitor 100.

[0354] With the above structure, the other of the source and drain of the transistor 200a, one electrode of the capacitor 100, and the gate of the transistor 200b are electrically connected to form a memory cell including two transistors and one capacitor (also referred to as a 2T1C memory cell). Note that by not providing the transistor 200b, a memory cell including one transistor and one capacitor (also referred to as a 1T1C memory cell) can also be formed.

[0355] 15(A) to 15(D), the semiconductor device of this embodiment can have a configuration in which the insulating layer 222 is thin in a region in the opening 291a that does not overlap with the insulating layer 255a and the semiconductor layer 230a and in a region in the opening 291b that does not overlap with the insulating layer 255b and the semiconductor layer 230b. The semiconductor device of this embodiment can also have a configuration in which grooves or openings are provided in the insulating layer 222 in a region in the opening 291a that does not overlap with the insulating layer 255a and the semiconductor layer 230a and in a region in the opening 291b that does not overlap with the insulating layer 255b and the semiconductor layer 230b. With this configuration, the lower surface of the conductive layer 260a located in the grooves or openings provided in the insulating layer 222 in the region in the opening 291a that does not overlap with the insulating layer 255a and the semiconductor layer 230a can be positioned below the lower surface of the semiconductor layer 230a. In addition, the lower surface of the conductive layer 260b located in the groove or opening provided in the insulating layer 222 in the region that does not overlap with the insulating layer 255b and the semiconductor layer 230b in the opening 291b can be positioned lower than the lower surface of the semiconductor layer 230b.

[0356] By positioning the lower surface of the conductive layer 260a below the lower surface of the semiconductor layer 230a, a sufficient gate electric field can be applied from the upper end to the lower end of the semiconductor layer 230a. In other words, within the opening in the insulating layer 280 or the like, the entire semiconductor layer 230a is electrically surrounded by the electric field of the conductive layer 260a, allowing it to function as a channel formation region. This configuration prevents the lower end of the semiconductor layer 230a from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistor behavior, that are caused by the parasitic channel. In other words, it is possible to improve the electrical characteristics of the transistor 200a.

[0357] Furthermore, as described above, by making the semiconductor layer 230a function as a channel formation region from the top to the bottom, the channel width can be increased, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200a.

[0358] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is called a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make the transistor less susceptible to the short channel effect.

[0359] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be considered to be substantially equivalent to a GAA (gate all around) structure or a lateral gate all around (LGAA) structure. By forming the transistor 200a with the S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the semiconductor layer 230a and the gate insulator can be the entire bulk of the semiconductor layer 230a. This increases the density of current flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor. In one embodiment of the present invention, the semiconductor layer 230a has a CAAC structure and a fin-like structure. This structure allows the current path between the source and drain of the transistor to be parallel to the ab-plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like structure has a conduction path similar to that of a two-dimensional semiconductor material. Furthermore, by using such an oxide semiconductor, a device with two-dimensional conduction can be fabricated.

[0360] In Fig. 13(A), the width of the conductive layer 260b in the A5-A6 direction at the portion indicated by the dashed-dotted line A5-A6 is shown to be equal to or approximately equal to the width of the conductive layer 260b in the A3-A4 direction at the portion indicated by the dashed-dotted line A3-A4, but the present invention is not limited to this. For example, as shown in Fig. 16(A), the conductive layer 260b may be provided so that the width of the conductive layer 260b in the A5-A6 direction at the portion indicated by the dashed-dotted line A5-A6 is greater than the width of the conductive layer 260b in the A3-A4 direction at the portion indicated by the dashed-dotted line A3-A4. Note that in Figs. 16(A) and 16(B), the width of the conductive layer 260b in the A5-A6 direction at the portion indicated by the dashed-dotted line A5-A6 is equal to or approximately equal to the width of the conductive layer 260b in the A1-A2 direction at the portion indicated by the dashed-dotted line A1-A2. With this structure, the area of ​​the portion where the conductive layer 242e1 functioning as the first electrode of the capacitor 100 and the conductive layer 260b functioning as the second electrode of the capacitor 100 overlap with the insulating layer 255b and the insulating layer 250b interposed therebetween can be increased. This allows the capacitance to be increased without significantly increasing the area occupied by the capacitor 100.

[0361] <Configuration Example 3 of Semiconductor Device> Another structural example of a semiconductor device will be described with reference to Fig. 17. Fig. 17A and Fig. 17B are a plan view and a cross-sectional view of a semiconductor device having a transistor over a substrate (not shown).

[0362] Fig. 17(A) is a plan view of a semiconductor device. Fig. 17(B) is a cross-sectional view of the semiconductor device. Fig. 17(B) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Fig. 17(A). In the plan view of Fig. 17(A), some elements are omitted for clarity, and some elements are shown transparently.

[0363] 17 includes a transistor 200c in addition to transistors 200a, 200b, and a capacitor 100. The semiconductor device shown in FIG. 17 differs from the semiconductor device shown in FIG. 13 mainly in that it includes transistor 200c. The semiconductor device shown in FIG. 17 also differs from the semiconductor device shown in FIG. 1 mainly in that it includes a capacitor 100 and a transistor 200c. Hereinafter, differences from the contents described using FIGS. 1, 13, etc. will be mainly described, and overlapping parts will be referred to and may not be described again.

[0364] 17 includes an insulating layer 216 over a substrate (not shown), an insulating layer 221 over the insulating layer 216, an insulating layer 222 over the insulating layer 221, a transistor 200a, a transistor 200b, a transistor 200c, and a semiconductor layer 230c over the insulating layer 222, and a capacitor 100, an insulating layer 275, and an insulating layer 280 over the semiconductor layer 230c. The transistors 200a and 200b can be described in detail with reference to the transistors 200a and 200b in FIG. 1, respectively. The capacitor 100 can be described in detail with reference to the capacitor 100 in FIG. 13.

[0365] The transistor 200c includes a semiconductor layer 230b, a conductive layer 242c and a conductive layer 242g over the semiconductor layer 230b and the insulating layer 222, an insulating layer 255c over the conductive layer 242c and the conductive layer 242g, an insulating layer 250c over the semiconductor layer 230b and the insulating layer 255c, and a conductive layer 260c over the insulating layer 250c. The conductive layer 242g includes a conductive layer 242g1 and a conductive layer 242g2 over the conductive layer 242g1. In FIG. 17B, the conductive layer 260c has a two-layer structure.

[0366] The semiconductor layer 230b has a region that functions as a channel formation region of the transistor 200c. The conductive layer 260c has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200c. The insulating layer 250c has a region that functions as a first gate insulating layer of the transistor 200c. The conductive layer 242c has a region that functions as one of the source electrode and drain electrode of the transistor 200c. The conductive layer 242g has a region that functions as the other of the source electrode and drain electrode of the transistor 200c. Note that Figure 17(B) can also be said to be a cross-sectional view of the transistor 200c in the channel length direction.

[0367] The transistors 200b and 200c are adjacent to each other and share the semiconductor layer 230b and the conductive layer 242c. This allows the two transistors (the transistors 200b and 200c) to be formed in an area smaller than the area of ​​two transistors (for example, the area of ​​1.5 transistors). This allows the transistors to be arranged more densely than when the transistors 200b and 200c do not share the semiconductor layer 230b and the conductive layer 242c, thereby achieving high integration in the semiconductor device.

[0368] By using the above structure, the other of the source and drain of transistor 200a, one of the electrodes of capacitor 100, and the gate of transistor 200b are electrically connected, and one of the source and drain of transistor 200b and one of the source and drain of transistor 200c are electrically connected, thereby forming a memory cell (also called a 3T1C memory cell) consisting of three transistors and one capacitor.

[0369] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0370] <<Substrate>> Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates containing metal nitrides, substrates containing metal oxides, substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0371] <<Insulators>> Examples of insulators that can be used for the insulating layer (insulating layer 215, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 223, insulating layer 275, insulating layer 280, insulating layer 250, insulating layer 255, insulating layer 241, insulating layer 282, insulating layer 283, insulating layer 285, etc., as well as insulating layer 287 and insulating layer 289, etc., which will be described later) include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0372] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, materials can be selected according to the insulator's function.

[0373] Examples of insulators with a high relative dielectric constant (also called high-dielectric-constant materials or high-k materials) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0374] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0375] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0376] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor layer 230, oxygen vacancies in the semiconductor layer 230 can be compensated for.

[0377] <<Conductors>> Conductors applicable to the conductive layers (conductive layer 242, conductive layer 260, conductive layer 240, conductive layer 205, etc., as well as conductive layer 245 described below) are preferably metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys containing the above-mentioned metal elements or alloys combining the above-mentioned metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Also, semiconductors with high conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0378] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0379] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0380] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0381] <Example of a method for manufacturing a semiconductor device> An example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to Figures 18 to 34. Here, the case of manufacturing the semiconductor device illustrated in Figures 13A to 13C will be described as an example.

[0382] 18 to 33, (A) in each figure shows a plan view. Also, (B) in each figure shows a cross-sectional view corresponding to the portion indicated by the dashed line A1-C1-B2 in (A) of each figure. Note that in the plan view of (A) of each figure, some elements are omitted for clarity.

[0383] In the following, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer can be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0384] There are three types of sputtering methods: RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0385] CVD methods can be classified into PECVD, thermal CVD, photo-CVD, etc. They can also be further divided into metal CVD (MCVD) and MOCVD depending on the source gas used.

[0386] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0387] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0388] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0389] Furthermore, the CVD method allows for the deposition of a film with any desired composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows for the deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When depositing a film while changing the flow rate ratio of the source gases, the time required for film deposition can be shortened compared to when depositing a film using multiple deposition chambers, since no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0390] Furthermore, the ALD method allows for the deposition of films of any desired composition by simultaneously introducing multiple different precursors, or by controlling the number of cycles for each precursor.

[0391] First, a substrate (not shown) is prepared, and an insulating layer 215 is formed on the substrate (see FIGS. 18A and 18B). As described above, the insulating layer 215 can be formed using an insulating layer similar to one or more of the insulating layers 282 and 283. The insulating layer 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulating layer 215.

[0392] Next, the insulating layer 216 is formed over the insulating layer 215. The insulating layer 216 is preferably formed by a sputtering method. The sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, so that the hydrogen concentration in the insulating layer 216 can be reduced. However, the method for forming the insulating layer 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is formed as the insulating layer 216 by a sputtering method.

[0393] The insulating layers 215 and 216 are preferably formed in succession without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This allows the insulating layers 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen entering the films between film formation steps.

[0394] Here, a first opening and a second opening that reach the insulating layer 215 are formed in the insulating layer 216, and a conductive layer 205a and a conductive layer 205b are formed in the first opening and the second opening, respectively, to form the transistor 200a and the transistor 200b shown in Figures 12A to 12D. The conductive layer 205a and the conductive layer 205b can be formed by depositing a conductive film that can be used for the conductive layer 205a and the conductive layer 205b so as to fill the first opening and the second opening, and then removing part of the conductive film by CMP treatment.

[0395] Next, the insulating layer 221 is formed over the insulating layer 216 (see FIGS. 18A and 18B).

[0396] The insulating layer 221 may be formed using any of the above insulators that have a barrier property against oxygen, hydrogen, and water. The insulating layer 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulating layer 221 by a PEALD method.

[0397] Next, the insulating layer 222 is formed over the insulating layer 221 (see FIGS. 18A and 18B).

[0398] The insulating layer 222 is preferably formed using an insulator containing one or both of aluminum and hafnium oxides. As the insulator containing one or both of aluminum and hafnium oxides, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. When the insulating layer 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the transistor through the insulating layer 222, thereby preventing oxygen vacancies from being generated in the semiconductor layer 230.

[0399] The insulating layer 222 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is formed as the insulating layer 222 by thermal ALD.

[0400] In this embodiment, silicon nitride is formed as the insulating layer 221 by a PEALD method, and hafnium oxide is formed as the insulating layer 222 by a thermal ALD method. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulating layer 221 in this manner, it is possible to suppress diffusion of hydrogen from underlying layers such as the transistors 200a and 200b. Furthermore, by using hafnium oxide, which has a function of capturing or fixing hydrogen, for the insulating layer 222, hydrogen contained in the semiconductor layer 230 can be captured or fixed to the insulating layer 222. This allows the hydrogen concentration in the semiconductor layer 230 and its vicinity to be reduced.

[0401] Next, an insulating film 223P is formed over the insulating layer 222 (see FIGS. 18A and 18B). For example, an insulator that can be used for the insulating layer 216 may be used as the insulating film 223P. The insulating film 223P can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is formed as the insulating film 223P by a sputtering method.

[0402] Next, the insulating film 223P is etched to form insulating layers 223a, 223b, and 223c (see FIGS. 19A and 19B). The insulating layers 223a to 223c function as templates for forming the semiconductor layer 230.

[0403] In this specification, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identifying reference numeral such as “_1”, “[n]”, or “[m,n]” may be added to the reference numeral. In this specification, when it is not necessary to distinguish between multiple elements, an identifying reference numeral may not be used. For example, when it is not necessary to distinguish between the insulating layers 223a to 223c, the insulating layers may be simply referred to as the “insulating layer 223.” Furthermore, in this specification, when referring to an arbitrary element, an identifying reference numeral may not be used. For example, when referring to an arbitrary insulating layer 223, the insulating layer 223 may be simply referred to as the “insulating layer 223.” The same applies to the transistor 200, the semiconductor layer 230, the insulating layer 241, the insulating layer 250, the insulating layer 255, the conductive layer 205, the conductive layer 240, the conductive layer 242, the conductive layer 245, the conductive layer 260, the opening 290, the opening 291, the opening 292, and the like.

[0404] The insulating layer 223 can be processed into an island shape by lithography. For this processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. In this embodiment, as shown in FIGS. 19A and 19B, three columnar insulating layers 223 (insulating layers 223a to 223c) are formed and arranged in the C1-B2 direction.

[0405] 19B, the side surface of the insulating layer 223 may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222. With such a structure, a smaller area and higher density can be achieved when providing a plurality of transistors.

[0406] Next, a semiconductor film 230P is formed to cover the insulating layer 223 (see FIGS. 20A and 20B). The semiconductor film 230P is a metal oxide film that will become the semiconductor layer 230 in a later step, and the above-mentioned metal oxide films can be used. The semiconductor film 230P can be formed by sputtering, CVD, MBE, PLD, or ALD.

[0407] Since the semiconductor film 230P is formed along the insulating layer 223, it is preferable that the semiconductor film 230P has good coverage. Therefore, it is preferable that the semiconductor film 230P is formed using an ALD method or the like that has good coverage. Furthermore, since it is preferable that the semiconductor layer 230 has a high aspect ratio, it is preferable that the semiconductor film 230P has a thin film thickness. Therefore, it is preferable that the semiconductor film 230P is formed using an ALD method that allows film thickness adjustment to a thin film thickness. By forming the semiconductor film 230P in this manner, the semiconductor film 230P is formed in contact with the upper surface and side surfaces of the insulating layer 223.

[0408] Here, the semiconductor film 230P is preferably formed by the same method as that for forming the oxide semiconductor layer 30 described in the above-mentioned [Method for manufacturing an oxide semiconductor layer]. By forming the semiconductor film 230P in this manner, the semiconductor film 230P is formed parallel or approximately parallel to the surface on which it is to be formed.

[0409] For example, as shown in FIG. 3B, when the semiconductor layer 230a has a three-layer structure including semiconductor layers 230a1 to 230a3, the films that become the semiconductor layers 230a1 and 230a3 can be deposited by ALD, and the film that becomes the semiconductor layer 230a2 can be deposited by sputtering. Specifically, the film that becomes the semiconductor layer 230a1 can be deposited to have a composition of In:Zn=2:1 (atomic ratio) or a composition similar thereto. Alternatively, indium oxide can be used for the film that becomes the semiconductor layer 230a1. Alternatively, the film that becomes the semiconductor layer 230a2 can be deposited using an oxide target with a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition similar thereto. Alternatively, the film that becomes the semiconductor layer 230a3 can be deposited to have a composition of In:Zn=2:1 (atomic ratio) or a composition similar thereto. Alternatively, indium oxide can be used for the film that becomes the semiconductor layer 230a3.

[0410] Next, heat treatment is preferably performed within a temperature range in which the semiconductor film 230P does not become polycrystallized. The heat treatment of the semiconductor film 230P may be performed by the same method as the heat treatment of the oxide semiconductor layer 30 described in the above-mentioned [Method for manufacturing an oxide semiconductor layer].

[0411] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0412] By forming the semiconductor film 230P using the above method and then performing a heat treatment, the semiconductor film 230P that will become the semiconductor layer 230 can be made into AG CAAC. This improves the on-state current, S value, field-effect mobility, and frequency characteristics of the transistor 200, thereby providing a semiconductor device with good electrical characteristics. In addition, a highly reliable semiconductor device can be provided.

[0413] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0414] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the semiconductor film 230P and the like as much as possible. Note that highly purified gas can also be used for the heat treatment before and after this step.

[0415] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the semiconductor film 230P. Reducing the impurities in the film in this way improves the crystallinity of the semiconductor film 230P, resulting in a denser, more compact structure. This increases the crystalline regions in the semiconductor film 230P, reducing in-plane variations in the crystalline regions in the semiconductor film 230P. This reduces in-plane variations in the electrical characteristics of the transistor.

[0416] Furthermore, by performing heat treatment, oxygen can be supplied to the semiconductor film 230P, and oxygen vacancies in the semiconductor film 230P can be reduced, thereby improving the reliability of the transistor 200.

[0417] Furthermore, by performing the heat treatment, hydrogen in the semiconductor film 230P moves to the insulating layer 222 and is absorbed into the insulating layer 222. In other words, hydrogen in the semiconductor film 230P diffuses into the insulating layer 222. Therefore, the hydrogen concentration in the insulating layer 222 increases, but the hydrogen concentration in the semiconductor film 230P decreases. Note that by providing the insulating layer 221 in contact with the lower surface of the insulating layer 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulating layer 221 during the heat treatment.

[0418] In particular, the semiconductor film 230P (later the semiconductor layers 230a and 230b) functions as a channel formation region of the transistor 200a and the transistor 200b. The transistor 200a and the transistor 200b formed using the semiconductor film 230P with a reduced hydrogen concentration are preferable because they have good reliability.

[0419] Note that it is preferable to perform a treatment to improve the crystallinity of the semiconductor film 230P during or after the formation of the semiconductor film 230P. Examples of treatments to improve the crystallinity of the semiconductor film 230P include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0420] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the semiconductor film 230P multiple times during the formation of the semiconductor film 230P. For example, when the semiconductor film 230P is formed by an ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each semiconductor film 230P having a thickness within a predetermined range, which can improve productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm as the semiconductor film 230P, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that there is no particular limitation on the method for forming the first oxide semiconductor film and the second oxide semiconductor film, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor film by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the elements contained in the layers constituting the formation surface inhibit crystallization of the oxide semiconductor (for example, when the layers contain silicon, carbon, or the like). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The semiconductor film 230P can be formed as a single layer or a stacked structure of three or more layers.

[0421] Furthermore, a treatment for increasing the crystallinity of the semiconductor film 230P may be performed after the semiconductor film 230P is formed. Specifically, the treatment may be performed directly on the formed semiconductor film 230P, or may be performed via another film, such as an insulating film, formed on the semiconductor film 230P. For example, a microwave plasma treatment may be performed directly after the semiconductor film 230P is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like) may be formed after the semiconductor film 230P is formed, and then a heat treatment or a microwave plasma treatment may be performed on the semiconductor film 230P via the insulating film.

[0422] The above-described treatment for increasing the crystallinity of the semiconductor film 230P can also serve as treatment for removing impurities contained in the semiconductor film 230P. For example, carbon, hydrogen, nitrogen, and the like contained in the semiconductor film 230P can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the semiconductor film 230P in an oxygen gas atmosphere, oxygen vacancies in the semiconductor film 230P can be reduced.

[0423] When performing the treatment to enhance the crystallinity of the semiconductor film 230P, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. to 600° C., or 300° C. to 450° C. The heat treatment temperature is preferably set to 100° C. to 700° C., or 300° C. to 450° C.

[0424] By increasing the crystallinity of the semiconductor film 230P, a highly reliable transistor can be realized.

[0425] Next, a portion of the semiconductor film 230P is removed by anisotropic etching to form semiconductor layers 230a to 230c (see FIGS. 21A and 21B). The semiconductor film 230P is mainly etched in a portion parallel to the substrate surface, and a sidewall-shaped semiconductor layer 230 is formed in contact with the side surface of the insulating layer 223. While FIG. 22B shows a structure in which curved shapes are formed on both the A1 side and the B2 side of the upper portion of the semiconductor layer 230, the present invention is not limited thereto, and a curved shape may be formed only on the side of the semiconductor layer 230 that is not in contact with the insulating layer 223. When removing a portion of the semiconductor film 230P by anisotropic etching, an insulator serving as a hard mask may be provided in the portion. Suitable insulating films that can be used include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide.

[0426] Anisotropic etching can form a semiconductor layer 230 with a high aspect ratio. By using the semiconductor layer 230, the channel width of the transistor 200 can be increased without increasing the occupied area, thereby improving the on-state current and frequency characteristics of the transistor 200. Furthermore, the contact area between the semiconductor layer 230 and the conductive layer 242 can be increased without increasing the occupied area, thereby improving the on-state current and frequency characteristics of the transistor 200. By forming the semiconductor layer 230 in this manner, the semiconductor layer 230 is formed parallel or approximately parallel to the surface on which it is formed.

[0427] It is preferable to use a dry etching method for anisotropically etching the semiconductor film 230P.

[0428] The etching gas used in the dry etching process may be an etching gas containing a halogen. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine may be used. For example, the etching gas may be C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas, either singly or in combination. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas may be added to the above-mentioned etching gas as appropriate. Depending on the workpiece to be dry-etched, a gas containing a hydrocarbon gas or hydrogen gas, but not a halogen gas, may be used as the etching gas. Hydrocarbons used in the etching gas include methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. Etching conditions can be set appropriately depending on the target to be etched.

[0429] The dry etching apparatus can be a capacitively coupled plasma (CCP) etching apparatus with parallel-plate electrodes. A capacitively coupled plasma etching apparatus with parallel-plate electrodes can be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency can be applied to each of the parallel-plate electrodes. Alternatively, multiple different high-frequency voltages can be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. A DF-CCP etching apparatus can be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, multiple different high-frequency voltages can be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus with a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as the dry etching apparatus with a high-density plasma source. The etching equipment can be configured appropriately depending on the object to be etched. In the dry etching equipment described above, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, allowing for highly anisotropic etching.

[0430] Next, the insulating layer 223 is removed (see FIGS. 22A and 22B). Note that the insulating layer 223 can be removed by dry etching or wet etching. For example, the insulating layer 223 is preferably removed by wet etching.

[0431] Furthermore, by using a material that is difficult to etch, such as hafnium oxide, for the insulating layer 222, the insulating layer 222 can function as an etching stopper in the etching process of the semiconductor film 230P and the insulating layer 223.

[0432] As shown in FIG. 22A, the top surface of the semiconductor layer 230a has a circumferential shape with both ends coinciding. After the insulating layer 223a is removed, the semiconductor layer 230a can also be said to have a shape with an opening in the center. Furthermore, when the semiconductor layer 230a has a three-layer structure of semiconductor layers 230a1 to 230a3 as described above, the circumferential semiconductor layer 230a is formed in the order of semiconductor layer 230a1, semiconductor layer 230a2, and semiconductor layer 230a3, centered on the region where the insulating layer 223a was formed. Therefore, as shown in FIG. 9A, in a cross-sectional view in the channel width direction, the semiconductor layers 230a3, 230a2, 230a1, 230a1, 230a2, and 230a3 are arranged symmetrically in this order.

[0433] Although the above description has been given of a configuration in which three circumferential semiconductor layers 230 are provided, the present invention is not limited to this. For example, one, two, or four or more circumferential semiconductor layers 230 may be provided. Furthermore, the circumferential semiconductor layers 230 may be joined to form a semiconductor layer 230 having a shape with multiple openings. For example, as shown in FIG. 4(B), a semiconductor layer 230 having three openings arranged in the B3-B4 direction in top view may be formed. In this case, three insulating layers 223 may be formed adjacent to each other at a short distance in the process shown in FIGS. 19(A) and 19(B). Furthermore, as shown in FIG. 4(C), a semiconductor layer 230 having a lattice shape in top view may be formed. In this case, a lattice-shaped trench may be formed in the insulating layer 223 in the process shown in FIGS. 19(A) and 19(B).

[0434] 22(A), the semiconductor layer 230 has a circumferential structure in top view, but etching may be further performed to remove a portion of the semiconductor layer 230. For example, in the structure shown in FIG. 22(A), by removing a portion, the semiconductor layer 230 can be made into a rectangular shape extending in the A5-A6 direction in top view.

[0435] 21A and 21B, one insulating layer 223a and one semiconductor layer 230a are provided for one transistor 200a, but the present invention is not limited to this. As shown in Figures 34A and 34B, one transistor may have two insulating layers 223a and two semiconductor layers 230a. In this manner, the transistor shown in Figure 4A can be manufactured.

[0436] Next, a conductive film 242P1 is formed over the insulating layer 222 and the semiconductor layer 230, and a conductive film 242P2 is formed over the conductive film 242P1 (see FIGS. 23A and 23B). The conductive film 242P1 may be formed using conductors corresponding to the conductive layers 242a1, 242b1, 242c1, 242d1, and 242e1. The conductive film 242P2 may be formed using conductors corresponding to the conductive layers 242a2, 242b2, 242c2, and 242d2.

[0437] The conductive films 242P1 and 242P2 can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. For example, tantalum nitride can be formed as the conductive film 242P1 by sputtering. Alternatively, titanium nitride can be formed as the conductive film 242P1 by CVD. Furthermore, tungsten can be formed as the conductive film 242P2 by sputtering or CVD. By forming the conductive film 242P1 to cover the semiconductor layer 230, the contact area between the semiconductor layer 230 and the conductive layer 242 can be increased without increasing the occupied area. This can improve the on-state current and frequency characteristics of the transistor 200.

[0438] Next, the conductive film 242P1 and the conductive film 242P2 are processed into an island shape using lithography to form a conductive layer 242Q (conductive layer 242Q1 and conductive layer 242Q2), a conductive layer 242R (conductive layer 242R1 and conductive layer 242R2), and a conductive layer 242S (conductive layer 242S1 and conductive layer 242S2) (see FIGS. 24(A) and 24(B)). The conductive layer 242Q1, the conductive layer 242R1, and the conductive layer 242S1 are formed by processing the conductive film 242P1, and the conductive layer 242Q2, the conductive layer 242R2, and the conductive layer 242S2 are formed by processing the conductive film 242P2. At this time, the conductive layers 242Q, 242R, and 242S are preferably formed to cover the semiconductor layers 230a, 230b, and 230c, respectively. In addition, the insulating layer 222 is exposed in regions that do not overlap with the conductive layers 242Q to 242S.

[0439] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. Note that the above description can be referred to for the conditions for the dry etching method and the dry etching apparatus.

[0440] The side surfaces of the conductive layers 242Q to 242S may be configured to be perpendicular or approximately perpendicular to the top surface of the insulating layer 222. With such a configuration, it is possible to reduce the area and increase the density when providing a plurality of transistors.

[0441] However, the present invention is not limited to the above, and the side surfaces of the semiconductor layer 230 and the conductive layers 242Q to 242S may each be tapered. The taper angle of the side surfaces of the semiconductor layer 230 and the conductive layers 242Q to 242S may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this way, coverage by the insulating layer 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0442] In the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductive layer, a semiconductor layer, an insulating layer, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam can be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0443] Note that the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0444] Furthermore, a hard mask made of an insulating layer or a conductive layer may be used under the resist mask. When using a hard mask, an insulating layer or a conductive layer serving as a hard mask material is formed on the conductive film 242P2, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242P2 and the like may be performed after removing the resist mask or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242P1 or the conductive film 242P2. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0445] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC and SOG films as masks can improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0446] Next, an insulating layer 275 is formed to cover the conductive layers 242Q to 242S, and an insulating layer 280 is further formed over the insulating layer 275 (see FIGS. 25A and 25B). The insulating layer 275 and the insulating layer 280 may be formed using any of the above-described insulators.

[0447] Here, the insulating layer 275 preferably contacts the upper surface of the insulating layer 222 .

[0448] The insulating layer 275 and the insulating layer 280 can each be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0449] It is preferable to form an insulating layer with a flat upper surface as the insulating layer 280 by forming an insulating film that will become the insulating layer 280 and performing CMP on the insulating film. Note that it is also possible to form a silicon nitride film on the insulating layer 280 by, for example, a sputtering method and perform CMP until the silicon nitride film reaches the insulating layer 280.

[0450] The insulating layer 275 is preferably formed using an insulator that has a function of suppressing oxygen permeation. For example, the insulating layer 275 is preferably formed by depositing silicon nitride by a PEALD method. Alternatively, the insulating layer 275 is preferably formed by depositing aluminum oxide by a sputtering method and then depositing silicon nitride thereon by a PEALD method. The insulating layer 275 having the above structure can improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0451] In this way, the semiconductor layer 230 and the conductive layers 242Q to 242S can be covered with the insulating layer 275, which has a function of suppressing oxygen diffusion. This makes it possible to suppress oxygen from diffusing directly from the insulating layer 280 or the like into the semiconductor layer 230 and the conductive layers 242Q to 242S in a later process.

[0452] The insulating layer 280 is preferably formed of silicon oxide by a sputtering method. The insulating layer 280 containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. The hydrogen concentration in the insulating layer 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating layer. The heat treatment may be performed under reduced pressure, and the insulating layer may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 275 can be removed, and the moisture and hydrogen concentrations in the semiconductor layer 230 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0453] Next, the conductive layer 242Q2, the conductive layer 242R2, the conductive layer 242S2, the insulating layer 275, and the insulating layer 280 are processed using lithography to form an opening 291a that reaches the conductive layer 242Q1 and the insulating layer 222, and an opening 291b that reaches the conductive layer 242Q1, the conductive layer 242R1, the conductive layer 242S1, and the insulating layer 222 (see FIGS. 26(A) and 26(B)). Here, the conductive layer 242Q2 is divided to form the conductive layer 242a2 and the conductive layer 242b2, the conductive layer 242R2 is divided to form the conductive layer 242c2 and the conductive layer 242d2, and the conductive layer 242S2 is divided to form the conductive layer 242e2 and the conductive layer 242f2. In a cross-sectional view of the transistor 200a in the channel length direction, the width of the opening 291a corresponds to the shortest distance between the conductive layer 242a2 and the conductive layer 242b2. The opening 291a is formed in a region overlapping with the semiconductor layer 230a, and the opening 291b is formed in a region overlapping with the semiconductor layer 230b and a region overlapping with the semiconductor layer 230c. Note that the conductive layer 242S1 is the conductive layer 242e1 shown in FIG. 13, and therefore in FIG. 26 and subsequent figures, the conductive layer 242S1 is shown as the conductive layer 242e1.

[0454] The lithography method can be any of the above-mentioned methods. In order to finely process the openings 291a and 291b, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0455] The above processing is preferably performed using a dry etching method. Dry etching is suitable for forming openings with high aspect ratios because it allows anisotropic etching. The above description can be referred to for the conditions of the dry etching method and the dry etching apparatus.

[0456] Next, an insulating film 255P is formed to cover the insulating layer 280, the conductive layer 242Q1, the conductive layer 242R1, the conductive layer 242e1, and the insulating layer 222 (see FIGS. 27(A) and 27(B)). The insulating film 255P is an insulating film that will become the insulating layer 255a and the insulating layer 255b in a later process, and the insulating layer described above can be used. The insulating film 255P can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0457] Since the insulating film 255P is formed along the openings 291a and 291b, it is preferable that the insulating film 255P has good coverage. Therefore, it is preferable that the insulating film 255P is formed using an ALD method or the like that has good coverage. For example, it is preferable that the insulating film 255P is formed of silicon nitride using the PEALD method.

[0458] Next, using lithography, the conductive layer 242Q1 and the insulating film 255P are processed at the opening 291a to form an opening 292a reaching the semiconductor layer 230a, and the conductive layer 242R1 and the insulating film 255P are processed at the opening 291b to form an opening 292b reaching the semiconductor layer 230b (see FIGS. 28(A) and 28(B)). Here, the conductive layer 242Q1 is divided to form the conductive layers 242a1 and 242b1, and the conductive layer 242R1 is divided to form the conductive layers 242c1 and 242d1. In a cross-sectional view of the transistor 200a in the channel length direction, the width of the opening 292a corresponds to the shortest distance between the conductive layers 242a1 and 242b1. Since the opening 292a is formed inside the opening 291a, the shortest distance between the conductive layer 242a1 and the conductive layer 242b1 is smaller than the shortest distance between the conductive layer 242a2 and the conductive layer 242b2.

[0459] The lithography method can be any of the above-mentioned methods. To finely process the openings 292a and 292b, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0460] 29(A) and 29(B), a groove or an opening is formed in the insulating layer 222 in a region that does not overlap with the semiconductor layer 230a in the opening 292a, and a groove or an opening is formed in the insulating layer 222 in a region that does not overlap with the semiconductor layer 230b in the opening 292b, thereby forming the transistor 200a and the transistor 200b shown in FIGS. 15(A) to 15(D). Note that when the groove or the opening is formed, the thickness of the semiconductor layer 230a in a region that overlaps with the opening 292a and the thickness of the semiconductor layer 230b in a region that overlaps with the opening 292b may be reduced.

[0461] After processing the conductive layer 242Q1 and the conductive layer 242R1, an ashing process using oxygen plasma may be performed. This oxygen plasma process can remove impurities generated during the etching process and diffused into the semiconductor layer 230. These impurities include those derived from components contained in the workpiece of the etching process and components contained in the etching gas. Examples of such impurities include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, when chlorine gas is used in processing the conductive layer 242Q1 and the conductive layer 242R1, the semiconductor layer 230 is exposed to an atmosphere containing chlorine gas. Therefore, it is preferable to remove chlorine adhering to the semiconductor layer 230. Removing impurities adhering to the semiconductor layer 230 in this manner can improve the electrical characteristics and reliability of the transistor.

[0462] Furthermore, a cleaning process may be performed to remove impurities and the like that have adhered to the surface of the semiconductor layer 230 during the etching process. Cleaning methods include wet cleaning using a cleaning solution (which may also be called a wet etching process), plasma processing using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0463] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0464] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution of ammonia water diluted with pure water may be referred to as "diluted ammonia water." The concentration and temperature of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0465] For ultrasonic cleaning, it is preferable to use a frequency of 200 kHz or more, and more preferably a frequency of 900 kHz or more, which can reduce damage to the semiconductor layer 230 and the like.

[0466] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0467] In this embodiment, the cleaning treatment is performed by wet cleaning using diluted ammonia water. By performing this cleaning treatment, impurities attached to the surface of the semiconductor layer 230 or diffused inside can be removed. Furthermore, the crystallinity of the semiconductor layer 230 can be improved.

[0468] It is preferable to perform a heat treatment after the etching or cleaning. The temperature of the heat treatment is 100°C to 650°C, preferably 250°C to 600°C, more preferably 300°C to 550°C, and even more preferably 350°C to 400°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment is preferably performed in an oxygen-containing atmosphere, for example, at a temperature of 350°C for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the semiconductor layer 230, thereby reducing oxygen vacancies. Furthermore, this heat treatment can improve the crystallinity of the semiconductor layer 230. Furthermore, the supplied oxygen reacts with hydrogen remaining in the semiconductor layer 230, thereby removing the hydrogen as HO (dehydration). As a result, hydrogen remaining in the semiconductor layer 230 recombines with the oxygen vacancies to form V. O The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor provided with the semiconductor layer 230 can be improved, and reliability can be improved. Furthermore, variation in the electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air. Furthermore, the heat treatment can also serve as the heat treatment described in Embodiment 1. Therefore, the heat treatment may cause growth of a crystalline region in the semiconductor layer 230.

[0469] When heat treatment is performed with the conductive layer 242a and the conductive layer 242b in contact with the semiconductor layer 230a, the sheet resistance may decrease in the region of the semiconductor layer 230a that overlaps with the conductive layer 242a and the region of the semiconductor layer 230a that overlaps with the conductive layer 242b. The carrier concentration may also increase. Therefore, the resistance of the region of the semiconductor layer 230a that overlaps with the conductive layer 242a and the region of the semiconductor layer 230a that overlaps with the conductive layer 242b can be reduced in a self-aligned manner. The same can be said for the semiconductor layer 230b.

[0470] As described above, the insulating layer 255 having an inorganic insulator that is resistant to oxidation is provided in contact with the side surfaces of the conductive layer 242a2, the conductive layer 242b2, the conductive layer 242c2, and the conductive layer 242d2. This prevents the conductive layer 242a2, the conductive layer 242b2, the conductive layer 242c2, and the conductive layer 242d2 from being excessively oxidized by the heat treatment, even if a tungsten film that is relatively easily oxidized is used for the conductive layer 242a2, the conductive layer 242b2, the conductive layer 242c2, and the conductive layer 242d.

[0471] Next, an insulating film 250P to be the insulating layer 250 is formed on the insulating film 255P, the semiconductor layer 230, and the insulating layer 222 (see FIGS. 30(A) and 30(B)). Here, the insulating film 250P is provided in contact with the insulating film 255P, the conductive layer 242a1, the conductive layer 242b1, the semiconductor layer 230, and the insulating layer 222 in the opening 292a, and is provided in contact with the insulating film 255P, the conductive layer 242c1, the conductive layer 242d1, the semiconductor layer 230, and the insulating layer 222 in the opening 292b.

[0472] The insulating film 250P can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250P is preferably formed using an ALD method. Like the insulating layer 250 described above, the insulating film 250P is preferably formed to a thin thickness, and it is necessary to minimize thickness variations. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The thickness can be adjusted by the number of times this cycle is repeated, allowing for precise thickness adjustment. Furthermore, the insulating film 250P needs to be formed with good coverage on the bottom and side surfaces of the openings 291 and 292. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the openings 291 and 292, allowing the insulating film 250P to be formed with good coverage on the openings 291 and 292.

[0473] When the insulating film 250P is formed by the ALD method, ozone (O), oxygen (O), water (H2O), etc. can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidizing agent, the amount of hydrogen diffusing into the semiconductor layer 230 can be reduced.

[0474] The insulating layer 250 can have a stacked structure as shown in Figure 3(A) etc. For example, as shown in Figure 3(A), the insulating layer 250 can have a stacked structure of insulating layers 250a1 to 250a4. In this case, the insulating layer 250a1 can be formed by depositing aluminum oxide by a thermal ALD method, the insulating layer 250a2 can be formed by depositing silicon oxide by a PEALD method, the insulating layer 250a3 can be formed by depositing hafnium oxide by a thermal ALD method, and the insulating layer 250a4 can be formed by depositing silicon nitride by a PEALD method.

[0475] After the insulating film 250P or any of the insulators constituting the insulating film 250P is formed, microwave plasma treatment is preferably performed in an atmosphere containing oxygen.

[0476] In the microwave plasma treatment, it is preferable to use a microwave plasma treatment apparatus having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave plasma treatment apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. The use of high-density plasma can generate high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves in the microwave plasma treatment apparatus is preferably 1000 W to 10,000 W, more preferably 2000 W to 5,000 W. Furthermore, the microwave plasma treatment apparatus may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently introduced into the semiconductor layer 230.

[0477] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa to 1000 Pa, and more preferably being 300 Pa to 700 Pa. The treatment temperature is preferably 750°C or less, more preferably 500°C or less, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C to 750°C, and more preferably 300°C to 500°C.

[0478] Furthermore, for example, the microwave plasma treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is preferably greater than 0% and less than 100%, more preferably greater than 0% and less than 50%, more preferably greater than 10% and less than 40%, and even more preferably greater than 10% and less than 30%. In this way, by performing microwave plasma treatment in an oxygen-containing atmosphere, the carrier concentration in the semiconductor layer 230 can be reduced. Furthermore, by preventing excessive oxygen from being introduced into the chamber during microwave plasma treatment, an excessive reduction in the carrier concentration in the semiconductor layer 230 can be prevented.

[0479] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductive layer 242a and the conductive layer 242b of the semiconductor layer 230. The action of the plasma, microwaves, etc., can reduce the V in the region. O The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when the structure shown in FIG. 3(A) is used, it is preferable to use an insulating film (for example, aluminum oxide) that has the function of capturing or fixing hydrogen as the insulating layer 250a1. With this structure, hydrogen generated by microwave plasma treatment can be captured or fixed by the insulating film 250P. In this way, V included in the channel formation region can be removed. OAs a result, oxygen vacancies in the channel formation region and V O By supplying oxygen radicals generated by the oxygen plasma to oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0480] The oxygen implanted into the channel formation region can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may be in one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulating layer 250 can be improved, thereby improving the reliability of the transistor.

[0481] Furthermore, by performing microwave plasma treatment, impurities such as carbon in the semiconductor layer 230 can also be removed. Removing carbon, which is an impurity in the semiconductor layer 230, can improve the crystallinity of the semiconductor layer 230. This allows the semiconductor layer 230 to become a c-axis aligned crystalline oxide semiconductor (CAAC-OS). In particular, when the semiconductor layer 230 is formed by the ALD method, carbon contained in the precursor may be incorporated into the semiconductor layer 230, so it is preferable to remove carbon by microwave plasma treatment.

[0482] Meanwhile, the semiconductor layer 230 has a region overlapping with either the conductive layer 242a or the conductive layer 242b. This region can function as a source region or a drain region. Here, the conductive layer 242a and the conductive layer 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when microwave plasma treatment is performed in an oxygen-containing atmosphere. Therefore, the conductive layer 242a and the conductive layer 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0483] The conductive layers 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, so that these effects do not reach the regions of the semiconductor layer 230 that overlap with either the conductive layer 242a or the conductive layer 242b. As a result, the microwave plasma treatment can reduce the V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0484] As described above, oxygen vacancies and V O By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low-resistance region state) before the microwave plasma treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0485] Furthermore, by performing microwave plasma treatment to modify the film quality of the insulating layer 250, it is possible to suppress the diffusion of hydrogen, water, impurities, and the like. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, and the like into the semiconductor layer 230 and the like through the insulating layer 250 in post-processes such as film formation of a conductive film that will become the conductive layer 260, or post-treatments such as heat treatment. In this way, by improving the film quality of the insulating layer 250, it is possible to improve the reliability of the transistor.

[0486] When the insulating layer 250 has a stacked structure of insulating layers 250a1 to 250a4, microwave plasma treatment is preferably performed after the insulating layer 250a2 is formed. Furthermore, microwave plasma treatment may be performed again after the insulating layer 250a3 is formed. In this manner, microwave plasma treatment in an atmosphere containing oxygen may be performed multiple times (at least twice or more). The microwave plasma treatment may also serve as the heat treatment described in Embodiment 1. Therefore, the microwave plasma treatment may grow a crystalline region in the semiconductor layer 230.

[0487] Furthermore, heat treatment may be performed while the reduced pressure state is maintained after the microwave plasma treatment. By performing such treatment, hydrogen in the insulating film and the semiconductor layer 230 can be efficiently removed. Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave plasma treatment may be repeated multiple times. By repeatedly performing the heat treatment, hydrogen in the insulating film and the semiconductor layer 230 can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. Furthermore, the heat treatment described above can also serve as the heat treatment described in Embodiment 1. Therefore, the heat treatment described above may cause growth of a crystalline region in the semiconductor layer 230.

[0488] Next, the insulating film 250P and the insulating film 255P are processed at the opening 291b using lithography to form an opening 293 that reaches the conductive layer 242b1 (see FIGS. 31(A) and 31(B)). The opening 293 preferably overlaps with the conductive layer 242b1. In other words, in a plan view, the periphery of the opening 293 is preferably located inside the conductive layer 242b1. With this configuration, a groove is formed in a region of the insulating layer 222 that does not overlap with the conductive layer 242b1, and it is possible to prevent a portion of the conductive film that will become the conductive layer 260b from remaining in the groove.

[0489] The lithography method can be any of the above-mentioned methods. To finely process the openings 292a and 292b, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0490] Next, a first conductive film to become the conductive layer 260a1 and the conductive layer 260b1, and a second conductive film to become the conductive layer 260a2 and the conductive layer 260b2 are sequentially formed (see FIGS. 32A and 32B). The first conductive film and the second conductive film can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, the first conductive film is formed by titanium nitride using a CVD method, and the second conductive film is formed by tungsten using a CVD method. The first conductive film and the second conductive film may be formed while heating the substrate. Heating the substrate can also serve as the above-mentioned heat treatment. Therefore, the above-mentioned substrate heating may cause the growth of a crystalline region in the semiconductor layer 230.

[0491] Next, the insulating film 255P, the insulating film 250P, the first conductive film, and the second conductive film are polished by CMP until the insulating layer 280 is exposed. That is, the portions of the insulating film 255P, the insulating film 250P, the first conductive film, and the second conductive film exposed from the openings 290, 291, and 292 are removed. As a result, the insulating layer 255a, the insulating layer 250a, and the conductive layer 260a (conductive layer 260a1 and conductive layer 260a2) are formed in the openings 291a and 292a, and the insulating layer 255b, the insulating layer 250b, and the conductive layer 260b (conductive layer 260b1 and conductive layer 260b2) are formed in the openings 291b, 292b, and 293 (see FIGS. 32A and 32B).

[0492] As a result, the insulating layer 255a is provided in contact with the insulating layer 280, the insulating layer 275, the conductive layer 242a, the conductive layer 242b, the semiconductor layer 230a, and the insulating layer 222 in the openings 291a and 292a. The insulating layer 250a is provided in contact with the insulating layer 255, the conductive layer 242a1, the conductive layer 242b1, the semiconductor layer 230a, and the insulating layer 222 in the openings 291a and 292a. The conductive layer 260a is arranged to fill the openings 291a and 292a with the insulating layer 250 interposed therebetween. In this manner, the transistor 200a is formed.

[0493] The insulating layer 255b is provided in contact with the insulating layer 280, the insulating layer 275, the conductive layer 242b, the conductive layer 242c, the conductive layer 242d, the conductive layer 242e1, the conductive layer 242e2, the conductive layer 242f2, the semiconductor layer 230b, and the insulating layer 222 in the opening 291b, the opening 292b, and the opening 293. The insulating layer 250b is provided in contact with the insulating layer 255b, the conductive layer 242b1, the conductive layer 242c1, the conductive layer 242d1, the conductive layer 242e1, the semiconductor layer 230b, and the insulating layer 222 in the opening 291b, the opening 292b, and the opening 293. The conductive layer 260b is arranged to fill the opening 291b, the opening 292b, and the opening 293 with the insulating layer 250b interposed therebetween. In this manner, the transistor 200b and the capacitor element 100 are formed.

[0494] Next, the insulating layer 282 is formed over the insulating layer 255, the insulating layer 250, the conductive layer 260, and the insulating layer 280 (see FIGS. 33A and 33B). The insulating layer 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 282 is preferably formed by a sputtering method. Alternatively, the insulating layer 282 may be formed by forming a first layer by an ALD method and then forming a second layer thereon by a sputtering method.

[0495] Furthermore, by depositing the insulating layer 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulating layer 280 during deposition. This allows the insulating layer 280 to contain excess oxygen. At this time, it is preferable to deposit the insulating layer 282 while heating the substrate. By depositing the insulating layer 282 in this manner, a suitable amount of oxygen can be supplied from the insulating layer 280 to the semiconductor layer 230 through the insulating layer 250. Furthermore, by providing the insulating layer 250a1 in the insulating layer 250, excessive oxygen can be supplied into the insulating layer 250, which can prevent the conductive layers 242a and 242b in the vicinity of the insulating layer 250 from being excessively oxidized.

[0496] The aluminum oxide film is formed using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen implanted into the insulating layer 280 can be controlled by the magnitude of the bias power applied to the substrate by sputtering. For example, the smaller the bias power, the less oxygen is implanted into the insulating layer 280, and the more likely the amount of oxygen is saturated even if the insulating layer 282 is thin. Furthermore, the greater the bias power, the more oxygen is implanted into the insulating layer 280. By reducing the bias power, the amount of oxygen implanted into the insulating layer 280 can be suppressed. When applying a substrate bias using an RF power supply, the RF frequency is preferably 10 MHz or higher. A typical frequency is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0497] Furthermore, by forming a second layer by sputtering on the first layer formed by the ALD method, the upper end of the insulating layer 250 and the upper surface of the conductive layer 260 can be protected from the impact of ion collisions caused by sputtering film formation.

[0498] Furthermore, heat treatment may be performed before the insulating layer 282 is formed. The heat treatment may be performed under reduced pressure, and the insulating layer 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating layer 280 can be removed and the moisture and hydrogen concentrations in the insulating layer 280 can be further reduced. The temperature for the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature for the heat treatment is 250° C.

[0499] Next, the insulating layer 283 is formed over the insulating layer 282 (see FIGS. 33A and 33B). The insulating layer 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 283 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas. In this embodiment, silicon nitride is formed as the insulating layer 283 by a sputtering method.

[0500] Here, the insulating layers 282 and 283 are preferably formed in succession without exposure to the air environment. By forming the insulating layers 282 and 283 without exposure to the air environment, impurities or moisture from the air environment can be prevented from adhering to the insulating layers 282 and 283, and the interface or the vicinity of the interface between the insulating layers 282 and 283 can be kept clean.

[0501] In this embodiment, silicon nitride is formed as the insulating layer 283, and aluminum oxide is formed as the insulating layer 282. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulating layer 283, hydrogen diffusion from the upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has a function of capturing or fixing hydrogen, for the insulating layer 282, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This allows the hydrogen concentration in the semiconductor layer 230 and its vicinity to be reduced.

[0502] Next, an insulating layer 285 is formed over the insulating layer 283 (see FIGS. 33A and 33B). The insulating layer 285 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating layer 285 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 285 can be reduced by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas. In this embodiment, silicon oxide is formed as the insulating layer 285 by a sputtering method.

[0503] Next, openings reaching the conductive layer 242a2, the conductive layer 242c2, and the conductive layer 242d2 are formed in the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 (see FIGS. 1B, 1C, and 13A). The openings may be formed by lithography. In forming the openings, it is preferable to process the workpiece by dry etching. The dry etching method is suitable for forming openings with a high aspect ratio because it allows anisotropic etching. When anisotropic etching is performed, for example, reactive ion etching is preferably performed. Note that the above description can be referred to for the conditions for the dry etching method and the dry etching apparatus. Note that although the shape of the opening is rectangular in top view in FIG. 13A, the shape is not limited thereto. For example, the opening may have a circular shape, an approximately circular shape such as an oval, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners when viewed from above.

[0504] Next, after the openings are formed, heat treatment may be performed. The temperature of the heat treatment is 100°C to 600°C, preferably 250°C to 550°C, more preferably 350°C to 450°C. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, since the conductive layers 242a2, 242c2, and 242d2 are exposed, the heat treatment is preferably performed in an atmosphere that does not contain an oxidizing gas or oxygen gas. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400°C for one hour. Note that the heat treatment may be performed under reduced pressure. The heat treatment allows oxygen contained in the insulating layer 280 to be supplied to the semiconductor layer 230 through the insulating layer 250. This reduces oxygen vacancies in the channel formation region of the semiconductor layer 230. The heat treatment can also serve as the heat treatment described above. Therefore, the heat treatment may cause a crystalline region of the semiconductor layer 230 to grow.

[0505] Here, because the side surfaces of the insulating layer 280 are exposed through the openings, the heat treatment can cause oxygen contained in the insulating layer 280 to diffuse outward, thereby controlling the amount of oxygen contained in the insulating layer 280. Meanwhile, because the insulating layers 282 and 283, which have barrier properties against oxygen, are provided on the insulating layer 280, oxygen does not diffuse outward from the upper surface of the insulating layer 280. This prevents excessive oxygen from diffusing outward from the insulating layer 280, which could lead to the formation of oxygen vacancies in the insulating layer 280. Furthermore, the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b are covered with the insulating layer 275 and the insulating layer 255. This prevents excessive oxygen from diffusing directly from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b during the heat treatment.

[0506] In this manner, the amount of oxygen in the insulating layer 280 can be more suitably adjusted, and a suitable amount of oxygen can be supplied to the semiconductor layer 230. This reduces oxygen vacancies in the semiconductor layer 230 and prevents excessive oxygen from being supplied to the semiconductor layer 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the step of exposing the side surfaces of the insulating layer 280 can also serve as the step of forming openings into which the conductive layers 240a to 240c are to be embedded, which simplifies the manufacturing...

Claims

1. a first transistor, a second transistor, and a first insulating layer; the first transistor includes a first semiconductor layer, first to fifth conductive layers, and a second insulating layer; the second transistor has a second semiconductor layer, a sixth conductive layer, and a third insulating layer; the first semiconductor layer and the second semiconductor layer are disposed on a substrate and spaced apart from each other; the first conductive layer and the second conductive layer are disposed on the first semiconductor layer; the third conductive layer is disposed on the first conductive layer; the fourth conductive layer is disposed on the second conductive layer; the first insulating layer is disposed on the third conductive layer, on the fourth conductive layer, and on the second semiconductor layer, and has a first opening and a second opening; the first opening is provided to overlap a region between the third conductive layer and the fourth conductive layer; the second opening is provided to overlap at least a portion of the second conductive layer and at least a portion of the second semiconductor layer; the second insulating layer is disposed in the first opening and overlies the first semiconductor layer; the fifth conductive layer is disposed on the second insulating layer in the first opening; the third insulating layer overlies the second semiconductor layer, is disposed in the second opening, and has a third opening overlapping the at least a portion of the second conductive layer; the sixth conductive layer has a region overlapping with the second semiconductor layer via the third insulating layer in the second opening, and a region in contact with the at least a portion of the second conductive layer in the third opening, A semiconductor device, wherein, in a cross-sectional view in a channel width direction, a height of the first semiconductor layer is greater than a width of the first semiconductor layer.

2. In claim 1, In a cross-sectional view in a channel width direction of the second transistor, the first semiconductor layer has a region facing the second semiconductor layer.

3. In claim 1, A semiconductor device, wherein a shortest distance between the first conductive layer and the second conductive layer is smaller than a shortest distance between the third conductive layer and the fourth conductive layer.

4. In claim 1, The fifth conductive layer and the sixth conductive layer have the same material.

5. In claim 1, A fourth insulating layer is provided. a fourth insulating layer having, in the first opening, a region in contact with at least a portion of an upper surface of the first conductive layer, a region in contact with at least a portion of an upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region in contact with a side surface of the fourth conductive layer.

6. In claim 1, the second transistor has seventh to tenth conductive layers; the seventh conductive layer and the eighth conductive layer are disposed on the second semiconductor layer; the ninth conductive layer is disposed on the seventh conductive layer; the tenth conductive layer is disposed on the eighth conductive layer; The second opening is provided to overlap a region between the ninth conductive layer and the tenth conductive layer.

7. In claim 6, A fifth insulating layer is provided. a semiconductor device, wherein the fifth insulating layer has, in the second opening, a region in contact with at least a portion of an upper surface of the seventh conductive layer, a region in contact with at least a portion of an upper surface of the eighth conductive layer, a region in contact with a side surface of the ninth conductive layer, a region in contact with a side surface of the tenth conductive layer, a side surface of the fourth conductive layer, and a region in contact with at least a portion of an upper surface of the second conductive layer.

8. In claim 6, 1. A semiconductor device comprising: a semiconductor device including: a first conductive layer; a second conductive layer; a seventh conductive layer; and an eighth conductive layer, each of which contains titanium and nitrogen.

9. In claim 6, 13. A semiconductor device comprising: a semiconductor device including: a first conductive layer and a second conductive layer; a second conductive layer and a third conductive layer;

10. a first transistor having a first semiconductor layer, a second transistor having a second semiconductor layer, a capacitor, a third semiconductor layer, and a first insulating layer; the first transistor has first to fifth conductive layers and a second insulating layer; the second transistor has a sixth conductive layer and a third insulating layer; the capacitive element includes a seventh conductive layer, the third insulating layer, and the sixth conductive layer; the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are disposed on a substrate and spaced apart from each other; the first conductive layer and the second conductive layer are disposed on the first semiconductor layer; the third conductive layer is disposed on the first conductive layer; the fourth conductive layer is disposed on the second conductive layer; the seventh conductive layer is disposed on the third semiconductor layer; the first insulating layer is disposed on the third conductive layer, on the fourth conductive layer, on the second semiconductor layer, and on the seventh conductive layer, and has a first opening and a second opening; the first opening is provided to overlap a region between the third conductive layer and the fourth conductive layer; the second opening is provided to overlap at least a portion of the second conductive layer, at least a portion of the seventh conductive layer, and at least a portion of the second semiconductor layer; the second insulating layer is disposed in the first opening and overlies the first semiconductor layer; the fifth conductive layer is disposed on the second insulating layer in the first opening; the third insulating layer overlies the second semiconductor layer, is disposed in the second opening, and has a third opening overlapping the at least a portion of the second conductive layer; the sixth conductive layer has a region overlapping with the second semiconductor layer via the third insulating layer in the second opening, a region overlapping with the seventh conductive layer via the third insulating layer in the second opening, and a region in contact with the at least a portion of the second conductive layer in the third opening, A semiconductor device, wherein, in a cross-sectional view in a channel width direction, a height of the first semiconductor layer is greater than a width of the first semiconductor layer.

11. In claim 10, In a cross-sectional view in a channel width direction of the second transistor, the first semiconductor layer has a region facing the second semiconductor layer, and the second semiconductor layer has a region facing the third semiconductor layer.

12. In claim 10, A semiconductor device, wherein a shortest distance between the first conductive layer and the second conductive layer is smaller than a shortest distance between the third conductive layer and the fourth conductive layer.

13. In claim 10, The fifth conductive layer and the sixth conductive layer have the same material.

14. In claim 10, A fourth insulating layer is provided. a fourth insulating layer having, in the first opening, a region in contact with at least a portion of an upper surface of the first conductive layer, a region in contact with at least a portion of an upper surface of the second conductive layer, a region in contact with a side surface of the third conductive layer, and a region in contact with a side surface of the fourth conductive layer.

15. In claim 10, the second transistor has eighth to eleventh conductive layers; the eighth conductive layer and the ninth conductive layer are disposed on the second semiconductor layer; the tenth conductive layer and the eleventh conductive layer are disposed on the eighth conductive layer and the ninth conductive layer, respectively; the second opening is provided to overlap a region between the tenth conductive layer and the eleventh conductive layer.

16. In claim 15, A fifth insulating layer is provided. A semiconductor device, wherein the fifth insulating layer has, in the second opening, a region in contact with at least a portion of an upper surface of the eighth conductive layer, a region in contact with at least a portion of an upper surface of the ninth conductive layer, a region in contact with a side surface of the tenth conductive layer, a region in contact with a side surface of the eleventh conductive layer, a region in contact with a side surface of the fourth conductive layer, and at least a portion of an upper surface of the second conductive layer, and a region located between the sixth conductive layer and the seventh conductive layer.

17. In claim 15, 1. A semiconductor device comprising: a semiconductor device including: a first conductive layer, a second conductive layer, a seventh conductive layer, an eighth conductive layer, and a ninth conductive layer, each of which contains titanium and nitrogen.

18. In claim 15, 13. A semiconductor device comprising: a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a tenth conductive layer, and an eleventh conductive layer, the third conductive layer, and the fourth conductive layer comprising tungsten.

19. In any one of claims 1 to 18, the first semiconductor layer comprises indium; the first semiconductor layer is formed perpendicular or substantially perpendicular to a surface of the substrate; A semiconductor device, wherein bright points arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in a cross-section of the first semiconductor layer observed using a transmission electron microscope.

20. In any one of claims 1 to 18, the first semiconductor layer comprises indium; the first semiconductor layer is formed perpendicular or substantially perpendicular to a surface of the substrate; the first semiconductor layer has a first region, a second region in contact with the first region, and a third region in contact with the second region; A semiconductor device, wherein, in cross-sectional observation of the first semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction perpendicular to the surface of the substrate are confirmed in each of the first region, the second region, and the third region.

21. In claim 20, the second region comprises zinc; the second region has crystals; A semiconductor device, wherein the c-axis of the crystal is approximately parallel to a normal direction to a side surface of the first semiconductor layer.

22. In claim 20, a content of indium in the first region is higher than a content of indium in the second region; A semiconductor device, wherein the third region has a higher indium content than the second region.

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