Display device and manufacturing method for the same

Abstract

To provide a display device whose yield can be improved.SOLUTION: A display device includes a lower electrode, a rib having a pixel opening overlapping with the lower electrode and covering an end part of the lower electrode, a partition wall including a bottom part disposed on the rib, a lower part disposed on the bottom part, and an upper part disposed on the lower part and projecting from a side surface of the lower part, an organic layer in contact with the lower electrode through the pixel opening and emitting light according to the voltage application, an upper electrode covering the organic layer in contact with at least one of the bottom part and the lower part, and a transparent conductive oxide layer disposed between the rib and the bottom part.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that enables improvement of yields in this type of display device is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield. [Means for solving the problem]

[0005] A display device according to one embodiment includes a lower electrode, a rib having a pixel opening overlapping the lower electrode and covering an end of the lower electrode, a partition including a bottom portion arranged on the rib, a lower portion arranged on the bottom portion, and an upper portion arranged on the lower portion and protruding from a side surface of the lower portion, an organic layer in contact with the lower electrode through the pixel opening and emitting light in response to application of a voltage, an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion, and a transparent conductive oxide layer arranged between the rib and the bottom portion.

[0006] A display device according to another embodiment includes a lower electrode, a rib having a pixel opening overlapping the lower electrode and covering an end of the lower electrode, a partition including a bottom portion arranged on the rib, a lower portion arranged on the bottom portion, and an upper portion arranged on the lower portion and protruding from a side surface of the lower portion, an organic layer in contact with the lower electrode through the pixel opening and emitting light in response to application of a voltage, an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion, and a transparent conductive oxide layer arranged between the lower electrode and the rib and having an opening overlapping the pixel opening.

[0007] A manufacturing method of a display device according to one embodiment includes forming a lower electrode, forming a rib having a pixel opening overlapping the lower electrode, forming a transparent conductive oxide layer covering the lower electrode and the rib, forming a partition wall on the conductive oxide layer, the partition wall including a bottom portion located above the rib, a lower portion located on the bottom portion, and an upper portion located on the lower portion and protruding from a side surface of the lower portion, removing a portion of the conductive oxide layer exposed from the bottom portion after forming the partition wall, forming an organic layer that contacts the lower electrode through the pixel opening and emits light in response to application of a voltage, and forming an upper electrode that covers the organic layer and is in contact with at least one of the bottom portion and the lower portion.

[0008] A manufacturing method of a display device according to another embodiment includes forming a lower electrode, forming a transparent conductive oxide layer covering the lower electrode, forming a rib covering the conductive oxide layer and having a pixel opening overlapping the lower electrode, forming a partition including a bottom portion located above the rib, a lower portion located on the bottom portion, and an upper portion located on the lower portion and protruding from a side surface of the lower portion, after forming the partition, removing a portion of the conductive oxide layer exposed from the rib through the pixel opening, forming an organic layer that contacts the lower electrode through the pixel opening and emits light in response to application of a voltage, and forming an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a layer structure that can be applied to the organic layer. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing an enlarged view of the partition wall and its vicinity according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an enlarged view of the bottom portion and the vicinity of the end of the conductive oxide layer according to the first embodiment. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a manufacturing process of the display device according to the first embodiment. [Figure 7B] FIG. 7B is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7A. [Figure 7C] FIG. 7C is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7C. [Figure 7E]FIG. 7E is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7D. [Figure 7F] FIG. 7F is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7E. [Figure 7G] FIG. 7G is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7F. [Figure 7H] FIG. 7H is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7G. [Figure 7I] FIG. 7I is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7H. [Figure 7J] FIG. 7J is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7I. [Figure 7K] FIG. 7K is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7J. [Figure 7L] FIG. 7L is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7K. [Figure 7M] FIG. 7M is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 7L. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a manufacturing process for forming a display element. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 8C. [Figure 9] FIG. 9 is a schematic cross-sectional view of a display device according to the second embodiment. [Figure 10] FIG. 10 is a schematic plan view of a rib, a lower electrode, and a conductive layer according to the second embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing an enlarged view of the partition wall and its vicinity shown in FIG. [Figure 12A] FIG. 12A is a schematic cross-sectional view showing a manufacturing process of the display device according to the second embodiment. [Figure 12B] FIG. 12B is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12A. [Figure 12C] FIG. 12C is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12B. [Figure 12D] FIG. 12D is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12C. [Figure 12E] FIG. 12E is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12D. [Figure 12F] FIG. 12F is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12E. [Figure 12G] FIG. 12G is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12F. [Figure 12H] FIG. 12H is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12G. [Figure 12I] FIG. 12I is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12H. [Figure 12J] FIG. 12J is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12I. [Figure 12K] FIG. 12K is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12J. [Figure 12L] FIG. 12L is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12K. [Figure 12M] FIG. 12M is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. 12L. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0011] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.

[0012] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0013] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to a first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0014] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0016] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0017] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0018] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0019] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0020] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0021] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0022] A rib 5 is disposed in the display area DA. The rib 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.

[0023] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0024] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib 5 surrounds each of these display elements DE1, DE2, and DE3.

[0025] A conductive partition wall 6 is disposed on the rib 5. The partition wall 6 overlaps the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6 has openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib 5 and the partition wall 6 are lattice-shaped in a planar view and surround each of the subpixels SP1, SP2, and SP3. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0026] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.

[0027] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0028] The partition wall 6 includes a conductive bottom portion 60 disposed above the rib 5, a conductive lower portion 61 disposed on the bottom portion 60, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape. In the example of FIG. 3, both ends of the bottom portion 60 also protrude beyond the side surfaces of the lower portion 61.

[0029] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, UE3 are in contact with at least one of the bottom portion 60 and the lower portion 61 of the partition wall 6.

[0030] The display element DE1 includes a cap layer CP1 disposed on an upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on an upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on an upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0031] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0032] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6 (a part that constitutes the display element DE3).

[0033] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0034] 3, the laminated film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition 6. In addition, the laminated film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition 6.

[0035] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least throughout the entire display area DA, and a part of them extends into the peripheral area SA.

[0036] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0037] The organic insulating layer 12 is made of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, and SE2 are made of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al 2 O 3 The resin layers RS1 and RS2 are formed of an inorganic insulating material such as epoxy resin or acrylic resin.

[0038] As will be described in detail later, the lower electrodes LE1, LE2, and LE3 include a reflective layer made of a metal material. The upper electrodes UE1, UE2, and UE3 are made of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0039] 4 is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including an emitting layer EML. In this embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of emitting layers EML.

[0040] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE1, SE2, and SE3. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0041] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with at least one of the bottom portion 60 and the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0042] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength region.

[0043] As another example, the emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the emitting layers EML into light of a color corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the emitting layers EML to generate light of a color corresponding to the subpixels SP1, SP2, and SP3.

[0044] 5 is a schematic cross-sectional view showing an enlargement of the partition wall 6 and its vicinity. In this figure, the substrate 10, the circuit layer 11, the organic insulating layer 12, the sealing layer SE11, the resin layers RS1 and RS2, and the sealing layer SE2 are omitted.

[0045] 5, the lower electrode LE1 includes a reflective layer RL, a first covering layer V1 covering the lower surface of the reflective layer RL, and a second covering layer V2 covering the upper surface of the reflective layer RL. In the pixel aperture AP1, the organic layer OR1 is in contact with the second covering layer V2.

[0046] The reflective layer RL is made of a metal material with excellent light reflectivity, such as silver. The covering layers V1 and V2 are made of a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The lower electrodes LE2 and LE3 have the same configuration as the lower electrode LE1.

[0047] 5, the upper portion 62 of the partition wall 6 includes a first top layer 63 disposed on the lower portion 61 and a second top layer 64 covering the first top layer 63. Both end portions of the first top layer 63 and the second top layer 64 protrude from the side surfaces of the lower portion 61. Parts of both end portions of the first top layer 63 are exposed from the second top layer 64.

[0048] The bottom portion 60 is made of a conductive metal material. Examples of the metal material that can be used include titanium (Ti), titanium nitride (TiN), molybdenum (Mo), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). The thickness of the bottom portion 60 is, for example, 10 to 50 nm.

[0049] The lower portion 61 is formed of, for example, a conductive metal material. As the metal material, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used. The thickness of the lower portion 61 is, for example, 400 to 1000 nm. The lower portion 61 may be formed of an insulating material.

[0050] The first top layer 63 is formed of, for example, a metal material. The second top layer 64 is formed of, for example, a transparent conductive oxide. The metal material forming the first top layer 63 may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the second top layer 64 may be, for example, ITO, IZO, or IGZO. The thickness of the first top layer 63 is, for example, 50 to 300 nm. The thickness of the second top layer 64 is, for example, 20 to 100 nm.

[0051] The bottom portion 60 and the lower portion 61 may include multiple layers made of different materials. The upper portion 62 may be formed of a single layer. The lower portion 61 and the upper portion 62 may include a layer made of an insulating material.

[0052] In this embodiment, a transparent conductive oxide layer CL is disposed between the rib 5 and the bottom portion 60. The conductive oxide layer CL can be formed of, for example, amorphous ITO, IZO, or IGZO.

[0053] The conductive oxide (ITO, IZO or IGZO) forming the covering layers V1 and V2 of the lower electrodes LE1, LE2, and LE3 is fired in a manufacturing process described later. Therefore, the covering layers V1 and V2 have higher crystallinity than the conductive oxide layer CL.

[0054] Fig. 6 is a schematic cross-sectional view enlarging the vicinity of the end of the bottom portion 60 and the conductive oxide layer CL. In the example of Fig. 6, the end E1 of the bottom portion 60 protrudes further than the end E2 of the conductive oxide layer CL. This forms a gap below the end E1. The protruding length of the end E1 from the end E2 is, for example, 50 nm to 1000 nm.

[0055] In the example of FIG. 6, a part of the organic layer OR1 is also located above the bottom portion 60. The hole injection layer HIL of the organic layer OR1 is divided at the end E1. On the other hand, the hole transport layer HTL is not divided at the end E1. Layers formed above the hole transport layer HTL in the organic layer OR1 (for example, the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL) are also not divided at the end E1. The upper electrode UE1 continuously covers the organic layer OR1 and contacts the bottom portion 60 and the lower portion 61.

[0056] When the hole injection layer HIL is electrically connected to the partition wall 6, a leakage current may occur through the hole injection layer HIL, which may reduce the display quality. Therefore, the hole injection layer HIL is preferably formed in a region that does not overlap with the bottom portion 60 or is divided at the end E1 as in the example of FIG. 6. For example, when the thickness T1 of the conductive oxide layer CL is larger than the thickness T2 of the hole injection layer HIL (T2 < T1), the hole injection layer HIL is likely to be divided at the end E1.

[0057] If the thickness T1 is too large, other layers of the organic layer OR1 and the upper electrode UE1 may also be divided. When the upper electrode UE1 is divided, it may hinder the voltage supply from the partition wall 6 to the upper electrode UE1, and the organic layer OR1 may not emit light. Therefore, the thickness T1 is preferably smaller than the total thickness T3 of the hole injection layer HIL and the hole transport layer HTL (T1 < T3). Thereby, it becomes difficult for the hole transport layer HTL to be divided at the end E1. As a result, division of layers located above the hole transport layer HTL in the organic layer OR1 and the upper electrode UE1 can be suppressed.

[0058] As an example, the thickness T1 is 15 to 50 nm. In FIG. 6, the conductive oxide layer CL is thinner than the bottom portion 60, but this is not limited to this example.

[0059] The region below the end E1 is filled, for example, with the hole transport layer HTL. However, voids may be formed in at least a part of this region.

[0060] 6, the structure near the end of the laminated film FL1 is focused on, but the end portions of the laminated films FL2 and FL3 have a similar structure. For example, the thicknesses of the hole injection layer HIL and the hole transport layer HTL of the organic layers OR2 and OR3 are the same as those of the hole injection layer HIL and the hole transport layer HTL of the organic layer OR1. That is, the hole injection layer HIL of the organic layers OR2 and OR3 is also divided at the end E1.

[0061] Next, an example of a manufacturing method for the display device DSP according to this embodiment will be described. 7A to 7M are schematic cross-sectional views showing the manufacturing process before the formation of the display elements DE1, DE2, and DE3. FIGs. 8A to 8D are schematic cross-sectional views showing the process of forming the display elements DE1, DE2, and DE3. In these figures, the substrate 10 and the circuit layer 11 are omitted.

[0062] In manufacturing the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Then, as shown in Fig. 7A, a first covering layer V1a formed of a transparent conductive oxide, a reflective layer RLa formed of a metal material, and a second covering layer V2a formed of a transparent conductive oxide are successively formed on the organic insulating layer 12. Furthermore, a resist R1 having a shape corresponding to the lower electrodes LE1, LE2, and LE3 is disposed on the second covering layer V2a.

[0063] The reflective layer RLa, the first covering layer V1a, and the second covering layer V2a are layers for processing into the above-mentioned reflective layer RL, the first covering layer V1, and the second covering layer V2. These layers are all formed over the entire display area DA and the peripheral area SA by, for example, sputtering.

[0064] Next, the reflective layer RLa and the covering layers V1a and V2a are patterned into the shape of the resist R1. Specifically, the reflective layer RLa and the covering layers V1a and V2a exposed from the resist R1 are removed by wet etching. As a result, as shown in FIG. 7B, the lower electrodes LE1, LE2, and LE3 are formed, which include the reflective layer RL, the first covering layer V1 covering the lower surface of the reflective layer RL, and the second covering layer V2 covering the upper surface of the reflective layer RL.

[0065] After the lower electrodes LE1, LE2, and LE3 are formed, the resist R1 is removed as shown in Fig. 7C. Furthermore, the entire substrate is heated, whereby the conductive oxide constituting the coating layers V1 and V2 is baked.

[0066] Next, as shown in Fig. 7D, a rib layer 5a covering the lower electrodes LE1, LE2, and LE3 is formed by CVD (Chemical Vapor Deposition). Furthermore, a resist R2 having a shape corresponding to the rib 5 is disposed on the rib layer 5a. The rib layer 5a is an inorganic insulating layer to be processed into the rib 5, and is formed over the entire display area DA and the peripheral area SA.

[0067] Next, the portion of the rib layer 5a exposed from the resist R2 is removed by dry etching. As a result, the rib 5 having pixel openings AP1, AP2, and AP3 overlapping with the lower electrodes LE1, LE2, and LE3 is formed as shown in Fig. 7E. After the rib 5 is formed, the resist R2 is removed as shown in Fig. 7F.

[0068] During the dry etching of the rib layer 5a, the resist R2 is also partially eroded and its width is gradually reduced, so that the ends of the rib 5 along the pixel openings AP1, AP2, and AP3 become tapered.

[0069] After the rib 5 is formed, as shown in FIG. 7G, the conductive oxide layer CLa, the bottom layer 60a, the lower layer 61a, the first top layer 63a, and the second top layer 64a are formed in this order by sputtering. Furthermore, a resist R3 having a shape corresponding to the partition wall 6 is disposed on the second top layer 64a. The conductive oxide layer CLa, the bottom layer 60a, the lower layer 61a, the first top layer 63a, and the second top layer 64a are layers for processing into the above-mentioned conductive oxide layer CL, the bottom part 60, the lower part 61, and the upper part 62 (the first top layer 63 and the second top layer 64), respectively, and are formed over the entire display area DA and the peripheral area SA. The conductive oxide layer CLa covers the lower electrodes LE1, LE2, LE3, and the rib 5.

[0070] The conductive oxide layer CLa is formed of an amorphous conductive oxide. In order to form such an amorphous conductive oxide layer CLa, it is preferable to sufficiently increase the partial pressure of water vapor in the chamber during sputtering of the conductive oxide layer CLa. In one example, the partial pressure of water vapor during sputtering when forming the conductive oxide layer CLa is higher than the partial pressure of water vapor during sputtering when forming the coating layers V1 and V2 of the lower electrodes LE1, LE2, and LE3.

[0071] Next, the portion of the second top layer 64a exposed from the resist R3 is removed by wet etching. This forms the second top layer 64 as shown in Fig. 7H. In the example of Fig. 7H, the width of the second top layer 64 is slightly reduced compared to the resist R3.

[0072] Furthermore, dry etching is performed using the resist R3 as a mask, and the portion of the first top layer 63a exposed from the resist R3 is removed, thereby forming the first top layer 63 as shown in FIG.

[0073] In addition, the dry etching also reduces the thickness of the portion of the lower layer 61a exposed from the resist R3. Also, the dry etching erodes a part of the resist R3, reducing its width.

[0074] Next, the lower layer 61a is wet-etched. As a result, the portion of the lower layer 61a exposed from the resist R3 is removed. Furthermore, the side surface of the lower layer 61a is eroded, and its width is reduced below that of the top layers 63 and 64. As a result, the lower portion 61 is formed as shown in FIG. 7J.

[0075] After the lower portion 61 is formed, the bottom layer 60a is patterned by dry etching. Specifically, the dry etching removes the portion of the bottom layer 60a exposed from the resist R3. As a result, the bottom portion 60 is formed as shown in FIG. 7K. In the dry etching, the width of the bottom portion 60 is reduced to a range equal to or smaller than the width of the top layers 63 and 64 and equal to or larger than the width of the lower portion 61.

[0076] Through the above steps, the partition wall 6 including the bottom portion 60, the lower portion 61, and the upper portion 62 (the first top layer 63 and the second top layer 64) is completed. After the partition wall 6 is formed, the conductive oxide layer CLa is patterned by wet etching. Specifically, the conductive oxide layer CLa exposed from the bottom portion 60 is removed by the wet etching. As a result, the conductive oxide layer CL is formed as shown in FIG. 7L. In the wet etching, the end E2 of the conductive oxide layer CL is set back from the end E1 of the bottom portion 60 as shown in FIG. 6.

[0077] The conductive oxide layer CLa is amorphous because it has not been baked before the wet etching. For example, oxalic acid can be used as an etching solution for the conductive oxide layer CLa. The second coating layer V2 of the lower electrodes LE1, LE2, and LE3 has been baked at the time of the wet etching and has higher crystallinity than the conductive oxide layer CLa. Therefore, the etching rate of the second coating layer V2 by oxalic acid is sufficiently slower than that of the conductive oxide layer CLa, and the layer is not easily eroded. In addition, if the wet etching is performed using oxalic acid, the rib 5 formed of silicon nitride, silicon oxide, or silicon oxynitride is also not easily eroded.

[0078] In the wet etching of the conductive oxide layer CLa, the second top layer 64 formed of a conductive oxide may also be eroded. As a result, as shown in Fig. 7L, the width of the second top layer 64 is reduced below the width of the first top layer 63. After the conductive oxide layer CL is formed, as shown in Fig. 7M, the resist R3 is removed.

[0079] Next, a process for forming the display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0080] In forming the display element DE1, first, a laminated film FL1 and a sealing layer SE11 are formed as shown in Fig. 8A. As shown in Fig. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1.

[0081] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition. The sealing layer SE11 is formed by CVD. The laminated film FL1 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0082] After the laminated film FL1 and the sealing layer SE11 are formed, a resist R4 is disposed on the sealing layer SE11 as shown in Fig. 8A. The resist R4 covers the subpixel SP1 and a part of the partition wall 6 around it.

[0083] Then, as shown in FIG. 8B, the laminated film FL1 and the sealing layer SE11 are etched using the resist R4 as a mask to remove the exposed portions of the resist R4. This forms a display element DE1 in the subpixel SP1. For example, the etching includes wet etching and dry etching that are sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R4 is removed.

[0084] The display element DE2 is formed in the same manner as the display element DE1. That is, in forming the display element DE2, a laminated film FL2 and a sealing layer SE12 are formed in the entire display area DA. As shown in FIG. 3, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0085] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the laminated film FL2 and the partition walls 6.

[0086] Next, the laminated film FL2 and the sealing layer SE12 are patterned, thereby forming a display element DE2 in the subpixel SP2, as shown in FIG.

[0087] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when the display element DE3 is formed, a laminated film FL3 and a sealing layer SE13 are formed in the entire display area DA. As shown in FIG. 3, the laminated film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0088] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into a plurality of parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the laminated film FL3 and the partition walls 6.

[0089] Next, the laminated film FL3 and the sealing layer SE13 are patterned, thereby forming a display element DE3 in the subpixel SP3, as shown in FIG 8D.

[0090] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are formed in this order, as shown in Fig. 3. Through these steps, the display device DSP is completed.

[0091] In the present embodiment described above, it is possible to obtain a display device DSP including display elements DE1, DE2, DE3 that are separated into sub-pixels SP1, SP2, SP3 by the overhanging partition wall 6 and individually sealed.

[0092] Furthermore, by disposing the conductive oxide layer CL below the partition 6, the yield of the display device DSP can be improved. That is, if the conductive oxide layer CL is not provided, the lower electrodes LE1, LE2, LE3 and the rib 5 may be damaged during etching to form the partition 6. In contrast, when the conductive oxide layer CL is provided, the conductive oxide layer CL functions as an etching stopper for etching to form the partition 6. Therefore, damage to the lower electrodes LE1, LE2, LE3 and the rib 5 is suppressed.

[0093] Even when the conductive oxide layer CL is not provided, it is possible to suppress damage to the rib 5 by forming the rib 5 from a material having a slow etching rate in dry etching, such as silicon oxide or silicon oxynitride. However, silicon oxide and silicon oxynitride have poorer coverage than silicon nitride. Therefore, for example, a moisture path may be formed in the rib 5 near the ends of the lower electrodes LE1, LE2, and LE3. In contrast, when the conductive oxide layer CL is provided, it is possible to suppress damage to the rib 5 even if the rib 5 is made of silicon nitride, which has a fast etching rate in dry etching but excellent coverage.

[0094] The second covering layer V2 of the lower electrodes LE1, LE2, LE3 protects the reflective layer RL from etching for forming the partition wall 6. This effect is improved as the second covering layer V2 is made thicker. However, if the second covering layer V2 is made thicker, the luminance and luminous efficiency of the display elements DE1, DE2, DE3 may decrease. In contrast, if the conductive oxide layer CL is provided on the second covering layer V2 as in this embodiment, the second covering layer V2 can be formed thinner than when the conductive oxide layer CL is not provided. This is expected to improve the luminance and luminous efficiency of the display elements DE1, DE2, DE3.

[0095] As a method for protecting the lower electrodes LE1, LE2, LE3 from the etching for forming the partition wall 6, instead of forming the partition wall 6 after forming the pixel openings AP1, AP2, AP3 as in this embodiment, it is also possible to form the pixel openings AP1, AP2, AP3 after forming the partition wall 6. However, in this case, the number of photolithography steps for processing the rib 5 will be increased compared to this embodiment.

[0096] That is, the partition wall 6 is connected to a power supply line of a common voltage through an opening in the rib 5 provided in the peripheral area SA. In order to provide this opening, a photolithography process must be performed on the rib 5 before forming the partition wall 6. Therefore, when forming the pixel openings AP1, AP2, AP3 after forming the partition wall 6, it is necessary to perform the photolithography process on the rib 5 at least twice.

[0097] In contrast, in the present embodiment, when the pixel openings AP1, AP2, and AP3 are provided before the formation of the partition wall 6, the openings in the peripheral area SA can be simultaneously provided in the photolithography process. Therefore, it is possible to reduce the number of photolithography processes compared to the case where the pixel openings AP1, AP2, and AP3 are formed after the formation of the partition wall 6.

[0098] Furthermore, when the pixel openings AP1, AP2, and AP3 are formed after the partition wall 6 is formed, there is a possibility that the resist for processing the rib 5 cannot be uniformly applied due to the overhanging partition wall 6. In contrast, when the pixel openings AP1, AP2, and AP3 are provided before the formation of the partition wall 6 as in this embodiment, the resist for processing the rib 5 (resist R2 in FIG. 7D) can be uniformly applied, improving the accuracy of the shape of the rib 5. In addition to the above, various other advantageous effects can be obtained from this embodiment.

[0099] [Second embodiment] The second embodiment will be described. The same elements as those in the first embodiment are given the same reference numerals, and the description thereof will be omitted. In addition, the configuration of the display device DSP and its manufacturing process, which are not specifically mentioned in this embodiment, can be the same as those in the first embodiment.

[0100] Fig. 9 is a schematic cross-sectional view of the display device DSP according to this embodiment, and shows the configuration of the partition wall 6 and its vicinity, similar to Fig. 5. In the example of Fig. 9, the position of the conductive oxide layer CL is different from that of the example of Fig. 5.

[0101] That is, in this embodiment, a conductive oxide layer CL is disposed between the lower electrodes LE1, LE2 and the rib 5. Although not shown in FIG. 9, a conductive oxide layer CL is also disposed between the lower electrode LE3 and the rib 5. The conductive oxide layer CL covers the peripheral edge of the second coating layer V2 of the lower electrodes LE1, LE2, LE3. In this embodiment, the bottom portion 60 of the partition wall 6 is in contact with the upper surface of the rib 5.

[0102] 10 is a schematic plan view of the rib 5, the lower electrodes LE1, LE2, LE3, and the conductive oxide layer CL according to this embodiment. The shaded area in the figure corresponds to the conductive oxide layer CL.

[0103] The conductive oxide layer CL is disposed in the region where the lower electrodes LE1, LE2, LE3 overlap with the rib 5. That is, the conductive oxide layer CL has openings APc overlapping with the pixel openings AP1, AP2, AP3, respectively. From another point of view, the conductive oxide layer CL surrounds the display elements DE1, DE2, DE3, respectively.

[0104] 10 shows one each of the lower electrodes LE1, LE2, and LE3 and three conductive oxide layers CL overlapping the lower electrodes LE1, LE2, and LE3. Such a conductive oxide layer CL is provided for each of the lower electrodes LE1, LE2, and LE3 of the display device DSP.

[0105] Fig. 11 is a schematic cross-sectional view showing an enlargement of the partition wall 6 and its vicinity shown in Fig. 9. In this figure, the substrate 10, the circuit layer 11, the organic insulating layer 12, the sealing layer SE11, the resin layers RS1 and RS2, and the sealing layer SE2 are omitted.

[0106] The conductive oxide layer CL is in contact with the upper surface of the second coating layer V2. In the example of Fig. 6, the end E3 of the rib 5 along the pixel aperture AP1 protrudes beyond the end E2 of the conductive oxide layer CL. This forms a gap below the end E3. The protruding length of the end E3 from the end E2 is, for example, 50 nm to 1000 nm.

[0107] In the example of FIG. 11, the hole injection layer HIL of the organic layer OR1 is divided at the end E3. Thus, similar to the first embodiment, the leakage current through the hole injection layer HIL can be suppressed.

[0108] On the other hand, the hole transport layer HTL is not divided at the end E3. Similarly, the layers formed above the hole transport layer HTL in the organic layer OR1 (for example, the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL) are not divided at the end E3.

[0109] Similar to the first embodiment, the thickness T1 of the conductive oxide layer CL is preferably larger than, for example, the thickness T2 of the hole injection layer HIL (T2 < T1) and smaller than the total thickness T3 of the hole injection layer HIL and the hole transport layer HTL (T1 < T3). Thereby, the hole injection layer HIL is likely to be divided at the end E3, and the hole transport layer HTL is less likely to be divided at the end E3.

[0110] In the example of FIG. 11, the region below the end E3 is filled with the hole transport layer HTL. However, voids may be formed in at least a part of this region. Although the configuration near the end of the laminated film FL1 is focused on in FIG. 11, the regions near the ends of the laminated films FL2 and FL3 also have a similar structure.

[0111] In the present embodiment, the conductive oxide layer CL is formed of, for example, amorphous IZO or IGZO. Further, the rib 5 is formed of, for example, silicon oxynitride.

[0112] Subsequently, an example of a method for manufacturing the display device DSP according to the present embodiment will be described. FIGS. 12A to 12M are schematic cross-sectional views showing the manufacturing processes up to before the formation of the display elements DE1, DE2, and DE3. In these figures, the illustration of the substrate 10 and the circuit layer 11 is omitted. The process of forming the display elements DE1, DE2, and DE3 is the same as that in FIGS. 8A to 8D.

[0113] In manufacturing the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Then, a first covering layer V1a, a reflective layer RLa, and a second covering layer V2a are formed in this order on the organic insulating layer 12, similarly to the first embodiment.

[0114] In this embodiment, as shown in Fig. 12A, a conductive oxide layer CLa is formed on the second coating layer V2a by sputtering. Furthermore, a resist R1 having a shape corresponding to the lower electrodes LE1, LE2, and LE3 is disposed on the conductive oxide layer CLa.

[0115] Next, the conductive oxide layer CLa, the reflective layer RLa, and the covering layers V1a and V2a are patterned in the shape of the resist R1. Specifically, the conductive oxide layer CLa, the reflective layer RLa, and the covering layers V1a and V2a are removed by wet etching from the portions exposed from the resist R1. As a result, as shown in FIG. 12B, the lower electrodes LE1, LE2, and LE3 including the reflective layer RL, the first covering layer V1, and the second covering layer V2 are formed. At this point, the entire lower electrodes LE1, LE2, and LE3 are covered with the conductive oxide layer CLa.

[0116] After the lower electrodes LE1, LE2, and LE3 are formed, the resist R1 is removed as shown in Fig. 12C. Furthermore, the entire substrate is heated, whereby the conductive oxide constituting the coating layers V1 and V2 is baked.

[0117] In this embodiment, the coating layers V1 and V2 are made of ITO. The conductive oxide layer CLa is made of IZO or IGZO. That is, the coating layers V1 and V2 and the conductive oxide layer CL are made of different conductive oxides.

[0118] The baking temperature is set to a temperature at which ITO crystallizes but IZO or IGZO does not crystallize, that is, the coating layers V1 and V2 are crystallized by the baking, but the conductive oxide layer CLa remains amorphous.

[0119] 12D, a rib layer 5a covering the lower electrodes LE1, LE2, and LE3 is formed by CVD. Furthermore, a resist R2 having a shape corresponding to the rib 5 is disposed on the rib layer 5a. In this embodiment, the rib layer 5a is formed of silicon oxynitride.

[0120] Next, the portion of the rib layer 5a exposed from the resist R2 is removed by dry etching. As a result, the rib 5 having pixel openings AP1, AP2, and AP3 overlapping with the lower electrodes LE1, LE2, and LE3 is formed as shown in Fig. 12E. After the rib 5 is formed, the resist R2 is removed as shown in Fig. 12F.

[0121] After the rib 5 is formed, a bottom layer 60a, a lower layer 61a, a first top layer 63a, and a second top layer 64a are formed in this order by sputtering, as shown in Fig. 12G. Furthermore, a resist R3 having a shape corresponding to the partition wall 6 is disposed on the second top layer 64a.

[0122] Next, the portion of the second top layer 64a exposed from the resist R3 is removed by wet etching. This forms the second top layer 64 as shown in Fig. 12H. In the example of Fig. 12H, the width of the second top layer 64 is slightly reduced compared to the resist R3.

[0123] Furthermore, dry etching is performed using the resist R3 as a mask, and the portion of the first top layer 63a exposed from the resist R3 is removed. As a result, the first top layer 63 is formed as shown in Fig. 12I. As in the first embodiment, the dry etching also reduces the thickness of the portion of the lower layer 61a exposed from the resist R3.

[0124] Next, the lower layer 61a is wet-etched. As a result, the portion of the lower layer 61a exposed from the resist R3 is removed. Furthermore, the side surface of the lower layer 61a is eroded, and its width is reduced below that of the top layers 63 and 64. As a result, the lower portion 61 is formed as shown in FIG. 12J.

[0125] After the lower portion 61 is formed, the bottom layer 60a is patterned by dry etching. Specifically, the dry etching removes the portion of the bottom layer 60a exposed from the resist R3. As a result, the bottom portion 60 is formed as shown in FIG. 12K.

[0126] Through the above steps, the partition wall 6 including the bottom portion 60, the lower portion 61, and the upper portion 62 is completed. After the partition wall 6 is formed, the conductive oxide layer CLa is patterned by wet etching. Specifically, in the wet etching, the portions of the conductive oxide layer CLa exposed from the rib 5 through the pixel openings AP1, AP2, and AP3 are removed. As a result, the conductive oxide layer CL covering the peripheral portions of the lower electrodes LE1, LE2, and LE3 is formed, as shown in FIG. 12L.

[0127] As in the first embodiment, for example, oxalic acid can be used as an etching solution for the conductive oxide layer CLa. In this wet etching, as shown in FIG. 11, the end E2 of the conductive oxide layer CL is set back from the end E3 of the rib 5 along the pixel openings AP1, AP2, and AP3.

[0128] After the conductive oxide layer CL is formed, the resist R3 is removed as shown in Fig. 12M. The process for forming the display elements DE1, DE2, and DE3 that is performed thereafter is similar to that of the first embodiment.

[0129] Even with the configuration of this embodiment, as with the first embodiment, the lower electrodes LE1, LE2, and LE3 can be protected from the etching for forming the partition wall 6. In addition, the second covering layer V2 can be formed thinner than when the conductive oxide layer CL is not provided, which is expected to improve the luminance and luminous efficiency of the display elements DE1, DE2, and DE3. Furthermore, since the pixel openings AP1, AP2, and AP3 are provided before the partition wall 6 is formed, the number of photolithography steps for the rib 5 can be reduced.

[0130] In this embodiment, the rib 5 is not covered with the conductive oxide layer CLa. Therefore, the rib 5 is exposed to the etching of the partition wall 6. However, by forming the rib 5 from silicon oxynitride as described above, damage to the rib 5 can be suppressed compared to the case where the rib 5 is formed from silicon nitride.

[0131] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices and manufacturing methods thereof disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0132] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0133] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0134] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13...sealing layer, CL...conductive oxide layer, 5...rib, 6...partition wall, 60...bottom portion, 61...lower portion, 62...upper portion, 63...first top layer, 64...second top layer.

Claims

1. A lower electrode; a rib having a pixel opening overlapping the lower electrode and covering an end portion of the lower electrode; a partition wall including a bottom portion disposed on the rib, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion; a transparent conductive oxide layer disposed between the rib and the bottom portion; A display device comprising:

2. The conductive oxide layer is formed of amorphous ITO, IZO, or IGZO. The display device according to claim 1 .

3. The rib is formed of silicon nitride, silicon oxide or silicon oxynitride. The display device according to claim 1 .

4. an end of the bottom portion protrudes from an end of the conductive oxide layer; The display device according to claim 1 .

5. the organic layer includes a hole injection layer in contact with the bottom electrode; the thickness of the conductive oxide layer is greater than the thickness of the hole injection layer; The display device according to claim 1 .

6. The organic layer further includes a hole transport layer overlying the hole injection layer, the thickness of the conductive oxide layer is less than the total thickness of the hole injection layer and the hole transport layer; The display device according to claim 5 .

7. The lower electrode is A reflective layer formed of a metal material; a covering layer formed of a transparent conductive oxide having a higher crystallinity than the conductive oxide layer and covering an upper surface of the reflective layer; Including, The display device according to claim 1 .

8. A lower electrode; a rib having a pixel opening overlapping the lower electrode and covering an end portion of the lower electrode; a partition wall including a bottom portion disposed on the rib, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion; a transparent conductive oxide layer disposed between the lower electrode and the rib, the transparent conductive oxide layer having an opening overlapping the pixel opening; A display device comprising:

9. The conductive oxide layer is formed of amorphous IZO or IGZO. The display device according to claim 8.

10. The rib is formed of silicon oxynitride. The display device according to claim 8.

11. an end of the rib along the pixel opening protrudes beyond an end of the conductive oxide layer; The display device according to claim 8.

12. the organic layer includes a hole injection layer in contact with the bottom electrode; the thickness of the conductive oxide layer is greater than the thickness of the hole injection layer; The display device according to claim 8.

13. The organic layer further includes a hole transport layer overlying the hole injection layer, the thickness of the conductive oxide layer is less than the total thickness of the hole injection layer and the hole transport layer; The display device according to claim 12.

14. The lower electrode is A reflective layer formed of a metal material; a covering layer formed of a transparent conductive oxide different from the conductive oxide layer and covering an upper surface of the reflective layer; Including, The display device according to claim 8.

15. Forming a lower electrode; forming a rib having a pixel opening overlapping the lower electrode; forming a transparent conductive oxide layer covering the lower electrode and the ribs; forming a partition wall on the conductive oxide layer, the partition wall including a bottom portion located above the rib, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; After forming the partition wall, a portion of the conductive oxide layer exposed from the bottom portion is removed; forming an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; forming an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion; A method for manufacturing a display device, comprising the steps of:

16. The bottom portion is patterned by dry etching; The conductive oxide layer is patterned by wet etching. The method of claim 15.

17. the conductive oxide layer is recessed from an end of the bottom portion during the wet etching; The method of claim 16.

18. Forming a lower electrode; forming a transparent conductive oxide layer covering the lower electrode; forming a rib covering the conductive oxide layer and having a pixel opening overlapping the lower electrode; forming a partition wall including a bottom portion located above the rib, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; After forming the partition wall, a portion of the conductive oxide layer exposed from the rib through the pixel opening is removed; forming an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; forming an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion; A method for manufacturing a display device, comprising the steps of:

19. The bottom portion is patterned by dry etching; The conductive oxide layer is patterned by wet etching. The method of claim 18.

20. the conductive oxide layer is recessed from the end of the rib along the pixel opening during the wet etching; The method of claim 19.

Images