Information processing apparatus and memory system

Abstract

To perform multiplication of elements that may become a negative value with a simple hardware configuration.SOLUTION: An information processing apparatus includes: a first positive wiring line carrying a current of a multiplication value of a first integer element and a second integer element when the multiplication value is zero or more; a first negative wiring line carrying a current of the multiplication value when the multiplication value is zero or less; a second positive wiring line activated when the second integer element is positive; a second negative wiring line activated when the second integer element is negative; a first calculator carrying the current through the first positive wiring line when the multiplication value of the first and second integer elements is zero or more; a second calculator carrying the current through the first negative wiring line when the multiplication value of the first and second integer elements is zero or less; a third calculator carrying the current through the first positive wiring line when the multiplication value of the first and second integer elements is zero or more; and a fourth calculator carrying the current through the first negative wiring line when the multiplication value of the first and second integer elements is zero or less.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present invention relates to an information processing device and a memory system. [Background technology]

[0002] By performing the calculation of the inner product between vectors with a large number of elements using a hardware circuit, the calculation of the inner product between vectors with a large number of elements can be performed at high speed. A CIM (Computer In Memory) is known as an example of such a hardware circuit.

[0003] The elements of a vector do not necessarily have values ​​greater than or equal to zero, but can also have values ​​less than or equal to zero. Therefore, the multiplication of elements can result in a negative value. In CIM, the calculation result is generally detected by changes in current or voltage, and if the calculation result is a negative value, it is necessary to reverse the current direction or make the voltage negative, which makes the circuit configuration complicated. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2019 / 049654 [Patent Document 2] International Publication No. 2021 / 009965 [Patent Document 3] Patent Publication No. 2022-50191 Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, one embodiment of the present invention provides an information processing device and a memory system that can perform multiplication of elements that can take negative values ​​with a simple hardware configuration. [Means for solving the problem]

[0006] In order to solve the above problem, according to one embodiment of the present invention, there is provided an information processing device that performs multiplication of a first integer element and a second integer element, comprising: a first positive wiring that passes a current according to a multiplication value of the first integer element and the second integer element when the multiplication value is equal to or greater than zero; a first negative wiring that passes a current according to the multiplied value when the multiplied value is equal to or less than zero; a second positive wiring that is activated when the second integer element is positive; a second negative wiring that is activated when the second integer element is negative; a first computing unit connected to the first positive wiring and the second positive wiring, which multiplies the first integer element and the second integer element and passes a current through the first positive wiring when the multiplied value is equal to or greater than zero; a second computing unit connected to the first negative wiring and the second positive wiring, multiplying the first integer element and the second integer element, and causing a current to flow through the first negative wiring when the multiplied value is equal to or less than zero; a third computing unit connected to the first positive wiring and the second negative wiring, multiplying the first integer element and the second integer element, and causing a current to flow through the first positive wiring when the multiplied value is equal to or greater than zero; a fourth computing unit connected to the first negative wiring and the second negative wiring, which multiplies the first integer element and the second integer element and passes a current through the first negative wiring when the multiplied value is equal to or less than zero; The direction of the current flowing through the first positive wiring is the same as the direction of the current flowing through the first negative wiring, the first integer element is a positive integer, a negative integer, or zero; the second integer element is a positive integer, a negative integer, or zero; An information processing device is provided. [Brief description of the drawings]

[0007] [Figure 1] Conceptual diagram of a CIM that calculates the dot product of vectors. [Figure 2A] FIG. 13 is a diagram showing an example of an element multiplication table including multiplication values ​​of all combinations of non-negative elements. [Figure 2B] A plot showing the distribution of multiplication values ​​between two 128-dimensional vectors with non-negative elements. [Figure 3A] FIG. 13 is a diagram showing an example of an element multiplication table including multiplication values ​​of all combinations of integer elements. [Figure 3B] A diagram showing the distribution of multiplication values ​​between two 128-dimensional vectors with integer elements. [Figure 4] FIG. 13 is a block diagram showing an example of a CIM that calculates the multiplication value of non-negative elements. [Diagram 5] FIG. 5 is a circuit diagram showing a specific example of the arithmetic unit in FIG. 4 . [Figure 6] FIG. 1 is a block diagram of an information processing apparatus according to a first embodiment. [Figure 7] 7 is a diagram showing an element multiplication table for the arithmetic processing performed by the arithmetic unit group in FIG. 6. [Figure 8] FIG. 4 is a block diagram showing first to fourth computing unit groups. [Figure 9] 4 is a specific circuit diagram of first to fourth computing units included in a first computing unit group. [Figure 10A] 4 is a diagram showing a correspondence relationship between a gate voltage of a first transistor of a string included in a first computing unit of a first computing unit group and a current flowing through the string. FIG. [Figure 10B] 13 is a diagram showing a correspondence relationship between a gate voltage of a first transistor of a string included in a second computing unit of a second computing unit group and a current flowing through the string. [Figure 10C] 13 is a diagram showing a correspondence relationship between a gate voltage of a first transistor of a string included in a third computing unit of the third computing unit group and a current flowing through the string. FIG. [Figure 10D] 13 is a diagram showing a correspondence relationship between a gate voltage of a first transistor of a string included in a fourth computing unit of a fourth computing unit group and a current flowing through the string. [Figure 11A] A diagram showing the fifth element multiplication table. [Figure 11B] A diagram showing the sixth element multiplication table. [Figure 12A] FIG. 11 is a block diagram of an information processing device according to a first modified example of the first embodiment. [Figure 12B] FIG. 11 is a block diagram of an information processing device according to a second modified example of the first embodiment. [Figure 13] FIG. 11 is a block diagram of an information processing apparatus according to a second embodiment. [Figure 14] FIG. 11 is a diagram showing an element multiplication table for multiplication between integer elements performed by a group of arithmetic units according to the second embodiment. [Figure 15] FIG. 13 is a diagram showing a first modified element multiplication table in which each multiplication value in the element multiplication table is uniformly shifted by a predetermined value. [Figure 16] 13 is a diagram showing the correspondence relationship between the gate voltage of a first transistor of a string and the current flowing through the string, which are included in a first computing unit and a second computing unit that perform the calculations of the first correction element multiplication table. FIG. [Figure 17] FIG. 13 is a diagram showing a second modified element multiplication table in which the value by which each multiplication value in the element multiplication table is shifted is changed for each query value. [Figure 18] 13 is a diagram showing the correspondence relationship between the gate voltage of the first transistor of the string 3 and the current flowing through the string, which are included in the first and second computing units that perform the computation of the second correction element multiplication table. FIG. [Figure 19A] FIG. 13 is a block diagram of an information processing device according to a first modified example of the second embodiment. [Figure 19B] FIG. 13 is a block diagram of an information processing device according to a second modified example of the second embodiment. [Figure 20] FIG. 11 is a block diagram showing a schematic configuration of a memory system according to a third embodiment. [Figure 21] FIG. 13 is a block diagram showing a schematic configuration of a memory system according to a modification of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of an information processing device and a memory system will be described with reference to the drawings. The following description will focus on the main components of the information processing device and the memory system, but the information processing device and the memory system may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0009] (First embodiment) FIG. 1 is a conceptual diagram of a CIM1 that calculates an inner product between vectors. The CIM1 includes one or more bit lines BL arranged in a memory cell array, and a plurality of strings SR0 to SRm, each of which has one end connected to the bit line BL. The strings SR0 to SRm are configured by connecting a plurality of memory cell transistors in series. Hereinafter, the memory cell transistors are simply referred to as transistors. Different word lines are connected to the gates of the plurality of transistors in the strings. In a normal memory cell array, the plurality of word lines are generally connected in common to the plurality of strings SR0 to SRm. However, in FIG. 1, the plurality of word lines are not necessarily connected in common to the plurality of strings, and a separate word line may be connected to each individual string.

[0010] The threshold voltages of the transistors in each string are set to values ​​according to corresponding elements of a first vector K (k0, k1, ..., km) having (m+1) elements. One of the word lines connected to each string is set to a voltage level according to a corresponding element of a second vector Q (q0, q1, ..., qm), where m is an integer equal to or greater than 1.

[0011] Of the multiple strings SR0 to SRm, string SR0 passes a current corresponding to the product of element k0 of first vector K and element q0 of second vector Q. String SRi passes a current corresponding to the product of element ki of first vector K and element qi of second vector Q. String SRm passes a current corresponding to the product of element km of first vector K and element qm of second vector Q.

[0012] The sum of the currents flowing through the multiple strings SR0 to SRm is a current according to the inner product of the first vector K and the second vector Q, and this current flows through the bit line BL. Therefore, the current flowing through the bit line BL changes according to the inner product of the first vector K and the second vector Q. The larger the inner product is, the larger the sum of the currents flowing through the multiple strings SR0 to SRm and the current flowing through the bit line BL become, and the larger the voltage level of the bit line BL drops.

[0013] When the elements of the first vector and the second vector contain negative values, the multiplication value of the elements may be negative. When the multiplication value is negative, the direction of the current flowing through the bit line BL and the string is reversed. However, depending on the circuit configuration of the string, the direction of the current may not be easily changed. Therefore, the embodiment described below is characterized in that the direction of the current flowing through the bit line BL and the string is not changed even if the elements of the vector contain negative values.

[0014] 2A is a diagram showing an example of an element multiplication table including all combinations of multiplication values ​​of elements when each element of a first vector and each element of a second vector are non-negative values ​​(values ​​equal to or greater than 0). The example of FIG. 2A shows multiplication values ​​of elements (0, 1, 2, 3) of a first vector arranged in a first direction X and elements (0, 1, 2, 3) of a second vector arranged in a second direction Y.

[0015] In the element multiplication table of Figure 2A, since the first and second vectors each have four types of elements (called four dimensions), there are 16 combinations of elements to be multiplied, and there are 16 multiplication values. The average value μ of the 16 multiplication values ​​is 2.25, and the standard deviation σ 2 is 4.763349.

[0016] If the first and second vectors are both 128-dimensional, the average value μ of the multiplication value is 288, and the standard deviation σ 2 is 609.7087. Figure 2B is a diagram showing the distribution of the multiplication value of two 128-dimensional vector elements with non-negative elements. The horizontal axis of Figure 2B is the multiplication value, and the vertical axis is the frequency. As shown in Figure 2B, the multiplication value of the elements of two vectors is, for example, normally distributed.

[0017] Fig. 3A is a diagram showing an example of an element multiplication table EL when each element of a first vector and each element of a second vector are integers (positive, negative, or zero values). The element multiplication table EL in Fig. 3A includes 25 multiplication values, which are all combinations of the five elements (-2, -1, 0, 1, 2) of a first vector arranged in a first direction X and the five elements (-2, -1, 0, 1, 2) of a second vector arranged in a second direction Y. The multiplication values ​​between the elements of the two vectors shown in Fig. 3A include positive values, negative values, and zero, and the average value μ of the multiplication values ​​is 0 and the standard deviation σ 2 is 1.036158. If the first and second vectors are 128-dimensional, the mean value μ of the multiplication value is 0, and the standard deviation σ 2 is 132.6282.

[0018] Figure 3B shows the distribution of the multiplication value between two 128-dimensional vectors with integer elements. Figure 3B shows a normal distribution like Figure 2B, but the most frequent multiplication value is zero.

[0019] As can be seen by comparing Figures 2B and 3B, the mean value μ and standard deviation σ of the multiplication value of the integer elements of two vectors are 2 are the mean μ and standard deviation σ of the product of the elements of two vectors whose elements have non-negative values. 2 The mean value μ and standard deviation σ of the multiplication value are smaller than 2 By reducing this, power consumption can be reduced.

[0020] Fig. 4 is a block diagram showing an example of a CIM100 that calculates a multiplication value of non-negative elements. The CIM100 in Fig. 4 multiplies a key K by a query Q, and has a calculator 2 connected to a word line WL and a bit line BL. The word line WL is set to a voltage corresponding to the query Q. The calculator 2 has a transistor with a threshold set corresponding to the key K. The bit line BL passes a current corresponding to the multiplication value of the query Q and the key K.

[0021] The key K is, for example, an element of a first vector, and the query Q is, for example, an element of a second vector. By providing a plurality of calculators 2 in FIG. 4, it is possible to calculate the inner product of the first vector and the second vector.

[0022] FIG. 5 is a circuit diagram showing a specific example of the computing unit 2 in FIG. 4. The computing unit 2 in FIG. 4 has a configuration similar to, for example, a NAND type flash memory. More specifically, the computing unit 2 in FIG. 4 has a string 3 connected to a bit line BL as shown in FIG. 5. The string 3 has a plurality of memory cell transistors 4 connected in series. Hereinafter, the memory cell transistor 4 may be simply referred to as a transistor 4. Each transistor 4 constituting the string 3 is, for example, an NMOS transistor.

[0023] Of the multiple transistors 4 constituting the string 3, one transistor 4a (hereinafter referred to as the first transistor) has a threshold voltage set according to the absolute value of the key K. The gate of the first transistor 4a is connected to a word line WL, and a voltage according to a query Q is input to the gate of the first transistor 4a via the word line WL.

[0024] Of the multiple transistors constituting the string 3, a predetermined threshold voltage is set for the transistor (hereinafter, second transistor) 4b other than the first transistor 4a. A voltage Vread of a predetermined voltage level that is much higher than the predetermined threshold voltage is input to the gate of the second transistor 4b. In this way, the threshold voltage and gate voltage of the second transistor 4b are predetermined fixed values, and the second transistor 4b is in an on state.

[0025] The number of second transistors 4b provided in the string 3 is arbitrary, and one or more second transistors 4b are provided. In addition, a selection transistor may be provided in the string 3. The selection transistor can select whether or not to pass a current through the string 3.

[0026] The first transistor 4a changes the current flowing between its drain and source depending on the values ​​of the query Q and the key K. Because the second transistor 4b is in the on state, the current flowing through the string 3 depends on the current flowing between the drain and source of the first transistor 4a, and the current flowing through the string 3 is determined by the values ​​of the query Q and the key K.

[0027] The current flowing through the string 3 is supplied from the bit line BL. That is, the current drawn from the bit line BL to the string 3 changes depending on the values ​​of the query Q and the key K. The larger the value of the key K is, the lower the threshold voltage is set for the first transistor 4a. Therefore, the larger the multiplication value of the query Q and the key K is, the larger the current flowing between the drain and source of the first transistor 4a is, and the current flowing through the bit line BL increases, resulting in a lower voltage level of the bit line BL.

[0028] In this way, the current flowing through the string 3 and the bit line BL changes, and the voltage level of the bit line BL changes, depending on the multiplication value of the query Q and the key K. Therefore, the multiplication value of the query Q and the key K can be detected by detecting the current or voltage value flowing through the bit line BL.

[0029] 6 is a block diagram of an information processing device 5 according to the first embodiment. The information processing device 5 according to the first embodiment can multiply a first integer element by a second integer element. The first integer element may be an element of a first vector. Similarly, the second integer element may be an element of a second vector.

[0030] The information processing device 5 according to the first embodiment shown in FIG. 6 includes a bit line pair BL+, BL-, a word line pair WL+, WL-, and a computing unit group 2g having four computing units 2 (hereinafter, a first computing unit 2a, a second computing unit 2b, a third computing unit 2c, and a fourth computing unit 2d).

[0031] One bit line in the bit line pair BL+, BL- (hereinafter, the first bit line BL+ or the first positive wiring) passes a current according to the multiplication value of the first integer element and the second integer element when the multiplication value is equal to or greater than zero. Each of the first integer element and the second integer element can be a positive integer, a negative integer, or zero. Here, "passing a current according to the multiplication value" includes the case where the current according to the multiplication value is zero.

[0032] The other bit line of the bit line pair BL+, BL- (hereinafter, the second bit line BL- or first negative line) passes a current according to the multiplication value of the first integer element and the second integer element when the multiplication value is zero or less.

[0033] In this way, a current flows through the second bit line BL- when the multiplied value of the first integer element and the second integer element is less than or equal to zero, but the direction of the current flowing through the second bit line BL- is the same as the direction of the current flowing through the first bit line BL+ when the multiplied value of the first integer element and the second integer element is greater than zero.

[0034] One of the word lines in the word line pair WL+, WL- (hereinafter, the first word line WL+ or the second positive wiring) is activated when the first integer element is positive. The other of the word line pair WL+, WL- (hereinafter, the second word line WL- or the second negative wiring) is activated when the first integer element is negative. Activation refers to applying a voltage higher than the ground voltage (e.g., 0V) to the first word line WL+ or the second word line WL-.

[0035] In this way, the second word line WL- is activated when the first integer element is negative, but the voltage level of the second word line WL- when activated is a voltage greater than the ground voltage (e.g., 0V), similar to the first word line WL+.

[0036] The first computing unit 2a is connected to the first bit line BL+ and the first word line WL+, and passes a current through the first bit line BL+1 when the product of the first integer element and the second integer element is equal to or greater than zero.

[0037] The second computing unit 2b is connected to the second bit line BL- and the first word line WL+, and passes a current through the second bit line BL- when the product of the first integer element and the second integer element is equal to or less than zero.

[0038] The third computing unit 2c is connected to the first bit line BL+ and the second word line WL-, and passes a current through the first bit line BL+ when the product of the first integer element and the second integer element is equal to or greater than zero.

[0039] The fourth computing unit 2d is connected to the second bit line BL- and the second word line WL-, and passes a current through the second bit line BL- when the product of the first integer element and the second integer element is equal to or less than zero.

[0040] As will be described later, each of the first to fourth computing units 2a to 2d has a string 3 having a configuration similar to that of Fig. 5. For each of the first to fourth computing units 2a to 2d, a voltage corresponding to a query Q can be input to the gate of the first transistor 4a in the string 3, and a threshold voltage corresponding to a key K can be set to the first transistor 4a. However, as will be described later, depending on the values ​​of the key K and the query Q, whether or not a voltage corresponding to the query Q is input to the gate of the first transistor 4a in each of the first to fourth computing units 2a to 2d, and whether or not a threshold voltage corresponding to the key K is set to the first transistor 4a, differs.

[0041] FIG. 7 is a diagram showing an element multiplication table EL0 of the arithmetic processing performed by the arithmetic unit group 2g of FIG. 6. The element multiplication table EL0 of FIG. 7 shows 25 multiplication values ​​which are arbitrary combinations of all possible values ​​of the first integer element and all possible values ​​of the second integer element. Since the first integer element and the second integer element can be positive, negative, or zero, the multiplication value of the first integer element and the second integer element can be positive, negative, or zero, as shown in FIG. 7. Specifically, when the first integer element and the second integer element can be 2, 1, 0, -1, -2, the multiplication value of the first integer element and the second integer element can be 4, 2, 1, 0, -1, -2, -4. Note that the first integer element and the second integer element are not limited to 2, 1, 0, -1, -2, but may be 1, 0, or -1. Alternatively, the first integer element and the second integer element may include values ​​greater than or equal to 3 and less than or equal to -3 in addition to 2, 1, 0, -1, and -2.

[0042] In this embodiment, as described above, when the multiplication value is a positive value, a current according to the multiplication value is passed through the first bit line BL+, and when the multiplication value is a negative value, a current according to the multiplication value is passed through the second bit line BL-. The direction of the current in the first bit line BL+ and the direction of the current in the second bit line BL- are made the same. When the multiplication value is zero, no current flows through either the first bit line BL+ or the second bit line BL-. In addition, when the query Q is a positive value, a positive voltage is applied to the first word line WL+, and when the query Q is a negative value, a positive voltage is applied to the second word line WL-. When the query Q is zero, the first word line WL+ and the second word line WL- are set to, for example, 0V.

[0043] The element multiplication table EL0 in FIG. 7 can be decomposed into first to fourth element multiplication tables EL1 to EL4 according to the combination of positive and negative values ​​of the key K and the query Q. The configuration of the arithmetic unit group 2g needs to be changed for each of the first to fourth element multiplication tables EL1 to EL4. In this embodiment, the configuration of the arithmetic unit group 2g that performs the calculation of the first element multiplication table EL1 is called the first arithmetic unit group 2ag, the configuration of the arithmetic unit group 2g that performs the calculation of the second element multiplication table EL2 is called the second arithmetic unit group 2bg, the configuration of the arithmetic unit group 2g that performs the calculation of the third element multiplication table EL3 is called the third arithmetic unit group 2cg, and the configuration of the arithmetic unit group 2g that performs the calculation of the fourth element multiplication table EL4 is called the fourth arithmetic unit group 2dg.

[0044] The first element multiplication table EL1 contains the multiplication values ​​of the 3×3 at the bottom right of the original element multiplication table EL0, and forces the multiplication values ​​of other elements to be 0. The first calculation unit group 2ag that performs the calculations of the first element multiplication table EL1 performs calculations of the 3×3 elements at the bottom right of the original element multiplication table EL0, and performs calculations to set the multiplication values ​​of other elements to 0.

[0045] The second element multiplication table EL2 contains multiplication values ​​obtained by converting the multiplication values ​​of the 3×3 at the bottom left of the original element multiplication table EL0 to positive values, and forcibly sets the multiplication values ​​of other elements to 0. The second calculation unit group 2bg that performs calculations of the second element multiplication table EL2 performs calculations of the 3×3 elements at the bottom left of the original element multiplication table EL0, and performs calculations to set the multiplication values ​​of other elements to 0.

[0046] The third element multiplication table EL3 contains the multiplication value of the top left 3×3 of the original element multiplication table EL0, and forces the multiplication values ​​of other elements to be 0. The third calculation unit group 2cg that performs the calculation of the third element multiplication table EL3 performs the calculation of the top left 3×3 elements of the original element multiplication table EL0, and performs the calculation to set the multiplication values ​​of other elements to be 0.

[0047] The fourth element multiplication table EL4 contains multiplication values ​​obtained by converting the multiplication values ​​of the 3×3 in the upper right corner of the original element multiplication table EL0 to positive values, and forcibly sets the multiplication values ​​of other elements to 0. The fourth calculation unit group 2dg, which performs calculations of the fourth element multiplication table EL4, performs calculations of the 3×3 elements in the upper right corner of the original element multiplication table EL0, and performs calculations to set the multiplication values ​​of other elements to 0.

[0048] In the information processing device 5 according to the first embodiment, when the first integer element is equal to or greater than zero and the second integer element is equal to or greater than zero, a current corresponding to the multiplication value calculated by the first calculator 2a flows through the first positive wiring, and the multiplication values ​​in the second calculator 2b, the third calculator 2c, and the fourth calculator 2d become 0. This calculation is performed by using the first calculator group 2ag.

[0049] When the first integer element is equal to or less than zero and the second integer element is equal to or greater than zero, a current according to the multiplication value calculated by the second calculator 2b flows through the first negative wiring, and the multiplication values ​​of the first calculator 2a, the third calculator 2c, and the fourth calculator 2d become zero. This calculation is performed by the second calculator group 2bg.

[0050] When the first integer element is equal to or less than zero and the second integer element is equal to or less than zero, a current according to the multiplication value calculated by the third calculator 2c flows through the first positive wiring, and the multiplication values ​​of the first calculator 2a, the second calculator 2b, and the fourth calculator 2d become 0. This calculation is performed by the third calculator group 2cg.

[0051] When the first integer element is equal to or greater than zero and the second integer element is equal to or less than zero, a current corresponding to the multiplication value calculated by the fourth calculator 2d flows through the first negative wiring, and the multiplication values ​​of the first calculator 2a, the second calculator 2b, and the third calculator 2c become zero. This calculation is performed by using the fourth calculator group 2dg.

[0052] Figure 8 is a block diagram showing a first group of arithmetic units 2ag that performs calculations of the first element multiplication table EL1, a second group of arithmetic units 2bg that performs calculations of the second element multiplication table EL2, a third group of arithmetic units 2cg that performs calculations of the third element multiplication table EL3, and a fourth group of arithmetic units 2dg that performs calculations of the fourth element multiplication table EL4.

[0053] In the first computing unit group 2ag, the first computing unit 2a and the fourth computing unit 2d multiply the key K by the query Q, and the second computing unit 2b and the third computing unit 2c set the multiplication value to zero regardless of the values ​​of the key K and the query Q. Since a voltage of 0V or more corresponding to the query Q is applied to the first word line WL+, the first computing unit 2a outputs a multiplication value consisting of a value of 0 or more. Since the second word line WL- is fixed to 0V, the fourth computing unit 2d outputs zero as a multiplication value regardless of the value of the key K. In this way, in the first computing unit group 2ag, the first computing unit 2a performs the 3×3 multiplication at the lower right of the first element multiplication table EL1 in FIG. 7, and the second computing unit 2b to the fourth computing unit 2d output zero as a multiplication value. Therefore, a current corresponding to the multiplication value of the first computing unit 2a flows in the first bit line BL+. No current flows in the second bit line BL-.

[0054] In the second computing unit group 2bg, the second computing unit 2b and the third computing unit 2c multiply the key K by the query Q, and the first computing unit 2a and the fourth computing unit 2d set the multiplication value to zero regardless of the values ​​of the key K and the query Q. Since a voltage of 0V or more corresponding to the query Q is applied to the first word line WL+, the second computing unit 2b outputs a multiplication value consisting of a value of 0 or more. Since the second word line WL- is fixed to 0V, the third computing unit 2c outputs zero as the multiplication value regardless of the value of the key K. In this way, in the second computing unit group 2bg, the second computing unit 2b performs the 3×3 multiplication at the bottom left of the first element multiplication table EL1 in FIG. 7, and the first computing unit 2a, the third computing unit 2c, and the fourth computing unit 2d output zero as the multiplication value. Therefore, a current corresponding to the multiplication value of the second computing unit 2b flows in the second bit line BL-. No current flows in the first bit line BL+.

[0055] In the third computing unit group 2cg, the second computing unit 2b and the third computing unit 2c multiply the key K by the query Q, and the first computing unit 2a and the fourth computing unit 2d set the multiplication value to zero regardless of the values ​​of the key K and the query Q. Since the first word line WL+ is fixed to 0V, the second computing unit 2b outputs zero as the multiplication value regardless of the value of the key K. Since a voltage of 0V or more corresponding to the query Q is applied to the second word line WL-, the third computing unit 2c outputs a multiplication value consisting of a value of 0 or more. Thus, in the third computing unit group 2cg, the third computing unit 2c performs the 3×3 multiplication at the top left of the first element multiplication table EL1 in FIG. 7, and the first computing unit 2a, the second computing unit 2b, and the fourth computing unit 2d output zero as the multiplication value. Therefore, a current corresponding to the multiplication value of the third computing unit 2c flows in the first bit line BL+. No current flows in the second bit line BL-.

[0056] In the fourth computing unit group 2dg, the first computing unit 2a and the fourth computing unit 2d multiply the key K by the query Q, and the second computing unit 2b and the third computing unit 2c set the multiplication value to zero regardless of the values ​​of the key K and the query Q. Since the first word line WL+ is fixed to 0V, the first computing unit 2a outputs zero as the multiplication value regardless of the value of the key K. Since a voltage of 0V or more according to the query Q is applied to the second word line WL-, the fourth computing unit 2d outputs a multiplication value consisting of a value of 0 or more. Thus, in the fourth computing unit group 2dg, the fourth computing unit 2d performs the 3×3 multiplication in the upper right of the fourth element multiplication table EL4 in FIG. 7, and the first computing unit 2a to the third computing unit 2c output zero as the multiplication value. Therefore, a current according to the multiplication value of the fourth computing unit 2d flows in the second bit line BL-. No current flows in the first bit line BL+.

[0057] FIG. 9 is a specific circuit diagram of the first to fourth computing units 2a to 2d included in the first computing unit group 2ag. As shown in FIG. 9, each of the first to fourth computing units 2a to 2d has a string 3. The string 3 includes a first transistor 4a and a second transistor 4b connected in series, as in FIG. 5, but the second transistor 4b is omitted in FIG. 9. The gate of the first transistor 4a is connected to the first word line WL+ or the second word line WL-. In the first computing unit group 2ag, since the query Q is equal to or greater than zero, a voltage of 0V or greater according to the query Q is input to the gate of the first transistor 4a in each string 3 of the first computing unit 2a and the second computing unit 2b via the first word line WL+. On the other hand, 0V is input to the gate of the first transistor 4a in each string 3 of the third computing unit 2c and the fourth computing unit 2d in the first computing unit group 2ag via the second word line WL-.

[0058] A threshold voltage according to the key K is set for the first transistor 4a in the string 3 of the first computing unit 2a. The larger the key K, the lower the threshold voltage is set, and the easier it is for a current to flow between the drain and source of the first transistor 4a. The drain-source current of the first transistor 4a of the first computing unit 2a changes according to the voltage difference between the voltage according to the query Q input to the gate and the threshold voltage according to the key K. That is, the drain-source current of the first transistor 4a changes according to the product of the key K and the query Q.

[0059] The current flowing through the string 3 of the first computing unit 2a is determined by the voltage difference between the gate voltage and the threshold voltage of the first transistor 4a in the string 3. In other words, the current flowing through the string 3 of the first computing unit 2a has a value according to the product of the query Q and the key K.

[0060] A high threshold voltage corresponding to the key K being zero is set to the first transistor 4a in each string 3 of the second computing unit 2b and the third computing unit 2c. Therefore, the second transistor 4b and the third transistor 4c are always in the off state.

[0061] A threshold voltage corresponding to the key K is set for the first transistor 4a in the string 3 of the fourth computing unit 2d, but since 0V is input to the gate, the first transistor 4a is turned off and no current flows between the drain and source.

[0062] As a result, no current flows through the strings 3 of the second to fourth computing units 2b to 2d among the first to fourth computing units 2a to 2d constituting the first computing unit group 2ag. On the other hand, a current corresponding to the product of the key K and the query Q flows through the string 3 of the first computing unit 2a. This current flows through the first bit line BL+.

[0063] 9, in each of the second to fourth computing unit groups 2bg to 2dg, the gate voltage and threshold voltage of the first transistor 4a of each string 3 of the first to fourth computing units 2a to 2d are similarly controlled to allow a current corresponding to the multiplication value of the second to fourth element multiplication tables EL2 to EL4 to flow through the first bit line BL+ or the second bit line BL-. Therefore, it is not necessary to separately provide the first to fourth computing units 2a to 2d for computing the first to fourth computing unit groups 2ag to 2dg, respectively. Depending on whether the key K and the query Q are positive or negative, it is determined which of the first group of computing units 2ag to the fourth group of computing units 2dg will be used, and by controlling the threshold voltage of the first transistor 4a of each string 3 of the first to fourth computing units 2a to 2d and the voltages of the first word line WL+ and the second word line WL- according to the determined computing unit group, the key K and the query Q can be multiplied using the first to fourth computing units 2a to 2d corresponding to the determined computing unit group, and a current according to the multiplication result can be passed through the first bit line BL+ or the second bit line BL-.

[0064] 10A is a diagram showing the correspondence relationship between the gate voltage of the first transistor 4a in the string 3 of the first computing unit 2a in the first computing unit group 2ag that performs the calculation of the first element multiplication table EL1 and the current flowing through the string 3. The horizontal axis of FIG. 10A represents the voltage difference between the voltage Vcgr corresponding to the query Q of the first word line WL+ and the threshold voltage Vth corresponding to the key K of the first transistor 4a in the string 3 of the first computing unit 2a. The vertical axis represents the current flowing through the string 3. The straight line W1 in FIG. 10A represents the case where the query Q is 1, and the straight line W2 represents the case where the query Q is 2.

[0065] As can be seen from the straight lines W1 and W2, the larger the potential difference (Vcgr-Vth) and the larger the query Q, the larger the current flowing through the first bit line BL+ and string 3. This means that the larger the product of the key K and the query Q, the larger the current drawn from the first bit line BL+ to the string 3.

[0066] 10B is a diagram showing the correspondence relationship between the gate voltage of the first transistor 4a in the string 3 of the second computing unit 2b of the second computing unit group 2bg that performs the calculation of the second element multiplication table EL2 and the current flowing through the string 3. The horizontal and vertical axes are the same as those in FIG. 10A, but the positive direction of the horizontal axis is the direction in which the potential difference (Vcgr-Vth), i.e., the negative absolute value of the key K, is larger. The straight line W3 in FIG. 10B indicates the case where the query Q is 1, and the straight line W4 indicates the case where the query Q is 2.

[0067] As can be seen from the straight lines W3 and W4, the larger the absolute value of the potential difference (Vcgr-Vth) and the larger the query Q, the larger the current flowing through the second bit line BL- and string 3. This indicates that the larger the negative absolute value of the product of the key K and the query Q, the larger the current drawn from the second bit line BL- to the string 3.

[0068] Fig. 10C is a diagram showing the correspondence relationship between the gate voltage of the first transistor 4a in the string 3 of the third computing unit 2c of the third computing unit group 2cg that performs the calculation of the third element multiplication table EL3 and the current flowing through the string 3. The horizontal and vertical axes are the same as those in Fig. 10A, but the positive direction of the horizontal axis is the direction in which the potential difference (Vcgr-Vth), i.e., the negative absolute value of the key K, is larger. The straight line W5 in Fig. 10C indicates the case where the query Q is -1, and the straight line W6 indicates the case where the query Q is -2.

[0069] As can be seen from lines W5 and W6, the larger the absolute value of the potential difference (Vcgr-Vth) is and the larger the negative absolute value of query Q is, the larger the current flowing through the second bit line BL+ and string 3. This indicates that the larger the absolute value of the product of key K and query Q is, the larger the current drawn from the second bit line BL+ to string 3 is.

[0070] Fig. 10D is a diagram showing the correspondence relationship between the gate voltage of the first transistor 4a in the string 3 of the fourth calculator 2d of the fourth calculator group 2dg that performs the calculation of the fourth element multiplication table EL4 and the current flowing through the string 3. The horizontal and vertical axes are the same as those in Fig. 10A. The straight line W7 in Fig. 10D indicates the case where the query Q is -1, and the straight line W8 indicates the case where the query Q is -2.

[0071] As can be seen from lines W7 and W8, the larger the potential difference (Vcgr-Vth) and the larger the negative absolute value of query Q, the larger the current flowing through the second bit line BL- and string 3. This means that the larger the negative absolute value of the product of key K and query Q, the larger the current drawn from the second bit line BL- to string 3.

[0072] 11A and 11B are diagrams showing an example in which the element multiplication table EL0 shown in FIG. 7 is decomposed into a fifth element multiplication table EL5 for passing a current through the first bit line BL+ and a sixth element multiplication table EL6 for passing a current through the second bit line BL-, where Fig. 11A shows the fifth element multiplication table EL5 and Fig. 11B shows the sixth element multiplication table EL6. The multiplication values ​​of the sixth element multiplication table EL6 essentially include negative values, but since a current is passed through the second bit line BL- in the same direction as the first bit line BL+, the multiplication values ​​of the sixth element multiplication table EL6 are set to positive values.

[0073] As shown in FIG. 11A, the average value μ of the multiplication value in both the fifth element multiplication table EL5 and the sixth element multiplication table EL6 is 0.281767, and the standard deviation σ 2 is 0.438686, and the multiplication values ​​are normally distributed. In contrast, the average value μ of the multiplication values ​​in the original element multiplication table EL0 shown in FIG. 7 is 0, and the standard deviation σ 2 is 1.036158. Comparing the fifth element multiplication table EL5 and the sixth element multiplication table EL6 with the original element multiplication table EL0, the average value is slightly higher, but the standard deviation can be significantly reduced.

[0074] FIG. 6 shows an example in which one arithmetic unit group 2g is connected to a bit line pair BL+, BL- consisting of a first bit line BL+ and a second bit line BL-, but multiple arithmetic unit groups 2g may be connected to the bit line pair BL+, BL-.

[0075] 12A is a block diagram of an information processing device 5 according to a first modification of the first embodiment. The information processing device 5 according to the first modification includes a plurality of arithmetic unit groups 2g connected to bit line pairs BL+, BL-, and a plurality of word line pairs WL+, WL- connected to the plurality of arithmetic unit groups 2g. A word line pair WL+, WL- is provided for each of the plurality of arithmetic unit groups 2g. Each of the plurality of arithmetic unit groups 2g is configured in the same manner as in FIG. 6.

[0076] Each of the multiple arithmetic unit groups 2g draws a current corresponding to the multiplication value of the key K and the query Q from the first bit line BL+ or the second bit line BL-. A current corresponding to the sum of the positive multiplication values ​​calculated by the multiple arithmetic unit groups 2g flows through the first bit line BL+, resulting in a voltage corresponding to this current. A current corresponding to the sum of the negative multiplication values ​​calculated by the multiple arithmetic unit groups 2g flows through the second bit line BL-, resulting in a voltage corresponding to this current.

[0077] In this way, the information processing device 5 in Fig. 12A transmits the result of the multiplication and accumulation of the positive multiplied value on the first bit line BL+, and transmits the result of the multiplication and accumulation of the negative multiplied value on the second bit line BL-. As will be described later, the final result of the multiplication and accumulation performed by the group of multiple calculators 2g in Fig. 12A can be generated by taking the difference between the voltage of the first bit line BL+ and the voltage of the second bit line BL- in a subsequent circuit.

[0078] 12B is a block diagram of an information processing device 5 according to a second modified example of the first embodiment. The information processing device 5 according to the second modified example multiplies a plurality of first integer elements of a first vector by a plurality of second integer elements of a second vector.

[0079] The information processing device 5 according to the second modification includes a plurality of bit line pairs BL+, BL-, at least one arithmetic unit group 2g connected to each of the bit line pairs BL+, BL-, and at least one word line pair WL+, WL-.

[0080] The multiple bit line pairs BL+, BL- are arranged in a first direction X and extend in a second direction Y intersecting the first direction X. A computing unit group 2g is disposed at each of the intersections between the multiple bit line pairs BL+, BL- and the word line pairs WL+, WL-.

[0081] In the information processing device 5 according to the second modification, multiple elements can be multiplied in parallel on multiple bit line pairs BL+, BL-. Therefore, the multiplication of elements of a first vector including multiple first integer elements and a second vector including multiple second integer elements can be performed in parallel, so that the inner product value of the first vector and the second vector can be calculated quickly.

[0082] In this way, the information processing device 5 according to the first embodiment can perform the multiplication of the first integer element and the second integer element, which can have a negative value, in a hardware circuit such as the CIM 1 without changing the direction of the current. Therefore, for example, a product-sum operation including a negative value used in machine learning can be performed in the hardware circuit.

[0083] In the first embodiment, when multiplying a first integer element and a second integer element that can have a negative value, a first word line WL+ for inputting a query Q of a value equal to or greater than zero, a second word line WL- for inputting a query Q of a value equal to or less than zero, a first bit line BL+ for passing a current according to a multiplication value of a value equal to or greater than zero, and a second bit line BL- for passing a current according to a multiplication value of a value equal to or less than zero are provided, a voltage equal to or greater than 0V is applied to the first word line WL+ and the second word line WL-, and a current is passed in the same direction to the first bit line BL+ and the second bit line BL-. Depending on whether the key K and the query Q are equal to or greater than zero or equal to or less than zero, the element multiplication table EL0 for multiplying the key K and the query Q is decomposed into first to fourth element multiplication tables EL1 to EL4, and the configuration of the computing unit group 2g is changed depending on which of the first to fourth element multiplication tables EL1 to EL4 is to be calculated. Specifically, first to fourth computing unit groups 2ag to 2dg are provided to perform the calculations of the first to fourth element multiplication tables EL1 to EL4. This makes it possible to align the directions of the voltages applied to the first and second word lines WL+, WL- and align the directions of the currents flowing through the first and second bit lines BL+, BL- even if the key K and the query Q include negative values. According to the first embodiment, the key K and the query Q can be multiplied with a simple circuit configuration without increasing the average current flowing through the first bit line BL+ and the second bit line BL-.

[0084] Second embodiment The information processing device 5 according to the first embodiment requires a group of arithmetic units 2g consisting of four arithmetic units 2 to multiply a pair of integer elements. Therefore, the area efficiency is not very good. Therefore, the information processing device 5 according to the second embodiment aims to improve the area efficiency more than that of the first embodiment.

[0085] 13 is a block diagram of an information processing device 5 according to the second embodiment. The information processing device 5 according to the second embodiment includes a bit line BL, a word line pair WL+, WL-, and a computing unit group 2g having two computing units 2 (hereinafter, a first computing unit 2a and a second computing unit 2b).

[0086] The bit line BL passes a current according to the product of the first integer element and the second integer element. In the second embodiment, a current passes through the bit line BL in only one direction. The first integer element and the second integer element can be a positive integer, a negative integer, or zero.

[0087] As described below, the second embodiment is characterized in that, even if at least one of the key K and the query Q is a negative value, a current corresponding to a modified multiplication value (hereinafter, the modified multiplication value) is passed through the bit line BL so that the multiplication value of the key K and the query Q becomes a value greater than or equal to zero.

[0088] The first word line WL+ is activated when the second integer element (query Q) is positive. The second word line WL- is activated when the first integer element is negative. A voltage of 0V or more according to the absolute value of query Q is applied to the first word line WL+ and the second word line WL-.

[0089] The first computing unit 2a is connected to the bit line BL and the first word line WL+, and passes a current corresponding to the product of the first integer element and the second integer element through the bit line BL.

[0090] The second computing unit 2b is connected to the bit line BL and the second word line WL-, and passes a current corresponding to the product of the first integer element and the second integer element through the bit line BL.

[0091] Fig. 14 is a diagram showing an element multiplication table EL0 for multiplication between integer elements performed by the arithmetic unit group 2g according to the second embodiment. The element multiplication table EL0 in Fig. 14 is the same as the element multiplication table EL0 in Fig. 7, and the multiplication value takes any one of 4, 2, 1, 0, -1, -2, and -4.

[0092] The element multiplication table EL0 in FIG. 14 can be decomposed into a first element multiplication table EL1a and a second element multiplication table EL2a depending on whether the query Q is positive or negative. The first element multiplication table EL1a shown in FIG. 14 is obtained by extracting multiplication values ​​with a query Q of zero or more from the element multiplication table EL0, and the second element multiplication table EL2a is obtained by extracting multiplication values ​​with a query Q of zero or less from the element multiplication table EL0. When the query Q is zero, it is included in both the first element multiplication table EL1a and the second element multiplication table EL2a. For example, the calculation of the first element multiplication table EL1a can be performed by the first calculator 2a in FIG. 13, and the calculation of the second element multiplication table EL2a can be performed by the second calculator 2b in FIG. 13. However, since the multiplication values ​​of the first element multiplication table EL1a and the second element multiplication table EL2a include positive and negative values, the direction of the current flowing through the bit line BL must be switched according to the multiplication value. The data processing device 5 according to the second embodiment is characterized in that a current always flows in the same direction through the bit lines BL.

[0093] FIG. 15 is a diagram showing the first modified element multiplication table EL0a in which each multiplication value in the element multiplication table EL0 is uniformly shifted by a predetermined value (for example, +4). In the first modified element multiplication table EL0a shown in FIG. 15, the above-mentioned predetermined value is set to the maximum negative absolute value (=+4) of each multiplication value in the element multiplication table EL0. As a result, while the maximum value of each multiplication value in the element multiplication table EL0 is 4 and the minimum value is -4, the maximum value of the multiplication value in the first modified element multiplication table EL0a is 8 and the minimum value is 0. Therefore, the average value μ of each multiplication value in the first modified element multiplication table EL0a is 4, and the standard deviation σ 2 becomes 1.036. In the first modified element multiplication table EL0a, all the multiplication values ​​are equal to or greater than zero, so that the average value μ becomes larger than the average value μ (=0) of the original element multiplication table EL0.

[0094] In this way, the first calculator 2a and the second calculator 2b add a value equal to or greater than the maximum absolute value of the negative values ​​among the multiplication values ​​of any combination of all possible values ​​of the first integer element and all possible values ​​of the second integer element to the multiplication value of the first integer element and the second integer element to generate the first modified multiplication value and the second modified multiplication value.

[0095] The first calculator 2a shown in FIG. 13 performs the calculations of the lower half of the first correction element multiplication table EL0a in FIG. 15, and the second calculator 2b performs the calculations of the upper half of the first correction element multiplication table EL0a in FIG.

[0096] 16 is a diagram showing the correspondence relationship between the gate voltage of the first transistor 4a of the string 3 included in the first computing unit 2a and the second computing unit 2b that perform the calculation of the first correction element multiplication table EL0a, and the current flowing through the string 3. The horizontal axis of FIG. 16 corresponds to the voltage difference between the voltage Vcgr corresponding to the query Q of the first word line WL+ or the second word line WL- and the threshold voltage Vth corresponding to the key K of the first transistor 4a in the string 3 of the first computing unit 2a or the second computing unit 2b. The vertical axis represents the current flowing through the string 3.

[0097] 16, a line W9 indicates the case where the query Q is 1 or -1, and a line W10 indicates the case where the query Q is 2 or -2. As shown in FIG 16, the lines W9 and W10 have different voltage differences (Vcgr-Vth) when the current flowing through the string 3 is zero (zero point).

[0098] Fig. 17 is a diagram showing a second modified element multiplication table EL0b in which the value by which each multiplication value of the element multiplication table EL0 is shifted is changed for each value of query Q. In the second modified element multiplication table EL0b shown in Fig. 17, the multiplication value is shifted by +2 when query Q is 1 or -1, and the multiplication value is shifted by +4 when query Q is 2 or -2.

[0099] The first calculator 2a and the second calculator 2b generate a first modified multiplication value and a second modified multiplication value by adding a value equal to or greater than the maximum absolute value of negative values ​​among multiple multiplication values ​​having the same second integer element (query Q) and different first integer elements (key K) to the multiplication value of the first integer element and the second integer element. The second modified element multiplication table EL0b includes the first modified multiplication value (=+2) and the second modified multiplication value (=+4).

[0100] That is, the first calculator 2a and the second calculator 2b add a value equal to or greater than the maximum absolute value of negative values ​​among the multiplication values ​​of all possible values ​​of the first integer element and any combination of the second integer element and the first integer element to the multiplication value of the first integer element and the second integer element to generate a first modified multiplication value and a second modified multiplication value.

[0101] 18 is a diagram showing the correspondence relationship between the gate voltage of the first transistor 4a of the string 3 included in the first computing unit 2a and the second computing unit 2b that perform the calculations of the second correction element multiplication table EL0b and the current flowing through the string 3. The horizontal and vertical axes in FIG. 18 are the same as those in FIG.

[0102] 18, a straight line W11 indicates the case where the query Q is 1 or -1, and a straight line W12 indicates the case where the query Q is 2 or -2. As shown in FIG 18, the straight lines W11 and W12 have the same voltage difference (Vcgr-Vth) when the current flowing through the string 3 is zero.

[0103] 19A is a block diagram of an information processing device 5 according to a first modification of the second embodiment. The information processing device 5 according to the first modification includes a plurality of arithmetic unit groups 2g connected to a bit line BL, and a plurality of word line pairs WL+, WL- connected to the plurality of arithmetic unit groups 2g. Each of the word line pairs WL+, WL- is connected to one of the arithmetic unit groups 2g. Each of the plurality of arithmetic unit groups 2g is configured in the same manner as in FIG.

[0104] Each of the multiple calculation unit groups 2g draws from the bit line BL a current corresponding to the multiplication value of the key K and the query Q. A current corresponding to the multiplication value calculated by the multiple calculation unit groups 2g flows through the bit line BL, and the voltage drops to a level corresponding to this current.

[0105] In this way, the information processing device 5 in FIG. 19A passes a current corresponding to the result of the product-sum operation of the key K and query Q calculated by a group of multiple calculators 2g through the bit line BL, and the bit line BL becomes at a voltage corresponding to the result of the product-sum operation.

[0106] 19B is a block diagram of an information processing device 5 according to a second modification of the second embodiment. The information processing device 5 according to the second modification includes a plurality of bit lines BL, at least one arithmetic unit group 2g connected to each bit line BL, and at least one word line pair WL+, WL-.

[0107] The multiple bit lines BL are arranged in a first direction X, and each extends in a second direction Y intersecting the first direction X. A group of arithmetic units 2g is disposed at each of the intersections between the multiple bit lines BL and the word line pairs WL+, WL-.

[0108] In the information processing device 5 according to the second modification, the multiplication of a plurality of elements can be performed in parallel on a plurality of bit lines BL. Therefore, the multiplication of elements of a first vector including a plurality of first integer elements and a second vector including a plurality of second integer elements can be performed in parallel, so that the inner product value of the first vector and the second vector can be calculated quickly.

[0109] In this way, the information processing device 5 according to the second embodiment can calculate the multiplication value of the first integer element and the second integer element using two arithmetic units 2, the word line pair WL+, WL-, and the bit line BL, and can reduce the circuit scale more than that of the first embodiment. By performing the calculation based on the first modified element multiplication table EL0a in which each multiplication value of the element multiplication table EL0 indicating the combination of the multiplication value of the first integer element and the second integer element is shifted to the positive side in accordance with the maximum absolute value of the negative value, or by performing the calculation based on the second modified element multiplication table EL0b in which the value to be shifted is changed for each query Q, the multiplication result of elements can be transmitted via the bit line BL without changing the direction of the current flowing through one bit line BL.

[0110] (Third embodiment) The information processing device 5 according to the first and second embodiments can be incorporated into a memory system.

[0111] 20 is a block diagram showing a schematic configuration of a memory system 10 according to the third embodiment. As shown in FIG. 20, the memory system 10 according to the third embodiment includes a memory cell array 11, a row selection circuit 12, a sense amplifier / column selection circuit 13, a data input / output buffer 14, a bit line operation circuit 15, and a controller 16.

[0112] 5, the memory cell array 11 has one or more bit lines BL and a plurality of strings 3, one end of each of which is connected to each bit line BL. Each string 3 has a first transistor 4a and a second transistor 4b connected in series.

[0113] The memory cell array 11 has a computing unit group 2g having first to fourth computing units 2a to 2d shown in FIG. 6, a bit line pair BL+, BL- consisting of a first bit line BL+ and a second bit line BL-, and a word line pair WL+, WL- consisting of a first word line WL+ and a second word line WL-.

[0114] The row selection circuit 12 controls the gate voltages of the first transistor 4a and the second transistor 4b of each string 3 in accordance with an instruction from the controller 16. More specifically, the row selection circuit 12 controls a voltage corresponding to the query Q of a first word line WL+ connected to the gates of the first transistor 4a of the first computing unit 2a and the second computing unit 2b, and a voltage corresponding to the query Q of a second word line WL- connected to the gates of the first transistor 4a of the third computing unit 2c and the fourth computing unit 2d.

[0115] The sense amplifier / column selection circuit 13 senses the voltage of each bit line BL. When there are multiple bit line pairs BL+, BL-, the voltages of each bit line pair BL+, BL- may be selected in sequence and output serially, or the voltages of multiple bit line pairs BL+, BL- may be selected in parallel and output in parallel.

[0116] The data input / output buffer 14 supplies the signal sensed by the sense amplifier / column selection circuit 13 to the bit line operation circuit 15, and also supplies data (key K) including a first vector K input from the outside to the sense amplifier / column selection circuit 13.

[0117] The bit line operation circuit 15 calculates a value corresponding to a voltage difference or current difference between the first bit line BL+ and the second bit line BL-, which constitute the bit line pair BL+ and BL-, based on the voltage or current of the first bit line BL+ and the voltage or current of the second bit line BL-. The bit line operation circuit 15 includes a complement generation circuit, an addition circuit, etc.

[0118] The controller 16 controls the row selection circuit 12 , the sense amplifier / column selection circuit 13 , the data input / output buffer 14 , and the bit line operation circuit 15 .

[0119] 21 is a block diagram showing a schematic configuration of a memory system 10a according to a modification of the embodiment 3. As shown in FIG. 21, the memory system 10a according to the modification includes a memory cell array 11, a row selection circuit 12, a sense amplifier / column selection circuit 13, a data input / output buffer 14, and a query shift unit 17.

[0120] The memory cell array 11 has first and second arithmetic units 2a and 2b, a bit line BL, and a word line pair WL+, WL- consisting of a first word line WL+ and a second word line WL-, as shown in Fig. 13. The bit line BL passes a current according to the product of integer elements, so that the bit line arithmetic circuit 15 as shown in Fig. 20 is not required.

[0121] The query shift unit 17 modifies the value of the query Q based on the first modified multiplication value or the second modified multiplication value. As a result, by outputting a gate voltage corresponding to the modified query Q output from the query shift unit 17 from the row selection circuit 12, a current corresponding to the first modified multiplication value or the second modified multiplication value can be caused to flow through the string 3 and the bit line BL.

[0122] In this way, in the third embodiment, the information processing device 5 according to the first and second embodiments can be incorporated into the memory system 10, 10a, and the dot product of the first and second vectors can be calculated by reusing an existing memory system.

[0123] [Note] [Item 1] An information processing device that multiplies a first integer element and a second integer element, a first positive wiring that passes a current according to a multiplication value of the first integer element and the second integer element when the multiplication value is equal to or greater than zero; a first negative wiring that passes a current according to the multiplied value when the multiplied value is equal to or less than zero; a second positive wiring that is activated when the second integer element is positive; a second negative wiring that is activated when the second integer element is negative; a first computing unit connected to the first positive wiring and the second positive wiring, which multiplies the first integer element and the second integer element and passes a current through the first positive wiring when the multiplied value is equal to or greater than zero; a second computing unit connected to the first negative wiring and the second positive wiring, multiplying the first integer element and the second integer element, and causing a current to flow through the first negative wiring when the multiplied value is equal to or less than zero; a third computing unit connected to the first positive wiring and the second negative wiring, multiplying the first integer element and the second integer element, and causing a current to flow through the first positive wiring when the multiplied value is equal to or greater than zero; a fourth computing unit connected to the first negative wiring and the second negative wiring, which multiplies the first integer element and the second integer element and passes a current through the first negative wiring when the multiplied value is equal to or less than zero; The direction of the current flowing through the first positive wiring is the same as the direction of the current flowing through the first negative wiring, the first integer element is a positive integer, a negative integer, or zero; the second integer element is a positive integer, a negative integer, or zero; Information processing device. [Item 2] a current corresponding to the multiplied value calculated by any one of the first calculator, the second calculator, the third calculator, and the fourth calculator flows through the first positive wiring or the first negative wiring based on whether the first integer element is equal to or greater than zero and whether the second integer element is equal to or greater than zero. Item 1. An information processing device according to item 1. [Item 3] When the first integer element is equal to or greater than zero and the second integer element is equal to or greater than zero, a current corresponding to the multiplication value calculated by the first calculator flows through the first positive wiring, and the multiplication values ​​in the second calculator, the third calculator, and the fourth calculator become zero; When the first integer element is equal to or less than zero and the second integer element is equal to or greater than zero, a current corresponding to the multiplication value calculated by the second calculator flows through the first negative wiring, and the multiplication values ​​in the first calculator, the third calculator, and the fourth calculator become zero; When the first integer element is equal to or less than zero and the second integer element is equal to or less than zero, a current corresponding to the multiplication value calculated by the third calculator flows through the first positive wiring, and the multiplication values ​​in the first calculator, the second calculator, and the fourth calculator become zero; When the first integer element is equal to or greater than zero and the second integer element is equal to or less than zero, a current corresponding to the multiplication value calculated by the fourth calculator flows through the first negative wiring, and the multiplication values ​​in the first calculator, the second calculator, and the third calculator become zero. Item 3. An information processing device according to item 2. [Item 4] a plurality of arithmetic unit groups each having the first arithmetic unit, the second arithmetic unit, the third arithmetic unit, and the fourth arithmetic unit; each of the plurality of groups of calculators calculates the multiplication value of the corresponding first integer elements and the corresponding second integer elements in a first vector including a plurality of the first integer elements and a second vector including a plurality of the second integer elements; 4. The information processing device according to any one of items 1 to 3. [Item 5] Each of the plurality of arithmetic unit groups is connected to the first positive wiring and the first negative wiring, the first positive wiring passes a current corresponding to a sum of positive multiplication values ​​calculated by the plurality of computing unit groups; the first negative wiring passes a current corresponding to a sum of negative multiplication values ​​calculated by the plurality of groups of calculators; Item 5. An information processing device according to item 4. [Item 6] a first wiring group arranged in a first direction and each of the first wiring groups extending in a second direction intersecting the first direction; the first wiring group includes a plurality of pairs of the first positive wiring and the first negative wiring, each pair being the first positive wiring and the first negative wiring; the second positive wiring and the second negative wiring are arranged so as to intersect with the first wiring groups; the group of arithmetic units is disposed in correspondence with the intersections of the second positive wiring and the second negative wiring with the first wiring group; Item 6. The information processing device according to item 4 or 5. [Item 7] each of the first computing unit, the second computing unit, the third computing unit, and the fourth computing unit has a transistor that passes a current corresponding to the multiplication value; 7. An information processing device according to any one of items 1 to 6. [Item 8] When a multiplication value of the first integer element and the second integer element is equal to or greater than zero, the transistor causes a current according to the multiplication value to flow from the first positive wiring or the first negative wiring. Item 8. An information processing device according to item 7. [Item 9] a threshold voltage corresponding to the first integer element is set for the transistor; A voltage according to the second integer element is input to a gate of the transistor via the second positive wiring or the second negative wiring. Item 9. The information processing device according to item 7 or 8. [Item 10] Each of the first computing unit, the second computing unit, the third computing unit, and the fourth computing unit has a string having one end connected to the first positive wiring or the first negative wiring, The string is a series of transistors including the transistor. 10. The information processing device according to any one of items 7 to 9. [Item 11] An information processing device that multiplies a first integer element and a second integer element, a first wiring that passes a current according to a product of the first integer element and the second integer element; a second positive wiring that is activated when the second integer element is positive; a second negative wiring that is activated when the second integer element is negative; a first computing unit that is connected to the first wiring and the second positive wiring and that causes a current corresponding to a first corrected multiplication value, which is corrected so that the multiplication value of the first integer element and the second integer element becomes a value equal to or greater than zero, to flow through the first wiring; a second computing unit connected to the first wiring and the second negative wiring, which causes a current corresponding to a second corrected multiplication value, which is corrected so that the multiplication value of the first integer element and the second integer element becomes a value equal to or greater than zero, to flow through the first wiring; the first integer element is a positive integer, a negative integer, or zero; the second integer element is a positive integer, a negative integer, or zero; Information processing device. [Item 12] the first computing unit and the second computing unit add a value equal to or greater than the maximum absolute value of negative values ​​among multiplication values ​​of any combination of all possible values ​​of the first integer element and all possible values ​​of the second integer element to a multiplication value of the first integer element and the second integer element to generate the first modified multiplication value and the second modified multiplication value. Item 12. An information processing device according to item 11. [Item 13] the first computing unit and the second computing unit add a value equal to or greater than a maximum absolute value of negative values ​​among multiplication values ​​of any combination of all possible values ​​of the first integer element and the second integer element to a multiplication value of the first integer element and the second integer element to generate the first modified multiplication value and the second modified multiplication value. Item 12. An information processing device according to item 11. [Item 14] a plurality of arithmetic unit groups each having the first arithmetic unit and the second arithmetic unit; each of the plurality of groups of calculators calculates the multiplication value of the corresponding first integer elements and the corresponding second integer elements in a first vector including a plurality of the first integer elements and a second vector including a plurality of the second integer elements; 14. The information processing device according to any one of items 11 to 13. [Item 15] each of the plurality of arithmetic unit groups is connected to the first wiring; the second positive wiring and the second negative wiring are connected to each of the plurality of arithmetic unit groups, the first wiring passes a current corresponding to a sum of the first modified multiplication value calculated by the first computing unit and the second modified multiplication value calculated by the second computing unit; Item 15. An information processing device according to item 14. [Item 16] a plurality of the first wirings arranged in a first direction and each extending in a second direction intersecting the first direction; the second positive wiring and the second negative wiring are arranged to intersect with the plurality of first wirings, the group of arithmetic units is disposed in correspondence with locations where the second positive wiring and the second negative wiring intersect with the plurality of first wirings; Item 16. The information processing device according to item 14 or 15. [Item 17] each of the first computing unit and the second computing unit has a transistor that passes a current according to the multiplication value; 17. An information processing device according to any one of items 11 to 16. [Item 18] The transistor causes a current corresponding to the first modified multiplication value or the second modified multiplication value to flow from the first wiring. Item 18. An information processing device according to item 17. [Item 19] 1. A memory system for computing an inner product of a first vector including a plurality of integer elements and a second vector including a plurality of integer elements, comprising: a first positive wiring that, when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or greater than zero, passes a current according to the multiplication value; a first negative wiring that, when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or less than zero, passes a current according to the multiplication value; a second positive wiring that is activated when an integer element of the first vector is positive; a second negative wiring that is activated when an integer element of the first vector is negative; a first computing unit connected to the first positive wiring and the second positive wiring, for causing a current to flow through the first positive wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or greater than zero; a second computing unit connected to the first negative wiring and the second positive wiring, for passing a current through the first negative wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or less than zero; a third computing unit connected to the first positive wiring and the second negative wiring, for causing a current to flow through the first positive wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or greater than zero; a fourth computing unit connected to the first negative wiring and the second negative wiring, which flows a current through the first negative wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or less than zero; and a fifth calculator that calculates the voltage or current of the first positive wiring and the first negative wiring. Memory system. [Item 20] 1. A memory system for computing an inner product of a first vector including a plurality of integer elements and a second vector including a plurality of integer elements, comprising: a first wiring that passes a current according to a multiplication value of corresponding integer elements of the first vector and the second vector; a second positive wiring that is activated when an integer element of the second vector is positive; a second negative wiring that is activated when the integer element of the second vector is negative; a first computing unit that is connected to the first wiring and the second positive wiring and that flows a current to the first wiring according to a first corrected multiplication value that is corrected so that a multiplication value of corresponding integer elements of the first vector and the second vector becomes a value equal to or greater than zero; a second computing unit that is connected to the first wiring and the second negative wiring and that flows a current to the first wiring according to a second corrected multiplication value that is corrected so that a multiplication value of corresponding integer elements of the first vector and the second vector becomes a value equal to or greater than zero; a wiring voltage correction unit that corrects a voltage corresponding to a corresponding integer element of the second vector based on the first correction multiplication value and the second correction multiplication value; the first computing unit causes a current corresponding to the first corrected multiplication value to flow through the first wiring by using the voltage corrected by the wiring voltage correction unit; the second computing unit causes a current corresponding to the second corrected multiplication value to flow through the first wiring by using the voltage corrected by the wiring voltage correcting unit; Memory system.

[0124] The aspects of the present disclosure are not limited to the above-mentioned individual embodiments, but include various modifications that may be conceived by a person skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0125] 1 CIM, 2 arithmetic unit, 2a first arithmetic unit, 2ag first arithmetic unit group, 2b second arithmetic unit, 2bg second arithmetic unit group, 2c third arithmetic unit, 2cg third arithmetic unit group, 2d fourth arithmetic unit, 2dg fourth arithmetic unit group, 2g arithmetic unit group, 3 string, 4 transistor, 4a first transistor, 4b second transistor, 5 information processing device, 10, 10a memory system, 11 memory cell array, 12 row selection circuit, 13 column selection circuit, 14 data input / output buffer, 15 bit line arithmetic circuit, 16 controller, 17 query shift unit

Claims

1. An information processing device that performs multiplication of a first integer element and a second integer element, a first positive wiring that, when a multiplication value of the first integer element and the second integer element is equal to or greater than zero, passes a current according to the multiplication value; a first negative wiring that passes a current according to the multiplied value when the multiplied value is equal to or less than zero; a second positive wiring that is activated when the second integer element is positive; a second negative wiring that is activated when the second integer element is negative; a first computing unit connected to the first positive wiring and the second positive wiring, which multiplies the first integer element and the second integer element and passes a current through the first positive wiring when the multiplied value is equal to or greater than zero; a second computing unit connected to the first negative wiring and the second positive wiring, multiplying the first integer element and the second integer element, and causing a current to flow through the first negative wiring when the multiplied value is equal to or less than zero; a third computing unit connected to the first positive wiring and the second negative wiring, multiplying the first integer element and the second integer element, and causing a current to flow through the first positive wiring when the multiplied value is equal to or greater than zero; a fourth computing unit connected to the first negative wiring and the second negative wiring, which multiplies the first integer element and the second integer element and passes a current through the first negative wiring when the multiplied value is equal to or less than zero; The direction of the current flowing through the first positive wiring is the same as the direction of the current flowing through the first negative wiring, the first integer element is a positive integer, a negative integer, or zero; the second integer element is a positive integer, a negative integer, or zero; Information processing device.

2. a current corresponding to the multiplied value calculated by any one of the first calculator, the second calculator, the third calculator, and the fourth calculator flows through the first positive wiring or the first negative wiring based on whether the first integer element is equal to or greater than zero and whether the second integer element is equal to or greater than zero. The information processing device according to claim 1 .

3. When the first integer element is equal to or greater than zero and the second integer element is equal to or greater than zero, a current corresponding to the multiplication value calculated by the first calculator flows through the first positive wiring, and the multiplication values ​​in the second calculator, the third calculator, and the fourth calculator become zero; When the first integer element is equal to or less than zero and the second integer element is equal to or greater than zero, a current corresponding to the multiplication value calculated by the second calculator flows through the first negative wiring, and the multiplication values ​​in the first calculator, the third calculator, and the fourth calculator become zero; When the first integer element is equal to or less than zero and the second integer element is equal to or less than zero, a current corresponding to the multiplication value calculated by the third calculator flows through the first positive wiring, and the multiplication values ​​in the first calculator, the second calculator, and the fourth calculator become zero; When the first integer element is equal to or greater than zero and the second integer element is equal to or less than zero, a current corresponding to the multiplication value calculated by the fourth calculator flows through the first negative wiring, and the multiplication values ​​in the first calculator, the second calculator, and the third calculator become zero. The information processing device according to claim 2 .

4. a plurality of arithmetic unit groups each having the first arithmetic unit, the second arithmetic unit, the third arithmetic unit, and the fourth arithmetic unit; each of the plurality of groups of calculators calculates the multiplication value of the corresponding first integer elements and the corresponding second integer elements in a first vector including a plurality of the first integer elements and a second vector including a plurality of the second integer elements; The information processing device according to claim 1 .

5. Each of the plurality of arithmetic unit groups is connected to the first positive wiring and the first negative wiring, the first positive wiring passes a current corresponding to a sum of positive multiplication values ​​calculated by the plurality of computing unit groups; the first negative wiring passes a current corresponding to a sum of negative multiplication values ​​calculated by the plurality of groups of calculators; The information processing device according to claim 4.

6. a plurality of first wiring groups arranged in a first direction and each extending in a second direction intersecting the first direction; the first wiring group includes a plurality of pairs of the first positive wiring and the first negative wiring, each pair being the first positive wiring and the first negative wiring; the second positive wiring and the second negative wiring are arranged so as to intersect with the first wiring groups; the computing unit group is disposed in correspondence with a location where the second positive wiring and the second negative wiring intersect with the first wiring group; The information processing device according to claim 4.

7. each of the first computing unit, the second computing unit, the third computing unit, and the fourth computing unit has a transistor that passes a current corresponding to the multiplication value; The information processing device according to claim 1 .

8. the transistor causes a current according to a multiplication value of the first integer element and the second integer element to flow from the first positive wiring or the first negative wiring when the multiplication value is equal to or greater than zero; The information processing device according to claim 7.

9. a threshold voltage corresponding to the first integer element is set for the transistor; a voltage according to the second integer element is input to a gate of the transistor via the second positive wiring or the second negative wiring; The information processing device according to claim 7.

10. Each of the first computing unit, the second computing unit, the third computing unit, and the fourth computing unit has a string having one end connected to the first positive wiring or the first negative wiring, The string is a series of transistors including the transistor. The information processing device according to claim 7.

11. An information processing device that performs multiplication of a first integer element and a second integer element, a first wiring that passes a current according to a product of the first integer element and the second integer element; a second positive wiring that is activated when the second integer element is positive; a second negative wiring that is activated when the second integer element is negative; a first computing unit connected to the first wiring and the second positive wiring, which causes a current corresponding to a first corrected multiplication value, which is corrected so that a multiplication value of the first integer element and the second integer element becomes a value equal to or greater than zero, to flow through the first wiring; a second computing unit connected to the first wiring and the second negative wiring, which causes a current corresponding to a second corrected multiplication value, which is corrected so that a multiplication value of the first integer element and the second integer element becomes a value equal to or greater than zero, to flow through the first wiring; the first integer element is a positive integer, a negative integer, or zero; the second integer element is a positive integer, a negative integer, or zero; Information processing device.

12. the first computing unit and the second computing unit add a value equal to or greater than a maximum absolute value of negative values ​​among multiplication values ​​of any combination of all possible values ​​of the first integer element and all possible values ​​of the second integer element to a multiplication value of the first integer element and the second integer element to generate the first modified multiplication value and the second modified multiplication value. The information processing device according to claim 11.

13. the first computing unit and the second computing unit add a value equal to or greater than a maximum absolute value of negative values ​​among multiplication values ​​of any combination of all possible values ​​of the first integer element and the second integer element to a multiplication value of the first integer element and the second integer element to generate the first modified multiplication value and the second modified multiplication value. The information processing device according to claim 11.

14. a plurality of arithmetic unit groups each having the first arithmetic unit and the second arithmetic unit; each of the plurality of groups of calculators calculates the multiplication value of the corresponding first integer elements and the corresponding second integer elements in a first vector including a plurality of the first integer elements and a second vector including a plurality of the second integer elements; The information processing device according to claim 11.

15. each of the plurality of computing unit groups is connected to the first wiring; the second positive wiring and the second negative wiring are connected to each of the plurality of arithmetic unit groups, the first wiring passes a current corresponding to a sum of the first modified multiplication value calculated by the first computing unit and the second modified multiplication value calculated by the second computing unit; The information processing device according to claim 14.

16. a plurality of the first wirings arranged in a first direction and each extending in a second direction intersecting the first direction; the second positive wiring and the second negative wiring are arranged to intersect with the first wirings, the group of arithmetic units is disposed in correspondence with the intersections of the second positive wiring and the second negative wiring with the plurality of first wirings; The information processing device according to claim 14.

17. each of the first computing unit and the second computing unit has a transistor that passes a current corresponding to the multiplication value; The information processing device according to claim 11.

18. the transistor causes a current corresponding to the first modified multiplication value or the second modified multiplication value to flow from the first wiring; The information processing device according to claim 17.

19. 1. A memory system for computing an inner product of a first vector including a plurality of integer elements and a second vector including a plurality of integer elements, comprising: a first positive wiring that, when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or greater than zero, passes a current according to the multiplication value; a first negative wiring that, when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or less than zero, passes a current according to the multiplication value; a second positive wiring that is activated when an integer element of the first vector is positive; a second negative wiring that is activated when an integer element of the first vector is negative; a first computing unit connected to the first positive wiring and the second positive wiring, for causing a current to flow through the first positive wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or greater than zero; a second computing unit connected to the first negative wiring and the second positive wiring, for causing a current to flow through the first negative wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or less than zero; a third computing unit connected to the first positive wiring and the second negative wiring, and configured to cause a current to flow through the first positive wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or greater than zero; a fourth computing unit connected to the first negative wiring and the second negative wiring, which causes a current to flow through the first negative wiring when a multiplication value of corresponding integer elements of the first vector and the second vector is equal to or less than zero; A fifth calculator that calculates the voltage or current of the first positive wiring and the first negative wiring. Memory system.

20. 1. A memory system for computing an inner product of a first vector including a plurality of integer elements and a second vector including a plurality of integer elements, comprising: a first wiring that passes a current according to a multiplication value of corresponding integer elements of the first vector and the second vector; a second positive wiring that is activated when an integer element of the second vector is positive; a second negative wiring that is activated when an integer element of the second vector is negative; a first computing unit that is connected to the first wiring and the second positive wiring and that flows a current to the first wiring according to a first corrected multiplication value that is corrected so that a multiplication value of corresponding integer elements of the first vector and the second vector becomes a value equal to or greater than zero; a second computing unit that is connected to the first wiring and the second negative wiring and that flows a current to the first wiring according to a second corrected multiplication value that is corrected so that a multiplication value of corresponding integer elements of the first vector and the second vector becomes a value equal to or greater than zero; a wiring voltage correction unit that corrects a voltage corresponding to a corresponding integer element of the second vector based on the first correction multiplication value and the second correction multiplication value; the first computing unit causes a current corresponding to the first corrected multiplication value to flow through the first wiring using the voltage corrected by the wiring voltage correcting unit; the second computing unit causes a current corresponding to the second corrected multiplication value to flow through the first wiring by using the voltage corrected by the wiring voltage correcting unit; Memory system.

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