Substrate parasite reduction technique

Abstract

To provide a protection circuit for DC power circuits for use in automotive or industrial high-power integrated circuits equipped with reverse battery protection and reverse current protection.SOLUTION: The protection circuit prevents formation of parasitic devices that may cause the high-power integrated circuit to malfunction or fail to turn on. The protection circuit is characterized by asynchronous operation of a pair of MOSFETs coupled between a power supply and a load. The protection circuit can be engaged at start-up or in response to transient conditions associated with a fault.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This patent application claims the benefit of U.S. patent application Ser. No. 18 / 461,781, entitled "Substrate Parasitic Reduction Technique," filed Sep. 6, 2023, the entire contents of which are incorporated by reference herein.

[0002] This disclosure relates to preventing the formation of parasitic devices in power supply integrated circuits, and more particularly, to implementing a protection circuit for preventing parasitic interference in power supply integrated circuits that features reverse battery protection and reverse current protection. [Background technology]

[0003] A semiconductor device assembly, e.g., a chip assembly, may be implemented using one or more semiconductor dies including direct current (DC) power integrated circuits, e.g., e-fuses, DC-DC converters, and load switches. The power transistors may include, e.g., insulated-gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), double-diffused metal oxide semiconductor (DMOS) devices, and the like. Fast recovery diodes (FRDs) may be used in conjunction with the power transistors. Such high power chip assemblies may be used in a variety of applications, such as electric vehicles (EVs), hybrid electric vehicles (HEVs), and industrial applications. Summary of the Invention

[0004] In some aspects, the techniques described herein relate to an apparatus including: a power supply terminal configured to receive a voltage supply for a circuit; a load terminal configured to be coupled to a load driven by the circuit; and a first metal-oxide-semiconductor field effect transistor (MOSFET) and a second MOSFET coupled in series between the power supply terminal and the load terminal, the first MOSFET and the second MOSFET configured to switch on and off asynchronously.

[0005] In some aspects, the techniques described herein relate to an apparatus, further comprising a first charge pump coupled between the source terminal and the gate terminal of the first MOSFET.

[0006] In some aspects, the techniques described herein relate to an apparatus, wherein a first charge pump is configured to lower an on-resistance of a first MOSFET.

[0007] In some aspects, the techniques described herein relate to an apparatus further including a second charge pump coupled between the source and gate terminals of the second MOSFET.

[0008] In some aspects, the techniques described herein relate to an apparatus, where a first charge pump has a first clock input and a second charge pump has a second clock input, and operation of the apparatus includes running the first clock input at a higher frequency than the second clock input.

[0009] In some aspects, the techniques described herein relate to an apparatus further including a first diode between the source and drain terminals of the first MOSFET.

[0010] In some aspects, the techniques described herein relate to an apparatus further including a second diode between the source and drain terminals of the second MOSFET.

[0011] In some aspects, the techniques described herein relate to an apparatus, where the first MOSFET protects a load from discharging to a supply voltage when the first MOSFET and the second MOSFET are both off.

[0012] In some aspects, the techniques described herein relate to an apparatus, where a first MOSFET and a second MOSFET are configured to be shut off at different times.

[0013] In some aspects, the techniques described herein relate to an apparatus, where operation of the circuit includes turning on a first MOSFET before turning on a second MOSFET.

[0014] In some aspects, the techniques described herein relate to a method that includes providing reverse battery protection to a power supply integrated circuit (IC) by a protection circuit when a reverse connection from the power supply IC to a power supply and ground occurs; providing reverse current protection to the power supply IC when a reverse flow of current occurs between the power supply and an output of the protection circuit; and preventing formation of a parasitic device between the power supply and an internal ground.

[0015] In some aspects, the techniques described herein relate to a method, wherein the parasitic device is a bipolar junction transistor.

[0016] In some aspects, the techniques described herein relate to a method, where coupling the protection device includes coupling a first metal-oxide-semiconductor field effect transistor (MOSFET) and coupling a second MOSFET, the protection device further configured to provide reverse current protection to the power supply IC by operating the first MOSFET before operating the second MOSFET.

[0017] In some aspects, techniques described herein relate to a method, where actuating a second MOSFET is delayed relative to actuating a first MOSFET by coupling a second clock signal to the second MOSFET, the second clock signal having a lower frequency than a first clock signal coupled to the first MOSFET.

[0018] In some aspects, techniques described herein relate to a method, further including coupling an RC delay network to the second MOSFET to delay actuating the second MOSFET relative to actuating the first MOSFET.

[0019] In some aspects, the techniques described herein relate to a method, where coupling the protection device includes engaging the protection device during start-up of the power IC.

[0020] In some aspects, the techniques described herein relate to a method, where coupling the protection device includes engaging the protection device during a transition state of the power IC.

[0021] In some aspects, the techniques described herein relate to a circuit including a power supply terminal and a load terminal and a protection device coupled between the power supply terminal and the load terminal, the protection device configured to provide reverse battery protection and reverse current protection and prevent formation of parasitic paths by asynchronously operating a first MOSFET and a second MOSFET.

[0022] In some aspects, the techniques described herein relate to a circuit, where forming a parasitic path includes forming a bipolar junction transistor.

[0023] In some aspects, the techniques described herein relate to a circuit, where a protection device enables the circuit to operate at a higher temperature. [Brief description of the drawings]

[0024] [Figure 1]FIG. 1 is a circuit diagram of a power supply IC including a protection circuit according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a timing diagram illustrating a generalized asynchronous gate drive according to an implementation of the present disclosure. [Diagram 3] FIG. 1 is a circuit diagram of a power supply IC with a protection circuit according to an embodiment of the present disclosure. [Figure 4] FIG. 13 is a timing diagram for an example of an asynchronous gate drive at start-up in a first operating mode in accordance with an implementation of the present disclosure. [Diagram 5] FIG. 13 is a timing diagram for an example of an asynchronous gate drive at start-up in a second operating mode in accordance with an implementation of the present disclosure. [Figure 6] FIG. 11 is a timing diagram illustrating an asynchronous gate drive response to a fault mode in accordance with an implementation of the present disclosure. [Figure 7] FIG. 11 is a timing diagram illustrating an asynchronous gate drive response to a fault mode in accordance with an implementation of the present disclosure. [Figure 8] FIG. 1 is a flow diagram illustrating a method for preventing formation of parasitic devices in a protection circuit in accordance with an implementation of the present disclosure.

[0025] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to practice in the industry, the various features in the drawings are not necessarily drawn to scale. Dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. In the drawings, the same reference numbers in different figures may indicate the same and / or similar components (elements, structures, etc.). The drawings generally illustrate various implementations discussed in the present disclosure by way of example, and not by way of limitation. A reference number shown in one drawing may not be repeated for the same and / or similar elements in related figures. A reference number that is repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but is provided for the context between the related figures. Also, when multiple examples of an element are shown, not all the same elements in the drawings are specifically referred to by one reference number. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Safety and reliability of high power electronic devices used in electric vehicles are important concerns. DC power supply circuits can include safety features such as reverse battery protection or reverse current protection. Reverse battery protection prevents users from accidentally connecting a battery by tying the supply side of the circuit to ground and the ground side of the circuit to the power source. Reverse current protection guards against external conditions that would cause current to flow from the output to the power source instead of from the power source to the output. Such external conditions may include, for example, a large capacitance at the output or a sudden voltage drop on the power source.

[0027] When both reverse battery protection and reverse current protection functions coexist within an integrated circuit (IC), parasitic path interactions may occur during start-up or other transition states. ICs with floating substrates that may be dynamically biased are prone to the formation of additional parasitic latches that interact with parasitics associated with the power MOSFETs of the IC. In some instances, parasitic interactions may prevent the chip from turning on or may cause malfunctions or deviations from normal circuit behavior. The present disclosure relates to implementations of power supply integrated circuits that can mitigate parasitic interference and prevent such errors from occurring without adding design complexity and without incurring a penalty for increased circuit area within the chip. Providing such a preventative measure may provide a competitive advantage to certain suppliers of power supply ICs over power supply ICs that do not address parasitic interference. Compensating for usage errors may result in the prevention of unnecessary overloads of the external power supply (VIN) even if the part does not include reverse battery protection, but only reverse current protection. Compensating for usage errors may result in higher grade ICs that are more likely to be included in automotive designs.

[0028] In some implementations, the protection circuit includes an additional MOSFET coupled between the power supply and the load to provide reverse current protection. However, in some implementations, one or both of the MOSFETs contribute to the formation of a parasitic device, e.g., a parasitic bipolar junction transistor (BJT). In some implementations, a solution to the parasitic interference includes operating the two MOSFETs asynchronously. In some implementations, a solution to the parasitic interference includes operating the additional MOSFET before operating the existing MOSFET. In some implementations, the protection circuit can prevent the parasitic device from discharging the power supply to an internal ground. In some implementations, the asynchronous operation of the two MOSFETs can be achieved by operating the MOSFETs using different clock signals at different frequencies. In some implementations, the protection circuit can be engaged during start-up of the power supply integrated circuit. In some implementations, the protection circuit can be engaged during a transition state of the power supply integrated circuit.

[0029] 1 is a circuit diagram of a power supply integrated circuit 100 with a protection circuit 101 according to a first implementation of the present disclosure. The power supply integrated circuit 100 includes a power supply 102, e.g., a battery, an input voltage VIN, a load 104 at an output VOUT, and a protection circuit 101 coupled between the power supply 102 and the load 104 to protect the load 104 from unexpected high current or high voltage. In some implementations, the load 104 is connected to a load resistor R L and the load capacitor C L 1 may be an RC stage in which external ground 105 and internal ground 106 are coupled in parallel. The load 104 shown in FIG. 1 represents a generic load. That is, load 104 may be any type of load powered by power supply 102. Load 104 is coupled to an external ground 105. Under certain circumstances, a connection to internal ground 106 may be made when power supply integrated circuit 100 creates a parasitic path to ground. One or both of external ground 105 and internal ground 106 may be provided by a substrate underlying power supply integrated circuit 100, such as a silicon substrate.

[0030] In some implementations, the protection circuit 101 includes a first MOSFET M1 and a second MOSFET M2, each having a gate terminal G, a source terminal S, and a drain terminal D. In some implementations, the drain terminals of the two MOSFETs are connected at a node having a voltage level VMID. The first MOSFET M1 may be controlled via a gate signal GATE1 by a first charge pump 110a driven by a first clock signal CLK1, and the second MOSFET M2 may be controlled via a gate signal GATE2 by a second charge pump 110b driven by a second clock signal CLK2. In some implementations, the first charge pump 110a is coupled to the gate and source terminals of the first MOSFET M1, and the second charge pump 110b is coupled to the gate and source terminals of the second MOSFET M2. The first charge pump 110a provides charge to the gate of the first MOSFET M1 to lower the on-resistance RDSON to turn on the first MOSFET M1. The first charge pump 110a and the second charge pump 110b may be further controlled by one or more enable signals. In the implementation shown in Figure 1, both the first charge pump 110a and the second charge pump 110b are controlled by a common enable signal EN.

[0031] In some implementations, a first body diode D1 is present between the source and drain terminals of the first MOSFET M1, and a second body diode D2 is present between the source and drain terminals of the second MOSFET M2. The first body diode D1 provides reverse current protection by preventing the load 104 from discharging into the power supply 102 when the first MOSFET M1 and the second MOSFET M2 are off. That is, the first body diode D1 allows current flow away from the power supply 102 while blocking current flow toward the power supply 102.

[0032] In some implementations, a parasitic device 108, for example, a parasitic current path to the internal ground 106 may be formed adjacent to the first body diode D1 and the second body diode D2 with the substrate. In some implementations, the parasitic device may include one or more parasitic body diodes and other diodes. In some implementations, the parasitic device may include a PNP BJT transistor. Under certain conditions, if the voltage drop from VIN to VMID is high enough to pass excessive current through the first body diode D1, the parasitic BJT may act as an alternative current path and discharge the excessive current to the substrate. Actuating the parasitic BJT may trigger a series of actions that randomly prevent the start-up of the power supply integrated circuit 100 or may cause the start-up of the power supply integrated circuit 100 to become unstable. Conditions that may result in a large voltage drop in VMID include partial actuation or turn-on of MOSFETs M1 and M2, resulting in a high resistance across the transistors that may shift VMID relative to VIN.

[0033] The protection circuit 101 is designed to prevent the formation of parasitic device 108 by controlling the timing of the operation of the first MOSFET M1 relative to the operation of the second MOSFET M2. For example, the formation of parasitic device 108 may be prevented by activating the first MOSFET M1 via gate signal GATE1 before and / or for a longer duration than activating the second MOSFET M2 via gate signal GATE2, as shown in FIG.

[0034] FIG. 2 shows a timing diagram 200 illustrating an asynchronous gate drive according to some implementations of the present disclosure. FIG. 2 shows the time relationship between two signals of the power supply integrated circuit 300, namely, the gate signal GATE1 and the gate signal GATE2. When the gate signal GATE1 is high, the first MOSFET M1 is in an "on" state. When the gate signal GATE2 is high, the second MOSFET M2 is in an "on" state. By turning on (e.g., switching) the first MOSFET M1 before turning on (e.g., switching) the second MOSFET M2 and by turning off (e.g., switching) the second MOSFET M2 before turning off (e.g., switching) the first MOSFET M1, the formation of the parasitic device 108 can be prevented by ensuring that the first body diode D1 is bypassed, i.e., by providing an alternative current path to the first body diode D1. In some implementations, if power is not a limitation, the second MOSFET M2 can be turned off while the first MOSFET M1 remains on indefinitely. By maintaining these relationships between the first MOSFET M1 and the second MOSFET M2, the power supply integrated circuit 100 allows the reverse battery protection function and the reverse current protection function to coexist. Maintaining an actuation sequence that avoids triggering the formation of the parasitic device 108 can be achieved by asynchronous operation of the first MOSFET M1 and the second MOSFET M2. The use of asynchronous gate drive prevents a condition in which both MOSFETs M1 and M2 are partially on. Thus, the current flow in the output path is constrained at start-up, so that VMID does not drop low enough to trigger the parasitic device 108. The use of asynchronous gate drive ensures a normal start-up and also prevents unnecessary overloading of VIN.

[0035] There are several strategies that can be used to achieve asynchronous gate drive. In some implementations, for example, as shown in FIG. 1, a first delay device 112a can be inserted between the first charge pump 110a and the gate terminal of the first MOSFET M1, and / or a second delay device 112b can be coupled between the enable signal EN and the second charge pump 110b to delay the charging of the second MOSFET M2. By adjusting the relative delays introduced by the first delay device 112a and the second delay device 112b, the first MOSFET M1 and the second MOSFET M2 can be switched on and / or off asynchronously. For example, the first MOSFET M1 can be switched on at a first time, and the second MOSFET M2 can be switched on or off at a second time after the first time. As another example, the first MOSFET M1 may be switched on or off at a first time, the second MOSFET M2 may be switched on a second time after the first time, and the second MOSFET M2 may be switched off a third time after the second time and before switching the first MOSFET M1 again. One or both of the first delay device 112a and the second delay device 112b may be implemented as an RC network.

[0036] Additionally or alternatively, a first enable signal EN1 and a separate second enable signal EN2 may be used in conjunction with a common clock signal to asynchronously switch on and / or off the first MOSFET M1 and the second MOSFET M2. The enable signals enable activation of the corresponding gate signals at the rising edge of the next clock pulse. In some implementations, the first enable signal EN1 may be set to transition before the second enable signal EN2, thus creating a turn-on delay in the second MOSFET M2. The turn-off delay of MOSFET M1 may be determined by V IN This can be achieved by delaying the disable signal of the first charge pump 110a associated with such an implementation, which is described below with reference to FIGS.

[0037] Additionally or alternatively, the first clock signal CLK1 and the second clock signal CLK2 can be set to different frequencies, resulting in the first MOSFET M1 and the second MOSFET M2 operating asynchronously. In some implementations, the first clock signal CLK1 can be set to run at a higher frequency than the second clock signal CLK2, thus causing a turn-on delay in the second MOSFET M2. The turn-off delay of MOSFET M1 is determined by V IN This can be achieved by delaying the disable signal of the first charge pump 110a associated with the first charge pump 110b. If two separate clock signals are used, a common enable signal can be used. Such an implementation is described below with reference to Figures 3 and 5.

[0038] 3 is a circuit diagram of a power supply integrated circuit 300 with a protection circuit 301 according to a second implementation of the present disclosure. The protection circuit 301 can be used to prevent the formation of a parasitic device 108. The power supply integrated circuit 300 is similar to the power supply integrated circuit 100, except that a separate enable signal EN2 replaces the delayed enable signal EN1 generated by the second delay device 112b as an input to the second charge pump 110b. The protection circuit 301 can be configured to control the MOSFETs by a separate enable signal (FIG. 4) and / or a separate clock signal (FIG. 5).

[0039] Figure 4 shows a timing diagram 400 illustrating a first mode of operating the power supply integrated circuit 300 shown in Figure 3 according to some implementations of the present disclosure. Figure 4 shows the time relationships of five signals at the start-up of the power supply integrated circuit 300: a first enable signal EN1, a second enable signal EN2, a common clock signal CLK1=CLK2, a gate signal GATE1 driving the first MOSFET M1, and a gate signal GATE2 driving the second MOSFET M2. Figure 4 shows the use of a protection circuit 301 to achieve asynchronous gate drive, where the clock signals CLK1 and CLK2 shown in Figure 3 are coupled together such that they are substantially identical, and the enable signal EN2 is delayed with respect to the enable signal EN1.

[0040] As shown in FIG. 4, at time t0, the enable signal EN1 transitions from low to high. The transition of the enable signal EN1 initiates a rising edge of the gate signal GATE1 at the next clock pulse, which turns on the first MOSFET M1 at t1. In some implementations, the first MOSFET is fully on at time t2, at least one more clock pulse later. Meanwhile, the second MOSFET M2 is still off. Then, at time t3, after the first MOSFET M1 is fully on, the enable signal EN2 is set to transition from low to high. The transition of the enable signal EN2 initiates a rising edge of the gate signal GATE2 at the next clock pulse, which turns on the second MOSFET M2 at t4. In some implementations, the second MOSFET M2 is fully on at time t5, at least one more clock pulse later.

[0041] By the time the second gate signal GATE2 begins to ramp up, the first gate signal GATE1 is already fully on, so neither the gate signal GATE1 nor the gate signal GATE2 have had time to transition while connected to the load. The two MOSFETs are not on at the same time, nor do they overlap in their turn-on transitions. By staggering the turn-on times of MOSFETS M1 and M2 in this manner, VMID is maintained at a high level, e.g., 1 VF below VIN, thereby limiting the peak current flow through the parasitic transistor, thus preventing parasitic action.

[0042] Fig. 5 shows a timing diagram 500 illustrating a second mode of operating the power supply integrated circuit 300 shown in Fig. 3 according to some implementations of the present disclosure. Fig. 5 shows the time relationships among five signals at the start-up of the power supply integrated circuit 300 according to a third implementation of the present disclosure: a common enable signal EN1=EN2, a clock signal CLK1, a clock signal CLK2, a gate signal GATE1 driving the first MOSFET M1, and a gate signal GATE2 driving the second MOSFET M2. Fig. 5 shows the use of the power supply integrated circuit 300 to achieve asynchronous gate drive, where the enable signals EN1 and EN2 are coupled together such that they are substantially identical, and the clock signals CLK1 and CLK2 have different frequencies.

[0043] As shown in FIG. 5, the enable signals EN1 and EN2 both transition from low to high at time t0, which coincides with the middle of the second clock pulse of the clock signal CLK1 as a random example. The transition of the enable signals EN1 and EN2 enables the next clock pulse of the clock signal CLK1 to start the rising edge of the gate signal GATE1, which turns on the first MOSFET M1 at time t1. At the same time t0, the enable signals EN1 and EN2 also enable the next clock pulse of the clock signal CLK2 to start the rising edge of the gate signal GATE2, which turns on the second MOSFET M2 at time t2. However, due to the frequency difference, the clock period of the second clock signal CLK2 is longer. This delays the charge pump settling time for the gate signal GATE2. Therefore, the gate signal GATE2 takes several clock pulses to rise. Meanwhile, the gate signal GATE1 is already fully on. Therefore, again, there is no time for both the gate signals GATE1 and GATE2 to transition while they are connected to the load. As a result, VMID is maintained at a high level, for example 1 VF below VIN, preventing parasitic action.

[0044] The frequencies of the clock signals CLK1 and CLK2 may be selected during the design stage to be sufficiently different to ensure that the gate signal GATE1 is fully on before the gate signal GATE2 begins to transition. Again, the two MOSFETs M1 and M2 are configured to provide protection against parasitic action since they do not turn on at the same time or have a time overlap in their turn-on transitions. In contrast, an unprotected circuit may be realized by using a shared clock signal and a shared enable signal that are both used to operate both MOSFETs simultaneously.

[0045] FIG. 6 is a timing diagram 600 corresponding to a mode of operating the power supply integrated circuit 300 shown in FIG. 3 according to some implementations of the present disclosure. The timing diagram 600 shows seven signals responsive to a fault, such as a short circuit to ground or a circuit breaker event, namely, the output voltage VOUT, the load current ILOAD, the source voltage VIN, VMID, the gate signal GATE1 driving the first MOSFET M1, the gate signal GATE2 driving the second MOSFET M2, and the parasitic current IPNP associated with the parasitic device 108. The circuit breaker event may cause a large current to flow through the two series MOSFETs. When a fault is detected, if the first MOSFET M1 and the second MOSFET M2 are cut off simultaneously, during the transition from the on state to the off state, both the first MOSFET M1 and the second MOSFET M2 become high resistance, turning on both body diodes D1, D2. However, if the first MOSFET M1 is still on while the second MOSFET M2 is cut off, the on resistance of the first MOSFET M1 is still low, suppressing the voltage across the body diode D1. Such an event that grounds the output voltage causes a spike in the load current, as shown in the top graph of Figure 6. In response, VMID drops as current flows out. However, because the gate signal GATE1 is delayed, only the second MOSFET M2 turns off, while the first MOSFET continues to provide reverse current protection that reduces voltage droop in VMID. Thus, a parasitic device is formed, but the parasitic current IPNP is small compared to the load current ILOAD and is small compared to a circuit in which both MOSFETs are turned off without delay.

[0046] FIG. 7 is a timing diagram 700 corresponding to a mode of operating the power supply integrated circuit 300 shown in FIG. 3 according to some implementations of the present disclosure. The timing diagram 700 shows two signals, namely, the output voltage VOUT and the output current IOUT, in response to a fault, such as a short circuit to ground or a circuit breaker event. FIG. 7 shows how the architecture of the protection circuit 301 avoids malfunctions when a short circuit occurs or the circuit activates. When a current flows into the substrate through the parasitic device 108, it may cause an undesirable load of the supply voltage VIN, which may trigger a protection device, such as an electronic fuse (e-fuse), designed to latch off, i.e., permanently cut off, the output voltage and current in response to an event. When the parasitic device 108 is formed, the latch-off function is incomplete and the VOUT and IOUT signals may not remain at zero but may exhibit transient variations. By suppressing the parasitic device, the protection circuit 301 ensures that the latch-off is effective in keeping the VOUT and IOUT signals in an off state, as shown in the timing diagram 700.

[0047] FIG. 8 is a flow diagram summarizing a method 800 for protecting a power supply IC according to some implementations of the present disclosure. The protection of a power supply IC, such as the power supply integrated circuit 100 or the power supply integrated circuit 300, prevents triggering the formation of a parasitic device. Operations 802-810 of the method 800 may be performed to form the power supply integrated circuit 100 according to some implementations as described above with reference to FIGS. 1-7. The operations of the method 800 may be performed in a different order or not depending on a particular application. It should be noted that the method 800 may not produce a complete power supply integrated circuit 100. Therefore, it should be understood that additional processes may be provided before, during, or after the method 800, and some of these additional processes may be briefly described herein.

[0048] At 802, the method 800 includes inserting a protection circuit, e.g., protection circuit 101 or protection circuit 301, in a power supply IC, e.g., power supply integrated circuit 100 or power supply integrated circuit 300, between a power supply voltage, e.g., power supply 102 (VIN), and an external load, e.g., load 104, where the protection circuit 101 or 103 includes two MOSFETs, e.g., a first MOSFET M1 and a second MOSFET M2. The protection circuit may be inserted in any power supply IC to protect against a power-to-ground condition or a circuit breaker event. In some implementations, the two MOSFETs are coupled in series between the power supply 102 and the load 104, and the first MOSFET is coupled between the power supply 102 and the second MOSFET. In a normal state, both the first MOSFET M1 and the second MOSFET M2 are in an "on" state.

[0049] At 804, the method 800 includes providing reverse current protection to the power supply IC. In some implementations, the reverse current protection may be provided by a first MOSFET M1 and a second MOSFET M2 coupled in series as shown in FIG. 1 or operating asynchronously as shown in FIG. 2. In some implementations, the reverse current protection may be provided by a first MOSFET M1 and a second MOSFET M2 coupled in series as shown in FIG. 3 or operating asynchronously as shown in FIG. 4, FIG. 5, or FIG. 6.

[0050] At 806, the method 800 includes providing a reverse battery protection circuit to the power supply IC. In some implementations, the reverse battery protection circuit may introduce additional parasitic devices that interact with the parasitic devices of the first MOSFET M1 and the second MOSFET M2 of the reverse current protection circuit. When the disclosed circuits and methods are implemented as described herein, the effects of such interactions between the parasitic devices may be mitigated, making the power supply IC robust in its start-up and overload operation.

[0051] At 808, the method 800 includes operating the two MOSFETs asynchronously to prevent the formation of parasitic devices. Asynchronous operation may be achieved by operating the first MOSFET M1 and the second MOSFET M2 at different times. During a start-up phase, the first MOSFET M1 may be turned on before the second MOSFET M2 is turned on, and in particular may wait until the first MOSFET M1 is fully on before the second MOSFET M2 starts to turn on, such that neither of the MOSFETs is partially on during connection to the load 104. In response to a circuit breaker event, operation of the first MOSFET M1 may be continued while the second MOSFET M2 is turned off to keep the resistance across the diode low, thereby inhibiting the formation of parasitic devices. One method of asynchronous operation includes using a common clock signal with staggered enable signals for the two MOSFETs, as shown and described with respect to FIG. 4. Another method of asynchronous operation includes using different clock signals to control each MOSFET, e.g., by clock signals of different frequencies, as shown and described with respect to FIG. 5. Another method of asynchronous operation involves inserting one or more delay devices in front of the gate drive signals of the two MOSFETs, as shown and described with respect to FIG.

[0052] By preventing the formation of parasitic devices, the asynchronous operation of the MOSFETs extends the temperature range of the protection circuit; that is, the parasitic devices do not activate until a higher temperature is reached. With protection circuit 101 or protection circuit 301 in place, the parasitic devices can withstand a higher load at a given temperature without turning on. Thus, the protection devices allow the circuit to operate at a higher temperature, thereby increasing the temperature margin of power supply integrated circuit 100.

[0053] As mentioned above, various implementations of protection circuits employing asynchronous gate drives can suppress the formation of parasitic devices that could otherwise cause malfunction of the power supply IC. In particular, the risk of parasitic interactions is relevant when both reverse battery protection and reverse current protection are provided by the protection circuit. Various implementations of asynchronous gate drives are described with reference to signal timing diagrams during start-up and in response to faults.

[0054] In the foregoing description, when an element, such as a layer, region, or substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it will be understood that it can be directly disposed on, connected to, or coupled to the other element, or that one or more intervening elements may be present. On the other hand, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, no intervening elements or layers are present. Throughout the detailed description of the present invention, the terms directly, directly connected, or directly coupled may not be used, but elements illustrated as being directly, directly connected, or directly coupled may be referred to as such. The claims of this application may be amended to describe the exemplary relationships described herein or shown in the figures.

[0055] As used herein, the singular can include the plural, unless in view of the context a specific instance clearly indicates. Spatially relative terms (e.g., throughout, above, above, below, lower, below, lower, top, bottom, etc.) are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

[0056] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including, but not limited to, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and / or others.

[0057] While certain features of the described implementations have been illustrated as described herein, those skilled in the art will now recognize numerous modifications, substitutions, changes, and equivalents. For example, features illustrated with respect to one implementation may be included in other implementations as appropriate. It will therefore be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It will be understood that these are presented by way of example only, and not by way of limitation, and that various changes in form and detail may be made. Any part of the apparatus and / or method described herein may be combined in any combination, except in mutually exclusive combinations. The implementations described herein may include various combinations and / or subcombinations of features, components and / or features of the different implementations described.

Claims

1. 1. An apparatus comprising: a power supply terminal configured to receive a voltage supply for the circuit; a load terminal configured to be coupled to a load driven by the circuit; a first metal-oxide-semiconductor field effect transistor (first MOSFET) and a second MOSFET coupled in series between the power supply terminal and the load terminal, the first MOSFET and the second MOSFET configured to switch on and off asynchronously.

2. a first diode between the source and drain terminals of the first MOSFET and a second diode between the source and drain terminals of the second MOSFET; or a first charge pump coupled between a source terminal and a gate terminal of the first MOSFET, the first charge pump configured to lower an on-resistance of the first MOSFET, and a second charge pump coupled between a source terminal and a gate terminal of the second MOSFET; 2. The apparatus of claim 1, wherein the first charge pump has a first clock input and the second charge pump has a second clock input, and operation of the apparatus includes running the first clock input at a higher frequency than the second clock input.

3. the first MOSFET and the second MOSFET are configured to be turned off at different times; or operating the circuit includes turning on the first MOSFET before turning on the second MOSFET; or 2. The apparatus of claim 1, wherein the first MOSFET protects the load from discharging into the voltage source when the first MOSFET and the second MOSFET are both off.

4. 1. A method comprising: providing reverse battery protection to a power supply integrated circuit (power supply IC) by a protection circuit when a reverse connection from the power supply IC to a power supply and ground is made; providing reverse current protection to the power supply IC when a reverse current occurs between the power supply and an output of the protection circuit; preventing formation of parasitic devices between the power supply and an internal ground; the parasitic device is a bipolar junction transistor; or Coupling the protection circuitry includes engaging the protection circuitry during start-up of the power IC or during a transient state of the power IC; or coupling the protection circuit includes coupling a first metal oxide semiconductor field effect transistor (first MOSFET) and coupling a second MOSFET, the protection circuit being further configured to provide reverse current protection to the power supply IC by activating the first MOSFET before activating the second MOSFET; wherein the actuating of the second MOSFET is delayed relative to the actuating of the first MOSFET by coupling a second clock signal to the second MOSFET having a lower frequency than a first clock signal coupled to the first MOSFET, or by coupling an RC delay network to the second MOSFET.

5. 1. A circuit comprising: A power terminal, The load terminals, a protection device coupled between the power supply terminal and the load terminal, the protection device configured to provide reverse battery protection and reverse current protection and prevent formation of parasitic paths by operating a first MOSFET and a second MOSFET asynchronously; forming the parasitic path includes forming a bipolar junction transistor; or The circuit, wherein the protection device allows the circuit to operate at a higher temperature.

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