Voltage pulse time-domain multiplexing

Abstract

To provide an apparatus, a plasma processing system, and a method for generation of a waveform for plasma processing of a substrate in a processing chamber.SOLUTION: A processing system includes a waveform generator 400 having a voltage source circuitry 410, a first switch S1 that is coupled between the voltage source circuitry and a first output node 402 of the waveform generator and is coupled to a chamber 100 through the first output node, and a second switch S3 coupled between the first output node and an electrical ground node. The waveform generator also includes a third switch S2 that is coupled between the voltage source circuitry and a second output node 404 of the waveform generator and is coupled to the chamber through the second output node, and a fourth switch S4 coupled between the second output node and the electrical ground node.SELECTED DRAWING: Figure 4A

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to systems used in semiconductor device manufacturing. In particular, embodiments of the present disclosure relate to plasma processing systems used to process substrates. [Background technology]

[0002]

[0002] Reliably producing high aspect ratio features is one of the key technological challenges for next generation semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process to bombard material formed on the surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003]

[0003] As technology nodes progress toward 2 nm, the fabrication of smaller features with higher aspect ratios requires atomic precision for plasma processing. For the development of reliable and repeatable device formation processes in the semiconductor equipment industry, ion energy control has always been difficult in etching processes in which plasma ions play a major role. In a typical plasma-assisted etching process, a substrate is placed on an electrostatic chuck (ESC) located in a processing chamber, a plasma is generated above the substrate, and ions are accelerated from the plasma across a plasma sheath (i.e., an electron-depleted region generated between the plasma and the surface of the substrate) toward the substrate. Conventional RF substrate biasing methods that use sinusoidal RF waveforms to excite the plasma and generate the plasma sheath have not been able to desirably generate these smaller device feature sizes. Recently, it has been discovered that the supply of high-voltage pulses to one or more electrodes in a processing chamber can be useful in desirably controlling the plasma sheath generated above the surface of the substrate. However, it is difficult to generate high-voltage pulses at medium to high frequencies. Such pulses can be particularly difficult to generate using standard electrical components due to heating of the switching components used to generate the high-voltage pulses.

[0004]

[0004] Therefore, there is a need in the art for a pulsed voltage supply and biasing method that enables the completion of a desired plasma-assisted process on a substrate. Summary of the Invention

[0005]

[0005] Embodiments provided herein broadly include an apparatus, plasma processing system, and method for generating a waveform for plasma processing of a substrate in a processing chamber.

[0006] One embodiment of the present disclosure is directed to a waveform generator for plasma processing, the waveform generator generally including a voltage source circuit, a first switch coupled between the voltage source circuit and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber, a second switch coupled between the first output node and an electrical ground node, a third switch coupled between the voltage source circuit and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber, and a fourth switch coupled between the second output node and an electrical ground node.

[0007] One embodiment of the present disclosure is directed to a method for waveform generation that generally includes coupling a voltage source circuit via a first switch to a first output node of a waveform generator, the first output node being coupled to a chamber, coupling the first output node via a second switch to an electrical ground node, coupling the voltage source circuit via a third switch to a second output node of the waveform generator, the second output node being coupled to the chamber, and coupling the second output node via a fourth switch to the electrical ground node.

[0008]

[0008] One embodiment of the present disclosure is directed to an apparatus for waveform generation. The apparatus generally includes a voltage source circuit, one or more switches coupled to the voltage source circuit, and a controller configured to control the one or more switches. The one or more switches include a first switch coupled between the voltage source circuit and a first output node of a waveform generator, the first output node being configured to be coupled to the chamber, a second switch coupled between the first output node and an electrical ground node, a third switch coupled between the voltage source circuit and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber, and a fourth switch coupled between the second output node and an electrical ground node.

[0009]

[0009] In order that the above features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate exemplary embodiments, and therefore should not be considered as limiting the scope of the present disclosure, as other equally effective embodiments may be acceptable. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view of a processing system according to one or more embodiments configured to perform the methods described herein. [Figure 2A]

[0011] 4 illustrates a voltage waveform established on a substrate by a voltage waveform applied to an electrode of a processing chamber. [Figure 2B]

[0012] 1 illustrates the effect of increasing plasma density on the voltage waveform established on a substrate by a voltage waveform applied to an electrode in a processing chamber. [Figure 2C]

[0013] FIG. 2C illustrates the effect on ion energy distribution (IED) associated with the effect of increasing plasma density as shown in relation to the voltage waveform of FIG. 2B. [Diagram 3]

[0014] 1 illustrates an example waveform generated using time multiplexing of voltage pulses, in accordance with certain embodiments of the present disclosure. [Figure 4A]

[0015] 1 illustrates an exemplary waveform generator, in accordance with certain embodiments of the present disclosure. [Figure 4B]

[0016] FIG. 4B is a timing diagram illustrating the states of the switches in the waveform generator of FIG. 4A. [Diagram 5]

[0017] 4 illustrates an IED associated with the waveforms shown in FIG. 3 in accordance with certain embodiments of the present disclosure. [Figure 6]

[0018] FIG. 1 is a process flow diagram illustrating a method for waveform generation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0019] Some embodiments of the present disclosure are generally directed to techniques for generating waveforms for controlling ion energy distribution (IED) during plasma processing. For example, a pulsed voltage waveform may be generated by time multiplexing voltage pulses from different sources (e.g., switches) and applied to one or more electrodes in a plasma processing chamber for plasma processing. In some embodiments, the pulsed voltage waveform may be generated using multiple switch pairs, allowing the pulsed voltage waveform to have a higher frequency compared to conventional implementations using a single switch pair. Due to physical and practical device limitations found in current conventional high voltage switching components, the switching speed of these conventional high voltage switches is limited to a "practical maximum switching speed" due to heat generated within the components during use. During a typical plasma processing process, the high voltage pulsed voltage waveform generated by the high voltage switch typically requires the switch to repeatedly perform over the life of the switch-containing device at voltage levels greater than about 200 volts, e.g., greater than about 500 volts, or greater than about 800 volts, or greater than about 1000 volts, or even greater than about 5000 volts. In one embodiment, the maximum practical switching speed of conventional switches, such as metal oxide semiconductor field effect transistors (MOSFETs), is typically limited to about 2.5 microseconds (μs) at switching voltages above about 800 volts. However, the use of higher frequency voltage waveforms can reduce voltage droop during the ion current phase of a voltage pulse used during plasma processing. As a result, narrower IEDs can be achieved, facilitating increased accuracy of plasma processing, as described in more detail herein. As used herein, voltage droop generally refers to the increase in voltage established at an electrode during the negative voltage-containing portion of a voltage pulse.

[0012] Several embodiments of a plasma processing system

[0020] 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma processing. However, it should be noted that the embodiments described herein may also be used with processing systems configured for use in other plasma-assisted processes, such as plasma deposition processes, e.g., plasma enhanced chemical vapor deposition (PECVD) processes, plasma enhanced physical vapor deposition (PEPVD) processes, plasma enhanced atomic layer deposition (PEALD) processes, plasma treatment processes, or plasma-based ion implantation processes (e.g., plasma enhanced doping (PLAD) processes).

[0013]

[0021] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP). In that case, the processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed within the processing space 129. The upper electrode faces a lower electrode (e.g., substrate support assembly 136) also disposed within the processing space 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper or lower electrodes and provides an RF signal configured to ignite and sustain a plasma (e.g., plasma 101). In this configuration, a plasma is capacitively coupled to each of the upper and lower electrodes and is disposed within the processing region therebetween. Typically, the other of the upper or lower electrode is coupled to ground or a second RF power source. In one embodiment, one or more components of the substrate support assembly 136, such as the support base 107, are electrically coupled to a plasma generator assembly 163. The plasma generator assembly 163 includes an RF generator 118, and the chamber lid 123 is electrically coupled to ground. As shown, the processing system 10 includes a processing chamber 100, a support assembly 136, and a system controller 126.

[0014]

[0022] The processing chamber 100 typically includes a chamber body 113. The chamber body 113 includes a chamber lid 123, one or more sidewalls 122, and a chamber base 124, which collectively define a processing space 129. The one or more sidewalls 122 and the chamber base 124 generally include a material sized and shaped to provide structural support for the elements of the processing chamber 100 and configured to withstand pressure and additional energy applied thereto. Meanwhile, the plasma 101 is generated in a reduced pressure environment that is maintained within the processing space 129 of the processing chamber 100 during processing. In one embodiment, the one or more sidewalls 122 and the chamber base 124 are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0015]

[0023] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more process gases to the process space 129 from a process gas source 119 in fluid communication with the process space 129. The substrate 103 is loaded into and removed from the process space 129 through an opening (not shown) in one of the one or more sidewalls 122 that is sealed by a slit valve (not shown) during plasma processing of the substrate 103.

[0016]

[0024] The system controller 126, also referred to herein as a process chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate bias method described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control the process chambers and sub-processors associated with the process chambers. The memory 134 described herein is generally non-volatile memory and may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). The support circuits 135 are conventionally coupled to the CPU 133 and include cache, clock circuits, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor in the CPU 133. The software programs (or computer instructions) readable by the CPU 133 in the system controller 126 specify which operations are executable by the components in the processing system 10.

[0017]

[0025] Typically, the program is readable by the CPU 133 in the system controller 126 and includes code that, when executed by the processor (CPU 133), performs operations associated with the plasma processing schemes described herein. The program may include instructions that are used to control various hardware and electrical components in the processing system 10 to thereby perform various process operations and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions that are used to perform one or more of the operations described below in connection with FIG. 6.

[0018]

[0026] The processing system may include a plasma generator assembly 163, a first PV source assembly 196 for establishing a first pulsed voltage (PV) waveform at the bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform at the edge control electrode 115. The first PV waveform or the second PV waveform may be generated using a waveform generator, as described in more detail herein with respect to FIG. 3, FIG. 4A, and FIG. 4B. In some embodiments, the plasma generator assembly 163 provides an RF signal to the support base 107 (e.g., an electrode or cathode). The support base 107 may be used to generate (sustain and / or ignite) the plasma 101 in a processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to provide an RF signal having a frequency of 1 MHz or more, or about 2 MHz or more, such as about 13.56 MHz or more.

[0019]

[0027] As described above, in some embodiments, the plasma generator assembly 163 includes the RF generator 118 and the RF generator assembly 160 and is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially constant sinusoidal frequency to the support base 107 of the substrate support assembly 136 based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107 disposed proximate to the substrate support 105 and within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain a processing plasma 101 of a processing gas disposed within the process space 129.

[0020]

[0028] In some embodiments, support base 107 is an RF electrode that is electrically coupled to RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, both of which are disposed within RF generator assembly 160. First filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of PV waveform generator 150 from flowing through RF power supply line 167 and damaging RF generator 118. First filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from PV pulse generator P1 in PV waveform generator 150, thus blocking the flow of current to RF matching circuit 162 and RF generator 118.

[0021]

[0029] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and sustain the processing plasma 101 using an electric field generated by the process gas disposed in the process space 129 and RF power (RF signal) provided by the RF generator 118 to the support base 107. The process space 129 is fluidly coupled to one or more dedicated vacuum pumps via a vacuum outlet 120. The one or more dedicated vacuum pumps maintain the process space 129 at sub-atmospheric pressure and evacuate the process gas and / or other gases from the process space 129. In some embodiments, a substrate support assembly 136 disposed in the process space 129 is disposed on a support shaft 138 that is grounded and extends through the chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to provide RF power to a bias electrode 104 disposed in the substrate support 105 relative to the support base 107.

[0022]

[0030] As briefly mentioned above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulator plate 111 and a ground plate 112, as described further below. The support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is interposed between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing.

[0023]

[0031] Typically, the substrate support 105 is formed of a dielectric material (e.g., a bulk sintered ceramic material such as a corrosion resistant metal oxide or metal nitride material), e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded within the dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the process region above the bias electrode 104 are identified and / or monitored by measuring an RF waveform established at the bias electrode 104.

[0024]

[0032] In one configuration, the bias electrode 104 is a chucking pole that is used to secure (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 relative to the processing plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0025]

[0033] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network 116. The clamping network 116 provides a chucking voltage, such as a static DC voltage between about -5000V and about 5000V, to the bias electrode 104 using an electrical conductor, such as a coaxial power supply line 106 (e.g., a coaxial cable). As described further below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply 155, and a bias compensation module blocking capacitor, also referred to herein as blocking capacitor C5. The blocking capacitor C5 is disposed between the output of the pulsed voltage (PV) waveform generator 150 and the bias electrode 104.

[0026]

[0034] The substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is disposed below the edge ring 114, surrounds the bias electrode 104, and / or is disposed at a distance from the center of the bias electrode 104. In general, in a processing chamber 100 configured to process a circuit board, the edge control electrode 115 is ring-shaped, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in FIG. 1, the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 1, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed at a similar distance (i.e., in the Z direction) as the bias electrode 104 from the substrate support surface 105A of the substrate support 105. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed on or within the region of the quartz tube 110. The quartz tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is disposed within or coupled to an edge ring 114 that is disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AlN, etc.).

[0027]

[0035] The edge control electrode 115 can be biased using a different PV waveform generator than the PV waveform generator 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 may be biased using the PV waveform generator 150, which is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, a first PV waveform generator 150 of a first PV source assembly 196 is configured to bias the bias electrode 104, and a second PV waveform generator 150 of a second PV source assembly 197 is configured to bias the edge control electrode 115.

[0028]

[0036] A power supply line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 with the optional filter assembly 151 and the bias electrode 104. The following description primarily discusses the power supply line 157 of the first PV source assembly 196 used to couple the PV waveform generator 150 to the bias electrode 104, but the voltage supply line 158 of the second PV source assembly 197 coupling the PV waveform generator 150 to the edge control electrode 115 will include the same or similar components. The electrical conductor(s) in the various portions of the voltage supply line 157 include one or a combination of the following: (a) a coaxial cable, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) insulated high voltage corona resistant circuit wire; (c) bare wire; (d) metal rods; (e) electrical connectors; or (f) any combination of the electrical elements of (a)-(e). Optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of RF generator 118 from flowing through power supply line 157 and damaging PV waveform generator 150. Optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by RF generator 118, thus blocking the flow of current to PV waveform generator 150.

[0029]

[0037] The second PV source assembly 197 includes a clamping network 116, whereby the bias applied to the edge control electrode 115 can be configured similarly to the bias applied to the bias electrode 104 by the clamping network 116 coupled in the first PV source assembly 196. Applying similarly configured PV waveforms and clamping voltages to the bias electrode 104 and the edge control electrode 115 can help improve the uniformity of the plasma across the surface of the substrate being processed, and therefore improve the results of the plasma treatment process.

[0030]

[0038] In some embodiments, the process chamber 100 further includes a quartz tube 110 or collar that at least partially circumscribes portions of the substrate support assembly 136 to prevent the substrate support 105 and / or support base 107 from contacting corrosive process gases or plasmas, cleaning gases or plasmas, or by-products thereof. Typically, the quartz tube 110, the insulator plate 111, and the ground plate 112 are circumscribed by a liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma generation in a space below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0031]

[0039] FIG. 2A illustrates an exemplary voltage waveform 200 established at a substrate in a processing chamber (e.g., processing chamber 100). In this example, the waveform 200 is generated by application of a waveform by the PV waveform generator 150 of the first PV source assembly 196. The waveform 200 includes an ion current phase and a sheath collapse phase, as shown. At the beginning of the ion current phase, a drop in the substrate voltage generated by a falling edge 204 creates a high voltage sheath that forms above the substrate, accelerating positive ions to the substrate. Positive ions that strike the surface of the substrate during the ion current phase deposit a positive charge on the substrate surface that, if not compensated for, will gradually increase the substrate voltage in a positive direction (i.e., a positive slope during phase 205 of the voltage waveform 200) during the ion current phase, as shown. However, uncontrolled accumulation of positive charge on the substrate surface will undesirably gradually discharge the sheath and chuck capacitors, slowly decreasing the sheath voltage drop and causing the substrate potential to approach zero. The accumulation of positive charge results in a voltage droop (ie, a positive slope during phase 205) in the voltage waveform established at the substrate.

[0032]

[0040] The voltage difference between the beginning and end of the ion current phase determines the ion energy distribution function (IEDF) width. FIG. 2B illustrates the effect of increasing plasma density on a voltage waveform established on a substrate by use of a PV source such as the waveform generator 150. As illustrated, an increase in plasma density during plasma processing (i.e., the arrows highlight the direction) due to a change in one or more plasma processing parameters (e.g., RF power applied by the plasma generator assembly 163) increases the voltage difference from the beginning to the end of the ion current phase, and thus tends to undesirably increase the voltage droop. The larger the voltage difference, the wider the IEDF width. For example, as illustrated in FIG. 2C, the ion energy distribution (IED) 201 widens with increasing ion current fluctuations without compensating for the voltage rise at the substrate. Thus, by using the high frequency voltage waveform techniques disclosed herein, the voltage droop in the voltage waveform generated by increasing the plasma density during plasma processing can be reduced, resulting in a narrower IED and improved accuracy of the plasma processing results on the substrate.

[0033]

[0041] In the reactor, the plasma may be generated by an inductively coupled source above the substrate (or a surrounding coil). The coil may be placed above a ceramic lid (vacuum boundary) or, in the case of a capacitively coupled plasma reactor, by applying RF power to either the electrostatic chuck or the upper electrode. As described, a waveform generator (e.g., waveform generator 150 of the first PV power assembly 196) outputs a short, narrow positive pulse of bipolarity that transitions from a negative voltage to a positive voltage greater than zero, as shown in FIG. 2A. The duration of the positive voltage pulse is controlled and returns to the negative voltage baseline. The voltage remains negative and returns to a positive pulse at the end of the period labeled T ON. The transition to the positive pulse is completed during the rising edge 202 portion of the voltage waveform 200. The duration of the positive section of the pulse can be varied and in some embodiments is controlled by the waveform period (T p ) between 5% and 15% of the waveform period (T p) between 1% and 20% of the frequency of the waveform 200. In one embodiment, the waveform period may be about 5 μs and the frequency of the waveform 200 may be about 200 kHz. In another embodiment, the waveform period may be about 2.5 μs and the frequency of the waveform 200 may be about 400 kHz.

[0034]

[0042] During a portion of the voltage waveform, the rising edge 202 of the pulse step attracts plasma bulk electrons to the substrate surface, but these electrons are unable to establish a negative DC sheath potential because an equal amount of positive charge exists on the electrode (e.g., electrode 104). The substrate and a dielectric disposed between the electrode and the substrate support surface 105A form a capacitor, which has an effective capacitance C esc , allowing an equal amount of positive charge on the electrode to cancel the electric field generated by the electrons placed on the substrate surface. At the falling edge 204 of the pulse step, the positive charge on the electrode is neutralized by the electrons from the waveform generator, thus establishing a negative DC voltage on the substrate surface. If the generated DC voltage is kept constant, monoenergetic ion bombardment is achieved. The negative DC voltage (V dc ) is calculated by the magnitude of the falling edge (ΔV) and C esc and sheath capacity C sheath It can be estimated using the ratio of V dc = ΔV * C esc / (C esc + C sheath )

[0035] Generation techniques for waveform generation

[0043] As semiconductor device features shrink, atomic precision is often required in today's substrate processing techniques, such as plasma etching and plasma deposition techniques. Etch processes, where plasma ions play a major role, often require precise ion energy control. Conventional radio frequency (RF) bias approaches use a sinusoidal waveform to excite the plasma and accelerate the ions. Ion energy distributions (IEDs) from conventional RF techniques are typically bimodal in shape. In recent years, pulsed techniques have also been investigated to generate IEDs with a single energy peak.

[0036]

[0044] In some implementations, due to issues related to system complexity and equipment cost, the positive ion current is not compensated during the ion current phase of the voltage waveform, and thus the negative voltage on the substrate decays (e.g., becomes less negative) over time. In other words, as described with respect to waveform 200, without compensation, the substrate voltage rises during the ion current phase, also referred to herein as voltage droop. This tendency is exacerbated with increasing plasma density (e.g., increasing ion current), resulting in the IED expanding or spreading toward lower energy regions, as shown in FIG. 2C.

[0037]

[0045] In some cases, a ramp voltage is generated to compensate for this voltage rise during a portion of the ion current phase (e.g., at least during phase 205) by using a current source or multiple voltage sources coupled to an electrode (e.g., electrode 104). However, at higher voltages (e.g., greater than 5 kV), it is difficult to generate a custom-tailored waveform using a ramp to compensate for this voltage rise.

[0038]

[0046] In some embodiments, a high frequency voltage waveform can be used to mitigate the effects of this voltage rise (i.e., droop) generated during the ion current phase. With the current state of high voltage switches available on the market today, it is problematic to generate a high frequency voltage pulse train at a pulse repetition frequency above 400 kHz due to physical and practical device limitations found in these conventional components. Thus, as briefly mentioned above, the switching speed of these conventional high voltage switches is limited to a practical maximum switching speed due to the damage caused to these components at medium to high frequencies due to heat generated during use. In certain embodiments of the present disclosure, time domain multiplexing of voltage pulses is used to generate a waveform that is provided to a complex load (e.g., electrostatic chuck and plasma 101 (FIG. 1)), whereby the load receives higher frequency pulses to mitigate the effects of voltage droop at the substrate surface. For example, a positive voltage pulse at a frequency of about 400 kHz can be used to periodically establish a negative direct current (DC) bias on the substrate, thereby obtaining an IED with a single energy peak. In other words, by the time the voltage at the substrate surface rises to a certain threshold during the ion current phase of the first voltage waveform pulse, a second voltage waveform pulse (e.g., from a different source or switch) can be applied, in effect resetting the voltage at the substrate surface during the next pulse cycle, as described in more detail herein.

[0039]

[0047] 3 illustrates a pulsed voltage bias scheme using a waveform 300 in accordance with certain embodiments of the present disclosure. As shown, a first pulsed voltage cycle 320 and a second pulsed voltage cycle 322 may be time multiplexed. To the electrostatic chuck and plasma 101, the frequency of the voltage pulses appears to be increased by the interleaving of the first pulsed voltage cycle 320 and the second pulsed voltage cycle 322. When the substrate voltage begins to droop during the ion current phase of the first voltage cycle generated from the first PV source, a second pulse is generated and applied by the second PV source to restore the DC voltage bias (negative) on the substrate and to restore the falling ion energy caused by the droop.

[0040]

[0048] In other words, the waveform 300 may include a positive voltage pulse 302 and a negative voltage pulse 304 during a first pulse voltage cycle 320, followed by another positive voltage pulse 306 and another negative voltage pulse 308 during a second pulse voltage cycle 322, as shown in FIG. 3. In some embodiments, the positive voltage pulse 302 and the negative voltage pulse 304 may be generated using a switch pair (e.g., S1 and S3 in FIG. 4A), and the other positive voltage pulse 306 and the other negative voltage pulse 308 may be generated using another switch pair (e.g., S2 and S4 in FIG. 4A). Using different switch pairs allows for higher frequency waveforms compared to conventional implementations that use only a single switch pair to generate positive and negative pulses. In other words, each switch may be implemented using one or more transistors, such as metal oxide semiconductor field effect transistors (MOSFETs). Due to heating, each MOSFET has a switching frequency limit (e.g., maximum practical switching speed), which prevents a single switch pair from generating pulses at high frequencies (e.g., 400 kHz). If the switches are operated at a frequency higher than the switching frequency limit of the switch, the voltage drop across the switch may increase due to the increase in the switch resistance caused by the heat generated in the switch in the presence of high switching voltages. For example, the voltage drop across the switch may increase by 10% or more depending on the switching frequency and switch type. Furthermore, when multiple switches are coupled in series, the voltage drops across the switches are cumulative. In other words, if three switches are coupled in series (e.g., to implement switches S1, S2, S3, or S4), the total voltage drop of the switches may increase by up to 30% if the voltage drop of each switch increases by 10%. Also, when comparing the voltage drop across a switch at the switch's switching frequency limit to when the switch is first used, at the same switch input voltage, it is believed that a voltage drop across a switch of 10% or more can lead to permanent damage to components within the switch (e.g., increased switching resistance over time) and / or a significantly shorter lifespan than a normal switch.

[0041]

[0049] 4A illustrates a waveform generator 400 for generating pulses during first and second pulsed voltage cycles 320, 322, in accordance with certain embodiments of the present disclosure. The waveform generator 400 may be part of the PV waveform generator 150. FIG 4B is a timing diagram 401 illustrating the states of the switches of the waveform generator 400.

[0042]

[0050] As shown, switch S1 may be closed during one phase to couple the output node 402 of the waveform generator to the voltage source V1 of the voltage source circuit 410, generating a positive voltage pulse 302. Switch S1 is then opened and switch S3 is closed during a second phase to ground the output node 402. Grounding the output node 402 results in a negative voltage pulse 304. In other words, during the positive voltage pulse 302, the capacitance between the output node 402 and the substrate is charged. After the positive voltage pulse 302, the output node 402 is coupled to an electrical ground node. Because the voltage across the capacitance between the output node 402 and the substrate cannot change instantaneously, the substrate voltage drops to a negative voltage in response to the closure of switch S3.

[0043]

[0051] After switch S3 is opened, switch S2 is closed during a third phase to couple the voltage source V2 of the voltage source circuit 410 to the output node 404 to actually implement the positive voltage pulse 306. Switch S2 is then opened and switch S4 is closed during a fourth phase to couple the output node 404 to the electrical ground node to actually implement the negative voltage pulse 308. As illustrated by the timing diagram 401, the first, second, third, and fourth phases are non-overlapping phases. As illustrated, the phases may be repeated to generate a continuous time-multiplexed pulse waveform that is delivered at a frequency higher than the maximum practical switching speed of the individual switches. In one embodiment, if the maximum practical switching speed limit of each switch limits the switching frequency of each switch to a frequency of 400 kHz, then a two voltage source configuration including the same switch may deliver a time-multiplexed pulse train having a frequency higher than 400 kHz and less than or equal to 800 kHz. In one non-limiting example, if the waveform generator 400 is required to generate an 800 kHz pulse train, switch combinations S1 / S3 and S2 / S4 are used separately to provide first and second pulse voltage cycles 320, 322, each with a period (T p ) but staggered in time by 2.5 μs intervals to generate the desired pulse train.

[0044]

[0052] In some embodiments, the output nodes 402, 404 may be coupled to the same node within the chamber. For example, the output nodes 402, 404 may be coupled to electrode 104. In some embodiments, the output nodes 402, 404 may be coupled to different nodes within the chamber. For example, the output node 402 may be coupled to electrode 104 and the output node 404 may be coupled to electrode 115.

[0045]

[0053] In some embodiments, the first voltage source circuit 410 of the waveform generator 400 forms part of the PV waveform generator 150 ( FIG. 1 ) of the first PV source assembly 196. In another embodiment, the first voltage source circuit 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the first PV source assembly 196, and the second voltage source circuit 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the second PV source assembly 197. In yet another embodiment, the first voltage source circuit 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the first PV source assembly 196, the second voltage source circuit 410 of the waveform generator 400 forms part of the PV waveform generator 150 of the second PV source assembly 197, and / or the third voltage source circuit 410 of the waveform generator 400 forms part of the PV waveform generator 150 of a third PV source assembly 198 coupled to the lid 123. In any of these configurations, the output nodes 402, 404 of the first voltage source circuit 410 are coupled to the electrodes 104, the output nodes 402, 404 of the second voltage source circuit 410 are coupled to the electrodes 115, and / or the output nodes 402, 404 of the third voltage source circuit 410 are coupled to the lid 123, as appropriate.

[0046]

[0054] In some embodiments, the voltage source circuit 410 may include a first voltage source V1 coupled to a switch S1 and a second voltage source V2 coupled to a switch S2. Each of the first and second voltage sources may be implemented using a capacitive element that is charged to a particular voltage by a power source. In some embodiments, the first and second voltage sources V1 or V2 of each voltage source circuit 410 may provide different voltages or the same voltage.

[0047]

[0055] Although the examples provided herein have described two switch pairs for ease of understanding, the embodiments of the present disclosure may be implemented with three or more switch pairs. For example, in addition to the first switch pair (e.g., S1 and S3) and the second switch pair (e.g., S2 and S4), a third switch pair may be implemented to generate positive and negative pulses, allowing for a higher frequency of operation. In other words, after generating the positive voltage pulse 306 and the negative voltage pulse 308 using the switch S2 and the switch S4, the third switch pair may be used to generate another positive pulse and another negative pulse before again generating the positive voltage pulse 302 and the negative voltage pulse 304 using the switch S1 and the switch S3. Thus, in some embodiments, multiple switch pairs are utilized in successive and repeated cycles to form a pulse train having a frequency higher than the practical maximum switching speed of the individual switches. Thereby, the maximum frequency of the pulse train is equal to N times the maximum frequency of each switch of the multiple switches, or at least the slowest switch, where N is equal to the number of switch pairs among the multiple switch pairs. Operating each switch pair during a different phase of the generated pulse train allows for the implementation of high frequency waveforms for plasma processing. The use of higher frequency waveforms can reduce voltage droop (e.g., voltage increase during an ion current phase) and improve the precision of plasma processing.

[0048]

[0056] 5 illustrates an ion energy distribution (IED) associated with a waveform 300, according to certain embodiments of the present disclosure. As illustrated, a narrower IED may be obtained when generating a waveform at a higher frequency (e.g., 400 kHz) as compared to a lower frequency waveform (e.g., waveform 200 of FIG. 2A having a frequency of 200 kHz). The narrower IED may facilitate greater feature formation accuracy, for example, during a typical etch plasma process.

[0049]

[0057] 6 is a process flow diagram illustrating a method 600 for waveform generation. The method 600 may be performed by a waveform generation system including a waveform generator, such as waveform generator 400, and a system controller, such as system controller 126.

[0050]

[0058] The method 600 begins with the waveform generation system coupling a voltage source circuit (e.g., voltage source circuit 410) to a first output node (e.g., output node 402) of a waveform generator (e.g., waveform generator 400) via a first switch (e.g., switch S1). The first output node is coupled to a chamber (e.g., chamber 100). In operation 604, the waveform generation system couples the first output node to an electrical ground node via a second switch (e.g., switch S3). In operation 606, the waveform generation system couples the voltage source circuit to a second output node (e.g., output node 404) of the waveform generator via a third switch (e.g., switch S2). The second output node is coupled to the chamber. In operation 608, the waveform generation system couples the second output node to an electrical ground node via a fourth switch (e.g., switch S4). In some embodiments, operations 602, 604, 606, and 608 can be repeated to generate a waveform for plasma processing.

[0051]

[0059] In some embodiments, a first pulsed voltage waveform (e.g., including a positive voltage pulse 302 and a negative voltage pulse 304) is generated in the chamber by coupling through a first switch and a second switch. Additionally, a second pulsed voltage waveform (e.g., including a positive voltage pulse 306 and a negative voltage pulse 308) is generated in the chamber by coupling through a third switch and a fourth switch. The first pulsed voltage waveform may be phase shifted (e.g., by 180°) from the second pulsed voltage waveform.

[0052]

[0060] In some embodiments, the coupling via the first switch, the second switch, the third switch, and the fourth switch is during the non-overlapping phases. For example, the voltage source circuit is coupled to the first output node during a first phase of the non-overlapping phases, and the first output node is coupled to the electrical ground node during a second phase of the non-overlapping phases, the second phase being after the first phase. Further, the voltage source circuit is coupled to the second output node during a third phase of the non-overlapping phases, the third phase being after the second phase, and the second output node is coupled to the electrical ground node during a fourth phase of the non-overlapping phases, the fourth phase being after the third phase.

[0053]

[0061] In some embodiments, the voltage source circuit includes a first voltage source (e.g., voltage source V1) coupled to the first switch and a second voltage source (e.g., voltage source V2) coupled to the second switch. The first voltage source may include a first capacitive element, and the second voltage source may include a second capacitive element. Each of the first switch, the second switch, the third switch, and the fourth switch may include one or more transistors (e.g., MOSFETs).

[0054]

[0062] In some embodiments, the waveform generation system may generate a first positive voltage pulse (e.g., positive voltage pulse 302) at a node within the chamber (e.g., substrate) by coupling a voltage source circuit to a first output node and may generate a first negative voltage pulse (e.g., negative voltage pulse 304) at a node within the chamber by coupling the first output node to an electrical ground node. Additionally, the waveform generation system may generate a second positive voltage pulse (e.g., positive voltage pulse 306) at a node within the chamber by coupling a voltage source circuit to a second output node and may generate a second negative voltage pulse (e.g., negative voltage pulse 308) at a node within the chamber by coupling the second output node to an electrical ground node.

[0055]

[0063] The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in physical contact with object C, then objects A and C may be considered to be coupled to one another even though objects A and C are not in direct physical contact. For example, a first object may be coupled to a second object even though the first object is not in direct physical contact with the second object.

[0056]

[0064] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of the disclosure being defined by the following claims.

Claims

1. 1. A waveform generator for plasma processing, comprising: Voltage source circuit, a first switch coupled between the voltage source circuit and a first output node of the waveform generator, the first output node being configured to be coupled to a chamber; a second switch coupled between the first output node and an electrical ground node; a third switch coupled between the voltage source circuit and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber; and A waveform generator comprising a fourth switch coupled between the second output node and the electrical ground node.

2. the first switch and the second switch are configured to generate a first pulsed voltage waveform that is provided to the chamber; 2. The waveform generator of claim 1, wherein the third switch and the fourth switch are configured to generate a second pulsed voltage waveform provided to the chamber, the first pulsed voltage waveform being phase shifted from the second pulsed voltage waveform.

3. 2. The waveform generator of claim 1, wherein the first switch, the second switch, the third switch, and the fourth switch are configured to be closed during non-overlapping phases.

4. the first switch is configured to be closed during a first phase of the non-overlapping phases; the second switch is configured to be closed during a second phase of the non-overlapping phases, the second phase being after the first phase; the third switch is configured to be closed during a third phase of the non-overlapping phases, the third phase being after the second phase; 4. The waveform generator of claim 3, wherein the fourth switch is configured to be closed during a fourth phase of the non-overlapping phases, the fourth phase being after the third phase.

5. 2. The waveform generator of claim 1, wherein the voltage source circuit comprises a first voltage source coupled to the first switch and a second voltage source coupled to the third switch.

6. 6. The waveform generator of claim 5, wherein the first voltage source comprises a first capacitive element and the second voltage source comprises a second capacitive element.

7. 2. The waveform generator of claim 1, wherein the first switch, the second switch, the third switch, and the fourth switch each comprise one or more transistors.

8. 2. The waveform generator of claim 1, wherein the first output node is coupled to the second output node.

9. 9. The waveform generator of claim 8, wherein the first output node and the second output node are coupled to electrodes disposed below a substrate support surface of a substrate support disposed within the chamber.

10. 10. The waveform generator of claim 9, wherein at least one of the first switch, the second switch, the third switch, or the fourth switch has a switching frequency limit, and the waveform generator is configured to generate a waveform at the electrodes having a frequency that exceeds the switching frequency limit.

11. 1. A method for waveform generation, comprising: coupling a voltage source circuit via a first switch to a first output node of a waveform generator, the first output node being coupled to the chamber; coupling the first output node to an electrical ground node via a second switch; coupling the voltage source circuit via a third switch to a second output node of the waveform generator, the second output node being coupled to the chamber; and coupling the second output node to the electrical ground node through a fourth switch.

12. a first pulsed voltage waveform is generated in the chamber by the coupling through the first switch and the second switch; 12. The method of claim 11 , wherein a second pulsed voltage waveform is generated in the chamber by the coupling through the third switch and the fourth switch, and the first pulsed voltage waveform is phase shifted from the second pulsed voltage waveform.

13. The method of claim 11 , wherein the coupling through the first switch, the second switch, the third switch, and the fourth switch is during a non-overlapping phase.

14. the voltage source circuit is coupled to the first output node during a first phase of the non-overlapping phases; the first output node is coupled to the electrical ground node during a second one of the non-overlapping phases, the second phase being after the first phase; the voltage source circuit is coupled to the second output node during a third phase of the non-overlapping phases, the third phase being after the second phase; 14. The method of claim 13, wherein the second output node is coupled to the electrical ground node during a fourth phase of the non-overlapping phases, the fourth phase being after the third phase.

15. The method of claim 11 , wherein the voltage source circuit comprises a first voltage source coupled to the first switch and a second voltage source coupled to the third switch.

16. 16. The method of claim 15, wherein the first voltage source comprises a first capacitive element and the second voltage source comprises a second capacitive element.

17. The method of claim 11 , wherein the first switch, the second switch, the third switch, and the fourth switch each comprise one or more transistors.

18. generating a first positive voltage pulse at a node within the chamber by coupling the voltage source circuit to the first output node; generating a first negative voltage pulse at the node within the chamber by coupling the first output node to the electrical ground node; generating a second positive voltage pulse at the node within the chamber by coupling the voltage source circuit to the second output node; and 12. The method of claim 11, further comprising generating a second negative voltage pulse at the node within the chamber by coupling the second output node to the electrical ground node.

19. The method of claim 11 , wherein the first output node and the second output node are coupled to electrodes disposed below a substrate support surface of a substrate support disposed within the chamber.

20. 20. The method of claim 19, wherein at least one of the first switch, the second switch, the third switch, or the fourth switch has a switching frequency limit, the method further comprising generating a waveform at the electrodes having a frequency that exceeds the switching frequency limit.

21. 1. An apparatus for generating a waveform, comprising: Voltage source circuit, one or more switches coupled to the voltage source circuit; and a controller configured to control the one or more switches, the one or more switches comprising: a first switch coupled between the voltage source circuit and a first output node of a waveform generator, the first output node being configured to be coupled to a chamber; a second switch coupled between the first output node and an electrical ground node; a third switch coupled between the voltage source circuit and a second output node of the waveform generator, the second output node being configured to be coupled to the chamber; and a fourth switch coupled between the second output node and the electrical ground node.

22. 22. The apparatus of claim 21, wherein the controller is configured to close the first switch, the second switch, the third switch, and the fourth switch during non-overlapping phases.

23. The controller: closing the first switch during a first phase of the non-overlapping phases; closing the second switch during a second phase of the non-overlapping phases, the second phase being after the first phase; closing the third switch during a third phase of the non-overlapping phases, the third phase being after the second phase; and 23. The apparatus of claim 22, configured to close the fourth switch during a fourth phase of the non-overlapping phases, the fourth phase being after the third phase.

24. 22. The apparatus of claim 21, wherein the voltage source circuit comprises a first voltage source coupled to the first switch and a second voltage source coupled to the third switch.

25. 22. The apparatus of claim 21, wherein the first output node and the second output node are coupled to electrodes disposed below a substrate support surface of a substrate support disposed within the chamber.

26. 26. The apparatus of claim 25, wherein at least one of the first switch, the second switch, the third switch, or the fourth switch has a switching frequency limit, and the apparatus is configured to generate a waveform at the electrodes having a frequency that exceeds the switching frequency limit.

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