Semiconductor module

Abstract

To provide a semiconductor module capable of suppressing the decrease in the current which can be output from a semiconductor chip within the allowable temperature range of the semiconductor chip.SOLUTION: The semiconductor module includes: a circuit board; a front side first semiconductor chip 201 mounted on the surface of the circuit board; a backside first semiconductor chip 251 mounted on the back of the circuit board; a housing 305 connected to the backside first semiconductor chip 251; and a choke coil 300 that smooths the current rectified by the front side first semiconductor chip 201 and the backside first semiconductor chip 251. The front side first semiconductor chip 201 and the backside first semiconductor chip 251 are connected in parallel to the choke coil 300. The electrical resistance of the current flowing from a first drain electrode 2012 on the front side of the front side first semiconductor chip 201 to the choke coil 300 is larger than the electrical resistance of the current flowing from a first drain electrode 2512 on the backside of the backside first semiconductor chip 251 to the choke coil 300.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor module. [Background technology]

[0002] Conventionally, as described in Patent Document 1, a semiconductor module has been known in which a plurality of semiconductor packages each having a semiconductor chip are arranged on one side of a printed circuit board opposite to the other side. The semiconductor chip is connected to a housing via a heat dissipation material. This allows the heat of the semiconductor chip to be conducted to the housing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-167605 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor module as described in Patent Document 1, semiconductor chips are arranged on one side and the other side of a printed circuit board and connected in parallel to reduce the loss of the semiconductor chips and to reduce the size of the semiconductor module. However, when a semiconductor chip is arranged on one side of a printed circuit board, the thermal conductivity of the printed circuit board is relatively low, so the heat of the semiconductor chip arranged on one side of the printed circuit board is less likely to be conducted to the housing than the heat of the semiconductor chip arranged on the other side of the printed circuit board. This makes it easy for the temperature of the semiconductor chip arranged on one side of the printed circuit board to rise. Therefore, the temperature of the semiconductor chip arranged on one side of the printed circuit board is likely to reach the allowable temperature, and the on-resistance of the semiconductor chip arranged on one side of the printed circuit board is likely to increase. Therefore, the current flowing through the semiconductor chip arranged on one side of the printed circuit board is likely to decrease. Therefore, the current that can be output from the semiconductor chip arranged on one side of the printed circuit board within the allowable temperature of the semiconductor chip decreases. In addition, the temperature of the semiconductor chip arranged on one side of the printed circuit board is a constraint, so the current that can be output from the semiconductor chip arranged on the other side of the printed circuit board decreases.

[0005] An object of the present disclosure is to provide a semiconductor module that suppresses a decrease in the current that can be output from a semiconductor chip within the allowable temperature range of the semiconductor chip. [Means for solving the problem]

[0006] The invention described in claim 1 is a semiconductor module comprising: a substrate (200) having a substrate front surface (2006) that is a surface intersecting a thickness direction (DT) and a substrate back surface (2007) that is a surface opposite to the substrate front surface; a front-side semiconductor chip (201) mounted on the substrate front surface and rectifying a current flowing through a first electrode (2011) and outputting the rectified current from a second electrode (2012); a back-side semiconductor chip (251) mounted on the substrate back surface and rectifying a current flowing through a third electrode (2511) and outputting the rectified current from a fourth electrode (2512); and a housing (305) connected to the side of the back-side semiconductor chip opposite to the substrate. ) and an element (300) that smoothes the current rectified by the front side semiconductor chip and the back side semiconductor chip, wherein the front side semiconductor chip has a property that the resistance of the front side semiconductor chip increases as the temperature of the front side semiconductor chip increases, and the back side semiconductor chip has a property that the resistance of the back side semiconductor chip increases as the temperature of the back side semiconductor chip increases, the front side semiconductor chip and the back side semiconductor chip are connected in parallel to the elements, and an electrical resistance (Rfc1) of a current flowing from the second electrode to the element is greater than an electrical resistance (Rbc1) of a current flowing from the fourth electrode to the element.

[0007] This makes it difficult for current to flow through the front-side semiconductor chip. This suppresses an increase in temperature of the front-side semiconductor chip. This suppresses the temperature of the front-side semiconductor chip from reaching the allowable temperature, and also suppresses an increase in the on-resistance of the front-side semiconductor chip. This suppresses a decrease in the current that can be output from the front-side semiconductor chip within the allowable temperature of the front-side semiconductor chip. Furthermore, by suppressing the temperature of the front-side semiconductor chip from reaching the allowable temperature, a decrease in the current that can be output from the back-side semiconductor chip is suppressed.

[0008] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram of a DC-DC converter in which a semiconductor module according to a first embodiment is used. [Diagram 2] FIG. [Diagram 3] FIG. 3 is a view taken along line III in FIG. 2 . [Figure 4] Cross-sectional view taken along line IV-IV in Figure 2. [Diagram 5] Cross-sectional view of line VV in Figure 2. [Figure 6] FIG. 6 is a view taken from the arrow VI in FIG. 2. [Figure 7] Cross-sectional view taken along line VII-VII in Figure 3. [Figure 8] FIG. 11 is a relationship diagram between current and temperature in a semiconductor module of a comparative example. [Figure 9] FIG. 4 is a relationship diagram between current and temperature in the semiconductor module of the first embodiment. [Figure 10] FIG. 11 is a circuit diagram of a DC-DC converter in which a semiconductor module according to a second embodiment is used. [Figure 11] FIG. [Figure 12] FIG. 11 is a circuit diagram of a DC-DC converter in which a semiconductor module according to a third embodiment is used. [Figure 13] FIG. [Figure 14] FIG. 13 is a circuit diagram of a DC-DC converter in which a semiconductor module according to a fourth embodiment is used. [Figure 15] FIG. [Figure 16] FIG. 16 is a view taken along the line XVI in FIG. 15 . [Figure 17] FIG. 17 is a view taken along the line XVII in FIG. 15 . [Figure 18] FIG. 13 is a cross-sectional view of a semiconductor module according to a fifth embodiment. [Figure 19] FIG. 19 is a view taken along the line XIX in FIG. 18 . [Figure 20] Cross-sectional view taken along line XX-XX in Figure 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals, and the description thereof will be omitted.

[0011] (First embodiment) In the semiconductor module of the present embodiment, a decrease in the current that can be output from the semiconductor chip within the allowable temperature range of the semiconductor chip is suppressed. The semiconductor module is used, for example, in a DC-DC converter for a vehicle. First, the DC-DC converter will be described.

[0012] As shown in FIGS. 1 to 7, the DC-DC converter 10 includes a DC power supply 12, a conversion circuit 14, a transformer 16, and a semiconductor module 20.

[0013] 1, the DC power supply 12 is connected to a conversion circuit 14, which will be described later. Furthermore, the DC power supply 12 applies a relatively high voltage to the conversion circuit 14.

[0014] The conversion circuit 14 has a plurality of transistors (not shown). The conversion circuit 14 also turns these transistors on and off. In this way, the conversion circuit 14 converts the DC voltage from the DC power supply 12 into an AC voltage. The conversion circuit 14 then applies the converted AC voltage to a transformer 16 (described later).

[0015] The transformer 16 has a primary winding 161 and a secondary winding 162. The primary winding 161 is connected to the conversion circuit 14. The secondary winding 162 is connected to a semiconductor module 20, which will be described later. The secondary winding 162 also includes an intermediate tap 163. The intermediate tap 163 is connected to ground. The transformer 16 then steps down the AC voltage from the conversion circuit 14 by the primary winding 161 and the secondary winding 162. Furthermore, the transformer 16 applies the stepped-down AC voltage to the semiconductor module 20, which will be described later.

[0016] 1 to 7, the semiconductor module 20 includes a substrate 200, a front-side first semiconductor chip 201, a front-side first source wiring 211, a front-side first drain wiring 221, a junction wiring 225, a front-side first gate wiring 231, and a first drive circuit 241. The semiconductor module 20 also includes a rear-side first semiconductor chip 251, a rear-side first source wiring 261, a first intermediate wiring 271, a rear-side first drain wiring 281, and a rear-side first gate wiring 291. The semiconductor module 20 also includes a front-side second semiconductor chip 202, a front-side second source wiring 212, a front-side second drain wiring 222, a front-side second gate wiring 232, and a second drive circuit 242. The semiconductor module 20 also includes a back-side second semiconductor chip 252, a back-side second source wiring 262, a second intermediate wiring 272, a back-side second drain wiring 282, a back-side second gate wiring 292, a choke coil 300, a housing 305, a connection member 310 and a cooling member 315.

[0017] The substrate 200 is a printed circuit board. As shown in Figs. 2 to 7, the substrate 200 has a first layer 2001, a second layer 2002, a third layer 2003, a fourth layer 2004, and a plurality of vias 2005. Here, the number of layers of the substrate 200 is four, but is not limited to this. The number of layers of the substrate 200 may be one or more. In the following, the thickness direction of the substrate 200 will be simply referred to as a thickness direction DT.

[0018] The first layer 2001 includes a substrate surface 2006 as shown in FIG. 2, FIG. 3, and FIG. 7. The substrate surface 2006 is a surface perpendicular to the thickness direction DT and corresponds to a surface intersecting the thickness direction DT. The second layer 2002 is connected to the first layer 2001 on the side opposite to the substrate surface 2006 in the thickness direction DT as shown in FIG. 2 and FIG. 7. The third layer 2003 is connected to the second layer 2002 on the side opposite to the first layer 2001 in the thickness direction DT. As a result, the second layer 2002 is disposed between the first layer 2001 and the third layer 2003. The fourth layer 2004 is connected to the third layer 2003 on the side opposite to the second layer 2002 in the thickness direction DT. As a result, the third layer 2003 is disposed between the second layer 2002 and the fourth layer 2004. Furthermore, the fourth layer 2004 includes a substrate back surface 2007 as shown in FIG. 2, FIG. 6, and FIG. 7. The substrate back surface 2007 is the surface opposite to the substrate front surface 2006. The substrate back surface 2007 is a surface perpendicular to the thickness direction DT, and corresponds to a surface intersecting the thickness direction DT.

[0019] The front-side first semiconductor chip 201 corresponds to the front-side semiconductor chip, and is connected to the substrate surface 2006 via the front-side first source wiring 211 and the front-side first drain wiring 221 as shown in Fig. 2 and Fig. 3. As a result, the front-side first semiconductor chip 201 is mounted on the substrate surface 2006. Furthermore, the front-side first semiconductor chip 201 has a transistor such as an FET, and has a characteristic that the on-resistance of the front-side first semiconductor chip 201 increases with an increase in the temperature of the front-side first semiconductor chip 201. Furthermore, the front-side first semiconductor chip 201 has a front-side first source electrode 2011, a front-side first drain electrode 2012, and a front-side first gate electrode 2013 as shown in Fig. 1.

[0020] The front-side first source electrode 2011 corresponds to the first electrode, and is connected to the secondary winding 162 via the front-side first source wiring 211. Moreover, the front-side first source wiring 211 is connected to the substrate surface 2006 in the thickness direction DT, as shown in Figs.

[0021] 1, the front-side first drain electrode 2012 corresponds to the second electrode, and is connected to a choke coil 300 described later via a front-side first drain wiring 221 and a merging wiring 225. Moreover, the front-side first drain wiring 221 is connected to the substrate surface 2006 and the thickness direction DT, as shown in FIGS.

[0022] Further, the junction wiring 225 is formed in the first layer 2001, the third layer 2003 and the fourth layer 2004 as shown in FIG. 3, FIG. 5 and FIG. 6. The junction wiring 225 in the first layer 2001 is connected to the substrate surface 2006 in the thickness direction DT. The junction wiring 225 in the third layer 2003 is connected to the junction wiring 225 in the first layer 2001 in the thickness direction DT through the via 2005. The junction wiring 225 in the fourth layer 2004 is connected to the junction wiring 225 in the third layer 2003 in the thickness direction DT through the via 2005. Moreover, the junction wiring 225 in the fourth layer 2004 is connected to the substrate back surface 2007 in the thickness direction DT.

[0023] 1, the front-side first gate electrode 2013 is connected to a first driving circuit 241 through a front-side first gate wiring 231 and a via 2005, etc. The first driving circuit 241 drives the front-side first semiconductor chip 201 and a back-side first semiconductor chip 251 described later.

[0024] In addition, the front-side first gate wiring 231 is formed between the substrate front surface 2006 and the substrate rear surface 2007, as shown in FIG. 4, and is formed in the second layer 2002. Furthermore, the front-side first gate wiring 231 extends in one direction Da perpendicular to the thickness direction DT. Furthermore, as shown in FIG. 3, the direction of at least a part of the current flowing from the front-side first drain electrode 2012 to the choke coil 300 described later is perpendicular to the one direction Da. Note that, although the front-side first gate wiring 231 is formed in the second layer 2002 here, it is not limited to being formed in the second layer 2002, and may be formed in the first layer 2001, the third layer 2003, and the fourth layer 2004. Furthermore, in FIG. 3, the direction of at least a part of the current flowing from the front-side first drain electrode 2012 to the choke coil 300 described later is indicated as Df1.

[0025] The backside first semiconductor chip 251 corresponds to a backside semiconductor chip, and is connected to the backside 2007 of the substrate via a backside first source wiring 261 and a backside first drain wiring 281, as shown in FIG. 2 and FIG. 6. As a result, the backside first semiconductor chip 251 is mounted on the backside 2007 of the substrate. Furthermore, the backside first semiconductor chip 251 has a transistor such as an FET, and has a characteristic that the on-resistance of the backside first semiconductor chip 251 increases with an increase in the temperature of the backside first semiconductor chip 251. Furthermore, the backside first semiconductor chip 251 has a backside first source electrode 2511, a backside first drain electrode 2512, and a backside first gate electrode 2513, as shown in FIG. 1.

[0026] The rear-side first source electrode 2511 corresponds to a third electrode, and is connected to the secondary winding 162 via the rear-side first source wiring 261. Moreover, as shown in FIG. 2 and FIG. 6, the rear-side first source wiring 261 is connected to the rear surface 2007 of the substrate in the thickness direction DT. Furthermore, as shown in FIG. 2 to FIG. 6, the rear-side first source wiring 261 is connected to the front-side first source wiring 211 in the thickness direction DT via the via 2005 and the first intermediate wiring 271. Therefore, as shown in FIG. 1, the front-side first semiconductor chip 201 and the rear-side first semiconductor chip 251 are connected in parallel to the secondary winding 162.

[0027] The rear-side first drain electrode 2512 corresponds to a fourth electrode, and is connected to a choke coil 300 described later via a rear-side first drain wiring 281 and a junction wiring 225. The rear-side first drain wiring 281 is connected to the rear surface 2007 of the substrate in the thickness direction DT, and is also connected to the junction wiring 225, as shown in FIGS.

[0028] Returning to FIG. 1, the rear-side first gate electrode 2513 is connected to the first driving circuit 241 via the rear-side first gate wiring 291 .

[0029] In addition, the rear first gate wiring 291 is formed between the substrate front surface 2006 and the substrate rear surface 2007 as shown in FIG. 4, and is formed in the second layer 2002. Furthermore, the rear first gate wiring 291 extends in one direction Da perpendicular to the thickness direction DT. Furthermore, as shown in FIG. 6, the direction of at least a part of the current flowing from the rear first drain electrode 2512 to the choke coil 300 described later is perpendicular to the one direction Da. Note that, although the rear first gate wiring 291 is formed in the second layer 2002 here, it is not limited to being formed in the second layer 2002, and may be formed in the first layer 2001, the third layer 2003, and the fourth layer 2004. Furthermore, in FIG. 6, the direction of at least a part of the current flowing from the rear first drain electrode 2512 to the choke coil 300 described later is indicated as Db1.

[0030] Moreover, the distance from the first driving circuit 241 to the rear-side first gate electrode 2513 is set to be the same as the distance from the first driving circuit 241 to the front-side first gate electrode 2013. Note that, here, "same" includes the manufacturing error range.

[0031] The front-side second semiconductor chip 202 is connected to the substrate surface 2006 via the front-side second source wiring 212 and the front-side second drain wiring 222, as shown in FIG. 2 and FIG. 7. As a result, the front-side second semiconductor chip 202 is mounted on the substrate surface 2006. Therefore, the front-side second semiconductor chip 202 is arranged with the front-side first semiconductor chip 201 on the substrate surface 2006 in a direction perpendicular to the thickness direction DT. Furthermore, the front-side second semiconductor chip 202 has a transistor such as an FET, and has a characteristic that the on-resistance of the front-side second semiconductor chip 202 increases with an increase in the temperature of the front-side second semiconductor chip 202. In addition, the front-side second semiconductor chip 202 has a front-side second source electrode 2021, a front-side second drain electrode 2022, and a front-side second gate electrode 2023, as shown in FIG. 1.

[0032] The front-side second source electrode 2021 corresponds to a fifth electrode, and is connected to the secondary winding 162 on the opposite side to the front-side first source electrode 2011 via a front-side second source wiring 212. In addition, the front-side second source wiring 212 is connected to the substrate surface 2006 in the thickness direction DT, as shown in Figs.

[0033] 1, the front-side second drain electrode 2022 corresponds to the sixth electrode, and is connected to a choke coil 300 described later via a front-side second drain wiring 222 and a junction wiring 225. In addition, the front-side second drain wiring 222 is connected to the substrate surface 2006 in the thickness direction DT, and is also connected to the junction wiring 225, as shown in FIGS.

[0034] 1, the front-side second gate electrode 2023 is connected to the second driving circuit 242 through the front-side second gate wiring 232 and the via 2005, etc. The second driving circuit 242 drives the front-side second semiconductor chip 202 and a back-side second semiconductor chip 252 described later.

[0035] In addition, the front-side second gate wiring 232 is formed between the substrate front surface 2006 and the substrate rear surface 2007, as shown in FIG. 4, and is formed in the second layer 2002. Furthermore, the front-side second gate wiring 232 extends in one direction Da perpendicular to the thickness direction DT. Furthermore, as shown in FIG. 3, the direction of at least a part of the current flowing from the front-side second drain electrode 2022 to the choke coil 300 described later is perpendicular to the one direction Da. Note that, although the front-side second gate wiring 232 is formed in the second layer 2002 here, it is not limited to being formed in the second layer 2002, and may be formed in the first layer 2001, the third layer 2003, and the fourth layer 2004. Furthermore, in FIG. 3, the direction of at least a part of the current flowing from the front-side second drain electrode 2022 to the choke coil 300 described later is indicated as Df2.

[0036] The backside second semiconductor chip 252 is connected to the substrate back surface 2007 via the backside second source wiring 262 and the backside second drain wiring 282, as shown in FIG. 6 and FIG. 7. As a result, the backside second semiconductor chip 252 is mounted on the substrate back surface 2007. Therefore, the backside second semiconductor chip 252 is arranged with the backside first semiconductor chip 251 in a direction perpendicular to the thickness direction DT on the substrate back surface 2007. Furthermore, the backside second semiconductor chip 252 has a transistor such as an FET, and has a characteristic that the on-resistance of the backside second semiconductor chip 252 increases with an increase in the temperature of the backside second semiconductor chip 252. Moreover, the backside second semiconductor chip 252 has a backside second source electrode 2521, a backside second drain electrode 2522, and a backside second gate electrode 2523, as shown in FIG. 1.

[0037] The back-side second source electrode 2521 corresponds to a seventh electrode, and is connected to the side of the secondary winding 162 opposite to the back-side first source electrode 2511 via the back-side second source wiring 262. Moreover, as shown in FIG. 6 and FIG. 7, the back-side second source wiring 262 is connected to the back surface 2007 of the substrate in the thickness direction DT. Furthermore, as shown in FIG. 3 to FIG. 7, the back-side second source wiring 262 is connected to the front-side second source wiring 212 in the thickness direction DT via the via 2005 and the second intermediate wiring 272. Therefore, as shown in FIG. 1, the front-side second semiconductor chip 202 and the back-side second semiconductor chip 252 are connected in parallel to the secondary winding 162.

[0038] The rear-side second drain electrode 2522 corresponds to an eighth electrode, and is connected to a choke coil 300 described later via a rear-side second drain wiring 282 and a junction wiring 225. As shown in Figs. 6 and 7, the rear-side second drain wiring 282 is connected to the rear surface 2007 of the substrate in the thickness direction DT, and is also connected to the junction wiring 225. In addition, as shown in Fig. 6, the rear-side second drain wiring 282 is connected to the rear-side first drain wiring 281 via the junction wiring 225.

[0039] Returning to FIG. 1, the rear-side second gate electrode 2523 is connected to the second driving circuit 242 via the rear-side second gate wiring 292 .

[0040] In addition, the rear side second gate wiring 292 is formed between the substrate surface 2006 and the substrate rear surface 2007 as shown in FIG. 4, and is formed in the second layer 2002. Furthermore, the rear side second gate wiring 292 extends in one direction Da perpendicular to the thickness direction DT. Furthermore, as shown in FIG. 6, the direction of at least a part of the current flowing from the rear side second drain electrode 2522 to the choke coil 300 described later is perpendicular to the one direction Da. Note that, although the rear side second gate wiring 292 is formed in the second layer 2002 here, it is not limited to being formed in the second layer 2002, and may be formed in the first layer 2001, the third layer 2003, and the fourth layer 2004. Furthermore, in FIG. 6, the direction of at least a part of the current flowing from the rear side second drain electrode 2522 to the choke coil 300 described later is indicated as Db2.

[0041] Moreover, the distance from the second driving circuit 242 to the rear-side second gate electrode 2523 is set to be the same as the distance from the second driving circuit 242 to the front-side second gate electrode 2023 .

[0042] The choke coil 300 corresponds to an element that smoothes the current rectified by the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252. Here, the choke coil 300 is formed on the back surface 2007 of the substrate. Furthermore, the choke coil 300 is connected to the front-side first drain wiring 221 and the back-side first drain wiring 281 through the junction wiring 225, the via 2005, and the like. Therefore, the front-side first semiconductor chip 201 and the back-side first semiconductor chip 251 are connected in parallel to the choke coil 300. Furthermore, the choke coil 300 is connected to the front-side second drain wiring 222 and the back-side second drain wiring 282 through the junction wiring 225, the via 2005, and the like. Therefore, the front-side second semiconductor chip 202 and the back-side second semiconductor chip 252 are connected in parallel to the choke coil 300. It should be noted that, although the choke coil 300 is formed on the rear surface 2007 of the substrate here, the present invention is not limited to this, and the choke coil 300 may be formed on the front surface 2006 of the substrate or the like.

[0043] Here, the electrical resistance of the current flowing from the front-side first drain electrode 2012 to the choke coil 300 is defined as the front-side first resistance Rfc1. The electrical resistance of the current flowing from the back-side first drain electrode 2512 to the choke coil 300 is defined as the back-side first resistance Rbc1. The electrical resistance of the current flowing from the front-side second drain electrode 2022 to the choke coil 300 is defined as the front-side second resistance Rfc2. The electrical resistance of the current flowing from the back-side second drain electrode 2522 to the choke coil 300 is defined as the back-side second resistance Rbc2. The connection portion between the front-side first drain wiring 221 and the junction wiring 225 is defined as the first connection portion. The connection portion between the front-side first drain electrode 2012 and the front-side first drain wiring 221 is defined as the second connection portion. The connection portion between the front-side second drain wiring 222 and the junction wiring 225 is defined as the third connection portion. The connection portion between the front-side second drain electrode 2022 and the front-side second drain wiring 222 is referred to as a fourth connection portion.

[0044] The front-side first resistance Rfc1 is larger than the back-side first resistance Rbc1, that is, Rfc1>Rbc1. For this reason, here, for example, the size of the first connection portion is smaller than the size of the second connection portion. This makes the front-side first resistance Rfc1 relatively large. For this reason, the front-side first resistance Rfc1 is larger than the back-side first resistance Rbc1.

[0045] Also, the front-side second resistance Rfc2 is larger than the back-side second resistance Rbc2, i.e., Rfc2>Rbc2. For this reason, here, for example, the size of the third connection part is smaller than the size of the fourth connection part. As a result, the front-side second resistance Rfc2 is relatively large. For this reason, the front-side second resistance Rfc2 is larger than the back-side second resistance Rbc2. Note that the size of the connection part refers to, for example, the length of the connection part in the thickness direction DT, the length of the connection part in the direction of the current flowing through the connection part, and the length of the connection part in the thickness direction DT and the direction perpendicular to the direction of the current flowing through the connection part.

[0046] The housing 305 is made of a metal having a relatively high thermal conductivity, such as aluminum or copper. As shown in Figs. 3 to 6, the housing 305 is connected to the substrate 200 via screws 307 or the like. As shown in Figs. 2 and 7, the housing 305 is connected to the opposite sides of the substrate 200 of the rear-side first semiconductor chip 251 and the rear-side second semiconductor chip 252 in the thickness direction DT via a connecting member 310 such as TIM. This makes it easier for the heat generated in the rear-side first semiconductor chip 251 and the rear-side second semiconductor chip 252 to be conducted to the housing 305 than the heat generated in the front-side first semiconductor chip 201 and the front-side second semiconductor chip 202. TIM is an abbreviation for Thermal Interface Material.

[0047] The cooling member 315 is, for example, a pipe, etc. The housing 305 is cooled by flowing cooling water through the cooling member 315. Therefore, the heat conducted to the housing 305 is easily dissipated from the housing 305.

[0048] As described above, the DC-DC converter 10 using the semiconductor module 20 of the first embodiment is configured. Next, the operation of the DC-DC converter 10 will be described.

[0049] As shown in Fig. 1, the DC power supply 12 applies a relatively high voltage to the conversion circuit 14. The conversion circuit 14 converts the DC voltage from the DC power supply 12 into an AC voltage. The conversion circuit 14 also applies the converted AC voltage to the transformer 16. The transformer 16 steps down the AC voltage from the conversion circuit 14. The transformer 16 further applies the stepped-down AC voltage to the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252.

[0050] Here, for example, it is assumed that the voltage of the first front-side source electrode 2011 is greater than the voltage of the first front-side drain electrode 2012 due to the stepped-down AC voltage from the transformer 16. At this time, the first drive circuit 241 controls the voltage of the first front-side gate electrode 2013 via the first front-side gate wiring 231. As a result, the first front-side semiconductor chip 201 is turned on. Therefore, for example, a positive part of the stepped-down AC voltage from the transformer 16 is output from the first front-side drain electrode 2012. Therefore, the first front-side semiconductor chip 201 rectifies the current flowing through the first front-side source electrode 2011 and outputs the rectified current from the first front-side drain electrode 2012.

[0051] Furthermore, for example, the voltage of the backside first source electrode 2511 is greater than the voltage of the backside first drain electrode 2512 due to the stepped-down AC voltage from the transformer 16. At this time, the first drive circuit 241 controls the voltage of the backside first gate electrode 2513 via the backside first gate wiring 291. As a result, the backside first semiconductor chip 251 is turned on. Therefore, for example, a positive part of the stepped-down AC voltage from the transformer 16 is output from the backside first drain electrode 2512. Therefore, the backside first semiconductor chip 251 rectifies the current flowing through the backside first source electrode 2511 and outputs the rectified current from the backside first drain electrode 2512.

[0052] Also, for example, assume that the voltage of the front-side second source electrode 2021 is greater than the voltage of the front-side second drain electrode 2022 due to the stepped-down AC voltage from the transformer 16. At this time, the second drive circuit 242 controls the voltage of the front-side second gate electrode 2023 via the front-side second gate wiring 232. As a result, the front-side second semiconductor chip 202 is turned on. Therefore, for example, a negative part of the stepped-down AC voltage from the transformer 16 is output from the front-side second drain electrode 2022. Therefore, the front-side second semiconductor chip 202 rectifies the current flowing through the front-side second source electrode 2021 and outputs the rectified current from the front-side second drain electrode 2022.

[0053] Furthermore, for example, the voltage of the backside second source electrode 2521 is greater than the voltage of the backside second drain electrode 2522 due to the stepped-down AC voltage from the transformer 16. At this time, the second drive circuit 242 controls the voltage of the backside second gate electrode 2523 via the backside second gate wiring 292. As a result, the backside second semiconductor chip 252 is turned on. Therefore, for example, a negative part of the stepped-down AC voltage from the transformer 16 is output from the backside second drain electrode 2522. Therefore, the backside second semiconductor chip 252 rectifies the current flowing through the backside second source electrode 2521 and outputs the rectified current from the backside second drain electrode 2522.

[0054] The current rectified by the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252 flows to the choke coil 300 via the junction wiring 225. The choke coil 300 smoothes the current rectified by the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252. The direct current smoothed by the choke coil 300 flows to the external device 350. The external device 350 is, for example, an auxiliary battery used for an audio device in a vehicle. When the external device 350 is an auxiliary battery, the auxiliary battery is charged by the direct current smoothed by the choke coil 300.

[0055] Moreover, heat generated in the front-side first semiconductor chip 201 and the front-side second semiconductor chip 202 is conducted to the housing 305 via the wiring, the vias 2005, the substrate 200, the back-side first semiconductor chip 251 and the back-side second semiconductor chip 252. Furthermore, heat generated in the back-side first semiconductor chip 251 and the back-side second semiconductor chip 252 is conducted to the housing 305 via the connection member 310. The heat conducted to the housing 305 is dissipated from the housing 305. Moreover, the housing 305 is cooled by the cooling member 315.

[0056] As described above, the DC-DC converter 10 operates. Next, it will be described how the semiconductor module 20 suppresses a decrease in the current that can be output from the semiconductor chip within the allowable temperature range of the semiconductor chip.

[0057] Here, in a semiconductor module as described in Patent Document 1, in order to reduce the loss of the semiconductor chip and to reduce the size of the semiconductor module, semiconductor chips are arranged on one side and the other side of the printed circuit board and connected in parallel. However, when a semiconductor chip is arranged on one side of the printed circuit board, the thermal conductivity of the printed circuit board is relatively low, so the heat of the semiconductor chip arranged on one side of the printed circuit board is less likely to be conducted to the housing than the heat of the semiconductor chip arranged on the other side of the printed circuit board. This makes it easy for the temperature of the semiconductor chip arranged on one side of the printed circuit board to rise. Therefore, the temperature of the semiconductor chip arranged on one side of the printed circuit board is likely to reach the allowable temperature, and the on-resistance of the semiconductor chip arranged on one side of the printed circuit board is likely to increase. Therefore, the current flowing through the semiconductor chip arranged on one side of the printed circuit board is likely to decrease. Therefore, the current that can be output from the semiconductor chip arranged on one side of the printed circuit board within the allowable temperature of the semiconductor chip decreases. In addition, the temperature of the semiconductor chip arranged on one side of the printed circuit board is a constraint, so the current that can be output from the semiconductor chip arranged on the other side of the printed circuit board decreases.

[0058] Therefore, the total current Ic_sum that can be output from the semiconductor chips arranged on one side and the other side of the printed circuit board is reduced. For example, assume that only the semiconductor chips arranged on the other side of the printed circuit board, which are connected to the housing via a heat dissipation material, are driven. In this case, as shown in FIG. 8, at the allowable temperature of 125°C, the current that can be output from the semiconductor chips arranged on the other side of the printed circuit board is set to 80A. Furthermore, when the semiconductor chips arranged on the one side and the other side of the printed circuit board are driven, the temperature of the semiconductor chips arranged on the one side of the printed circuit board is likely to rise, and therefore is likely to reach the allowable temperature of 125°C. Therefore, at the allowable temperature of 125°C, the total current Ic_sum is set to 54A. Therefore, the current that can be output from the semiconductor chips is reduced from 80A to 54A. In FIG. 8, the temperature of the semiconductor chips arranged on the other side of the printed circuit board is indicated as Tb. The temperature of the semiconductor chips arranged on the one side of the printed circuit board is indicated as Tf.

[0059] In contrast to this, in the semiconductor module 20 of the present embodiment, the front-side first resistance Rfc1 is larger than the back-side first resistance Rbc1, that is, Rfc1>Rbc1.

[0060] This makes it difficult for a current to flow through the front-side first semiconductor chip 201. This suppresses a rise in temperature of the front-side first semiconductor chip 201. This suppresses the temperature of the front-side first semiconductor chip 201 from reaching the allowable temperature, and also suppresses an increase in the on-resistance of the front-side first semiconductor chip 201. This suppresses a decrease in the current that can be output from the front-side first semiconductor chip 201 within the allowable temperature of the front-side first semiconductor chip 201. Furthermore, by suppressing the temperature of the front-side first semiconductor chip 201 from reaching the allowable temperature, a decrease in the current that can be output from the back-side first semiconductor chip 251 is suppressed.

[0061] For this reason, as shown in Fig. 9, in the semiconductor module 20 of this embodiment, when the temperature of the front-side first semiconductor chip 201 is below the allowable temperature, the total current Ic_sum output from the front-side first semiconductor chip 201 and the back-side first semiconductor chip 251 is set to 80 A. Therefore, a decrease in the current that can be output from the semiconductor chip within the allowable temperature of the semiconductor chip is suppressed. In Fig. 9, the temperature of the front-side first semiconductor chip 201 is indicated as Tf. The temperature of the back-side first semiconductor chip 251 is indicated as Tb.

[0062] In the semiconductor module 20 of the present embodiment, the front-side second resistance Rfc2 is larger than the rear-side second resistance Rbc2, that is, Rfc2>Rbc2.

[0063] As a result, similarly to the above, a current does not easily flow through the front-side second semiconductor chip 202. This suppresses a rise in temperature of the front-side second semiconductor chip 202. This suppresses the temperature of the front-side second semiconductor chip 202 from reaching the allowable temperature, and also suppresses an increase in the on-resistance of the front-side second semiconductor chip 202. This suppresses a decrease in the current that can be output from the front-side second semiconductor chip 202 within the allowable temperature of the front-side second semiconductor chip 202. Furthermore, by suppressing the temperature of the front-side second semiconductor chip 202 from reaching the allowable temperature, a decrease in the current that can be output from the back-side second semiconductor chip 252 is suppressed.

[0064] Furthermore, in the semiconductor module 20 of this embodiment, the front-side first semiconductor chip 201 and the front-side second semiconductor chip 202 are mounted on the substrate front surface 2006. Also, the rear-side first semiconductor chip 251 and the rear-side second semiconductor chip 252 are mounted on the substrate rear surface 2007. This reduces the size of the semiconductor module 20 in the direction perpendicular to the thickness direction DT compared to a case where the semiconductor chips are mounted in parallel on only one of the substrate front surface 2006 and the substrate rear surface 2007. This prevents the semiconductor module 20 from becoming larger.

[0065] Furthermore, the semiconductor module 20 of the first embodiment also provides the following advantages.

[0066] [1-1] As shown in FIG. 5 and FIG. 6, the semiconductor module 20 further includes a rear-side first drain wiring 281, a junction wiring 225, and a via 2005. The rear-side first drain wiring 281 is connected to the substrate rear surface 2007 and the rear-side first drain electrode 2512. The junction wiring 225 of the fourth layer 2004 is connected to the rear-side first drain wiring 281 and the choke coil 300. The via 2005 is connected to the junction wiring 225 of the fourth layer 2004 and extends in the thickness direction DT. The junction wiring 225 of the third layer 2003 is formed between the substrate front surface 2006 and the substrate rear surface 2007 and is connected to the junction wiring 225 of the fourth layer 2004 through the via 2005. The rear-side first drain wiring 281 corresponds to the rear wiring. The junction wiring 225 of the fourth layer 2004 corresponds to the first junction wiring. The junction wiring 225 on the third layer 2003 corresponds to the second junction wiring.

[0067] Since the junction wiring 225 of the third layer 2003 is formed, the back-side first resistance Rbc1 is smaller than when the junction wiring 225 of the third layer 2003 is not present. This makes it easier for a current to flow from the back-side first drain electrode 2512 to the choke coil 300. This reduces the wiring loss of the current flowing from the back-side first drain electrode 2512 to the choke coil 300.

[0068] The semiconductor module 20 further includes a back-side second drain wiring 282. The back-side second drain wiring 282 is connected to the substrate back surface 2007 and the back-side second drain electrode 2522. The junction wiring 225 of the fourth layer 2004 is connected to the back-side second drain wiring 282 and the choke coil 300.

[0069] As a result, similarly to the above, the back side second resistance Rbc2 becomes smaller, so that a current easily flows from the back side second drain electrode 2522 to the choke coil 300. Therefore, the wiring loss for the current flowing from the back side second drain electrode 2522 to the choke coil 300 is reduced.

[0070] [1-2] The semiconductor module 20 includes a first driving circuit 241. The first driving circuit 241 drives the front-side first semiconductor chip 201 and the back-side first semiconductor chip 251. Furthermore, the distance from the first driving circuit 241 to the back-side first gate electrode 2513 is set to be the same as the distance from the first driving circuit 241 to the front-side first gate electrode 2013.

[0071] This makes the path lengths of signals output from the first drive circuit 241 to the front-side first semiconductor chip 201 and the back-side first semiconductor chip 251 the same. Therefore, the communication time between the first drive circuit 241 and the front-side first semiconductor chip 201 is the same as the communication time between the first drive circuit 241 and the back-side first semiconductor chip 251. This suppresses variations in the start of turning on the front-side first semiconductor chip 201 and the back-side first semiconductor chip 251.

[0072] The semiconductor module 20 also includes a second drive circuit 242. The second drive circuit 242 drives the front-side second semiconductor chip 202 and the back-side second semiconductor chip 252. Furthermore, the distance from the second drive circuit 242 to the back-side second gate electrode 2523 is set to be the same as the distance from the second drive circuit 242 to the front-side second gate electrode 2023.

[0073] This makes the path lengths of signals output from the second drive circuit 242 to the front-side second semiconductor chip 202 and the back-side second semiconductor chip 252 the same. Therefore, the communication time between the second drive circuit 242 and the front-side second semiconductor chip 202 is the same as the communication time between the second drive circuit 242 and the back-side second semiconductor chip 252. This suppresses variations in the start of turning on the front-side second semiconductor chip 202 and the back-side second semiconductor chip 252.

[0074] [1-3] As shown in FIG. 4, the front-side first gate wiring 231 extends in one direction Da. The back-side first gate wiring 291 extends in one direction Da. The front-side second gate wiring 232 extends in one direction Da. The back-side second gate wiring 292 extends in one direction Da. Also, as shown in FIG. 3 and FIG. 6, the direction of at least a part of the current flowing from the front-side first drain electrode 2012 to the choke coil 300 is perpendicular to the one direction Da. The direction of at least a part of the current flowing from the back-side first drain electrode 2512 to the choke coil 300 is perpendicular to the one direction Da. The direction of at least a part of the current flowing from the front-side second drain electrode 2022 to the choke coil 300 is perpendicular to the one direction Da. The direction of at least a part of the current flowing from the back-side second drain electrode 2522 to the choke coil 300 is perpendicular to the one direction Da.

[0075] As a result, the current flowing through the first front gate wiring 231, the first rear gate wiring 291, the second front gate wiring 232, and the second rear gate wiring 292 is less susceptible to the magnetic field caused by the current flowing from the first front drain electrode 2012 to the choke coil 300. Also, the current flowing through the first front gate wiring 231, the first rear gate wiring 291, the second front gate wiring 232, and the second rear gate wiring 292 is less susceptible to the magnetic field caused by the current flowing from the first rear drain electrode 2512 to the choke coil 300. Also, the current flowing through the first front gate wiring 231, the first rear gate wiring 291, the second front gate wiring 232, and the second rear gate wiring 292 is less susceptible to the magnetic field caused by the current flowing from the second front drain electrode 2022 to the choke coil 300. Moreover, the current flowing through the first front gate wiring 231, the first back gate wiring 291, the second front gate wiring 232 and the second back gate wiring 292 is less susceptible to the magnetic field caused by the current flowing from the second back drain electrode 2522 to the choke coil 300. For these reasons, noise in the signal to the first front gate electrode 2013, the signal to the first back gate electrode 2513, the signal to the second front gate electrode 2023 and the signal to the second back gate electrode 2523 is suppressed.

[0076] Second embodiment In the second embodiment, the semiconductor module 20 further includes a first resistor 401 and a second resistor 402, as shown in Figures 10 and 11. The rest is the same as in the first embodiment.

[0077] Here, the first resistor 401 is disposed on the substrate surface 2006 side, and is connected to the front-side first drain wiring 221 and the merging wiring 225 of the first layer 2001. The electric resistance of the first resistor 401 is greater than the electric resistance of the front-side first drain wiring 221. The first resistor 401 makes the front-side first resistance Rfc1 greater than the back-side first resistance Rbc1, that is, Rfc1>Rbc1. Here, the electric resistance of the first resistor 401 is greater than the electric resistance of the front-side first drain wiring 221, but may be greater than the electric resistance of the back-side first drain wiring 281.

[0078] Here, the second resistor 402 is disposed on the substrate surface 2006 side, and is connected to the front-side second drain wiring 222 and the merging wiring 225 of the first layer 2001. The electrical resistance of the second resistor 402 is greater than the electrical resistance of the front-side second drain wiring 222. The second resistor 402 makes the front-side second resistance Rfc2 greater than the back-side second resistance Rbc2, that is, Rfc2>Rbc2. Here, the electrical resistance of the second resistor 402 is greater than the electrical resistance of the front-side second drain wiring 222, but may be greater than the electrical resistance of the back-side second drain wiring 282.

[0079] Here, the electrical resistance of the first resistor 401 is the first resistance Rr1. The electrical resistance of the second resistor 402 is the second resistance Rr2. The on-resistance of the front-side first semiconductor chip 201 is the front-side first on-resistance Ron_f1. The on-resistance of the back-side first semiconductor chip 251 is the back-side first on-resistance Ron_b1. The on-resistance of the front-side second semiconductor chip 202 is the front-side second on-resistance Ron_f2. The on-resistance of the back-side second semiconductor chip 252 is the back-side second on-resistance Ron_b2.

[0080] The front-side first semiconductor chip 201, the back-side first semiconductor chip 251, and the first resistor 401 are formed so that the following relational expressions (1-1) and (1-2) are established. That is, the first resistance Rr1 is set to be 0.5 times or more the front-side first on-resistance Ron_f1 and 10.0 times or less the front-side first on-resistance Ron_f1. Also, the first resistance Rr1 is set to be 0.5 times or more the back-side first on-resistance Ron_b1 and 10.0 times or less the back-side first on-resistance Ron_b1.

[0081] Furthermore, the front-side second semiconductor chip 202, the back-side second semiconductor chip 252, and the second resistor 402 are formed so that the following relational expressions (2-1) and (2-2) are established. That is, the second resistance Rr2 is set to be 0.5 times or more the front-side second on-resistance Ron_f2 and 10.0 times or less the front-side second on-resistance Ron_f2. Also, the second resistance Rr2 is set to be 0.5 times or more the back-side second on-resistance Ron_b2 and 10.0 times or less the back-side second on-resistance Ron_b2.

[0082] Ron_f1×0.5≦Rr1≦Ron_f1×10.0 (1-1) Ron_b1×0.5≦Rr1≦Ron_b1×10.0 (1-2) Ron_f2×0.5≦Rr2≦Ron_f2×10.0 (2-1) Ron_b2×0.5≦Rr2≦Ron_b2×10.0 (2-2)

[0083] The semiconductor module 20 of the second embodiment is configured as described above. The second embodiment also provides the same advantages as the first embodiment. The second embodiment also provides the following advantages.

[0084] [2-1] The semiconductor module 20 further includes a first resistor 401. The first resistor 401 is connected to the front-side first drain wiring 221 and has a larger electrical resistance than the front-side first drain wiring 221. The first resistor 401 makes the front-side first resistance Rfc1 larger than the back-side first resistance Rbc1, that is, Rfc1>Rbc1. The front-side first drain wiring 221 corresponds to the front-side wiring.

[0085] This makes it easier for the front-side first resistance Rfc1 to be greater than the back-side first resistance Rbc1. Therefore, as in the above, current is less likely to flow through the front-side first semiconductor chip 201. This prevents the temperature of the front-side first semiconductor chip 201 from reaching the allowable temperature. This prevents a decrease in the current that can be output from the front-side first semiconductor chip 201 within the allowable temperature of the front-side first semiconductor chip 201, and also prevents a decrease in the current that can be output from the back-side first semiconductor chip 251.

[0086] The semiconductor module 20 further includes a second resistor 402. The second resistor 402 is connected to the front-side second drain wiring 222 and has an electric resistance greater than the electric resistance of the front-side second drain wiring 222. Due to the second resistor 402, the front-side second resistance Rfc2 is greater than the back-side second resistance Rbc2, i.e., Rfc2>Rbc2.

[0087] This makes it easier for the front-side second resistance Rfc2 to be greater than the back-side second resistance Rbc2. Therefore, as in the above, current is less likely to flow through the front-side second semiconductor chip 202. This prevents the temperature of the front-side second semiconductor chip 202 from reaching the allowable temperature. This prevents a decrease in the current that can be output from the front-side second semiconductor chip 202 within the allowable temperature of the front-side second semiconductor chip 202, and also prevents a decrease in the current that can be output from the back-side second semiconductor chip 252.

[0088] [2-2] The front-side first semiconductor chip 201, the back-side first semiconductor chip 251 and the first resistor 401 are formed so that the above relational expressions (1-1) and (1-2) are established.

[0089] Since the first resistance Rr1 is 0.5 times or more the front-side first on-resistance Ron_f1 and the back-side first on-resistance Ron_b1, a current is less likely to flow through the front-side first semiconductor chip 201. Furthermore, since the first resistance Rr1 is 10.0 times or less the front-side first on-resistance Ron_f1 and the back-side first on-resistance Ron_b1, a situation in which a current does not flow through the front-side first semiconductor chip 201 is suppressed.

[0090] Moreover, the front-side second semiconductor chip 202, the back-side second semiconductor chip 252, and the second resistor 402 are formed so that the above relational expressions (2-1) and (2-2) are established.

[0091] Since the second resistance Rr2 is 0.5 times or more the front-side second on-resistance Ron_f2 and the back-side second on-resistance Ron_b2, a current is less likely to flow through the front-side second semiconductor chip 202. Furthermore, since the second resistance Rr2 is 10.0 times or less the front-side second on-resistance Ron_f2 and the back-side second on-resistance Ron_b2, a situation in which a current does not flow through the front-side second semiconductor chip 202 is suppressed.

[0092] Third embodiment In the third embodiment, the semiconductor module 20 further includes a common wiring 403 and a resistor 405, as shown in Figures 12 and 13. The rest is the same as in the first embodiment.

[0093] The common wiring 403 is connected to the substrate surface 2006 in the thickness direction DT, and is also connected to the front-side first drain wiring 221 and the front-side second drain wiring 222. The front-side first drain wiring 221 corresponds to the front-side first wiring. The front-side second drain wiring 222 corresponds to the front-side second wiring.

[0094] Here, the resistor 405 is disposed on the substrate surface 2006 side, and is connected to the front side second drain wiring 222 and the merging wiring 225 of the first layer 2001. The electrical resistance of the resistor 405 is greater than the electrical resistance of the front side second drain wiring 222. The electrical resistance of the resistor 405 may be greater than the electrical resistances of the front side first drain wiring 221, the back side first drain wiring 281, and the back side second drain wiring 282.

[0095] The electrical resistance of the resistor 405 is set to be 0.5 times or more the first front-side on resistance Ron_f1 and the first back-side on resistance Ron_b1, and 10.0 times or less the first front-side on resistance Ron_f1 and the first back-side on resistance Ron_b1. The electrical resistance of the resistor 405 is set to be 0.5 times or more the second front-side on resistance Ron_f2 and the second back-side on resistance Ron_b2, and 10.0 times or less the second front-side on resistance Ron_f2 and the second back-side on resistance Ron_b2.

[0096] Moreover, the common wiring 403 and the resistor 405 make the front-side first resistance Rfc1 larger than the rear-side first resistance Rbc1, i.e., Rfc1>Rbc1. Furthermore, the resistor 405 makes the front-side second resistance Rfc2 larger than the rear-side second resistance Rbc2, i.e., Rfc2>Rbc2.

[0097] The semiconductor module 20 of the third embodiment is configured as described above. The third embodiment also provides the same effects as the first embodiment. The third embodiment also provides the same effects as those described in [2-1] and [2-2] above.

[0098] (Fourth embodiment) In the fourth embodiment, the semiconductor module 20 further includes a common wiring 403 and a resistor 405, as shown in Figures 14, 15, 16 and 17. The rest is the same as in the first embodiment.

[0099] The common wiring 403 is connected to the substrate surface 2006 , the front-side first drain wiring 221 and the front-side second drain wiring 222 .

[0100] Here, the resistor 405 is disposed on the back surface 2007 side of the substrate instead of on the front surface 2006 side of the substrate. Furthermore, the resistor 405 is connected to the housing 305 in the thickness direction DT via a TIM or the like.

[0101] Moreover, the resistor 405 is connected to the rear first drain wiring 281 and the junction wiring 225 of the fourth layer 2004. Furthermore, the resistor 405 is connected to the front first drain wiring 221 through the junction wiring 225 of the fourth layer 2004 and the via 2005. Therefore, the current from the front first drain electrode 2012 flows to the choke coil 300 through the front first drain wiring 221, the via 2005, the junction wiring 225 of the fourth layer 2004, the resistor 405, the rear first drain wiring 281, and the rear second drain wiring 282. Moreover, the current from the front second drain electrode 2022 flows to the common wiring 403 through the front second drain wiring 222. A current from the common wiring 403 flows through the front side first drain wiring 221 , the via 2005 , the merging wiring 225 of the fourth layer 2004 , the resistor 405 , the rear side first drain wiring 281 and the rear side second drain wiring 282 to the choke coil 300 .

[0102] Furthermore, the electrical resistance of the resistor 405 is greater than the electrical resistance of the front-side first drain wiring 221 and the front-side second drain wiring 222. Note that the electrical resistance of the resistor 405 may be greater than the electrical resistance of the back-side first drain wiring 281 and the back-side second drain wiring 282.

[0103] Moreover, the resistor 405 makes the front-side first resistance Rfc1 larger than the rear-side first resistance Rbc1, i.e., Rfc1>Rbc1. Furthermore, the common wiring 403 and the resistor 405 make the front-side second resistance Rfc2 larger than the rear-side second resistance Rbc2, i.e., Rfc2>Rbc2.

[0104] The semiconductor module 20 of the fourth embodiment is configured as described above. The fourth embodiment also provides the same effects as the first embodiment. The fourth embodiment also provides the same effects as those described in [2-1] and [2-2] above. Furthermore, the fourth embodiment also provides the effects described below.

[0105] [3] The resistor 405 is connected to the housing 305. This allows heat generated in the resistor 405 to be conducted to the housing 305. This prevents the resistor 405 from increasing in temperature. This makes it easier for the temperature of the resistor 405 to drop below the allowable temperature. This prevents the resistor 405 from being damaged.

[0106] Fifth embodiment In the fifth embodiment, as shown in Figures 18, 19 and 20, the semiconductor module 20 further includes a heat dissipation member 410. Other than this, the same effects as those of the second embodiment are achieved.

[0107] The heat dissipation member 410 is formed of a metal having a relatively high thermal conductivity, such as aluminum or copper. The heat dissipation member 410 is connected to the surface of the front-side first semiconductor chip 201 opposite to the substrate surface 2006 in the thickness direction DT via a TIM or the like. The heat dissipation member 410 is connected to the surface of the front-side second semiconductor chip 202 opposite to the substrate surface 2006 in the thickness direction DT via a TIM or the like. The heat dissipation member 410 is connected to the surface of the first resistor 401 opposite to the substrate surface 2006 in the thickness direction DT via a TIM or the like. The heat dissipation member 410 is connected to the surface of the second resistor 402 opposite to the substrate surface 2006 in the thickness direction DT via a TIM or the like.

[0108] The semiconductor module 20 of the fifth embodiment is configured as described above. The fifth embodiment also provides the same effects as the second embodiment. The fifth embodiment also provides the following effects.

[0109] [4-1] The semiconductor module 20 further includes a heat dissipation member 410. The heat dissipation member 410 is connected to the side of the front-side first semiconductor chip 201 opposite to the substrate surface 2006.

[0110] As a result, heat generated in the front-side first semiconductor chip 201 is conducted to the heat dissipation member 410. This suppresses a rise in temperature of the front-side first semiconductor chip 201. Therefore, as in the above, the temperature of the front-side first semiconductor chip 201 is suppressed from reaching the allowable temperature. This suppresses a decrease in the current that can be output from the front-side first semiconductor chip 201 within the allowable temperature of the front-side first semiconductor chip 201, and also suppresses a decrease in the current that can be output from the back-side first semiconductor chip 251.

[0111] Moreover, the heat dissipation member 410 is connected to the side of the front-side second semiconductor chip 202 opposite to the substrate surface 2006 .

[0112] As a result, heat generated in the front-side second semiconductor chip 202 is conducted to the heat dissipation member 410. This suppresses a rise in temperature of the front-side second semiconductor chip 202. Therefore, as in the above, the temperature of the front-side second semiconductor chip 202 is suppressed from reaching the allowable temperature. Therefore, within the allowable temperature of the front-side second semiconductor chip 202, a decrease in the current that can be output from the front-side second semiconductor chip 202 is suppressed, and a decrease in the current that can be output from the back-side second semiconductor chip 252 is suppressed.

[0113] [4-2] The heat dissipation member 410 is connected to the first resistor 401 and the second resistor 402.

[0114] As a result, heat generated in the first resistor 401 and the second resistor 402 is conducted to the heat dissipation member 410. This suppresses the temperature rise of the first resistor 401 and the second resistor 402. This makes it easier for the temperatures of the first resistor 401 and the second resistor 402 to be equal to or lower than the allowable temperature. This suppresses damage to the first resistor 401 and the second resistor 402.

[0115] (Other embodiments) The present disclosure is not limited to the above-described embodiments, and appropriate modifications can be made to the above-described embodiments. Furthermore, in each of the above-described embodiments, it goes without saying that the elements constituting the embodiments are not necessarily essential, except in cases where they are particularly clearly stated as essential or where they are clearly considered essential in principle.

[0116] In each of the above embodiments, FETs are given as the transistors of the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252. In contrast, the transistors of the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252 are not limited to FETs, and may be IGBTs or the like. IGBT is an abbreviation for Insulated Gate Bipolar Transistor.

[0117] In each of the above embodiments, the first front-side semiconductor chip 201, the first back-side semiconductor chip 251, the second front-side semiconductor chip 202, and the second back-side semiconductor chip 252 each have a transistor that rectifies the AC current stepped down from the transformer 16. In contrast, the device that rectifies the AC current stepped down from the transformer 16 is not limited to being a transistor. The device that rectifies the AC current stepped down from the transformer 16 may be, for example, a rectifier diode or the like.

[0118] In each of the above embodiments, the choke coil 300 is given as an element that smoothes the current rectified by the front-side first semiconductor chip 201, the back-side first semiconductor chip 251, the front-side second semiconductor chip 202, and the back-side second semiconductor chip 252. However, the above element is not limited to the choke coil 300, and may be, for example, an RLC circuit or the like.

[0119] In each of the above embodiments, the number of semiconductor chips arranged in the direction perpendicular to the thickness direction DT is two, but is not limited to this. The number of semiconductor chips arranged in the direction perpendicular to the thickness direction DT may be one, or three or more. [Explanation of symbols]

[0120] 20 Semiconductor Module 200 boards 201 Front side first semiconductor chip 251 Backside 1st semiconductor chip 300 Choke Coil 305 Case 401 1st resistor 402 2nd resistor 403 Common Wiring 405 resistor

Claims

1. A semiconductor module, comprising: A substrate (200) having a substrate front surface (2006) that is a surface intersecting a thickness direction (DT) and a substrate back surface (2007) that is a surface opposite to the substrate front surface; a front-side semiconductor chip (201) mounted on the surface of the substrate, rectifying a current flowing through a first electrode (2011) and outputting the rectified current from a second electrode (2012); A backside semiconductor chip (251) mounted on the backside of the substrate, rectifying a current flowing through a third electrode (2511) and outputting the rectified current from a fourth electrode (2512); a housing (305) connected to the backside semiconductor chip on the opposite side to the substrate; An element (300) for smoothing a current rectified by the front-side semiconductor chip and the back-side semiconductor chip; Equipped with the front-side semiconductor chip has a characteristic that a resistance of the front-side semiconductor chip increases with an increase in temperature of the front-side semiconductor chip; the backside semiconductor chip has a characteristic that a resistance of the backside semiconductor chip increases with an increase in temperature of the backside semiconductor chip; the front-side semiconductor chip and the back-side semiconductor chip are connected in parallel to the element; The semiconductor module, wherein an electrical resistance (Rfc1) for a current flowing from the second electrode to the element is greater than an electrical resistance (Rbc1) for a current flowing from the fourth electrode to the element.

2. A front side wiring (221) connected to the substrate surface and the second electrode; A resistor (401) connected to the front side wiring and having an electrical resistance greater than the electrical resistance of the front side wiring; Further equipped with 2 . The semiconductor module according to claim 1 , wherein the resistor provides a larger electrical resistance to a current flowing from the second electrode to the element than a current flowing from the fourth electrode to the element.

3. the front-side semiconductor chip and the back-side semiconductor chip each have a transistor; The on-resistance of the front-side semiconductor chip is Ron_f, The on-resistance of the backside semiconductor chip is Ron_b, If the electrical resistance of the resistor is Rr, The front-side semiconductor chip, the back-side semiconductor chip, and the resistor are Ron_f×0.5≦Rr≦Ron_f×10.0 Ron_b×0.5≦Rr≦Ron_b×10.0 3. The semiconductor module according to claim 2, which is formed so that the following holds true:

4. The front-side semiconductor chip is a front-side first semiconductor chip, The backside semiconductor chip is a backside first semiconductor chip, The semiconductor module includes: a front-side second semiconductor chip (202) mounted on the surface of the substrate, rectifying a current flowing through a fifth electrode (2021) and outputting the rectified current from a sixth electrode (2022); A rear-side second semiconductor chip (252) mounted on the rear surface of the substrate, rectifying a current flowing through a seventh electrode (2521) and outputting the rectified current from an eighth electrode (2522); a front-side first wiring (221) connected to the substrate surface and the second electrode; a front-side second wiring (222) connected to the substrate surface and the sixth electrode; a common wiring (403) connected to the substrate surface, the front-side first wiring, and the front-side second wiring; a resistor (405) connected to the front-side second wiring and having an electrical resistance greater than the electrical resistance of the front-side second wiring; Further equipped with an electrical resistance of a current flowing from the second electrode to the element by the common wiring and the resistor is greater than an electrical resistance of a current flowing from the fourth electrode to the element; 2. The semiconductor module according to claim 1, wherein the resistor provides an electrical resistance (Rfc2) for a current flowing from the sixth electrode to the element greater than an electrical resistance (Rbc2) for a current flowing from the eighth electrode to the element.

5. A front side wiring (221) connected to the substrate surface and the second electrode; A backside wiring (281) connected to the back side of the substrate and the fourth electrode; a resistor (405) connected to the backside wiring and the housing, and connected to the frontside wiring through a via (2005), the resistor having an electrical resistance greater than the electrical resistance of the frontside wiring and the backside wiring; Further equipped with 2 . The semiconductor module according to claim 1 , wherein the resistor provides a larger electrical resistance to a current flowing from the second electrode to the element than a current flowing from the fourth electrode to the element.

6. A backside wiring (281) connected to the back side of the substrate and the fourth electrode; A first merging wiring (225) connected to the rear surface of the substrate, the rear wiring, and the element; a via (2005) connected to the first joining wiring and extending in the thickness direction; A second merging wiring (225) formed between the substrate front surface and the substrate back surface and connected to the first merging wiring through the via; The semiconductor module according to claim 1 , further comprising:

7. The semiconductor module further includes a drive circuit (241) for driving the front-side semiconductor chip and the back-side semiconductor chip, the front-side semiconductor chip and the back-side semiconductor chip each have a transistor; A semiconductor module described in any one of claims 1, 2, 4, and 5, wherein the distance from the driving circuit to the gate electrode (2013) of the front-side semiconductor chip is the same as the distance from the driving circuit to the gate electrode (2513) of the back-side semiconductor chip.

8. the front-side semiconductor chip has a transistor; The semiconductor module includes: Further comprising a gate wiring (231) connected to a gate electrode (2013) of the front-side semiconductor chip, The gate wiring extends in one direction (Da) perpendicular to the thickness direction, 6. The semiconductor module according to claim 1, wherein a direction (Df1) of at least a part of a current flowing from the second electrode to the element is perpendicular to the one direction.

9. the backside semiconductor chip has a transistor; The semiconductor module includes: Further comprising a gate wiring (291) connected to a gate electrode (2513) of the backside semiconductor chip; The gate wiring extends in one direction (Da) perpendicular to the thickness direction, 6. The semiconductor module according to claim 1, wherein a direction (Db1) of at least a part of a current flowing from the fourth electrode to the element is perpendicular to the one direction.

10. 6. The semiconductor module according to claim 1, further comprising a heat dissipation member (410) connected to a side of the front-side semiconductor chip opposite to the substrate surface.

11. The semiconductor module includes: A heat dissipation member (410) connected to the side of the front-side semiconductor chip opposite to the substrate surface; A front side wiring (221) connected to the substrate surface and the second electrode; a resistor (405) connected to the heat dissipation member and the front-side wiring and having an electrical resistance greater than the electrical resistance of the front-side wiring; Further equipped with 2 . The semiconductor module according to claim 1 , wherein the resistor provides a larger electrical resistance to a current flowing from the second electrode to the element than a current flowing from the fourth electrode to the element.

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