Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device 100 that is improved in load capacity.SOLUTION: A semiconductor device 100 comprises: a semiconductor chip 1; a support substrate 2 which has a first surface 2a and a second surface 2b facing in mutually opposite directions, and has the semiconductor chip 1 connected to the first surface 2a; a sealing resin 3 which at least seals the semiconductor chip 1 and the first surface 2a of the support substrate 2; one or two or more columns 4 which have a first end 4a and a second end 4b where the first end 4a is in contact with the first surface 2a of the support substrate 2 and the second end 4b is located at the same height with a surface 3a of the sealing resin 3 or protrudes from the surface 3a of the sealing resin 3; and a heat radiation substrate 9 which is pressed and joined to the second surface 2b of the support substrate 2.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a transistor package for use in an inverter and a method for manufacturing the transistor package. The transistor is in thermal contact with a substrate and is sealed with a sealing material. The substrate is sintered to a heat sink via a sintered layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 080801 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a substrate sealed with a sealing material is sintered to a heat sink via a sintered layer. Therefore, the heat and load required for sinter bonding are directly applied to the sealing material, causing the temperature of the sealing material to rise above the glass transition point, resulting in plastic deformation of the sealing material.

[0005] The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device with improved load resistance and a method for manufacturing a semiconductor device with improved load resistance. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention comprises a semiconductor chip, a supporting substrate having a first surface and a second surface, with the semiconductor chip connected to the first surface, a sealing resin sealing at least the semiconductor chip and the first surface of the supporting substrate, one or more pillars having a first end and a second end, the first end contacting the first surface of the supporting substrate and the second end being positioned at the same height as the surface of the sealing resin or protruding above the surface of the sealing resin, and a heat dissipation substrate pressure-bonded to the second surface of the supporting substrate. Effect of the Invention

[0007] According to one aspect of the present invention, the load resistance of a semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 1A is a cross-sectional view showing the configuration of a semiconductor device 100 according to the first embodiment. [Figure 1B] FIG. 1B is a plan view showing the configuration of the semiconductor device 100 according to the first embodiment. [Diagram 2] FIG. 2 is a flowchart showing an example of a method for manufacturing the semiconductor device 100 according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view showing an ultrasonic inspection for checking the pressurized bonding state. [Figure 4A] FIG. 4A is a cross-sectional view showing the configuration of a semiconductor device 101 according to the second embodiment. [Figure 4B] FIG. 4B is a plan view showing the configuration of the semiconductor device 101 according to the second embodiment. [Figure 5A] FIG. 5A is a cross-sectional view showing a configuration of a semiconductor device 102 according to the first modification. [Figure 5B] FIG. 5B is a cross-sectional view showing the configuration of a semiconductor device 103 according to the second modification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a semiconductor device and a method for manufacturing a semiconductor device according to the embodiments will be described in detail with reference to the drawings. Note that the embodiments described below are comprehensive or specific examples. The numerical values, shapes, materials, installation positions and connection forms of components shown in the following embodiments are examples and are not intended to limit the present disclosure. In addition, among the components in the following embodiments, components that are not described in the independent claims showing the highest concept are described as optional components. Furthermore, the dimensional ratios in the drawings are exaggerated for the convenience of explanation and may differ from the actual ratios. In addition, the following embodiments and examples thereof may include similar components, and similar components are given common symbols and overlapping explanations are omitted.

[0010] (First embodiment) [Semiconductor device 100] Fig. 1A is a cross-sectional view showing the configuration of the semiconductor device 100 according to the first embodiment. Fig. 1B is a plan view showing the configuration of the semiconductor device 100 according to the first embodiment. The cross-sectional view of Fig. 1A is a cross-sectional view taken along the line AA in Fig. 1B. Fig. 1B shows a state in which the sealing resin 3 in Fig. 1A has been removed.

[0011] The semiconductor device 100 includes one or more semiconductor chips 1, a support substrate 2, a sealing resin 3, pillars 4, and a heat dissipation substrate 9.

[0012] The semiconductor chip 1 is an individual semiconductor element (die), and is, for example, one or more power switching elements such as an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), and a thyristor formed on a silicon (Si) substrate or a silicon carbide (SiC) substrate. In the embodiment, the number of semiconductor chips 1 is four, but the number of semiconductor chips 1 is not limited to this, and may be one to three, or five or more. As shown in FIG. 1B, the semiconductor chips 1 are arranged in a matrix on a support substrate 2.

[0013] The support substrate 2 has a first surface 2a and a second surface 2b facing in opposite directions. The first surface 2a faces the Z direction shown in FIGS. 1A and 1B, and the second surface 2b faces the opposite direction to the Z direction. The semiconductor chip 1 is connected to the first surface 2a of the support substrate 2. The semiconductor chip 1 is bonded to the support substrate 2 by an adhesive layer containing, for example, silver or copper (not shown). Heat generated by the semiconductor chip 1 is transferred to the support substrate 2 via the adhesive layer.

[0014] As shown in FIG. 1A, the support substrate 2 has a ceramic substrate 6, wiring patterns 5a and 5b bonded to a first surface 2a of the ceramic substrate 6, and a metal film 7 bonded to a second surface 2b of the ceramic substrate 6. The semiconductor chip 1 is connected to the surface of the wiring pattern 5b, which is a part of the first surface 2a of the support substrate 2. The support substrate 2 is, for example, a DBC (Direct Bonded Copper) substrate in which wiring containing copper is directly bonded to a ceramic substrate 6 made of aluminum oxide, aluminum nitride, silicon nitride, or the like. Alternatively, the support substrate 2 may be a DBA (Direct Bonded Aluminum) substrate in which wiring containing aluminum instead of copper is directly bonded. The wiring patterns 5a and 5b and the metal film 7 correspond to wiring containing copper or aluminum.

[0015] The sealing resin 3 seals at least the semiconductor chip 1 and the first surface 2a of the support substrate 2. The sealing resin 3 further seals the wiring patterns 5a and 5b. The sealing resin 3 has a function of protecting the semiconductor chip 1 and the wiring patterns 5a and 5b from the environment such as light, heat, and humidity. The sealing resin 3 is made of a thermosetting molding material mainly composed of epoxy resin and added with silica filler and the like. Although not shown in the figure, the sealing resin 3 seals wiring such as a lead frame, a bus bar, and a bonding wire electrically connected to the semiconductor chip 1 in addition to the semiconductor chip 1. Of course, a part of the pillar 4 including the first end 4a (the end opposite to the Z direction) is also sealed by the sealing resin 3. As shown in FIG. 1A, it is desirable that the surface 3a of the sealing resin 3 is a flat surface that is approximately parallel to the first surface 2a.

[0016] The pillars 4 are made of a high-strength material selected from the group including metal, carbon, and fiber-reinforced plastic. The pillars 4 have a first end 4a and a second end 4b. The first end 4a of the pillars 4 is in contact with the surface of the wiring pattern 5a, which is a part of the first surface 2a of the support substrate 2. The second end 4b of the pillars 4 is located at the same height as the surface 3a of the sealing resin 3, or protrudes from the surface 3a of the sealing resin 3 as shown in FIG. 1A. At least in the pressurized bonding process for bonding the heat dissipation substrate 9 to the second surface 2b of the support substrate 2, the second end 4b of the pillars 4 may be at the same height as the surface 3a of the sealing resin 3 or protrude from the surface 3a. For example, when the thermal expansion coefficient of the pillars 4 is larger than that of the sealing resin 3, the second end 4b of the pillars 4 may be at the same height as the surface 3a of the sealing resin 3 or protrude from the surface 3a only during the pressurized bonding process, and the second end 4b of the pillars 4 may not protrude from the surface 3a under normal conditions.

[0017] The pillars 4 extend in a direction (Z direction) perpendicular to the first surface 2a of the support substrate 2. Here, "perpendicular" includes the range of angle error resulting from the processing accuracy of the pillars 4 and the attachment accuracy of the pillars 4 to the first surface 2a of the support substrate 2. The pillars 4 can transmit the load F1 applied from their second ends 4b in the direction opposite to the Z direction to the support substrate 2, from the first ends 4a.

[0018] As shown in FIG. 1B, the pillar 4 is disposed in the center of the first surface 2a of the support substrate 2. In detail, the pillar 4 is in contact with the wiring pattern 5a located in the central portion of the first surface 2a of the support substrate 2. The pillar 4 can apply a uniform load within the first surface 2a. The pillar 4 is, for example, a quadrangular pillar. In other words, the shape of the end faces exposed at the first end 4a and the second end 4b is quadrangular. The shape of the end faces is not particularly limited and may be circular or another polygonal shape.

[0019] The support substrate 2 has a plurality of wiring patterns 5a, 5b arranged on the first surface 2a. The pillars 4 are electrically connected to the wiring pattern 5a which is electrically insulated from the semiconductor chip 1. The wiring pattern 5a to which the pillars 4 are connected is electrically insulated from the wiring pattern 5b to which the semiconductor chip 1 is connected. The wiring patterns 5b on which the semiconductor chips 1 are arranged may also be electrically insulated from each other.

[0020] The heat dissipation substrate 9 is pressure-bonded to the second surface 2b of the support substrate 2 via a pressure bonding layer 8. Heat from the semiconductor chip 1 transferred to the support substrate 2 is transferred to the heat dissipation substrate 9 via the pressure bonding layer 8. The pressure bonding layer 8 includes a sintered bonding layer containing, for example, silver or copper. The sintered bonding layer improves heat resistance and heat dissipation compared to lead solder. The use of a sintered bonding material containing metal as a main component reduces the thermal resistance of the semiconductor device 100, enabling greater integration of the semiconductor chip 1 and increased power of the semiconductor device 100.

[0021] [Method of Manufacturing Semiconductor Device 100] 2 is a flowchart showing an example of a method for manufacturing the semiconductor device 100 according to the first embodiment. The semiconductor device 100 is manufactured through a first step S1 and a second step S2. First, in the first step S1, a power module having a semiconductor chip 1, a support substrate 2, a sealing resin 3, and pillars 4 shown in FIGS. 1A and 1B is manufactured. Specifically, the first step S1 includes steps S11 to S13.

[0022] In step S11 (die bonding), the individual semiconductor chip 1 is fixed onto the support substrate 2. Proceeding to step S12, the pillars 4 are fixed onto the support substrate 2. There is no particular restriction on the specific method for fixing the semiconductor chip 1 and the pillars 4, and silver sintering or copper sintering may be used, for example. Thereafter, proceeding to step S13, the semiconductor chip 1 and the first surface 2a of the support substrate 2 are sealed with resin.

[0023] Thereafter, the power module is taken out of the clean room, and the second step S2 is performed. In the second step S2, the heat dissipation substrate 9 is pressure-bonded to the power module. Specifically, the second surface 2b of the support substrate 2 and the heat dissipation substrate 9 are superimposed via a sintered bonding material containing copper or silver, and heat and pressure are applied to the sintered bonding material through the second end 4b of the pillar 4 and the heat dissipation substrate 9, thereby pressure-bonding the heat dissipation substrate 9 to the second surface 2b of the support substrate 2. Although not shown, a load of the same magnitude as the load F1 in FIG. 1A is applied to the heat dissipation substrate 9 from the opposite direction (Z direction). Specifically, the semiconductor device 100 is sandwiched from both sides in the Z direction between a pair of pressure surfaces provided in a manufacturing device (heater) for the semiconductor device 100, and a load and heat are applied to the upper end 4b of the pillar 4 and the back surface of the heat dissipation substrate 9. For example, a pressure of 10 to 20 MPa is applied from the direction indicated by the load F1 (opposite direction to the Z direction) in a high-temperature environment of 200° to 300°. This allows the heat dissipation substrate 9 to be pressure-bonded to the power module.

[0024] [Effects] As described above, according to the first embodiment, the following advantageous effects can be obtained.

[0025] After the semiconductor chip 1 is molded with the sealing resin 3, the power module (1-4) is taken out of the clean room. Thereafter, the power module (1-4) and the heat dissipation substrate 9 are superimposed, sandwiched between the pressure surfaces of the semiconductor manufacturing equipment (heater) from above and below perpendicular to the first surface 2a, and heated and pressurized. As a result, the heat dissipation substrate 9 is pressure-bonded to the second surface 2b of the support substrate 2. If there are no pillars 4, the sealing resin 3 is directly pressurized and heated. This may cause the sealing resin 3 to plastically deform or may cause the sealing resin 3 to be heated to a temperature exceeding the glass transition point. For this reason, it has been necessary to use a sealing resin with high heat and pressure resistance, or to perform sintering bonding under low temperature and low pressure conditions.

[0026] Therefore, the pillars 4, whose first ends 4a are in contact with the first surface 2a of the support substrate 2, are extended in the normal direction of the first surface 2a. The second ends 4b of the pillars 4 are made to be at the same height as the surface of the sealing resin 3 or protrude from the surface. As a result, during pressure bonding, pressure and heat are applied to the second ends 4b of the pillars 4 instead of the sealing resin 3, and the pressure and heat can be transmitted to the support substrate 2 via the pillars 4. This prevents the sealing resin 3 from being directly pressurized and heated, thereby preventing the sealing resin 3 from being plastically deformed and exceeding its glass transition point. In this way, direct pressure is avoided on the sealing resin 3, and the load-bearing capacity of the semiconductor device 100 is improved.

[0027] In addition, as shown below, the inspection accuracy is improved in ultrasonic inspection for checking the pressure bonding state. As shown in FIG. 3, ultrasonic waves 12 emitted from an ultrasonic inspection device 11 enter the column 4 from the second end 4b of the column 4 toward the support substrate 2. The ultrasonic waves 12 penetrate the inside of the column 4 and enter the support substrate 2. The ultrasonic waves (reflected waves 13) reflected by the pressure bonding layer 8 travel in the opposite direction along the same path as the ultrasonic waves 12, and return to the ultrasonic inspection device 11. The ultrasonic inspection device 11 can check the pressure bonding state of the pressure bonding layer 8 using the reflected waves 13. Since part of the ultrasonic waves 12 and the reflected waves 13 are reflected at the interface of materials with different acoustic impedances, the intensities of the transmitted ultrasonic waves 12 and the reflected waves 13 are attenuated.

[0028] When the pillars 4 are not present, the number of material interfaces through which the ultrasonic waves 12 and the reflected waves 13 pass, such as resin, bus bar wiring, bonding wires, and die bonding material, is large, and the ultrasonic waves 12 and the reflected waves 13 are significantly attenuated, resulting in a decrease in inspection accuracy. According to the first embodiment, the ultrasonic waves 12 and the reflected waves 13 can be transmitted through the pillars 4. Therefore, the number of material interfaces is reduced compared to when the pillars 4 are not present, and therefore the attenuation of the ultrasonic waves 12 and the reflected waves 13 is suppressed, improving inspection accuracy.

[0029] 1B, the pillar 4 is disposed in the center of the support substrate 2 when viewed from the normal direction (Z direction) of the first surface 2a. When the number of pillars 4 is one, the in-plane distribution of the load F1 applied from the pillar 4 to the support substrate 2 can be made flat.

[0030] The pillars 4 may be made of a material mainly composed of metal such as aluminum or copper. The pillars 4 are made of a material mainly composed of metal, which is a dense body with few voids inside. Reflection due to voids inside the pillars 4 is suppressed. Attenuation of the ultrasonic waves 12 and the reflected waves 13 that pass through the inside of the pillars 4 is suppressed, and the inspection accuracy can be improved.

[0031] The wiring pattern 5a to which the pillar 4 is connected and the wiring pattern 5b to which the semiconductor chip 1 is connected are electrically insulated. In other words, the pillar 4 is electrically connected to the wiring pattern 5a electrically insulated from the semiconductor chip 1. When the voltage applied to the semiconductor chip 1 is also applied to the pillar 4, the layout of the pillar 4 may be restricted in order to ensure electrical insulation of the pillar 4. Therefore, by electrically connecting the pillar 4 to the wiring pattern 5a electrically insulated from the semiconductor chip 1, the voltage applied to the semiconductor chip 1 is prevented from being applied to the pillar 4. Therefore, the pillar 4 can be electrically insulated from the semiconductor chip 1 by the wiring patterns 5a and 5b of the support substrate 2. It is not necessary to ensure an insulating distance between the pillar 4 and other components inside the semiconductor device 101 and external components, and the semiconductor device 100 and a device incorporating the semiconductor device 100 can be made smaller.

[0032] Second embodiment Fig. 4A is a cross-sectional view showing the configuration of the semiconductor device 101 according to the second embodiment. Fig. 4B is a plan view showing the configuration of the semiconductor device 101 according to the second embodiment. The cross-sectional view of Fig. 4A is a cross-sectional view taken along the line BB in Fig. 4B. Fig. 4B shows a state in which the sealing resin 3 in Fig. 4A has been removed.

[0033] The semiconductor device 101 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in that the semiconductor device 101 has a plurality of columns (for example, five). By providing a plurality of columns, the load applied to the columns is dispersed, and the load per column can be reduced. Compared to the case where there is a single column 4, the in-plane distribution of the load F1 applied to the support substrate 2 from the columns 4A to 4E can be made even flatter.

[0034] The semiconductor device 101 has pillars 4A to 4E. As shown in FIG. 4B, the pillar 4A is disposed in the center of the first surface 2a of the support substrate 2, similar to the pillar 4 in the first embodiment. The remaining pillars 4B to 4E are disposed at positions on the first surface 2a that are point-symmetric with respect to the center of the support substrate 2, as viewed from the normal direction of the first surface 2a of the support substrate 2. For example, as shown in FIG. 4B, they are disposed at the corners of the first surface 2a of the support substrate 2 having a rectangular shape. Alternatively, the pillars 4B to 4E may be disposed in the center of each side of the first surface 2a.

[0035] The wiring pattern 5a on which the pillars 4A to 4E are arranged is electrically insulated from the wiring pattern 5b on which the semiconductor chip 1 is arranged. Furthermore, the wiring patterns 5a on which the pillars 4A to 4E are arranged are electrically insulated from each other. This makes it unnecessary to ensure an insulating distance between the pillars 4A to 4E and other components inside the semiconductor device 101 and between the external components and the other components, and allows the semiconductor device 101 and a device incorporating the semiconductor device 101 to be miniaturized.

[0036] The second ends 4b of all the columns 4A to 4E are at the same height as or protrude above the surface of the sealing resin 3. This allows the load F2 to be applied to all the columns 4A to 4E. It is also desirable that all the columns 4A to 4E have the same length. The second ends 4b of all the columns 4A to 4E can be disposed in the same plane. When the pressure surface of the heater is flat, a uniform load F2 can be applied to the columns 4A to 4E.

[0037] (Modification) The following describes first and second modifications of the heat dissipation substrate 9.

[0038] Fig. 5A is a cross-sectional view showing the configuration of a semiconductor device 102 according to Modification 1. Fig. 5B is a cross-sectional view showing the configuration of a semiconductor device 103 according to Modification 2. The cross-sectional views of Fig. 5A and Fig. 5B correspond to the cross-sectional view of Fig. 1A and are cross-sectional views taken along the AA cut surface of Fig. 1B.

[0039] In the semiconductor device 102 according to the first embodiment, cooling fins 9Aa are formed on the rear surface of the heat dissipation substrate 9A. The surface area for exchanging heat with the outside air is increased, improving the heat exchange efficiency.

[0040] 5B, a cooling flow path 9Ba through which a cooling liquid flows is formed inside the heat dissipation substrate 9B. Heat can be dissipated to the outside of the semiconductor device 103 by the cooling liquid flowing through the cooling flow path 9Ba.

[0041] As described above, the embodiment of the present invention has been described, but the description and drawings forming a part of this disclosure should not be understood as limiting this invention. From this disclosure, various alternative embodiments, examples and operating techniques will become apparent to those skilled in the art.

[0042] Modification 1 (FIG. 5A) and Modification 2 (FIG. 5B) can also be applied to the semiconductor device 101 according to the second embodiment shown in FIG. 4A and FIG. 4B. Modification 1 (FIG. 5A) and Modification 2 (FIG. 5B) may be implemented in combination. [Explanation of symbols]

[0043] 1. Semiconductor chip 2 Support substrate 2a 1st page 2b 2nd side 3 Sealing resin 3a Surface of sealing resin 4, 4A~4E pillars 4a 1st end 4b 2nd end 5a, 5b Wiring patterns 9 Heat dissipation board 9Aa Cooling fin 9Ba Cooling Channel

Claims

1. A semiconductor chip; a support substrate having a first surface and a second surface facing in opposite directions, the semiconductor chip being connected to the first surface; a sealing resin that seals at least the semiconductor chip and the first surface of the support substrate; one or more pillars each having a first end and a second end, the first end being in contact with the first surface of the support substrate, and the second end being located at the same height as a surface of the sealing resin or protruding from the surface of the sealing resin; a heat dissipation substrate pressure-bonded to the second surface of the support substrate; A semiconductor device comprising:

2. The semiconductor device according to claim 1 , wherein the number of the pillars is more than one.

3. 2 . The semiconductor device according to claim 1 , wherein the one or more pillars are arranged at a center of the support substrate or at a position on the first surface that is point-symmetric with respect to the center when viewed from a normal direction of the first surface.

4. 2. The semiconductor device according to claim 1, wherein the pillars are made of a material containing a metal as a main component.

5. 2 . The semiconductor device according to claim 1 , wherein the support substrate has a plurality of metal patterns arranged on the first surface, and the pillars are electrically connected to the metal patterns that are electrically insulated from the semiconductor chip.

6. The semiconductor device according to claim 1 , wherein the heat dissipation substrate has at least one of a cooling fin and a cooling flow path.

7. 2. The semiconductor device according to claim 1, wherein the second surface of the support substrate and the heat dissipation substrate are sintered and bonded to each other using a material mainly containing a metal.

8. A semiconductor chip; a support substrate having a first surface and a second surface facing in opposite directions, the semiconductor chip being connected to the first surface; a sealing resin that seals at least the semiconductor chip and the first surface of the support substrate; a pillar having a first end and a second end, the first end being in contact with the first surface of the support substrate, and the second end being located at the same height as a surface of the sealing resin or protruding from the surface of the sealing resin; The second surface of the support substrate and the heat dissipation substrate are overlapped with each other via a pressure bonding material; applying heat and pressure to the second ends of the posts and the heat dissipation substrate to pressure-bond the heat dissipation substrate to the second surface of the support substrate; A method for manufacturing a semiconductor device.

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