Display device

Abstract

To provide a display device that can improve the yield or improve the display quality.SOLUTION: A display device in an embodiment includes a first lower electrode having a first end part, a second lower electrode having a second end part that is apart from the first end part, a rib layer including a first pixel opening that overlaps with the first lower electrode and a second pixel opening that overlaps with the second lower electrode and covering the first end part and the second end part, a partition wall including a lower part existing between the first pixel opening and the second pixel opening and disposed over the rib layer, and an upper part having an end part projecting from a side surface of the lower part, a first organic layer disposed in contact with the first lower electrode through the first pixel opening and emitting light in accordance with voltage application, a second organic layer disposed in contact with the second lower electrode through the second pixel opening and emitting light in accordance with voltage application, a first upper electrode covering the first organic layer, and a second upper electrode covering the second organic layer. The first end part overlaps with the lower part in a plan view, and the second end part does not overlap with the lower part in the plan view.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present embodiment relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have been put to practical use. For this type of display device, technology that enables improvement of yield and display quality is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of improving the yield or the display quality. [Means for solving the problem]

[0005] According to one aspect of the embodiment, the display device includes a first lower electrode having a first end, a second lower electrode having a second end spaced from the first end, a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode, a rib layer covering the first end and the second end, a partition including a lower portion located between the first pixel opening and the second pixel opening and disposed above the rib layer, and an upper portion having an end protruding from a side surface of the lower portion, a first organic layer contacting the first lower electrode through the first pixel opening and emitting light in response to application of a voltage, a second organic layer contacting the second lower electrode through the second pixel opening and emitting light in response to application of a voltage, a first upper electrode covering the first organic layer, and a second upper electrode covering the second organic layer. Furthermore, the first end overlaps the lower portion in a plan view, and the second end does not overlap the lower portion in a plan view.

[0006] According to another aspect of the embodiment, a display device includes a lower electrode having a first end and a second end, a rib layer having a pixel opening overlapping the lower electrode and covering the first end and the second end, a lower portion disposed above the rib layer, and an upper portion having an end protruding from a side surface of the lower portion, a partition wall surrounding the pixel opening, an organic layer contacting the lower electrode through the pixel opening and emitting light in response to application of a voltage, and an upper electrode covering the organic layer. Further, the first end overlaps the lower portion in a plan view, and the second end does not overlap the lower portion in a plan view. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels according to the first embodiment. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line AB in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the display device taken along line CD in FIG. [Diagram 5]FIG. 5 is a diagram showing an example of a layer structure that can be applied to the organic layer. [Figure 6] FIG. 6 is a schematic enlarged plan view of the subpixel shown in FIG. [Figure 7] FIG. 7 is a schematic enlarged cross-sectional view of the lower electrode, the rib layer, and the partition wall shown on the left in FIG. [Figure 8] FIG. 8 is a schematic enlarged cross-sectional view of the vicinity of both ends of the lower electrode shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of a configuration according to a comparative example. [Figure 10] FIG. 10 is a schematic cross-sectional view of a configuration according to another comparative example. [Figure 11] FIG. 11 is a schematic cross-sectional view of a display device according to the second embodiment. [Figure 12] FIG. 12 is a schematic enlarged plan view of a subpixel according to the third embodiment. [Figure 13] FIG. 13 is a schematic enlarged plan view of a sub-pixel according to the fourth embodiment. [Figure 14] FIG. 14 is a schematic enlarged plan view of a sub-pixel according to the fifth embodiment. [Figure 15] FIG. 15 is a schematic enlarged plan view of a sub-pixel according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0009] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to a first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] A gate electrode of the pixel switch 2 is connected to a scanning line GL. A source electrode of the pixel switch 2 is connected to a signal line SL. A drain electrode of the pixel switch 2 is connected to a gate electrode of the driving transistor 3 and a capacitor 4. A source electrode of the driving transistor 3 is connected to a power line PL and a capacitor 4. A drain electrode of the driving transistor 3 is connected to a display element DE.

[0017] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of the sub-pixels SP1, SP2, and SP3. In the example of Fig. 2, a column in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and a column in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed. These columns are alternately arranged in the X direction.

[0019] For example, the subpixels SP1, SP2, and SP3 have the same width in the X direction. The width of the subpixel SP1 in the Y direction is equal to the combined width of the subpixels SP2 and SP3 in the Y direction.

[0020] The layout of the subpixels SP1, SP2, and SP3 and the sizes of the subpixels SP1, SP2, and SP3 are not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 may be aligned in the X direction. Furthermore, at least two of the subpixels SP1, SP2, and SP3 may have the same size.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.

[0022] In the display region DA, partition walls 6 are disposed. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the partition walls 6 have a lattice shape in a plan view and surround each of the pixel openings AP1, AP2, and AP3.

[0023] Subpixel SP1 has a display element DE1 including a lower electrode LE1 overlapping pixel aperture AP1. Subpixel SP2 has a display element DE2 including a lower electrode LE2 overlapping pixel aperture AP2. Subpixel SP3 has a display element DE3 including a lower electrode LE3 overlapping pixel aperture AP3.

[0024] The pixel circuits 1 of the subpixels SP1, SP2, and SP3 are disposed below the lower electrodes LE1, LE2, and LE3, respectively. The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0025] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in Fig. 2. Fig. 4 is a schematic cross-sectional view of the display device DSP taken along the line CD in Fig. 2.

[0026] 3 and 4, a circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in FIG.

[0027] The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11. The contact holes CH1, CH2, and CH3 shown in FIG.

[0028] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5.

[0029] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhang shape.

[0030] 3, the lower portion 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5, and is formed thinner than the axial layer 64. For example, both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64.

[0031] 3, the upper portion 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64. The second top layer 66 is disposed on the first top layer 65. The second top layer 66 may be formed thinner than the first top layer 65 as shown. The second top layer 66 may also have a smaller width than the first top layer 65.

[0032] As shown in Fig. 3, a laminated film FL1 and a sealing layer SE11 are disposed in the subpixel SP1, and a laminated film FL2 and a sealing layer SE12 are disposed in the subpixel SP2. Also, as shown in Fig. 4, a laminated film FL3 and a sealing layer SE13 are disposed in the subpixel SP3.

[0033] The laminated film FL1 includes an organic layer OR1, an upper electrode UE1, and a cap layer CP1. The laminated film FL2 includes an organic layer OR2, an upper electrode UE2, and a cap layer CP2. The laminated film FL3 includes an organic layer OR3, an upper electrode UE3, and a cap layer CP3.

[0034] The organic layer OR1 covers the rib layer 5 and is in contact with the lower electrode LE1 through a pixel opening AP1. The organic layer OR2 covers the rib layer 5 and is in contact with the lower electrode LE2 through a pixel opening AP2. The organic layer OR3 covers the rib layer 5 and is in contact with the lower electrode LE3 through a pixel opening AP3.

[0035] The upper electrodes UE1, UE2, and UE3 cover the organic layers OR1, OR2, and OR3, respectively. The upper electrodes UE1, UE2, and UE3 are in contact with at least one of the bottom layer 63 and the axis layer 64 of the partition wall 6. The cap layers CP1, CP2, and CP3 cover the upper electrodes UE1, UE2, and UE3, respectively.

[0036] The lower electrode LE1 and the laminated film FL1 overlap with the pixel aperture AP1 to form the display element DE1 of the subpixel SP1. The lower electrode LE2 and the laminated film FL2 overlap with the pixel aperture AP2 to form the display element DE2 of the subpixel SP2. The lower electrode LE3 and the laminated film FL3 overlap with the pixel aperture AP3 to form the display element DE3 of the subpixel SP3.

[0037] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6 (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6 (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6 (a part that constitutes the display element DE3).

[0038] The sealing layers SE11, SE12, and SE13 are formed to be thicker than the laminated films FL1, FL2, and FL3. The sealing layers SE11, SE12, and SE13 are not divided by the partition wall 6 and continuously cover the laminated films FL1, FL2, and FL3 and the side portions of the partition wall 6, respectively.

[0039] 3, the laminate film FL1 and the sealing layer SE11 on the partition 6 between the subpixels SP1 and SP2 are separated from the laminate film FL2 and the sealing layer SE12 on the partition 6. In the example of Fig. 4, the laminate film FL2 and the sealing layer SE12 on the partition 6 between the subpixels SP2 and SP3 are separated from the laminate film FL3 and the sealing layer SE13 on the partition 6.

[0040] 3 and 4, the sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are continuously provided at least throughout the entire display area DA, and a part of them extends into the peripheral area SA.

[0041] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0042] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. The reflective layer can be made of a metal material with excellent light reflectivity, such as silver. Each conductive oxide layer can be made of a transparent conductive oxide, such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0044] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0045] 5 is a diagram showing an example of a layer structure applicable to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including an emitting layer EML. In this embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of emitting layers EML.

[0046] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of the light emitted by the organic layers OR1, OR2, and OR3, respectively. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0047] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed, for example, from different metal materials. The metal material of the bottom layer 63 may be, for example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). The metal material of the shaft layer 64 may be, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of multiple layers. The shaft layer 64 may also include a layer formed from an insulating material.

[0048] For example, the first top layer 65 of the partition wall 6 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. The metal material of the first top layer 65 can be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide of the second top layer 66 can be, for example, ITO or IZO. The upper portion 62 may have a single-layer structure formed of a specific material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0049] A common voltage is supplied to the partition 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. That is, the partition 6 serves as a wiring that supplies the common voltage to the upper electrodes UE1, UE2, and UE3. A pixel voltage corresponding to the video signal of the signal line SL is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0050] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in the red wavelength region.

[0051] As another example, the emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the emitting layers EML into light of a color corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the emitting layers EML to generate light of a color corresponding to the subpixels SP1, SP2, and SP3.

[0052] Fig. 6 is a schematic enlarged plan view of the subpixels SP1, SP2, and SP3 shown in Fig. 2. These subpixels SP1, SP2, and SP3 constitute the above-mentioned pixel PX. Hereinafter, the shapes of the rib layer 5, the partition wall 6, and the lower electrodes LE1, LE2, and LE3 will be described in detail with reference to Figs. 4 to 6.

[0053] 6, the lower electrode LE1 has ends E1a, E1b, E1c, and E1d. The lower electrode LE2 has ends E2a, E2b, E2c, and E2d. The lower electrode LE3 has ends E3a, E3b, E3c, and E3d. The ends E1a, E1b, E2a, E2b, E3a, and E3b extend parallel to the Y direction. The ends E1c, E1d, E2c, E2d, E3c, and E3d extend parallel to the X direction. Each end is covered by a rib layer 5.

[0054] 6 (the portion with the dot pattern) corresponds to the shape of the lower portion 61, more specifically, the shape of the axis layer 64. The lower portion 61 has roughly the same width overall. However, a portion 61X of the lower portion 61 that extends in the X direction between the subpixels SP2 and SP3 has a width greater than the other portions.

[0055] In this embodiment, a portion (first end) of each end of the lower electrodes LE1, LE2, LE3 overlaps with the axis layer 64, and the remaining portion (second end) does not overlap with the axis layer 64. Here, the ends of the lower electrodes LE1, LE2, LE3 overlap with the lower portion 61 means that these ends are located below the lower portion 61.

[0056] Specifically, ends E1a and E1c of the lower electrode LE1 overlap with the lower portion 61, but ends E1b and E1d do not overlap with the lower portion 61. Furthermore, ends E2a, E2c, and E2d of the lower electrode LE2 overlap with the lower portion 61, but end E2b does not overlap with the lower portion 61. Furthermore, ends E3a and E3c of the lower electrode LE3 overlap with the lower portion 61, but ends E3b and E3d do not overlap with the lower portion 61.

[0057] For example, when focusing on the lower electrodes LE1, LE2 and the lower portion 61 therebetween, one of the ends of these lower electrodes LE1, LE2 overlaps with the lower portion 61, and the other does not overlap with the lower portion 61. In this manner, the relationship in which the lower portion 61 overlaps with one end (first end) of the adjacent lower electrode, but does not overlap with the other end (second end) is established in most of the lower portion 61. However, the portion 61X overlaps with both the end E2d of the lower electrode LE2 and the end E3c of the lower electrode LE3.

[0058] 6, the partition wall 6 (lower portion 61) overlapping with the end portion E1a has a protrusion P1 protruding toward the pixel aperture AP1. The pixel aperture AP1 has a recess R recessed into a shape corresponding to the protrusion P1. The contact hole CH1 is located between the end portion E1a and the pixel aperture AP1, and overlaps with the protrusion P1.

[0059] An end E2d of the lower electrode LE2 has a protrusion P2 protruding toward the lower electrode LE3. An end E3c of the lower electrode LE3 has a protrusion P3 protruding toward the lower electrode LE2. Both of these protrusions P2 and P3 overlap with the portion 61X. A contact hole CH2 overlaps with the protrusion P2 and the portion 61X. A contact hole CH3 overlaps with the protrusion P3 and the portion 61X.

[0060] The positions of the contact holes CH1, CH2, and CH3 are not limited to the example in Fig. 6. For example, the contact hole CH1 may be provided between the end E1c and the pixel aperture AP1. In this case, the partition wall 6 overlapping with the end E1c may have a protrusion P1.

[0061] 3 and 4, a step portion ST corresponding to the ends of the lower electrodes LE1, LE2, and LE3 is generated on the upper surface of the rib layer 5. For example, the step portion ST (first step portion) generated by the end portion located below the partition wall 6, such as the ends E1a, E2a, E2c, E2d, and E3c shown in Fig. 3 and 4, is covered by the bottom layer 63 and the shaft layer 64. The upper surfaces of the shaft layer 64, the first top layer 65, and the second top layer 66 may be deformed according to the step portion ST.

[0062] On one hand, for example, like the end portions E1b, E2b, E3d shown in FIGS. 3 and 4, the step portion ST (second step portion) generated by the end portion not located below the partition wall 6 is not covered by the bottom layer 63 and the shaft layer 64. The laminated films FL1, FL2, FL3 can be deformed according to such a step portion ST.

[0063] FIG. 7 is a schematic enlarged cross-sectional view of the lower electrodes LE1, LE2, the rib layer 5, and the partition wall 6 shown on the left side of FIG. 3. Hereinafter, with this figure being typically used, the details of the configuration applicable to a pair of adjacent lower electrodes, the rib layer 5 overlapping the pair of lower electrodes, and the partition wall 6 overlapping one end portion of the pair of lower electrodes will be described.

[0064] The rib layer 5 shown in FIG. 7 has a width Wa. The partition wall 6 has a width Wb smaller than the width Wa (Wa > Wb). The width Wa corresponds to the distance between the pixel openings AP1, AP2. The width Wb corresponds to the width of the upper portion 62, more specifically, the width of the first top layer 65.

[0065] The distance Da between the lower electrodes LE1, LE2 is smaller than the width Wa (Da < Wa). The distance Da is, for example, equivalent to the width Wb. In one example, the width Wa is 8 to 10 μm, and the widths Wb and Da are 4 to 5 μm respectively.

[0066] The end portion E2b of the lower electrode LE2 and the upper portion 62 are spaced apart from each other in plan view. The distance Db in plan view between the end portion E2b and the upper portion 62 is, for example, at least 1 / 2 of the total thickness T of the rib layer 5 and the lower portion 61 (bottom layer 63 and shaft layer 64).

[0067] In the present embodiment, the distance Dc1 (first distance) between the end portion E1a and the pixel opening AP1 in plan view is larger than the distance Dc2 (second distance) between the end portion E2b and the pixel opening AP2 in plan view (Dc1 > Dc2). The distance Dc1 corresponds to the width of the region where the lower electrode LE1 is covered by the rib layer 5 in FIG. 7. The distance Dc2 corresponds to the width of the region where the lower electrode LE2 is covered by the rib layer 5 in FIG. 7.

[0068] The structure shown in Fig. 7 can also be applied to the structure near adjacent lower electrodes LE1 and LE3, the structure near adjacent lower electrodes LE2 and LE3, and the structure near two adjacent lower electrodes LE1. However, the structure near portion 61X shown in Fig. 6 is as shown on the left side of Fig. 4 and is different from the structure in Fig. 7.

[0069] Fig. 8 is a schematic enlarged cross-sectional view of the vicinity of ends E1a and E1b of the lower electrode LE1 shown in Fig. 3. In Fig. 7, the structure has been described by focusing on the ends of two adjacent lower electrodes. Such a structure also occurs when focusing on the end of one lower electrode as illustrated in Fig. 8.

[0070] 8, the end E1b and the upper portion 62 of the lower electrode LE1 are spaced apart from each other in a plan view. A distance Db between the end E1b and the upper portion 62 in a plan view is, for example, equal to or greater than ½ of the total thickness T of the rib layer 5 and the lower portion 61. In addition, a distance Dc1 between the end E1a and the pixel opening AP1 is greater than a distance Dc2 between the end E1b and the pixel opening AP1 (Dc1>Dc2).

[0071] For example, the structures of ends E1c and E1d of the lower electrode LE1, ends E2a and E2b of the lower electrode LE2, ends E3a and E3b of the lower electrode LE3, and further ends E3c and E3d of the lower electrode LE3 are similar to those shown in FIG.

[0072] 9 and 10 are schematic cross-sectional views of a configuration according to a comparative example, which focus on the ends E1a and E2b of the lower electrodes LE1 and LE2, the rib layer 5, and the partition wall 6, as in FIG.

[0073] 9, neither the end E1a of the lower electrode LE1 nor the end E2b of the lower electrode LE2 is located below the partition wall 6. As a result, a step portion ST formed by these ends E1a and E2b is exposed from the lower portion 61.

[0074] When the partition wall 6 is formed, layers to be processed into the bottom layer 63, the axis layer 64, the first top layer 65, and the second top layer 66 are formed over the entire display area DA. These layers may deform in response to the step portion ST. If the step portion ST is designed to be close to the lower portion 61, the end portion of the upper portion 62 (the first top layer 65 and the second top layer 66) protruding from the lower portion 61 may include a portion that is deformed due to the effect of the step portion ST. Specifically, the end portion of the upper portion 62 may be warped upward.

[0075] Each layer constituting the laminated films FL1, FL2, FL3 is formed over the entire display area DA by vapor deposition and is divided by the overhanging partition wall 6. If the end of the upper part 62 is curved upward, for example, the organic layers OR1, OR2, OR3 may adhere to a wide area of ​​the lower part 61, which may hinder contact between the lower part 61 and the upper electrodes UE1, UE2, UE3 to be formed later.

[0076] 9, it is necessary to sufficiently separate the ends E1a, E2b of the lower electrodes LE1, LE2 from the partition wall 6. For example, by setting the distance Db in a plan view between the upper portion 62 and the ends E1a, E2b to be equal to or greater than ½ of the total thickness T of the rib layer 5 and the lower portion 61 (Db≧T / 2) as described above, it is possible to suppress shape defects at the ends of the upper portion 62.

[0077] 9, however, it is necessary to ensure a distance Db on both sides of the partition 6. This also increases the width Wa of the rib layer 5. As an example, when the width Wb of the partition 6 is 4 to 5 μm, the width Wa of the rib layer 5 must be 10 to 12 μm in the configuration of FIG. 9. When the width Wa of the rib layer 5 increases in this way, the pixel apertures AP1, AP2, AP3 become smaller accordingly, and the aperture ratio of the sub-pixels SP1, SP2, SP3 decreases.

[0078] 10, both ends E1a, E2b of the lower electrodes LE1, LE2 are located below the lower portion 61. As a result, both steps ST caused by the ends E1a, E2b are covered by the lower portion 61. In this case, it is possible to suppress shape defects of the end of the upper portion 62 caused by the step ST.

[0079] It is difficult to make the distance Da between the lower electrodes LE1, LE2, and LE3 smaller than, for example, 4 to 5 μm. Therefore, it is necessary to increase the width Wb of the partition wall 6 in the configuration of FIG.

[0080] In addition, in the vicinity of the partition 6, the deposition material emitted from the deposition source is blocked by the upper portion 62, so the thickness of the laminated films FL1, FL2, FL3 is reduced. Therefore, in order to form the laminated films FL1, FL2, FL3 with a good thickness at the pixel openings AP1, AP2, AP3, the partition 6 and the pixel openings AP1, AP2, AP3 must be separated to a certain extent. Considering such a margin, the width Wa of the rib layer 5 needs to be 10 to 12 μm even in the example of FIG.

[0081] 7, the width Wa of the rib layer 5 can be reduced while suppressing the shape defect of the upper portion 62, and the aperture ratio of the subpixels SP1, SP2, and SP3 can be increased. This makes it possible to improve the yield of the display device DSP and to enhance the display quality.

[0082] 7, the step ST caused by the end E1a of the lower electrode LE1 is covered by the lower portion 61, thereby suppressing the deformation of the upper portion 62 caused by the step ST. In addition, by setting the distance Db to be equal to or greater than ½ of the total thickness T, the deformation of the upper portion 62 caused by the step ST caused by the end E2b of the lower electrode LE2 is also suppressed.

[0083] 7, since the distance Db is ensured, even if the distance Dc2 between the end E2b and the pixel aperture AP2 is reduced, the laminated film FL2 can be formed with a good thickness at the pixel aperture AP2. This makes it possible to reduce the width Wa of the rib layer 5 compared to the comparative examples of FIGS.

[0084] Note that, here, the effects of this embodiment have been described by focusing on the structure near the ends of adjacent lower electrodes LE1, LE2 as shown in Figures 7, 9, and 10, but the same effects can be obtained based on the structure near the ends of adjacent lower electrodes LE1, LE3, the structure near the ends of adjacent lower electrodes LE2, LE3, and the structure near the ends of two adjacent lower electrodes LE1.

[0085] The second to sixth embodiments will be described below. The configuration of the display device DSP not mentioned in each embodiment is the same as that of the first embodiment.

[0086] [Second embodiment] Fig. 11 is a schematic cross-sectional view of a display device DSP according to a second embodiment. The cross-section shown here corresponds to a cut along the X direction of the subpixel SP1 shown in Fig. 2 and Fig. 3. In this figure, the substrate 10, the circuit layer 11, the resin layers RS1 and RS2, and the sealing layer SE2 are omitted.

[0087] As in the first embodiment, the end E1a (first end) of the lower electrode LE1 is located below the lower portion 61 of the partition wall 6, and the end E1b (second end) is spaced apart from the partition wall 6 in the X direction. As a result, the step ST of the rib layer 5 caused by the end E1a is covered by the lower portion 61, while the step ST caused by the end E1b is exposed from the lower portion 61.

[0088] The upper electrode UE1 has ends Ea and Eb in the X direction. The end Ea (third end) is located on the end E1a side of the lower electrode LE1. The end Eb (fourth end) is located on the end E1b side of the lower electrode LE1.

[0089] 11, the end Ea is in contact with the lower portion 61 (the bottom layer 63 and the axis layer 64). Meanwhile, the end Eb is spaced apart from the lower portion 61. Such a configuration can be realized, for example, by tilting the deposition source of the upper electrode UE1 with respect to the Z direction. By tilting the deposition source, it is possible to form the upper electrode UE1 such that at least the end Ea is in good contact with the lower portion 61.

[0090] In addition, since the upper electrode UE1 is thin, there is a possibility that it may be divided by the step portion ST generated by the end portion E1b. On the other hand, the step portion ST generated by the end portion E1a is covered by the lower portion 61. Therefore, the division of the upper electrode UE1 caused by the step portion ST is suppressed, and the lower portion 61 and the upper electrode UE1 can be satisfactorily conducted to each other.

[0091] Although the structure of the subpixel SP1 has been described here, the same structure can be applied to the subpixels SP2 and SP3. That is, the upper electrodes UE2 and UE3 may have an end portion in contact with the lower portion 61 and an end portion spaced apart from the lower portion 61. In one example, the upper electrodes UE1 and UE2 are in contact with at least the portion 61X shown in FIG. 6.

[0092] [Third embodiment] Fig. 12 is a schematic enlarged plan view of the subpixels SP1, SP2, and SP3 according to the third embodiment. In the example of Fig. 12, ends E1b and E1c of the lower electrode LE1, ends E2b, E2c, and E2d of the lower electrode LE2, and ends E3b and E3c of the lower electrode LE3 overlap with the lower portion 61. On the other hand, ends E1a and E1d of the lower electrode LE1, ends E2a of the lower electrode LE2, and ends E3a and E3d of the lower electrode LE3 do not overlap with the lower portion 61.

[0093] 12, the partition wall 6 (lower portion 61) overlapping with the end portion E1b has a protrusion P1 protruding toward the pixel aperture AP1. The pixel aperture AP1 has a recess R recessed in a shape corresponding to the protrusion P1. The contact hole CH1 is located between the end portion E1b and the pixel aperture AP1, and overlaps with the protrusion P1.

[0094] [Fourth embodiment] Fig. 13 is a schematic enlarged plan view of the subpixels SP1, SP2, and SP3 according to the fourth embodiment. In the example of Fig. 13, ends E1a and E1d of the lower electrode LE1, ends E2a, E2c, and E2d of the lower electrode LE2, and ends E3a and E3c of the lower electrode LE3 overlap with the lower portion 61. On the other hand, ends E1b and E1c of the lower electrode LE1, ends E2b of the lower electrode LE2, and ends E3b and E3d of the lower electrode LE3 do not overlap with the lower portion 61.

[0095] [Fifth embodiment] Fig. 14 is a schematic enlarged plan view of the subpixels SP1, SP2, and SP3 according to the fifth embodiment. In the example of Fig. 14, ends E1a and E1d of the lower electrode LE1, ends E2a and E2d of the lower electrode LE2, and ends E3a, E3c, and E3d of the lower electrode LE3 overlap with the lower portion 61. On the other hand, ends E1b and E1c of the lower electrode LE1, ends E2b and E2c of the lower electrode LE2, and end E3b of the lower electrode LE3 do not overlap with the lower portion 61.

[0096] [Sixth embodiment] Fig. 15 is a schematic enlarged plan view of the sub-pixels SP1, SP2, and SP3 according to the fifth embodiment. In the example of Fig. 15, an end E1c of the lower electrode LE1, ends E2a, E2b, and E2d of the lower electrode LE2, and ends E3a, E3b, E3c, and E3d of the lower electrode LE3 overlap with the lower portion 61. That is, in the example of Fig. 15, the entire periphery of the lower electrode LE3 overlaps with the lower portion 61. On the other hand, ends E1a, E1b, and E1d of the lower electrode LE1 and end E2c of the lower electrode LE2 do not overlap with the lower portion 61.

[0097] Even in the configurations of the third to sixth embodiments described above, a configuration is realized in which, except for the ends E2d and E3c, one of the ends of the adjacent lower electrodes overlaps with the lower portion 61 and the other does not overlap. Therefore, the same effect as in the first embodiment can be obtained. In the third to sixth embodiments, the configuration described with reference to FIG. 7 can also be applied to the ends of the two adjacent lower electrodes, the rib layer 5 covering these ends, and the lower portion 61 thereon.

[0098] The positional relationship between the ends of the lower electrodes LE1, LE2, LE3 and the lower portion 61 is not limited to that exemplified in each embodiment. For example, in each embodiment, the end E2d of the lower electrode LE1 and the end E3c of the lower electrode LE3 overlap with the lower portion 61 (portion 61X), but at least one of the ends E2d and E3c does not have to overlap with the lower portion 61.

[0099] All display devices that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0100] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0101] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0102] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...sub-pixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a first bottom electrode having a first end; a second lower electrode having a second end spaced apart from the first end; a rib layer having a first pixel opening overlapping the first lower electrode and a second pixel opening overlapping the second lower electrode, the rib layer covering the first end portion and the second end portion; a partition wall including a lower portion located between the first pixel opening and the second pixel opening and disposed above the rib layer, and an upper portion having an end portion protruding from a side surface of the lower portion; a first organic layer that is in contact with the first lower electrode through the first pixel opening and emits light in response to application of a voltage; a second organic layer that is in contact with the second lower electrode through the second pixel opening and emits light in response to application of a voltage; a first upper electrode covering the first organic layer; a second upper electrode covering the second organic layer; Equipped with The first end overlaps with the lower portion in a plan view, The second end does not overlap with the lower portion in a plan view. Display device.

2. The second end and the upper portion are spaced apart in a plan view. The display device according to claim 1 .

3. A distance between the second end and the upper portion in a plan view is equal to or greater than ½ of a total thickness of the rib layer and the lower portion. The display device according to claim 2 .

4. an upper surface of the rib layer has a first step portion generated by the first end portion, The lower portion covers the first step portion. The display device according to claim 1 .

5. an upper surface of the rib layer has a second step portion generated by the second end portion; The lower portion does not cover the second step portion. The display device according to claim 4.

6. a first distance between the first end and the first pixel opening in a plan view is greater than a second distance between the second end and the second pixel opening in a plan view; The display device according to claim 1 .

7. a pixel circuit disposed below the first lower electrode; an organic insulating layer disposed between the first lower electrode and the pixel circuit; Further equipped with the first lower electrode is connected to the pixel circuit through a contact hole provided in the organic insulating layer; the contact hole is located between the first end and the first pixel opening in a plan view. The display device according to claim 1 .

8. the partition wall has a protrusion protruding toward the first pixel opening in a plan view, the contact hole overlaps with the protruding portion in a plan view. The display device according to claim 7.

9. The lower portion is A shaft layer formed of a metal material; a bottom layer formed of a metal material different from that of the shaft layer and positioned between the shaft layer and the rib layer; Including, The display device according to claim 1 .

10. The upper portion is a first top layer formed of a metallic material; a second top layer formed of a transparent conductive oxide and disposed on the first top layer; Including, The display device according to claim 1 .

11. a bottom electrode having a first end and a second end; a rib layer having a pixel opening overlapping the lower electrode and covering the first end and the second end; a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion and surrounding the pixel opening; an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer; Equipped with The first end overlaps with the lower portion in a plan view, The second end does not overlap with the lower portion in a plan view. Display device.

12. The second end and the upper portion are spaced apart in a plan view. The display device according to claim 11.

13. A distance between the second end and the upper portion in a plan view is equal to or greater than ½ of a total thickness of the rib layer and the lower portion. The display device according to claim 12.

14. an upper surface of the rib layer has a first step portion generated by the first end portion, The lower portion covers the first step portion. The display device according to claim 11.

15. an upper surface of the rib layer has a second step portion generated by the second end portion; The lower portion does not cover the second step portion. The display device according to claim 14.

16. a first distance between the first end and the pixel opening in a plan view is greater than a second distance between the second end and the pixel opening in a plan view; The display device according to claim 11.

17. A pixel circuit disposed below the lower electrode; an organic insulating layer disposed between the lower electrode and the pixel circuit; Further equipped with the lower electrode is connected to the pixel circuit through a contact hole provided in the organic insulating layer; the contact hole is located between the first end and the pixel opening in a plan view. The display device according to claim 11.

18. the partition wall has a protrusion protruding toward the pixel opening in a plan view, the contact hole overlaps with the protruding portion in a plan view. The display device according to claim 17.

19. the upper electrode has a third end on the first end side and a fourth end on the second end side, the third end contacts the lower portion; The fourth end is spaced from the lower portion. The display device according to claim 11.

20. The lower portion is A shaft layer formed of a metal material; a bottom layer formed of a metal material different from that of the shaft layer and positioned between the shaft layer and the rib layer; Including, The display device according to claim 11.

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