Semiconductor device

Abstract

To reduce a planar surface size of each semiconductor unit in a construction in which a plurality of semiconductor units are connected in parallel.SOLUTION: A semiconductor device 100 includes: a plurality of semiconductor units 30 connected in parallel; a housing case 10 that surrounds the plurality of semiconductor units 30; a lid part that is installed in the housing case 10, and is opposite to the plurality of semiconductor units 30; a wiring part that is installed at the lid part; and a plurality of connection parts corresponding to the plurality of semiconductor units 30, respectively. Each of the plurality of semiconductor units 30 comprises: a first conductor; a semiconductor chip installed in the first conductor; and a second conductor for control connected to the semiconductor chip. Each of the plurality of connection parts is positioned between the second conductor of the semiconductor unit 30 corresponding to the connection part and the wiring part, and electrically connects the second conductor and the wiring part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices using various semiconductor chips have been proposed in the past. For example, Patent Document 1 discloses a semiconductor device including a mounting board on which a semiconductor chip is mounted, a container for accommodating the mounting board, and a lid for closing the opening of the container. The tip of a connection member bonded to the mounting board is pressed against a circuit pattern provided on the back surface of the lid. Patent Document 2 discloses a semiconductor device including a power semiconductor element bonded to an insulating board, a case for accommodating the power semiconductor element, and a cover for closing the opening of the case. A spring terminal is provided that penetrates the cover and reaches the outside of the case. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-112585 A [Patent Document 2] JP 2006-165499 A Summary of the Invention [Problem to be solved by the invention]

[0004] Meanwhile, a semiconductor device has been proposed in which a plurality of semiconductor units including semiconductor chips are connected in parallel for the purpose of controlling large currents, etc. In the above configuration, a conductive pattern for electrically connecting the control electrodes of each semiconductor chip across the plurality of semiconductor units needs to be provided in each semiconductor unit. Therefore, there is a problem that the reduction in size of each semiconductor unit is limited. In consideration of the above circumstances, one aspect of the present disclosure aims to reduce the planar size of each semiconductor unit in a configuration in which a plurality of semiconductor units are connected in parallel. [Means for solving the problem]

[0005] In order to solve the above problems, a semiconductor device according to one embodiment of the present disclosure comprises a plurality of semiconductor units connected in parallel, a container case surrounding the plurality of semiconductor units, a lid portion installed on the container case and facing the plurality of semiconductor units, a wiring portion installed on the lid portion, and a plurality of connection portions corresponding to the plurality of semiconductor units, each of the plurality of semiconductor units including a first conductor, a semiconductor chip installed on the first conductor, and a second conductor for control connected to the semiconductor chip, and each of the plurality of connection portions is located between the second conductor of the semiconductor unit corresponding to the connection portion and the wiring portion, and electrically connects the second conductor and the wiring portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 2 is a plan view of a semiconductor unit. [Figure 4] FIG. [Diagram 5] 5 is a cross-sectional view taken along line VV in FIG. 4. [Figure 6] FIG. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6. [Figure 8] FIG. [Figure 9] FIG. 13 is a plan view of a semiconductor device in comparison. [Figure 10] FIG. 11 is a plan view of a wiring board according to a second embodiment. [Figure 11] FIG. 11 is a plan view of a wiring board according to a second embodiment. [Figure 12] FIG. 13 is a plan view of a conductive member in a third embodiment. [Figure 13]13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. [Figure 14] FIG. 13 is a plan view of a conductive member in a third embodiment. [Figure 15] 15 is a cross-sectional view taken along line XV-XV in FIG. 14. [Figure 16] FIG. 11 is a side view of a connection portion in a modified example. [Figure 17] FIG. 11 is a side view of a connection portion in a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The embodiments for carrying out the present disclosure will be described with reference to the drawings. Note that in each drawing, the dimensions and scale of each element may differ from those of the actual product. The embodiment described below is an exemplary embodiment assumed when carrying out the present disclosure. Therefore, the scope of the present disclosure is not limited to the embodiment exemplified below.

[0008] A: First embodiment 1 and 2 are plan views of a semiconductor device 100 according to a first embodiment of the present disclosure. The semiconductor device 100 of the first embodiment is a power semiconductor module used in, for example, an inverter circuit of a power conversion device.

[0009] In the following description, three mutually orthogonal axes (X-axis, Y-axis, Z-axis) are assumed. Also, one direction along the Z-axis is denoted as the Z1 direction, and the opposite direction to the Z1 direction is denoted as the Z2 direction. In actual use, the semiconductor device 100 is installed in any direction, but for convenience in the following description, the Z1 direction is assumed to be downward, and the Z2 direction is assumed to be upward. Therefore, the surface of any element of the semiconductor device 100 facing the Z1 direction may be denoted as the "bottom surface", and the surface of the element facing the Z2 direction may be denoted as the "top surface". Also, observing an object with a line of sight along the Z-axis is hereinafter denoted as a "planar view".

[0010] The semiconductor device 100 of the first embodiment includes a housing case 10, a lid portion 20, and six semiconductor units 30. In Fig. 1, the lid portion 20 is omitted from illustration for convenience. Note that the number of semiconductor units 30 constituting the semiconductor device 100 is not limited to six and can be changed arbitrarily.

[0011] The storage case 10 is a rectangular frame-shaped structure that contains and surrounds six semiconductor units 30. The six semiconductor units 30 are contained in the storage case 10 in a state where they are aligned in the X-axis direction. The six semiconductor units 30 are connected in parallel to each other.

[0012] 2 is a flat plate-like structure that closes the opening of the storage case 10. The lid portion 20 is installed on the storage case 10. Specifically, a side surface of the lid portion 20 is joined to an inner wall surface of the storage case 10 by, for example, an adhesive. In a state in which the lid portion 20 is installed on the storage case 10, the lid portion 20 faces six semiconductor units 30. That is, the lid portion 20 overlaps with the six semiconductor units 30 in a plan view.

[0013] The storage case 10 and the lid portion 20 are formed from various insulating resins, such as polyphenylene sulfide (PPS) resin, polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile-butadiene-styrene (ABS) resin.

[0014] Fig. 3 is a plan view illustrating the configuration of any one of the semiconductor units 30. The six semiconductor units 30 have a common configuration. As illustrated in Fig. 3, each semiconductor unit 30 includes a mounting substrate 31, four semiconductor chips 35, and two semiconductor chips 36.

[0015] The mounting substrate 31 is a wiring substrate on which four semiconductor chips 35 and two semiconductor chips 36 are mounted. For example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, an IMS (Insulated Metal Substrate) substrate, or the like is used as the mounting substrate 31.

[0016] The mounting board 31 is configured by laminating an insulating board 32 and a plurality of conductive patterns 33 (33a, 33b, 33c, 33g1, 33e1, 33g2, 33e2). The insulating board 32 is a rectangular plate-like member formed of an insulating material. The insulating board 32 is formed of a ceramic material such as aluminum oxide, aluminum nitride, or silicon nitride, or a resin material such as epoxy resin. A heat sink (not shown) formed of a metal material with high thermal conductivity such as copper is installed on the lower surface of the mounting board 31. In the first embodiment, a configuration in which the insulating board 32 is an individual member for each semiconductor unit 30 is illustrated, but the insulating board 32 may be a single member that is continuous across six semiconductor units 30.

[0017] The plurality of conductive patterns 33 are thin plate-like conductors disposed on the upper surface of the insulating substrate 32. Each conductive pattern 33 is formed of a low-resistance conductive material such as copper or a copper alloy. The plurality of conductive patterns 33 in the first embodiment include conductive pattern 33a, conductive pattern 33b, conductive pattern 33c, conductive pattern 33g1, conductive pattern 33e1, conductive pattern 33g2, and conductive pattern 33e2.

[0018] The conductive pattern 33g1 and the conductive pattern 33e1 are located on the opposite side of the conductive pattern 33a from the conductive pattern 33b. That is, the conductive pattern 33b is located between the set of the conductive pattern 33g1 and the conductive pattern 33e1 and the conductive pattern 33a. The conductive pattern 33g2 and the conductive pattern 33e2 are located on the opposite side of the conductive pattern 33a from the conductive pattern 33b. That is, the conductive pattern 33a is located between the set of the conductive pattern 33g2 and the conductive pattern 33e2 and the conductive pattern 33b. As can be understood from the above description, the set of the conductive pattern 33g1 and the conductive pattern 33e1 and the set of the conductive pattern 33g2 and the conductive pattern 33e2 are located on diagonals of the rectangular semiconductor unit 30 in a plan view.

[0019] 1, pairs of conductive patterns 33g1 and 33e1 are arranged in the X-axis direction across six semiconductor units 30. Similarly, pairs of conductive patterns 33g2 and 33e2 are arranged in the X-axis direction across six semiconductor units 30. The arrangement of multiple pairs of conductive patterns 33g1 and 33e1 and the arrangement of multiple pairs of conductive patterns 33g2 and 33e2 extend parallel to each other in the X-axis direction with an interval in the Y-axis direction.

[0020] 1 and 3, a wiring member 41 is connected to the conductive patterns 33a of the six semiconductor units 30. A wiring member 42 is connected to the conductive patterns 33c of the six semiconductor units 30. A wiring member 43 is connected to the conductive patterns 33b of the six semiconductor units 30. The wiring member 43 is a wiring for power output. The wiring members 41, 42, and 43 are conductors (e.g., lead frames) that extend in the X-axis direction in the space between each semiconductor unit 30 and the lid portion 20.

[0021] As illustrated in FIG. 2, a positive terminal 21, a negative terminal 22, and an output terminal 23 are installed on the upper surface of the cover 20. The positive terminal 21 (P terminal) is connected to a wiring member 41. A high-level power supply voltage is supplied to the positive terminal 21. That is, the high-level power supply voltage is supplied to the conductive pattern 33a of each semiconductor unit 30 via the positive terminal 21 and the wiring member 41. The negative terminal 22 (N terminal) is connected to a wiring member 42. A low-level power supply voltage is supplied to the negative terminal 22. That is, the low-level power supply voltage is supplied to the conductive pattern 33c of each semiconductor unit 30 via the negative terminal 22 and the wiring member 42. In addition, the output terminal 23 is connected to the wiring member 43. That is, AC power corresponding to the operation of each semiconductor unit 30 is output from the output terminal 23.

[0022] 3 is a power semiconductor element mounted on the mounting substrate 31 and is used as a switching element for switching between conduction and interruption of current. The semiconductor chip 35 in this embodiment is, for example, an IGBT (Insulated Gate Bipolar Transistor). The semiconductor chip 35 is bonded to the conductive pattern 33 by a conductive bonding material such as solder or a sintered material.

[0023] Each semiconductor chip 35 includes a first electrode E1, a second electrode E2, and a control electrode G. The first electrode E1 and the second electrode E2 are main electrodes to which the current to be controlled is input or output. The first electrode E1 is a collector electrode constituting the lower surface of the semiconductor chip 35, and also functions as a cathode electrode of the FWD. The first electrode E1 of each semiconductor chip 35 is joined to the conductive pattern 33. The second electrode E2 is an emitter electrode constituting the upper surface of the semiconductor chip 35, and also functions as an anode electrode of the FWD. The control electrode G is a gate electrode to which a control voltage for controlling the on / off of the semiconductor chip 35 is applied, and constitutes the upper surface of the semiconductor chip 35 together with the second electrode E2.

[0024] Each semiconductor chip 36 is a free wheeling diode (FWD) including an anode Ea and a cathode Ek. The anode Ea constitutes the upper surface of the semiconductor chip 36, and the cathode Ek constitutes the lower surface of the semiconductor chip 36.

[0025] The four semiconductor chips 35 constituting one semiconductor unit 30 are divided into two semiconductor chips 35a and two semiconductor chips 35b. The two semiconductor chips 36 constituting one semiconductor unit 30 are divided into a semiconductor chip 36a and a semiconductor chip 36b. The two semiconductor chips 35a and the one semiconductor chip 36a form an upper arm of an inverter circuit, and the two semiconductor chips 35b and the one semiconductor chip 36b form a lower arm of the inverter circuit.

[0026] The two semiconductor chips 35a and one semiconductor chip 36a are bonded to a conductive pattern 33a. The conductive pattern 33a on which each semiconductor chip 35a is disposed is an example of the "first conductor" in claim 1. The control electrodes G of the two semiconductor chips 35a are connected to each other, for example, by a wire W (bonding wire). In addition, the second electrodes E2 of the two semiconductor chips 35a and the anode Ea of the one semiconductor chip 36a are connected to each other by a wire W, and are also connected to the conductive pattern 33b by the wire W. That is, the two semiconductor chips 35a are connected to each other in parallel.

[0027] The conductive pattern 33g2 and the control electrode G of each semiconductor chip 35a are connected by, for example, a wire W. That is, the conductive pattern 33g2 is electrically connected to the control electrode G of each semiconductor chip 35a. On the other hand, the conductive pattern 33e2 and the second electrode E2 of each semiconductor chip 35a are connected by, for example, a wire W. That is, the conductive pattern 33e2 is electrically connected to the second electrode E2 of each semiconductor chip 35a.

[0028] Moreover, the conductive pattern 33g1 and the control electrode G of each semiconductor chip 35b are connected by, for example, a wire W. That is, the conductive pattern 33g1 is electrically connected to the control electrode G of each semiconductor chip 35b. On the other hand, the conductive pattern 33e1 and the second electrode E2 of each semiconductor chip 35b are connected by, for example, a wire W. That is, the conductive pattern 33e1 is electrically connected to the second electrode E2 of each semiconductor chip 35b.

[0029] The conductive pattern 33g1 and the conductive pattern 33g2 are control terminals connected to the control electrode G of each semiconductor chip 35 to control each semiconductor chip 35. The conductive pattern 33g1 and the conductive pattern 33g2 are an example of the "first conductive pattern" in claim 3. On the other hand, the conductive pattern 33e1 and the conductive pattern 33e2 are auxiliary terminals connected to the second electrode E2 of each semiconductor chip 35. Specifically, the conductive pattern 33e1 and the conductive pattern 33e2 are auxiliary emitter terminals for accurately controlling the voltage between the control electrode G and the second electrode E2 of each semiconductor chip 35. The conductive pattern 33e1 and the conductive pattern 33e2 are an example of the "second conductive pattern" in claim 4. As can be understood from the above explanation, the conductive pattern 33g1, the conductive pattern 33g2, the conductive pattern 33e1, and the conductive pattern 33e2 are control conductors connected to the semiconductor chip 35, and correspond to the "second conductor" in claim 1.

[0030] 1 to 3, the semiconductor device 100 of the first embodiment includes a wiring board 50a and a wiring board 50b. The wiring board 50a is a circuit board for connecting the conductive patterns 33g1 to each other across six semiconductor units 30 and for connecting the conductive patterns 33e1 to each other across six semiconductor units 30. The wiring board 50b is a circuit board for connecting the conductive patterns 33g2 to each other across six semiconductor units 30 and for connecting the conductive patterns 33e2 to each other across six semiconductor units 30.

[0031] The wiring boards 50a and 50b are placed on the lid portion 20. Specifically, the wiring boards 50a and 50b are placed on the lower surface (surface in the Z1 direction) of the lid portion 20. Therefore, the wiring boards 50a and 50b overlap the mounting boards 31 of the semiconductor units 30 in a plan view. The wiring boards 50a and 50b are joined to the lower surface of the lid portion 20 by, for example, an adhesive. Note that the wiring boards 50a and 50b may be fixed to the lid portion 20 by, for example, fasteners such as screws.

[0032] Fig. 4 is a plan view of wiring board 50a. Fig. 5 is a cross-sectional view of line VV in Fig. 4. Note that in Fig. 5, in addition to wiring board 50a, lid portion 20 and mounting board 31 are also shown.

[0033] As illustrated in FIG. 4 and FIG. 5, the wiring board 50a includes an insulating board 51a, a wiring 52g1, and a wiring 52e1. The insulating board 51a is an insulating plate-like member formed of various resin materials such as epoxy resin. The insulating board 51a includes a first face Fa1 and a second face Fa2. The first face Fa1 and the second face Fa2 are opposite surfaces of the insulating board 51a. Specifically, the first face Fa1 is a lower face facing the opposite side (Z1 direction) from the lid part 20, and the second face Fa2 is an upper face facing the lower face of the lid part 20.

[0034] The wiring 52g1 and the wiring 52e1 are conductors formed on the insulating substrate 51a. As described above, the insulating substrate 51a is disposed on the lid portion 20. Therefore, the wiring 52g1 and the wiring 52e1 are disposed on the lid portion 20 via the insulating substrate 51a. The wiring 52g1 and the wiring 52e1 are an example of the "wiring portion" in claim 1. In other words, the "wiring portion" includes the wiring 52g1 and the wiring 52e1.

[0035] The wiring 52g1 is a conductor for connecting the conductive patterns 33g1 of each semiconductor unit 30 to each other across six semiconductor units 30. The wiring 52g1 is an example of the "first wiring" in claim 3. The wiring 52g1 is formed on the first surface Fa1 of the insulating substrate 51a. As illustrated in Fig. 4, the wiring 52g1 of the first embodiment is a conductive pattern including an extension portion 53g1, six branch portions 54g1, and six connection terminals 55g1.

[0036] The extension portion 53g1 is a portion that extends linearly in the X-axis direction along which the six semiconductor units 30 are arranged. The extension portion 53g1 is an example of a "first extension portion" in claim 5. The six connection terminals 55g1 are arranged in the X-axis direction at intervals along the extension portion 53g1. The six branch portions 54g1 are portions that branch out in the Y-axis direction from the extension portion 53g1 toward each connection terminal 55g1. The tip of each branch portion 54g1 is connected to the connection terminal 55g1.

[0037] The wiring 52e1 is a conductor for connecting the conductive patterns 33e1 of the semiconductor units 30 to each other across six semiconductor units 30. The wiring 52e1 is an example of the "second wiring" in claim 4. As illustrated in FIG. 4, the wiring 52e1 of the first embodiment is a conductive pattern including an extension portion 53e1, six branch portions 54e1, and six connection terminals 55e1. The six connection terminals 55e1 are formed on the first surface Fa1 of the insulating substrate 51a, and the extension portion 53e1 and the six branch portions 54e1 are formed on the second surface Fa2 of the insulating substrate 51a. That is, the extension portion 53g1 is provided on the first surface Fa1, and the extension portion 53e1 is provided on the second surface Fa2.

[0038] The extension portion 53e1 is a portion that extends linearly in the X-axis direction along which the six semiconductor units 30 are arranged. The extension portion 53e1 is an example of a "second extension portion" in claim 5. The six connection terminals 55e1 are arranged in the X-axis direction at intervals along the extension portion 53e1. The six branch portions 54e1 are portions that branch out in the Y-axis direction from the extension portion 53e1 toward each connection terminal 55e1. The tip portion of each branch portion 54e1 is electrically connected to the connection terminal 55e1 via a conductive hole formed in the insulating substrate 51a.

[0039] As illustrated in FIG. 5, each connection terminal 55g1 of the wiring board 50a and each conductive pattern 33g1 of the semiconductor unit 30 face each other. The connection terminal 55g1 and the conductive pattern 33g1 are electrically connected via a connection portion 60g1. The connection portion 60g1 is a conductor interposed between the connection terminal 55g1 and the conductive pattern 33g1, and is installed corresponding to each semiconductor unit 30. That is, each connection portion 60g1 electrically connects the conductive pattern 33g1 of the semiconductor unit 30 corresponding to the connection portion 60g1 to the wiring 52g1 of the wiring board 50. As described above, according to the first embodiment, the control electrode G of the semiconductor chip 35b in each of the six semiconductor units 30 can be electrically connected to the wiring 52g1 via the conductive pattern 33g1 and the connection portion 60g1.

[0040] Similarly, each connection terminal 55e1 of the wiring board 50a and each conductive pattern 33e1 of the semiconductor unit 30 face each other. The connection terminal 55e1 and the conductive pattern 33e1 are electrically connected via the connection portion 60e1. The connection portion 60e1 is a conductor interposed between the connection terminal 55e1 and the conductive pattern 33e1, and is installed corresponding to each semiconductor unit 30. That is, each connection portion 60e1 electrically connects the conductive pattern 33e1 of the semiconductor unit 30 corresponding to the connection portion 60e1 to the wiring 52e1 of the wiring board 50a. As described above, according to the first embodiment, the second electrode E2 of the semiconductor chip 35b in each of the six semiconductor units 30 can be electrically connected to the wiring 52e1 via the conductive pattern 33e1 and the connection portion 60e1.

[0041] Fig. 6 is a plan view of wiring board 50b. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6. In Fig. 7, lid portion 20 and mounting board 31 are also shown in addition to wiring board 50b.

[0042] 6 and 7, wiring board 50b includes insulating substrate 51b, wiring 52g2, and wiring 52e2. Insulating substrate 51b is an insulating plate-like member similar to insulating substrate 51a. Insulating substrate 51b includes first surface Fb1 and second surface Fb2 located on opposite sides to each other.

[0043] The wiring 52g2 and the wiring 52e2 are conductors formed on the insulating substrate 51b. That is, the wiring 52g2 and the wiring 52e2 are installed on the lid portion 20 via the insulating substrate 51b. The wiring 52g2 and the wiring 52e2 are an example of the “wiring portion” in claim 1.

[0044] The wiring 52g2 is a conductor for connecting the conductive patterns 33g2 of each semiconductor unit 30 to each other across six semiconductor units 30. The wiring 52g2 is an example of the "first wiring" in claim 3. The wiring 52g2 is formed on the first surface Fb1 of the insulating substrate 51b. As illustrated in Fig. 6, the wiring 52g2 of the first embodiment is a conductive pattern including an extension portion 53g2, six branch portions 54g2, and six connection terminals 55g2.

[0045] The extension portion 53g2 is a portion that extends linearly in the X-axis direction along which the six semiconductor units 30 are arranged. The extension portion 53g2 is an example of a "first extension portion" in claim 5. The six connection terminals 55g2 are arranged in the X-axis direction at intervals along the extension portion 53g2. The six branch portions 54g2 are portions that branch out in the Y-axis direction from the extension portion 53g2 toward each connection terminal 55g2. The tip of each branch portion 54g2 is connected to the connection terminal 55g2.

[0046] The wiring 52e2 is a conductor for connecting the conductive patterns 33e2 of the semiconductor units 30 to each other across the six semiconductor units 30. The wiring 52e2 is an example of the "second wiring" in claim 4. As illustrated in FIG. 6, the wiring 52e2 of the first embodiment is a conductive pattern including an extension portion 53e2, six branch portions 54e2, and six connection terminals 55e2. The six connection terminals 55e2 are formed on the first surface Fb1 of the insulating substrate 51b, and the extension portion 53e2 and the six branch portions 54e2 are formed on the second surface Fb2 of the insulating substrate 51b. That is, the extension portion 53g2 is provided on the first surface Fb1, and the extension portion 53e2 is provided on the second surface Fb2.

[0047] The extension portion 53e2 is a portion that extends linearly in the X-axis direction along which the six semiconductor units 30 are arranged. The extension portion 53e2 is an example of a "second extension portion" in claim 5. The six connection terminals 55e2 are arranged in the X-axis direction at intervals along the extension portion 53e2. The six branch portions 54e2 are portions that branch out in the Y-axis direction from the extension portion 53e2 toward each connection terminal 55e2. The tip portion of each branch portion 54e2 is electrically connected to the connection terminal 55e2 via a conductive hole formed in the insulating substrate 51b.

[0048] As illustrated in FIG. 7, each connection terminal 55g2 of the wiring board 50b and each conductive pattern 33g2 of the semiconductor unit 30 face each other. The connection terminal 55g2 and the conductive pattern 33g2 are electrically connected via a connection portion 60g2. The connection portion 60g2 is a conductor interposed between the connection terminal 55g2 and the conductive pattern 33g2, and is installed corresponding to each semiconductor unit 30. That is, each connection portion 60g2 electrically connects the conductive pattern 33g2 of the semiconductor unit 30 corresponding to the connection portion 60g2 to the wiring 52g2 of the wiring board 50. As described above, according to the first embodiment, the control electrode G of the semiconductor chip 35a in each of the six semiconductor units 30 can be electrically connected to the wiring 52g2 via the conductive pattern 33g2 and the connection portion 60g2.

[0049] Similarly, each connection terminal 55e2 of the wiring board 50b and each conductive pattern 33e2 of the semiconductor unit 30 face each other. The connection terminal 55e2 and the conductive pattern 33e2 are electrically connected via the connection portion 60e2. The connection portion 60e2 is a conductor interposed between the connection terminal 55e2 and the conductive pattern 33e2, and is installed corresponding to each semiconductor unit 30. That is, each connection portion 60e2 electrically connects the conductive pattern 33e2 of the semiconductor unit 30 corresponding to the connection portion 60e2 to the wiring 52e2 of the wiring board 50b. As described above, according to the first embodiment, the second electrode E2 of the semiconductor chip 35a in each of the six semiconductor units 30 can be electrically connected to the wiring 52e2 via the conductive pattern 33e2 and the connection portion 60e2.

[0050] As illustrated in Fig. 5 and Fig. 7, a sealant 12 is formed in the space inside the housing case 10. The sealant 12 is a resin material that seals each semiconductor unit 30. The sealant 12 is formed from various resin materials such as silicone gel, epoxy resin, or phenol resin. Note that the sealant 12 may contain various fillers such as silicon oxide or aluminum oxide. As illustrated in Fig. 5 and Fig. 7, a portion of each connection portion 60 is covered with the sealant 12.

[0051] Fig. 8 is a side view of the connection portion 60. Although the connection portion 60g1 is illustrated in Fig. 8 for convenience, each of the connection portions 60 (60e1, 60g2, 60e2) other than the connection portion 60g1 has the same configuration.

[0052] As illustrated in FIG. 8, each connection portion 60g1 is a conductor including an elastic body 61 and a terminal portion 62. The elastic body 61 and the terminal portion 62 are integrally formed of a low-resistance conductive material such as copper or a copper alloy. The elastic body 61 is a structure capable of elastic deformation. Specifically, the elastic body 61 is a coil spring capable of elastic expansion and contraction. The terminal portion 62 is a connection terminal connected to the lower end of the elastic body 61. The terminal portion 62 is joined to the conductive pattern 33g1 by a conductive joining material such as solder or a sintered material. That is, the connection portion 60g1 protrudes from the upper surface of the mounting board 31 in the Z2 direction.

[0053] An upper end of the elastic body 61 contacts the connection terminal 55g1 of the wiring 52g1 in the wiring board 50. Specifically, in a state in which the elastic body 61 is contracted by being sandwiched between the conductive pattern 33g1 and the connection terminal 55g1 (wiring 52g1), the connection portion 60g1 is placed between the semiconductor unit 30 and the lid portion 20. That is, the elastic body 61 of each connection portion 60g1 is placed in a contracted state between the conductive pattern 33g1 and the connection terminal 55g1. As can be understood from the above description, the upper end of the elastic body 61 is pressed by the connection terminal 55g1.

[0054] According to the above configuration, by a simple process of contracting the elastic body 61 by the lid portion 20 during the process of installing the lid portion 20 on the storage case 10, it is possible to reliably establish electrical continuity between the conductive pattern 33g1 and the wiring 52g1 via the connection portion 60g1.

[0055] In the above description, attention has been focused on the connection portion 60g1 between the conductive pattern 33g1 and the connection terminal 55g1, but each connection portion 60 (60e1, 60g2, 60e2) other than the connection portion 60g1 is disposed in the same manner. Specifically, the connection portion 60e1 is disposed between the conductive pattern 33e1 and the connection terminal 55e1 when the elastic body 61 is contracted. The connection portion 60g2 is disposed between the conductive pattern 33g2 and the connection terminal 55g2 when the elastic body 61 is contracted. Moreover, the connection portion 60e2 is disposed between the conductive pattern 33e2 and the connection terminal 55e2 when the elastic body 61 is contracted.

[0056] 2, control terminals 25g1, 25e1, 25g2, and 25e2 are provided on the upper surface of cover 20. Control terminal 25g1 is connected to wiring 52g1 of wiring board 50a, and control terminal 25e1 is connected to wiring 52e1 of wiring board 50a. Control terminal 25g2 is connected to wiring 52g2 of wiring board 50b, and control terminal 25e2 is connected to wiring 52e2 of wiring board 50b.

[0057] 2, control terminals 25g1 and 25e1 are located at the center in the X-axis direction of cover portion 20. Similarly, control terminals 25g2 and 25e2 are located at the center in the X-axis direction of cover portion 20. Positive terminal 21, negative terminal 22, and output terminal 23 are installed in a region extending in the X-axis direction between the pair of control terminals 25g1 and 25e1 and the pair of control terminals 25g2 and 25e2.

[0058] 9 (hereinafter referred to as the “Comparative Example”) is also conceivable as a configuration for connecting six semiconductor units 30 in parallel. In the comparative example, a plurality of relay patterns 38 (38g1, 38e1, 38g2, 38e2) are provided on the mounting board 31 of each semiconductor unit 30.

[0059] To each relay pattern 38g1, the control electrodes G of the two semiconductor chips 35b in one semiconductor unit 30 are connected. The relay patterns 38g1 of each semiconductor unit 30 are connected by wires W across the six semiconductor units 30. To each relay pattern 38e1, the second electrodes E2 of the two semiconductor chips 35b in one semiconductor unit 30 are connected. The relay patterns 38e1 of each semiconductor unit 30 are connected by wires W across the six semiconductor units 30.

[0060] Similarly, the control electrodes G of the two semiconductor chips 35a in one semiconductor unit 30 are connected to each relay pattern 38g2. The relay patterns 38g2 of each semiconductor unit 30 are connected to the six semiconductor units 30 by wires W. The second electrodes E2 of the two semiconductor chips 35a in one semiconductor unit 30 are connected to each relay pattern 38e2. The relay patterns 38e2 of each semiconductor unit 30 are connected to the six semiconductor units 30 by wires W.

[0061] As described above, in the comparative example, it is necessary to provide a plurality of relay patterns 38 (38g1, 38e1, 38g2, 38e2) on the mounting substrate 31 of each semiconductor unit 30. This poses a problem that it limits the reduction in size of each semiconductor unit 30. In the comparative example, it is particularly difficult to reduce the size of each semiconductor unit 30 in the Y-axis direction.

[0062] In contrast to the comparative example, in the first embodiment, the conductive patterns 33 (33g1, 33e1, 33g2, 33e2) in each of the six semiconductor units 30 are electrically connected to the wiring 52 (52g1, 52e1, 52g2, 52e2) provided on the lid portion 20. Therefore, compared to the comparative example in which the relay pattern 38 connected across the six semiconductor units 30 is provided in each semiconductor unit 30, the planar size of each semiconductor unit 30 can be reduced. In addition, in the first embodiment, the relay pattern 38 in the comparative example is omitted from each semiconductor unit 30, which has the advantage that the area available for providing the semiconductor chip 35 in each semiconductor unit 30 can be expanded.

[0063] B: Second embodiment A second embodiment will be described. Note that, for elements having the same functions as those in the first embodiment in each of the following exemplary aspects, the same reference numerals as those in the first embodiment will be used, and detailed descriptions of each will be omitted as appropriate.

[0064] In the second embodiment, the configurations of the wiring board 50a and the wiring board 50b are different from those of the first embodiment. The configurations other than the wiring board 50a and the wiring board 50b are the same as those of the first embodiment. Therefore, the second embodiment also achieves the same effects as the first embodiment.

[0065] 10 is a plan view of a wiring board 50a according to the second embodiment. In the first embodiment, the configuration in which the extension portion 53g1 of the wiring 52g1 and the extension portion 53e1 of the wiring 52e1 are disposed at different positions in the Y-axis direction is illustrated. That is, the extension portion 53g1 and the extension portion 53e1 do not overlap in a plan view.

[0066] In contrast to the first embodiment, in the wiring board 50a of the second embodiment, as illustrated in Fig. 10, the extension portion 53g1 of the wiring 52g1 and the extension portion 53e1 of the wiring 52e1 overlap each other in a plan view. That is, in the second embodiment, the extension portion 53g1 and the extension portion 53e1 are disposed at the same position in the Y-axis direction. This can also be expressed as a configuration in which the extension portion 53g1 and the extension portion 53e1 face each other across the insulating substrate 51a.

[0067] As described above, in the second embodiment, the extension 53g1 connected to the control electrode G of each semiconductor chip 35b and the extension 53e1 connected to the second electrode E2 of each semiconductor chip 35b overlap each other in a plan view. Therefore, compared with a configuration in which the extension 53g1 and the extension 53e1 do not overlap, the inductive components associated with the wiring 52g1 and the wiring 52e1 can be reduced.

[0068] 11 is a plan view of a wiring board 50b according to the second embodiment. In the first embodiment, the configuration in which the extending portion 53g2 of the wiring 52g2 and the extending portion 53e2 of the wiring 52e2 are disposed at different positions in the Y-axis direction is illustrated. That is, the extending portion 53g2 and the extending portion 53e2 do not overlap in a plan view.

[0069] In contrast to the first embodiment, in the wiring board 50b of the second embodiment, as illustrated in Fig. 11, the extension portion 53g2 of the wiring 52g2 and the extension portion 53e2 of the wiring 52e2 overlap each other in a plan view. That is, in the second embodiment, the extension portion 53g2 and the extension portion 53e2 are disposed at the same position in the Y-axis direction. This can also be expressed as a configuration in which the extension portion 53g2 and the extension portion 53e2 face each other across the insulating substrate 51b.

[0070] As described above, in the second embodiment, the extension 53g2 connected to the control electrode G of each semiconductor chip 35a and the extension 53e2 connected to the second electrode E2 of each semiconductor chip 35a overlap each other in a plan view. Therefore, compared to a configuration in which the extension 53g2 and the extension 53e2 do not overlap, the inductive components associated with the wiring 52g2 and the wiring 52e2 can be reduced.

[0071] C: Third embodiment Fig. 12 is a plan view relating to the connection of the conductive pattern 33g1 and the conductive pattern 33e1 in the third embodiment. Fig. 13 is a cross-sectional view taken along the line XIII-XIII in Fig. 12.

[0072] 12 and 13, in the third embodiment, the wiring board 50a of the first embodiment is replaced with a conductive member 70g1 and a conductive member 70e1. The conductive member 70g1 and the conductive member 70e1 are plate-shaped conductors (lead frames) made of a low-resistance conductive material such as copper or a copper alloy. The conductive member 70g1 and the conductive member 70e1 may be plated with nickel, a nickel-phosphorus alloy, a nickel-boron alloy, or the like.

[0073] The conductive member 70g1 and the conductive member 70e1 are disposed on the lower surface of the lid portion 20. The conductive member 70g1 and the conductive member 70e1 are disposed on the lid portion 20 by, for example, insert molding. Note that the conductive member 70g1 and the conductive member 70e1 may be disposed on the lid portion 20 after the lid portion 20 is molded.

[0074] 12, the conductive member 70g1 includes an extension portion 71g1, six branch portions 72g1, and six connection terminals 73g1. The extension portion 71g1 is a portion that extends in the X-axis direction. The six connection terminals 73g1 are arranged in the X-axis direction at intervals. The six branch portions 72g1 are portions that connect the extension portion 71g1 and each of the connection terminals 73g1.

[0075] The conductive member 70e1 includes an extending portion 71e1, six branch portions 72e1, and six connection terminals 73e1. The extending portion 71e1 is a portion that extends in the X-axis direction. The six connection terminals 73e1 are arranged in the X-axis direction at intervals from one another. The six branch portions 72e1 are portions that connect the extending portion 71e1 and the connection terminals 73e1.

[0076] 12, the extending portion 71g1 and the extending portion 71e1 extend in parallel with each other with a gap therebetween. In a plan view, the connecting terminals 73g1 and the connecting terminals 73e1 are alternately arranged along the X-axis between the extending portion 71g1 and the extending portion 71e1.

[0077] 13, each connection terminal 73g1 of the conductive member 70g1 and each conductive pattern 33g1 of the semiconductor unit 30 are electrically connected via a connection portion 60g1. Similarly, each connection terminal 73e1 of the conductive member 70e1 and each conductive pattern 33e1 of the semiconductor unit 30 are electrically connected via a connection portion 60e1. The configurations of the connection portion 60g1 and the connection portion 60e1 are similar to those of the first embodiment.

[0078] In the above embodiment, the plate-shaped conductive member 70g1 and the conductive member 70e1 installed in the lid portion 20 are connected to the semiconductor unit 30. Therefore, the configuration of the semiconductor device 100 is simplified compared to the embodiment in which the wiring board 50a is connected to the semiconductor unit 30.

[0079] Fig. 14 is a plan view of the connection between the conductive pattern 33g2 and the conductive pattern 33e2 in the third embodiment. Fig. 15 is a cross-sectional view of the XV-XV line in Fig. 14. In the third embodiment, the wiring board 50b in the first embodiment is replaced with the conductive member 70g2 and the conductive member 70e2. The conductive member 70g2 and the conductive member 70e2 are plate-shaped conductors (lead frames) made of a low-resistance conductive material such as copper or a copper alloy. The conductive member 70g2 and the conductive member 70e2 may be plated with nickel, a nickel-phosphorus alloy, a nickel-boron alloy, or the like.

[0080] The conductive member 70g2 and the conductive member 70e2 are disposed on the lower surface of the lid portion 20. The conductive member 70g2 and the conductive member 70e2 are disposed on the lid portion 20 by, for example, insert molding. Note that the conductive member 70g2 and the conductive member 70e2 may be disposed on the lid portion 20 after the lid portion 20 is molded.

[0081] The conductive member 70g2 and each conductive pattern 33g2 of the semiconductor unit 30 are electrically connected via a connection portion 60g2. Similarly, the conductive member 70e2 and each conductive pattern 33e2 of the semiconductor unit 30 are electrically connected via a connection portion 60e2. The configurations of the connection portion 60g2 and the connection portion 60e2 are similar to those of the first embodiment.

[0082] In the above embodiment, the plate-shaped conductive member 70g2 and the conductive member 70e2 installed on the lid portion 20 are connected to the semiconductor unit 30. Therefore, the configuration of the semiconductor device 100 is simplified compared to the embodiment in which the wiring board 50a is connected to the semiconductor unit 30.

[0083] In the first and second embodiments, the wiring board 50a and the wiring board 50b are installed. Therefore, there is an advantage that it is easy to ensure the degree of freedom in designing each wiring 52 (52g1, 52e1, 52g2, 52e2). For example, as illustrated in the second embodiment, a configuration in which the extension portion 53g1 of the wiring 52g1 and the extension portion 53e1 of the wiring 52e1 overlap in a planar view, or a configuration in which the extension portion 53g2 of the wiring 52g2 and the extension portion 53e2 of the wiring 52e2 overlap in a planar view can be adopted.

[0084] D: Variation Specific modified aspects that can be added to the above-described embodiment are illustrated below. Two or more aspects selected from the following examples may be appropriately combined to the extent that they are not inconsistent.

[0085] (1) The configuration of the connection portion 60 is not limited to the examples of the above-mentioned embodiments. For example, as illustrated in FIG. 16, the connection portion 60 may include a terminal portion 63 in addition to the elastic body 61 and the terminal portion 62 similar to the above-mentioned embodiments. The terminal portion 63 is a connection terminal connected to the upper end of the elastic body 61. When the elastic body 61 contracts, the terminal portion 63 is pressed by the connection terminal 55g1. The connection portion 60 of FIG. 16 may be adopted in the second and third embodiments.

[0086] As illustrated in FIG. 17, the connection portion 60 may include a receiving portion 64 in addition to the elastic body 61 and the terminal portion 62 similar to those in the first embodiment. The receiving portion 64 is a structure provided on the connection terminal 55g1. A recess is formed on the lower surface of the receiving portion 64. The upper end of the elastic body 61 is accommodated in the recess. According to the above configuration, the upper end of the elastic body 61 is suppressed from being displaced by being accommodated in the receiving portion 64. In other words, it is possible to reduce the possibility that the upper end of the elastic body 61 will be displaced in a direction intersecting the Z-axis.

[0087] (2) In the above embodiment, the semiconductor chip 35 is an IGBT, but the embodiment of the semiconductor chip 35 is not limited to the above embodiment. For example, various electronic elements such as an RC-IGBT (Reverse Conducting IGBT) or an SBD (Schottky Barrier Diode) in which the semiconductor chip 35 and the semiconductor chip 36 in the above embodiment are integrated may be used as the semiconductor chip 35. Also, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in which a semiconductor layer is formed of silicon (Si) or silicon carbide (SiC) may be used as the semiconductor chip 35. In the embodiment in which the semiconductor chip 35 is a MOSFET, the first electrode E1 is a drain electrode, and the second electrode E2 is a source electrode.

[0088] (3) The term "nth" (n is a natural number) in this application is used only as a formal and convenient label to distinguish each element in the description and does not have any substantial meaning. Therefore, there is no room for restrictive interpretation of the position of each element or the order of production, etc., based on the term "nth".

[0089] E: Notes From the above-described exemplary embodiments, the following configurations can be understood, for example.

[0090] A semiconductor device according to one aspect (aspect 1) of the present disclosure comprises a plurality of semiconductor units connected in parallel, a container case surrounding the plurality of semiconductor units, a lid portion installed on the container case and facing the plurality of semiconductor units, a wiring portion installed on the lid portion, and a plurality of connection portions corresponding to the plurality of semiconductor units, each of the plurality of semiconductor units including a first conductor, a semiconductor chip installed on the first conductor, and a second conductor for control connected to the semiconductor chip, and each of the plurality of connection portions is located between the second conductor of the semiconductor unit corresponding to the connection portion and the wiring portion, and electrically connects the second conductor and the wiring portion.

[0091] In the above configuration, the second conductor in each of the multiple semiconductor units is electrically connected to the wiring portion installed in the lid portion. Therefore, the planar size of each semiconductor unit can be reduced compared to a configuration in which a conductive pattern (routing wiring) connected across multiple semiconductor units is installed in each semiconductor unit. In addition, since the conductor for connecting the second conductor of each semiconductor unit is omitted from each semiconductor unit, the area available for installing a semiconductor chip in each semiconductor unit can be expanded.

[0092] In a specific example (Aspect 2) of Aspect 1, each of the plurality of connection parts includes an elastic body that is placed in a contracted state between the second conductor and the wiring part. According to the above aspect, the second conductor and the wiring part can be reliably electrically connected by the connection part through a simple process of contracting the elastic body by the lid part in the process of placing the lid part on the storage case.

[0093] In a specific example (Aspect 3) of Aspect 1 or Aspect 2, the second conductor includes a first conductive pattern electrically connected to a control electrode of the semiconductor chip, the wiring portion includes a first wiring, and each of the plurality of connection portions includes a connection portion that electrically connects the first conductive pattern of the semiconductor unit corresponding to the connection portion and the first wiring. According to the above aspect, the control electrode of the semiconductor chip in each of the plurality of semiconductor units can be electrically connected to the first wiring via the first conductive pattern and the first connection body.

[0094] In a specific example (Aspect 4) of Aspect 3, the semiconductor chip includes a first electrode bonded to a mounting board and a second electrode opposite to the first electrode, the second conductor includes a second conductive pattern electrically connected to the second electrode, the wiring portion includes a second wiring, and each of the multiple connection portions includes a connection portion that electrically connects the second conductive pattern of the semiconductor unit corresponding to the connection portion and the second wiring. According to the above aspect, an auxiliary emitter terminal of the semiconductor chip in each of the multiple semiconductor units can be electrically connected to the second wiring via the second conductive pattern and the second connection body.

[0095] In a specific example (Aspect 5) of Aspect 4, the first wiring includes a first extension portion extending in the arrangement direction of the semiconductor units, and the second wiring includes a second extension portion extending in the arrangement direction of the semiconductor units, and the first extension portion and the second extension portion overlap each other in a planar view. According to the above aspect, the first extension portion connected to the control electrode of each semiconductor chip and the second extension portion connected to the second electrode of each semiconductor chip overlap each other in a planar view. Therefore, compared to a configuration in which the first extension portion and the second extension portion do not overlap each other in a planar view, it is possible to reduce inductive components associated with the first wiring and the second wiring.

[0096] In a specific example (Aspect 6) of Aspect 5, an insulating substrate is further provided on the lid, the insulating substrate including a first surface and a second surface opposite to the first surface, the first extension portion is provided on the first surface, and the second extension portion is provided on the second surface. With the above configuration, the first extension portion and the second extension portion can be overlapped in a plan view by a simple configuration in which the first extension portion and the second extension portion are formed on opposite plate surfaces of the insulating substrate.

[0097] In a specific example (Aspect 7) of any one of Aspects 1 to 5, a wiring board is provided on the lid, and the wiring board includes an insulating substrate and the wiring portion provided on the insulating substrate. In the above aspects, a wiring board including an insulating substrate and a wiring portion is provided on the lid. Therefore, sufficient freedom in designing the wiring portion can be ensured.

[0098] In a specific example (Aspect 8) of any one of Aspects 1 to 5, the wiring portion is made of a plate-shaped conductive material. In the above aspects, since the wiring portion is made of a plate-shaped conductive material, the configuration of the semiconductor device is simplified. [Explanation of symbols]

[0099] 100...semiconductor device, 10...accommodating case, 12...sealing material, 20...lid, 30...semiconductor unit, 31...mounting board, 32...insulating board, 33a, 33b, 33c, 33g1, 33e1, 33g2, 33e2...conductive pattern, 35, 35a, 35b...semiconductor chip, 36, 36a, 36b...semiconductor chip, 50a, 50b...wiring board, 51a, 51b...insulating board, 52g1, 52e1, 52g2, 52e2...wiring, 53g1, 53e1, 53g2 ,53e2...Extension part, 54g1,54e1,54g2,54e2...Branch part, 55g1,55e1,55g2,55e2...Connection terminal, 60g1,60e1,60g2,60e2...Connection part, 61...Elastic body, 62,63...Terminal part , 70g1,70e1,70g2,70e2...conductive member, 71g1,71e1,71g2,71e2...extension part, 72g1,72e1,72g2,72e2...branch part, 73g1,73e1,73g2,73e2...connecting terminal.

Claims

1. A plurality of semiconductor units connected in parallel; a housing case that encloses the plurality of semiconductor units; a cover portion disposed in the housing case and facing the plurality of semiconductor units; A wiring portion installed in the lid portion; a plurality of connection portions respectively corresponding to the plurality of semiconductor units; Each of the plurality of semiconductor units is A first conductor; a semiconductor chip disposed on the first conductor; a second conductor for control connected to the semiconductor chip; Each of the plurality of connection portions is located between the second conductor of the semiconductor unit corresponding to the connection portion and the wiring portion, and electrically connects the second conductor and the wiring portion. Semiconductor device.

2. Each of the plurality of connection portions includes an elastic body that is disposed in a contracted state between the second conductor and the wiring portion. The semiconductor device according to claim 1.

3. the second conductor includes a first conductive pattern electrically connected to a control electrode of the semiconductor chip; The wiring portion includes a first wiring, Each of the plurality of connection portions includes a connection portion that electrically connects the first conductive pattern of the semiconductor unit corresponding to the connection portion and the first wiring.

3. The semiconductor device according to claim 1.

4. the semiconductor chip includes a first electrode bonded to a mounting substrate and a second electrode opposite to the first electrode; the second conductor includes a second conductive pattern electrically connected to the second electrode; The wiring portion includes a second wiring, Each of the plurality of connection portions includes a connection portion that electrically connects the second conductive pattern of the semiconductor unit corresponding to the connection portion and the second wiring. The semiconductor device according to claim 3.

5. the first wiring includes a first extension portion extending in an arrangement direction of the plurality of semiconductor units, the second wiring includes a second extension portion extending in an arrangement direction of the plurality of semiconductor units, The first extension portion and the second extension portion overlap each other in a plan view. The semiconductor device according to claim 4.

6. Further comprising an insulating substrate disposed on the lid portion, The insulating substrate is The first page and a second surface opposite the first surface; The first extension portion is disposed on the first surface, The second extension portion is disposed on the second surface. The semiconductor device according to claim 5.

7. A wiring board is provided on the cover, The wiring board includes: An insulating substrate; The wiring portion is disposed on the insulating substrate. The semiconductor device according to claim 1.

8. The wiring portion is made of a plate-shaped conductive material. The semiconductor device according to claim 1.

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