Memory system and data rearrangement method
Patent Information
- Application Number
- JP2023149122
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-09-14
- Publication Date
- 2025-03-27
Smart Images
Figure 2025042237000001_ABST
Abstract
Description
[Technical field]
[0001] 1. Field of the Invention The present invention relates to a memory system and a data rearrangement method. [Background technology]
[0002] Memory systems equipped with flash memories, such as solid state drives (SSDs), are widely used.
[0003] In this type of memory system, as the flash memory becomes worn out, it may become necessary to allocate data in units of host access, called a cluster (sector), when sending and receiving data to the memory system across multiple pages of the flash memory.
[0004] Placing clusters across multiple pages of flash memory can degrade the performance of the memory system. [Prior art documents] [Patent documents]
[0005] [Patent Document 1] US Patent Application Publication No. 2023 / 0073249 Summary of the Invention [Problem to be solved by the invention]
[0006] One embodiment provides a memory system and a data relocation method that can suppress performance degradation due to wear of a flash memory. [Means for solving the problem]
[0007] According to an embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory has a plurality of blocks each including a plurality of pages. The controller has a counter that counts the number of accesses of data stored in the non-volatile memory in units of accesses of data from a host, is connectable to the host, and controls the non-volatile memory. The controller determines whether a read command received from the host is a command for sequential read or random read, and if it is a random read, increments a value of a counter corresponding to data specified by the read command, and in a process of moving data of a first block to a second block, if it is necessary to arrange data of an access unit of data of the host across two pages in the second block, controls a relocation of data of the first block to the second block based on the value of the counter. [Brief description of the drawings]
[0008] [Figure 1] FIG. 1 is a diagram showing an example of a configuration of a memory system according to an embodiment. [Diagram 2] FIG. 2 is a first diagram for explaining an example of a cause of performance degradation due to wear of a NAND memory in the memory system of the embodiment. [Diagram 3] FIG. 11 is a second diagram for explaining an example of a cause of performance degradation due to wear of the NAND memory in the memory system of the embodiment. [Figure 4] FIG. 11 is a third diagram for explaining an example of a cause of performance degradation due to wear of the NAND memory in the memory system of the embodiment. [Diagram 5] 1A and 1B are diagrams for explaining a method for controlling the placement of clusters executed by the memory system according to the embodiment. [Figure 6] 11A and 11B are diagrams for explaining a method for dealing with the occurrence of a cluster that is arranged across two pages during compaction of the memory system of the embodiment. [Figure 7] 1 is a diagram showing an example in which the memory system according to the embodiment adaptively controls the arrangement of clusters in response to wear-out of a NAND memory. [Figure 8]10 is a flowchart showing an operation procedure when a read command is received in the memory system of the embodiment. [Figure 9] 1 is a flowchart showing a procedure of a compaction operation in the memory system according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] Hereinafter, embodiments will be described with reference to the drawings.
[0010] 1 is a diagram showing an example of a configuration of a memory system 1 according to an embodiment. FIG. 1 also shows an example of a connection between the memory system 1 and a host 2. The memory system 1 and the host 2 are connected to each other via, for example, a PCI Express TM (PCIe TM ) standard compliant interface.
[0011] The memory system 1 includes a controller 11 and a NAND memory 12 .
[0012] The controller 11 controls the process of writing data to the NAND memory 12 and the process of reading data from the NAND memory 12 in response to a command from the host 2. The controller 11 autonomously performs the process of writing data to the NAND memory 12 and the process of reading data from the NAND memory 12 for the purpose of optimizing the state of the NAND memory 12, regardless of a command from the host 2. The controller 11 is configured as, for example, an SoC (System on a Chip).
[0013] The NAND memory 12 is a storage medium that includes a plurality of blocks, each of which includes a plurality of pages, and does not allow data to be overwritten in a storage area where data has already been written. Data stored in the NAND memory 12 is updated by invalidating the original data and writing new data separately. In order to make the storage area in which the invalidated data is stored available for data writing again, the controller 11 appropriately executes processes called compaction or garbage collection (hereinafter referred to as compaction). When executing compaction, the controller 11 autonomously writes data to the NAND memory 12 and reads data from the NAND memory 12 without relying on a command from the host 2.
[0014] The controller 11 has a host interface unit 110, a control unit 120, and a NAND interface unit 130. These may be realized by a program being executed by a CPU, or may be realized as hardware such as an electric circuit.
[0015] The host interface unit 110 is a processing unit that functions as a front end. The host interface unit 110 is, for example, an NVM Express TM (NVMe TM ) standard to control communication with host 2.
[0016] The control unit 120 is a processing unit that functions as the core of the controller 11. The control unit 120 cooperates with the host interface unit 110 and the NAND interface unit 130 to control the writing of data to the NAND memory 12 and the reading of data from the NAND memory 12 in response to commands from the host 2. The above-mentioned writing and reading of data autonomously performed by the controller 11 is also executed as an internal process of the memory system 1 under the control of the control unit 120.
[0017] The NAND interface unit 130 is a processing unit that functions as a backend, and controls transmission and reception of data to and from the NAND memory 12. The NAND interface unit 130 has an access counter 131. Details of the use of the access counter 131 will be described later.
[0018] Here, an example of a cause of the performance degradation of the memory system 1 due to the fatigue of the NAND memory 12 will be described with reference to FIGS.
[0019] 2 shows an example of change in the arrangement of ECC frames in a page of the memory system 1 due to wear of the NAND memory 12 when the user data length fixing method is applied. The user data length fixing method is a method in which the user data length is fixed and the ECC (Error Correcting Code) frame length is variable.
[0020] When the controller 11 receives a write command from the host 2, it generates an ECC frame. The ECC frame is a combination of the user data to be written received from the host 2 and an ECC (parity) that can detect errors when reading the user data and correct the errors. The controller 11 writes the generated ECC frame to the NAND memory 12.
[0021] The NAND memory 12 includes a plurality of blocks. A block is a unit of data erasure in the NAND memory 12. Each of the plurality of blocks includes a plurality of pages. A page is a unit of data writing in the NAND memory 12. When storing an ECC frame in each block, the controller 11 controls the arrangement of the ECC frame for each of a predetermined number of pages among the plurality of pages included in the block. In other words, the controller 11 controls the arrangement of the ECC frame with a storage area of a predetermined number of pages as one section. FIG. 2 shows an example in which the ECC frame is arranged with a storage area of two pages as one section.
[0022] As the NAND memory 12 becomes worn out, the number of errors that can occur in the user data increases. Accordingly, it is necessary to increase the code length of the ECC to correct the errors. When an ECC frame is generated using the fixed user data length method, the length of the user data included in each ECC frame is constant, and the code length of the ECC is variable. Therefore, the length of the ECC frame increases by the amount that the code length of the ECC increases. In other words, the ECC frame in the fixed user data length method is variable length. Also, the length of the user data in the fixed user data length method is the same as the above-mentioned cluster, that is, the access unit of the data of the host 2.
[0023] FIG. 2 shows an example in which the number of ECC frames that can be arranged in every two pages decreases to 8, 7, and 6 as the NAND memory 12 becomes worn out ((A) → (B) → (C)). When a condition for increasing the ECC code length is met (such as the degree of wear in the NAND memory 12 exceeding a certain range), the ECC code length increases and the number of ECC frames that can be arranged in one page decreases. In FIG. 2, "exceeding the threshold" indicates that a condition for increasing the ECC code length is met. Reducing the number of ECC frames that the controller 11 writes to one section of pages is also called "cluster crushing".
[0024] 2 also shows a state (a1) in which a certain ECC frame is arranged across two pages, that is, a state in which a certain cluster is arranged across two pages. If a cluster is arranged across two pages, it may deteriorate the performance of the memory system 1. The effect on the performance of the memory system 1 due to the cluster being arranged across two pages will be described later.
[0025] 3 shows an example of the performance degradation of the memory system 1 due to the fatigue of the NAND memory 12 when a fixed frame length method is applied, in which the ECC frame length is fixed and the user data length is variable. FIG. 3 also shows an example of arranging the ECC frame with a storage area of two pages as one section.
[0026] FIG. 3 shows an example in which the proportion of the ECC code length in the ECC frame arranged for each page increases as the NAND memory 12 becomes worn out ((A) → (B) → (C)). As described above, as the NAND memory 12 becomes worn out, the ECC code length for correcting errors becomes longer. In the fixed frame length method, the length of each ECC frame is kept constant, so the length of the user data and the ECC code length are made variable. As a result, the length of the user data included in the ECC frame becomes shorter.
[0027] In the case of the fixed frame length method, the number of ECC frames that can be arranged per page does not change with the wear of the NAND memory 12. In other words, an ECC frame is not arranged across two pages. However, since the length of user data in each ECC frame becomes shorter, there is a possibility that a cluster, which is data in units of access by the host 2, is divided and arranged in two ECC frames. The two ECC frames indicated by the symbol b1 in FIG. 3 are two ECC frames in which a cluster is divided and arranged, and each of the ECC frames is divided and arranged in two pages.
[0028] That is, even in the case of the fixed frame length method, a situation may arise in which a cluster is arranged across two pages. If a cluster is arranged across two pages, this may deteriorate the performance of the memory system 1.
[0029] Next, the effect on the performance of the memory system 1 caused by arranging a cluster across two pages will be described with reference to Fig. 4. Fig. 4 shows an example in which the user data length fixing method is applied.
[0030] Here, it is assumed that the NAND memory 12 has two planes, and data is written to and read from each plane. In this case, the controller 11 can write and read two ECC frames to and from the NAND memory 12 in parallel for each plane.
[0031] In addition, it is assumed here that one section of each block is formed by two pages belonging to two different planes. Figure 4 shows an example of an arrangement of ECC frames in page 2 of one section in block M, and an example of an arrangement of ECC frames in page 2 of one section in block N.
[0032] Now, assume that the memory system 1 is in a state of reading a cluster of block M of plane 1 from the NAND memory 12 (c1). At this time, if a read command targeting, for example, a cluster of block N of plane 0 is received from the host 2, the controller 11 can immediately execute a read process of the cluster from the NAND memory 12 (c2). In contrast, if a read command targeting, for example, a cluster spanning block N of plane 0 and block N of plane 1 is received from the host 2, the controller 11 cannot execute a read process of the cluster from the NAND memory 12 until the reading of the preceding cluster indicated by reference symbol c1 is completed (c3).
[0033] In other words, the latency of a read command process for a cluster located on only one of planes 0 or 1 is determined by the state of the plane in which it is located. On the other hand, the latency of a read command process for a cluster that spans planes 0 and 1 is determined by the states of both planes in which it is located. For this reason, reading a cluster that spans two planes may take longer than reading a cluster located on only one plane.
[0034] In this way, when a cluster is arranged across two pages, there is a possibility that the performance of the memory system 1 may be deteriorated. Furthermore, when data that is frequently read is written to a cluster that spans two planes, there is a high possibility that the performance of the memory system 1 may be deteriorated further.
[0035] Although Fig. 4 shows an example in which the fixed user data length method is applied, the same applies when the fixed frame length method is applied. Consider a case in which two ECC frames including a certain cluster are arranged on two separate pages, and a read command targeting the cluster is received from host 2. In this case, a situation may arise in which one ECC frame corresponding to the cluster can be read immediately, but the other ECC frame must wait before reading it.
[0036] The memory system 1 of this embodiment can suppress the deterioration of performance caused by a cluster being arranged across two pages due to the exhaustion of the NAND memory 12. Returning to FIG. 1, the mechanism of the memory system 1 of this embodiment will be described.
[0037] The host 2 issues a read command to the memory system 1 to read multiple clusters. Whether the host 2 performs a sequential read or a random read, multiple clusters of data are the target, so a certain number of read commands or more are issued consecutively. When the host 2 issues a read command, the read command is received by the host interface unit 110 of the controller 11.
[0038] The host interface unit 110 transfers the read command to the control unit 120. The control unit 120, which has received the read command, first converts the logical address specified in the read command into a physical address. This process is called address resolution or the like. The logical address is an address indicating a location in the logical address space, that is, a logical location of the NAND memory 12. The physical address is an address indicating a location in the physical address space, that is, a physical location of the NAND memory 12. For address resolution, the control unit 120 manages information that holds the correspondence between logical addresses and physical addresses. The information that holds this correspondence is called a logical-physical conversion table or the like.
[0039] The control unit 120 sends an instruction to the NAND interface unit 130 to read data (ECC frame) from a position in the NAND memory 12 that is indicated by the converted physical address. The NAND interface unit 130 executes communication with the NAND memory 12 to output the instructed data (ECC frame) to the NAND memory 12. The NAND interface unit 130 passes the data (ECC frame) obtained from the NAND memory 12 to the control unit 120.
[0040] When the control unit 120 receives an ECC frame, it checks whether an error has occurred in the user data in the ECC frame by using the ECC in the ECC frame. If an error has occurred, the control unit 120 corrects the error by the ECC. The control unit 120 transfers the user data, after error correction as necessary, to the host interface unit 110.
[0041] The host interface unit 110 transmits the user data received from the control unit 120 to the host 2 as a response to the read command.
[0042] In addition to the above basic operation when a read command is received, in the memory system 1 of the embodiment, the host interface unit 110 first determines whether the read command received from the host 2 is a command related to a sequential read or a random read. As described above, whether the host 2 performs a sequential read or a random read, a certain number or more of read commands are issued consecutively. Therefore, the host interface unit 110 determines whether the logical addresses specified in these read command groups are consecutive. If they are consecutive, the host interface unit 110 determines that it is a sequential read, and if they are not consecutive, it determines that it is a random read.
[0043] The host interface unit 110 notifies the NAND interface unit 130 of the determination result of whether a read command is a sequential read or a random read upon receiving the read command via the control unit 120. When the NAND interface unit 130 receives the determination result that the read command is a random read from among the notifications, it increments the counter value in the access counter 131 that corresponds to the data to be read by the read command. In other words, the access counter 131 is a counter for counting the number of times each data item is randomly read.
[0044] The determination of whether the read command is a sequential read or a random read may be performed by the NAND interface unit 130 instead of the host interface unit 110. In this case, the NAND interface unit 130 determines whether the physical addresses of the instruction group sent consecutively from the control unit 120 are consecutive. If they are consecutive, the NAND interface unit 130 determines that it is a sequential read, and if they are not consecutive, it determines that it is a random read.
[0045] In addition, in the NAND interface unit 130, the unit of data for counting the number of random reads by the access counter 131 may be per ECC frame or per cluster, that is, per access unit of the host 2, in the case of the fixed user data length method. In the case of the fixed user data length method, counting the number of random reads per ECC frame is substantially the same as counting the number of random reads per cluster, that is, per access unit of the host 2. On the other hand, in the case of the fixed frame length method, it is preferable to count the number of random reads per cluster, that is, per access unit of the host 2. In the case of the fixed frame length method, by counting the number of random reads per cluster, it becomes unnecessary to manage the combination of two ECC frames to which the clusters are distributed. In other words, it is possible to prevent the number of random reads of a cluster distributed to two ECC frames from being counted twice the actual value.
[0046] Next, with reference to FIG. 5, a method will be described in which the memory system 1 of the embodiment uses the number of random reads counted by the access counter 131 to control the arrangement of clusters so as to suppress deterioration in performance due to wear of the flash memory.
[0047] As described above, the controller 11 executes compaction as appropriate. A typical example of compaction is moving data excluding invalidated data in N (N is a natural number equal to or greater than 2) blocks to M (M is a natural number less than N) blocks, making a storage area of NM blocks reusable. Compaction is executed when the number of remaining blocks in a state where data can be written falls below a threshold.
[0048] FIG. 5 is a diagram showing the placement control of clusters executed by the memory system. In FIG. 5, the two pages in the upper row are pages for one section in the block from which data is moved in compaction. On the other hand, the two pages in the lower row are pages for one section in the block to which data is moved in compaction. In FIG. 5, it is assumed that the user data length fixing method is applied. In FIG. 5, "low", "high", and "medium" indicate the relative magnitude of the number of random reads counted by the access counter 131 in the one section. In FIG. 5, "low", "medium", and "high" are written in order of the number of random reads. The controller 11 evaluates the number of random reads counted by the access counter 131 relatively in the first section and determines "low", "high", and "medium".
[0049] 5, before compaction is performed, an ECC frame including data 3 with a large number of random reads is arranged across two pages. When compaction is performed, the controller 11 obtains the value of the access counter 131 from the NAND interface unit 130, and controls the relocation of the ECC frame to the destination block based on this value.
[0050] More specifically, the controller 11 The ECC frame of the source block is moved to the destination block so that an ECC frame including data with a smaller number of random reads is arranged across two pages, instead of an ECC frame including data 3 with a larger number of random reads.
[0051] Here, the controller 11 arranges an ECC frame containing data with a "low" random read count across two pages instead of an ECC frame containing data with a "high" random read count, but it may also arrange an ECC frame containing data with a "low" random read count across two pages instead of an ECC frame containing data with a "medium" random read count.
[0052] The controller 11 selects, for example, an ECC frame including data that has been randomly read the least number of times among the data to be moved, as a candidate for allocation across two pages.
[0053] The controller 11 may control the arrangement of ECC frames for every two or more pages, for example. When the controller 11 controls the arrangement of ECC frames for every four pages, three page boundaries exist within one section formed by the four pages. When an ECC frame straddles two of the three page boundaries, the controller 11 selects two pieces of data in descending order of the number of random reads, and arranges the two ECC frames including the data on the boundaries of the two pages. In other words, the controller 11 arranges the ECC frames so that the two ECC frames including the data straddle two pages.
[0054] In other words, the memory system 1 of the embodiment places an ECC frame containing data with a low number of random reads across two pages, thereby reducing the access frequency of clusters that are placed across two pages, and thereby suppressing performance degradation.
[0055] The controller 11 may omit the control of the relocation involving the replacement of the ECC frames when the random read count of the data arranged across two pages may be judged to be "high" in the partition including the page, but may be judged to be relatively "low" in the entire memory system 1. For example, when the random read count of the data arranged across two pages does not meet the threshold, the data may be arranged across two pages in the destination. In other words, the control may be performed so that the data with the random read count equal to or greater than the threshold is not arranged across two pages. The threshold may be determined based on the upper limit of the latency of the read command processing. In this case, the occurrence of overhead can be suppressed as much as possible within the range where the performance can be maintained.
[0056] It should be noted that when the fixed frame length method is applied, the controller 11 places two ECC frames including a cluster with the fewest random read counts among the data to be moved in different pages.
[0057] 5 shows an example in which the number of ECC frames that can be placed in two pages of one section in the source block and the destination block of compaction is the same. There is a possibility that the degree of fatigue of the NAND memory 12 at the time when data is written to the destination block by compaction is greater than the degree of fatigue of the NAND memory 12 at the time when data is written to the source block. In this case, the number of ECC frames that can be placed in the destination block is smaller than that of the source block.
[0058] In this case, there is no cluster that is arranged across two pages in the source block, but there is a possibility that a cluster that is arranged across two pages will occur in the destination block. With reference to Fig. 6, cluster arrangement control in the case where a cluster that is arranged across two pages occurs in the destination block during compaction will be described. Fig. 6 is a diagram showing cluster arrangement control executed by the memory system. Here, it is assumed that the user data length fixing method is applied.
[0059] During compaction, the controller 11 reads the ECC frame from the source block, checks whether an error has occurred in the user data using the ECC, and if an error is detected, corrects the error using the ECC. When the controller 11 moves the user data to the destination block, it generates a new ECC and generates an ECC frame including the user data and the new ECC. The code length of the ECC generated after the fatigue level of the NAND memory 12 has progressed is longer than the code length of the previous ECC. Accordingly, in the case of the fixed user data length method, the ECC frame length becomes longer.
[0060] Figure 6 shows an example in which it may be necessary to place an ECC frame across two pages during compaction, in which data is moved from a source block before "cluster collapsing" to a destination block after "cluster collapsing".
[0061] The controller 11 uses, for example, a storage area of a static RAM (random access memory) (not shown) in the controller 11 or a dynamic RAM (DRAM) (not shown) connected to the controller 11 as a work area. The controller 11 first arranges an ECC frame to be written to a destination block in a work area that resembles the destination block, and checks whether an ECC frame arranged across two pages exists in the destination block. If an ECC frame exists, the controller 11 controls writing of the ECC frame to the destination block such that an ECC frame including data with a small number of random reads is arranged across two pages.
[0062] 6 shows an example in which an ECC frame including data 4 with a small number of random reads is arranged across two pages. If the ECC frames are mechanically rearranged to the destination block according to the order in the source block, the ECC frame including data 3 with a large number of random reads will be arranged across two pages. Therefore, the controller 11 arranges an ECC frame including data 4 with a small number of random reads across two pages, instead of the ECC frame including data 3 with a large number of random reads.
[0063] In this way, the memory system 1 of the embodiment can adaptively control the rearrangement of data in accordance with the progression of wear of the NAND memory 12 in order to suppress deterioration of performance.
[0064] In the case of the fixed frame length method, the cluster is not distributed to two ECC frames in the source block, but due to the wear of the NAND memory 12, the cluster may be distributed to two ECC frames in the destination block. In addition, there are cases where the two ECC frames in which the clusters are distributed must be arranged in two pages. In such a case, the controller 11 may select two ECC frames in which data (clusters) with a small number of random reads are distributed as candidates for the ECC frames to be arranged in two pages.
[0065] As the "cluster collapse" progresses, conversely, there may be cases where an ECC frame that was allocated across two pages in the source block of the compaction does not need to be allocated across two pages in the destination block. Figure 7 shows an example of a case where, as a result of the "cluster collapse", there are no ECC frames allocated across two pages.
[0066] Also, in the case of the fixed frame length method, for example, if the number of ECC frames that can be placed on each page becomes a multiple of the number of ECC frames to which clusters are distributed due to the progress of "cluster crushing," a case may arise in which a cluster is placed across two pages in the source block, but there are no clusters placed across two pages in the destination block.
[0067] FIG. 8 is a flowchart showing an operation procedure when the memory system 1 of the embodiment receives a read command.
[0068] When the controller 11 receives a read command (S101: YES), it determines the read type of the read command (S102). Specifically, it determines whether the read type is a sequential read or a random read.
[0069] In the case of a random read (S103: YES), the controller 11 increments the value of the access counter 131 corresponding to the data specified by the read command (S104). In the case of a sequential read (S103: NO), the controller 11 skips the process of step S104, that is, the increment of the value of the access counter 131 corresponding to the data.
[0070] FIG. 9 is a flowchart showing the operation procedure of compaction in the memory system 1 of the embodiment.
[0071] The controller 11 first determines whether the number of ECC frames included in the destination page group is the same as the number of ECC frames included in the source page group (S201). If the numbers are the same (S201: Yes), the process of S202 is skipped. If they are not the same (S201: No), the controller 11 places the data of the source page group in a work area that resembles the destination page group (S202). Here, the controller 11 checks whether there is data to be placed across two pages (S203).
[0072] If data is arranged across two pages (S203: YES), the controller 11 changes the arrangement of data in the destination page group in the work area (S204) so that data with a smaller number of random reads is arranged across two pages based on the value of the access counter 131. If data is not arranged across two pages (S203: NO), the controller 11 skips the process of step S204.
[0073] Then, the controller 11 writes the data allocated in the work area to the destination page group (S205).
[0074] As described above, the memory system 1 of the embodiment counts the number of random reads and controls the cluster with a small number of random reads to be placed across two pages in the destination block. In other words, the memory system 1 moves data so as to reduce the access frequency of the cluster across two pages.
[0075] As a result, the memory system 1 of the embodiment can suppress the deterioration of performance due to the fatigue of the NAND memory 12.
[0076] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]
[0077] 1...memory system, 2...host, 11...controller, 12...NAND memory, 110...host interface unit, 120...control unit, 130...NAND interface unit, 131...access counter.
Claims
1. a non-volatile memory having a number of blocks, each block containing a number of pages; A controller connectable to a host and controlling the non-volatile memory; Equipped with the controller has a counter that counts the number of accesses of the data stored in the nonvolatile memory in units of accesses of the data by the host; determining whether the read command received from the host is a command for sequential read or random read; If the read command is a random read, increment the value of a counter corresponding to the data specified by the read command; when it is necessary to allocate data of an access unit of the host data across two pages in the second block in the process of moving the data of the first block to the second block, the relocation of the data of the first block to the second block is controlled based on the value of the counter; Memory system.
2. the controller generates a frame including the user data received from the host and an error correction code for detecting and correcting an error in the user data, and writes the frame to the non-volatile memory; The memory system according to claim 1 , wherein the length of the user data is an access unit of data of the host.
3. the controller generates a frame including the user data received from the host and an error correction code for detecting and correcting an error in the user data, and writes the frame to the non-volatile memory; 2. The memory system according to claim 1, wherein the length of the frame remains unchanged before and after the process of moving the data of the first block to the second block.
4. The controller: Controlling data placement for each block of the non-volatile memory for each first number of pages among the plurality of pages included in each block; controlling a relocation of the data of the first block to the second block such that data having a small value of the counter among the data to be allocated in the first number of pages is allocated across two pages; 2. The memory system of claim 1.
5. 2. The memory system of claim 1, wherein the controller controls a relocation of data in the first block to the second block so that data whose counter value is equal to or greater than a threshold value is not allocated across two pages.
6. The controller: comparing a first logical address indicating a logical location of the non-volatile memory specified in the first read command with a second logical address specified in a second read command following the first read command, and determining whether the first read command and the second read command are commands relating to a sequential read or a random read; 2. The memory system of claim 1.
7. The controller: comparing a first physical address indicating a physical location of the non-volatile memory associated with a first logical address indicating a logical location of the non-volatile memory specified in a first read command with a second physical address associated with a second logical address specified in a second read command following the first read command, thereby determining whether the first read command and the second read command are commands relating to a sequential read or a random read; 2. The memory system of claim 1.
8. The controller: when a write command is received from the host, generating a frame including user data received from the host and an error correction code for detecting and correcting an error in the user data, and writing the frame to the non-volatile memory; when the frame is generated by a first method in which the user data has a fixed length and the error correction code and the frame have variable lengths, the counter counts the number of times data is accessed for each frame; when the frame is generated by a second method in which the frame has a fixed length and the user data and the error correction code have variable lengths, the counter counts the number of times the data has been accessed for each access unit of the host.
2. The memory system of claim 1.
9. The controller: When the frame is generated by the first method, a relocation of the data of the first block to the second block is controlled so that one frame including data whose counter value is equal to or greater than a threshold value is not allocated across two pages; When the frame is generated by the second method, a reallocation of the data of the first block to the second block is controlled so that two frames in which data having a value of the counter equal to or greater than a threshold value is distributed are not allocated to two separate pages.
9. The memory system of claim 8.
10. 1. A data relocation method executed by a controller that controls a non-volatile memory that is connectable to a host and includes a plurality of blocks, each of the blocks including a plurality of pages, the method comprising: determining whether the read command received from the host is a command for sequential read or random read; In the case of a random read, incrementing a value of a counter corresponding to the data designated by the read command in a counter for counting the number of accesses of the data stored in the non-volatile memory for each access unit of the host or for each frame including user data received from the host and an error correction code for detecting and correcting errors in the user data; when it is necessary to allocate the host access unit or the frame across two pages in the second block in the process of moving the data of the first block to the second block, the relocation of the data of the first block to the second block is controlled based on the value of the counter; Data rearrangement method.
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Memory system and control method
US20230073249A1