Receiving device and transmitting / receiving system

Abstract

To provide a receiving device and a transmitting / receiving system having a de-skew function for estimating an accurate amount of skew in a short time over a wide range of data rates.SOLUTION: In a transmitting / receiving system 1, a receiving device 20 includes a clock delay unit 21, a sampling unit 22, and a delay amount setting unit 23. The clock delay unit delays a received clock and outputs the clock with delay added. The sampling unit samples a data signal received with the delayed clock output by the clock delay unit. The delay amount setting unit sequentially sets a clock delay amount to each value during a training period in which a training data signal and a clock are sent from a transmitting device 10, samples the training data signal output by the sampling unit at each set value to obtain a data sequence, and after the end of the training period, sets the clock delay amount within a matching range in which the data sequence obtained at each set value matches the training data signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a receiving device and a transmitting / receiving system. [Background technology]

[0002] In a transmission / reception system having a transmitting device and a receiving device, a digital data signal and a clock sent from the transmitting device are sent to the receiving device via a transmission line and received by the receiving device, where the received data signal is sampled based on the received clock.

[0003] There are cases where separate transmission paths between a transmitting device and a receiving device are provided for a data signal and a clock (Patent Document 1). In this case, in order for the receiving device to accurately sample the data signal based on the clock (i.e., to suppress the occurrence of data reception errors), it is essential that the difference between the timing of the data signal and the clock when received by the receiving device is sufficiently small compared to the timing of the data signal and the clock when sent by the transmitting device.

[0004] The propagation time [sec] for the data signal and clock sent from the transmitting device to reach the receiving device via the transmission path is expressed as the transmission path length [m] / propagation speed [m / sec]. Therefore, in order to suppress the occurrence of data reception errors, it is required that the difference in transmission path length between the transmission path for propagating the data signal and the transmission path for propagating the clock is sufficiently small, and that the difference in propagation speed between the data signal and the clock is sufficiently small.

[0005] In applications that transmit large amounts of data from a transmitter to a receiver, the data rate of the signal may exceed Gbps. In this case, the signal wavelength is short, about a few centimeters. Therefore, both the transmission path length difference and the propagation speed difference between the data signal and the clock must be strictly controlled.

[0006] On the other hand, as a technique to avoid the above-mentioned strict requirements when separate transmission paths are provided for the data signal and the clock, CDR (clock data recovery) is known, which transmits a data signal with an embedded clock from a transmitting device to a receiving device. In CDR, the receiving device recovers the clock from the received data signal and samples the data signal based on this clock.

[0007] In a CDR, no transmission line for clock propagation is required, and the above problems do not occur when separate transmission lines are provided for the data signal and the clock. However, in a CDR, additional circuits such as an oscillator and a phase detection circuit are required in the receiving device, and an increase in power consumption is unavoidable.

[0008] In applications that require low power consumption, it is preferable to provide separate transmission paths for the data signal and the clock, rather than the CDR. An example of a standard for such a configuration is MIPI (registered trademark). MIPI (Mobile Industry Processor Interface) is used for communication between a camera sensor and a processor in devices that require video communication, such as mobile terminals and personal computers, as well as industrial equipment and in-vehicle equipment. MIPI D-PHY, one of the physical layer standards of MIPI, has a high data rate of several Gbps. For this reason, it is specified that the timing deviation (skew) between the data signal and the clock should be compensated (deskewed) in the receiving device.

[0009] A deskew circuit is implemented in a receiving device to compensate for the propagation time difference between a data signal and a clock. The deskew circuit estimates the amount of skew between the data signal and the clock when the receiving device receives the signal, sets a skew compensation amount based on the estimated skew amount, and compensates (deskews) the skew based on the set skew compensation amount. By compensating for the skew based on an appropriate skew compensation amount, it is possible to suppress the occurrence of data reception errors.

[0010] The data rate of the data signal transmitted from the transmitter to the receiver is not fixed, but may vary over a wide range. For example, in the transmission of images and videos assumed by MIPI D-PHY, the image size changes from moment to moment depending on the scene used by the user, and the amount of data transmitted and received may change to FHD, 4K, etc. as necessary, and the data rate of the data signal may change accordingly.

[0011] When the data rate of the data signal changes in this way, the deskew circuit must appropriately compensate for the skew at various data rates. For example, MIPI D-PHY version 3.0 specifies that deskewing must be performed smoothly in a data rate range of about 1.5 Gbps to 4.5 Gbps. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] U.S. Patent No. 9,281,935 Summary of the Invention [Problem to be solved by the invention]

[0013] As described above, in applications that require low power consumption, it is preferable to provide separate transmission paths for the data signal and the clock, but in that case, it is necessary to implement a deskew circuit that compensates for the skew in the receiving device. This deskew circuit is required to properly compensate for the skew over a wide range of data rates, as well as to be able to estimate the amount of skew in a short time and to estimate the amount of skew accurately. However, it is not easy to realize a deskew circuit that can meet all of these requirements.

[0014] The present invention has been made to solve the above problems, and has an object to provide a receiver having a deskew function capable of estimating an accurate amount of skew in a short time over a wide range of data rates, and a transmitting / receiving system including such a receiver and a transmitting device. [Means for solving the problem]

[0015] The receiving device of the present invention is a receiving device that receives a data signal and a clock transmitted from a transmitting device, and samples the received data signal based on the received clock.

[0016] A first aspect of the receiving device of the present invention includes (1) a clock delay unit that delays a received clock and outputs the delayed clock, (2) a sampling unit that samples a received data signal at a timing indicated by the clock output from the clock delay unit and outputs the sampled data, and (3) a delay setting unit that sets the amount of delay that the clock delay unit gives to the clock. The delay setting unit (a) sets the amount of delay to each value in sequence from an initial value to an end value during a training period in which a known training data signal and a clock are sent from the transmitting device, and acquires a data sequence output by the sampling unit by sampling the training data signal at each delay setting value, and (b) sets the amount of delay after the training period ends within a matching range in which the data sequence acquired during the training period at each delay setting value is consistent with the training data signal.

[0017] In a second aspect of the receiving device of the present invention, in addition to the first aspect, when the set value of the delay amount has not reached the end value at the end of a first training period among the multiple training periods, the delay amount setting unit (a) sets the delay amount to each value in sequence in the next second training period, following the first training period, and acquires a data sequence output by the sampling unit by sampling the training data signal at each set value of the delay amount, and (b) after the end of the second training period, sets the delay amount within a consistency range in which the data sequence acquired at each set value of the delay amount in past training periods including the first training period and the second training period is consistent with the training data signal.

[0018] In a third aspect of the receiving device of the present invention, in addition to the first or second aspect, the delay amount setting section sets the delay amount to the center of the matching range after the training period ends.

[0019] In a fourth aspect of the receiving device of the present invention, in addition to any of the first to third aspects, the delay amount setting unit sets the delay amount within the widest matching range among multiple matching ranges after the end of the training period.

[0020] In a fifth aspect of the receiving device of the present invention, in addition to any one of the first to fourth aspects, the clock delay unit includes a delay element including a first inverter unit and a second inverter unit connected in series. Each of the first inverter unit and the second inverter unit includes a PMOS transistor and an NMOS transistor whose drains are connected to each other, a first resistor circuit that is provided between the source of the PMOS transistor and a high potential supply end and has a variable resistance, and a second resistor circuit that is provided between the source of the NMOS transistor and a low potential supply end and has a variable resistance. Each of the first inverter unit and the second inverter unit outputs a clock that is a logical inversion of a clock input to the gates of the PMOS transistor and the NMOS transistor from the drains of the PMOS transistor and the NMOS transistor, and provides the clock with a delay according to the resistance of each of the first resistor circuit and the second resistor circuit.

[0021] In a sixth aspect of the receiving device of the present invention, in addition to the fifth aspect, the clock delay section includes a plurality of delay elements connected in series.

[0022] In a seventh aspect of the receiving device of the present invention, in addition to the fifth or sixth aspect, the clock delay section further comprises a driving buffer that receives as input the clock delayed by the delay element and outputs the clock to the sampling section.

[0023] In an eighth aspect of the receiving device of the present invention, in addition to any one of the first to seventh aspects, the receiving device complies with the MIPI standard.

[0024] The transmission / reception system of the present invention comprises (1) a transmitting device that transmits a data signal and a clock, and (2) the above-mentioned receiving device of the present invention that receives the data signal and clock sent from the transmitting device and samples the received data signal based on the received clock. Effect of the Invention

[0025] According to the present invention, it is possible to provide a receiving device having a deskew function that can estimate an accurate amount of skew in a short time over a wide range of data rates. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 is a diagram showing a configuration of a transmission / reception system 1. As shown in FIG. [Diagram 2] FIG. 2 is a timing chart illustrating an example of the operation of the sampling section 22. As shown in FIG. [Diagram 3] FIG. 3 is a diagram illustrating an example of the configuration of the clock delay unit 21. As shown in FIG. [Figure 4] FIG. 4 is a diagram showing schematic examples of waveforms of the input clock and the output clock in the clock delay section 21A. [Diagram 5] FIG. 5 is a diagram showing another example of the configuration of the clock delay unit 21. In FIG. [Figure 6]FIG. 6 is a diagram showing yet another example of the configuration of the clock delay unit 21. In FIG. [Figure 7] FIG. 7 is a diagram showing still another example of the configuration of the clock delay unit 21. In FIG. [Figure 8] FIG. 8 is a flowchart for explaining the process contents of the delay amount setting unit 23 during the training period. [Figure 9] FIG. 9 is a diagram for explaining the processing contents of the delay amount setting unit 23 after the end of the training period. [Figure 10] FIG. 10 is a diagram for explaining the process of the delay amount setting unit 23 when there are multiple training periods. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated descriptions are omitted. The present invention is not limited to these examples, but is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0028] 1 is a diagram showing a configuration of a transmission / reception system 1. The transmission / reception system 1 includes a transmission device 10 and a reception device 20. A transmission path 31 and a transmission path 32 are provided between the transmission device 10 and the reception device 20. The transmission path 31 transmits a data signal output from the transmission device 10 to the reception device 20. The transmission path 32 transmits a clock output from the transmission device 10 to the reception device 20.

[0029] The transmitting device 10 includes a selection unit 11. The selection unit 11 receives a data signal and a clock, selects either the data signal or the clock according to the logical value of a CALEN signal, and sends it to a transmission path 31. During the training period, the selection unit 11 selects the clock and outputs it to the transmission path 31 as a training data signal. During a normal period other than the training period, the selection unit 11 selects the data signal and outputs it to the transmission path 31.

[0030] The training period is a period for estimating the amount of skew in the receiving device 20. For example, the training period is provided immediately after the system is started up, and is also provided periodically or irregularly during the operation of the system.

[0031] The receiving device 20 receives the data signal (or the training data signal) and the clock sent from the transmitting device 10. The receiving device 20 includes a clock delay unit 21, a sampling unit 22, and a delay amount setting unit 23. The clock delay unit 21 delays the received clock and outputs the delayed clock to the sampling unit 22. The sampling unit 22 samples the received data signal at the timing indicated by the clock output from the clock delay unit 21, and outputs the sampled data. The delay amount setting unit 23 estimates the amount of skew based on the data output from the sampling unit 22, and sets the amount of delay (skew compensation amount) that the clock delay unit 21 gives to the clock based on the estimation result.

[0032] The clock delay unit 21 and the delay amount setting unit 23 configure a deskew circuit. That is, the clock delay unit 21 and the delay amount setting unit 23 estimate the amount of skew between the training data signal and the clock when the receiving device 20 receives the signal, set the amount of skew compensation based on the estimated amount of skew, and compensate (deskew) the skew based on the set amount of skew compensation.

[0033] The sampling section 22 preferably includes flip-flops 41 to 44 and a conversion section 45. Fig. 2 is a timing chart for explaining an example of the operation of the sampling section 22. This diagram shows an example of the operation of the sampling section 22 in a state where the skew is compensated.

[0034] Each of the flip-flops 41, 43, and 44 latches the input data at the rising edge of the clock output from the clock delay unit 21. The flip-flop 42 latches the input data at the falling edge of the clock output from the clock delay unit 21.

[0035] Flip-flop 41 latches the data signal received by receiving device 20 at the rising edge of the clock and outputs the latched data to flip-flop 43. Flip-flop 42 latches the data signal received by receiving device 20 at the falling edge of the clock and outputs the latched data to flip-flop 44.

[0036] Flip-flop 43 latches the data output from flip-flop 41 at the rising edge of the clock and outputs the latched data to conversion unit 45. Flip-flop 44 latches the data output from flip-flop 42 at the rising edge of the clock and outputs the latched data to conversion unit 45.

[0037] The conversion unit 45 receives the 2-bit parallel data output from the flip-flops 43 and 44 during each period of four cycles of the clock output from the clock delay unit 21, and outputs 8-bit parallel data consisting of these data. The delay amount setting unit 23 receives the 8-bit parallel data output from the conversion unit 45.

[0038] FIG. 2 shows a timing chart in the case where the conversion unit 45 converts 2-bit parallel data into 8-bit parallel data. However, the present invention is not limited to this. For example, the conversion unit 45 may convert the 2-bit parallel data output from the flip-flops 43 and 44 into 4-bit parallel data during each period of two cycles of the clock output from the clock delay unit 21. The frequency of the clock for driving the delay amount setting unit 23 can be slowed down by further converting the 2-bit parallel data into multi-bit parallel data by the conversion unit 45. The conversion unit 45 may convert the 2-bit parallel data output from the flip-flops 43 and 44 into serial data. The conversion unit 45 may not be provided, and the 2-bit parallel data output from the flip-flops 43 and 44 may be output as it is and input to the delay amount setting unit 23.

[0039] 3 is a diagram showing a configuration example of the clock delay unit 21. The clock delay unit 21A shown in this diagram is a delay element 50 consisting of a first inverter unit 51 and a second inverter unit 52 connected in series. The first inverter unit 51 and the second inverter unit 52 have a common configuration. Each of the first inverter unit 51 and the second inverter unit 52 includes a PMOS transistor 61, an NMOS transistor 62, a first resistor circuit 63, and a second resistor circuit 64.

[0040] The drains of the PMOS transistor 61 and the NMOS transistor 62 are connected to each other. The gates of the PMOS transistor 61 and the NMOS transistor 62 are connected to each other. The first resistance circuit 63 is provided between the source of the PMOS transistor 61 and a high potential supply end. The second resistance circuit 64 is provided between the source of the NMOS transistor 62 and a low potential supply end (ground potential supply end). The resistance values ​​of the first resistance circuit 63 and the second resistance circuit 64 are variable and are adjusted by instructions from the delay amount setting unit 23. The resistance circuits 63 and 64 can have a common configuration.

[0041] The first inverter section 51 and the second inverter section 52 each output a clock that is a logical inversion of a clock input to the gate of the PMOS transistor 61 and the NMOS transistor 62, which are connected to each other, from the drain of the PMOS transistor 61 and the NMOS transistor 62, which are connected to each other.

[0042] In the clock delay unit 21A, the delay of the output clock relative to the input clock depends on the resistance values ​​of the resistance circuits 63, 64 of the first inverter unit 51 and the second inverter unit 52. The resistance values ​​of the resistance circuits 63, 64 are preferably set to the same value.

[0043] 4 is a diagram showing an example of the waveforms of the input clock and the output clock in the clock delay unit 21A. Fig. 4(a) shows that the delay amount of the output clock with respect to the input clock is d when the resistance value R of the resistor circuits 63, 64 of the first inverter unit 51 and the second inverter unit 52 is set to approximately 0. Fig. 4(b) shows that the delay amount of the output clock with respect to the input clock is d+Δt when the resistance value R of the resistor circuits 63, 64 of the first inverter unit 51 and the second inverter unit 52 is set to a certain value.

[0044] Each of the resistance circuits 63, 64 includes a plurality of resistors and one or more switches, and the resistance value can be set by turning on / off each switch. The current flowing through the inverter units 51, 52 during operation is determined by the potential difference between the high potential supply end and the low potential supply end and the resistance value of the resistance circuits 63, 64. Therefore, the clock delay amount (d+Δt) in the clock delay unit 21A can be adjusted by turning on / off each switch in the resistance circuits 63, 64.

[0045] The larger the resistance value R of the resistor circuits 63, 64, the longer the delay amount (d+Δt) of the output clock relative to the input clock in the clock delay unit 21A. By appropriately setting the resistance values ​​of the resistor circuits 63, 64, the delay amount (d+Δt) of the output clock relative to the input clock can have good linearity with respect to the resistance value R. The delay adjustment amount Δt is approximately proportional to the resistance value R. The adjustment step Δt of the delay amount of the output clock relative to the input clock min corresponds to the adjustment step of the resistance value R.

[0046] In order to prevent the clock from being damaged by the delay provided by the clock delay unit 21A, it is preferable to adjust the resistance value R of the resistance circuits 63, 64 so that the delay adjustment amount Δt does not exceed 1 UI (unit interval). To realize a larger delay amount, a clock delay unit having the configuration example shown in FIG. 5 may be used.

[0047] 5 is a diagram showing another example of the configuration of the clock delay unit 21. The clock delay unit 21B shown in this figure includes N delay elements 50 connected in series. 1 ~50 N and a driving buffer 70. N is an integer equal to or greater than 2. N delay elements 50 1 ~50 N Each of them has a similar configuration to the delay element 50 (clock delay unit 21A) shown in FIG.

[0048] The larger N or the larger the resistance R, the greater the delay element 50 N The slew rate (the rate of change of the output voltage over time) of the clock output from the sampling section 22 is small. On the other hand, the slew rate of the clock supplied to the sampling section 22 is preferably large in order to determine the timing of sampling data in the sampling section 22. Therefore, it is preferable to provide a driving buffer 70. The driving buffer 70 is a clock that is supplied to the delay element 50 at the final stage. NThe clock output from the clock delay unit 21B is input and output to the sampling unit 22. By providing the driving buffer 70, the slew rate of the output clock from the clock delay unit 21B can be increased.

[0049] N delay elements 50 1 ~50 N The n-th delay element 50 n The delay in d+Δt n Then, the delay of the output clock relative to the input clock is Nd+Δt 1 +Δt 2 +···+Δt N Among these, the delay adjustment amount ΔT=Δt 1 +Δt 2 +···+Δt N is N delay elements 50 1 ~50 N This can be adjusted by setting the resistance values ​​of the respective resistor circuits 63 and 64.

[0050] 6 is a diagram showing yet another example of the configuration of the clock delay unit 21. The clock delay unit 21C shown in this diagram includes a plurality of inverters 80 connected in series and a voltage adjustment unit 81. The voltage adjustment unit 81 adjusts the voltage value provided to each of the plurality of inverters according to an instruction from the delay amount setting unit 23. In the clock delay unit 21C, the delay of the output clock relative to the input clock corresponds to the voltage value provided to each of the plurality of inverters.

[0051] 7 is a diagram showing yet another example of the configuration of the clock delay unit 21. The clock delay unit 21D shown in this diagram includes a plurality of inverters 80 connected in series and a selection unit 82. The selection unit 82 selects and outputs a clock output from one of the plurality of inverters 80 in response to an instruction from the delay amount setting unit 23. In the clock delay unit 21D, the delay of the output clock relative to the input clock corresponds to the number of inverters 80 through which the clock passes from input to output.

[0052] Among clock delay unit 21A (FIG. 3), clock delay unit 21B (FIG. 5), clock delay unit 21C (FIG. 6), and clock delay unit 21D (FIG. 7), the configurations of clock delay unit 21A (FIG. 3) and clock delay unit 21B (FIG. 5) are preferable for the following reasons.

[0053] In the clock delay unit 21C (FIG. 6), the terminal voltage of the transistor of the nonlinear element constituting each inverter changes directly, so the linearity of the delay amount with respect to the voltage value applied to each inverter is not good, and therefore it is difficult to estimate the skew amount. In order to deskew appropriately over a wide range of data rates, it is necessary to have a wide range of delay amount variation, which requires a large number of inverters connected in series. This is undesirable because it increases power consumption.

[0054] In the clock delay unit 21D (FIG. 7), the delay adjustment step is the sum of the delays of two inverter stages. Therefore, the maximum data rate at which deskewing is possible is determined by the performance of the transistors that make up each inverter, which is a major constraint. Also, to deskew at a low data rate, the number of inverters connected in series must be increased. This is undesirable because it increases power consumption.

[0055] Compared to clock delay unit 21C (FIG. 6) and clock delay unit 21D (FIG. 7), clock delay unit 21A (FIG. 3) and clock delay unit 21B (FIG. 5) are preferable because they consume less power, have excellent linearity in the amount of delay, and can accommodate a wide range of data rates.

[0056] In the flip-flops 41 to 44 included in the sampling unit 22, depending on the input timing of the data and the clock, a setup violation or a hold violation occurs, and erroneous data is latched. The clock delay unit 21 gives an appropriate delay to the received clock so that neither a setup violation nor a hold violation occurs, and outputs the delayed clock to the sampling unit 22. To achieve this, the amount of delay that the clock delay unit 21 gives to the clock is adjusted by an adjustment width MΔt min In the range of adjustment steps Δt min If there are (M+1) possible settings, the delay adjustment step Δt min is preferably smaller than "1UI-(setup time+hold time)", and the delay amount adjustment width MΔt min is preferably greater than the "setup time + hold time."

[0057] Next, the processing contents of the delay amount setting unit 23 will be described in detail. The processing of the delay amount setting unit 23 includes processing during a training period and processing after the end of the training period. The training period is a period during which the receiving device 20 receives a training data signal to estimate the amount of skew. In MIPI, immediately after the system is started, 15 A training period of at least 20 minutes will be provided, and training will be conducted periodically or irregularly during the operation of the system. 10 There will be training periods beyond the UI, and the frequency of training periods will vary depending on the requirements of the application.

[0058] During the training period, a known training data signal and a clock are sent from the transmitting device 10 to the receiving device 20. The training data signal is preferably a signal in which a data string of a certain pattern is repeated. In MIPI, a signal whose logical value is inverted every 1 UI is sent as the training data signal. The training data signal sent from the transmitting device 10 may have the same waveform as the clock sent from the transmitting device 10. In the configuration shown in FIG. 1, during the training period, a clock is selected by the selection unit 11 in the transmitting device 10, and this is sent to the transmission path 31 as the training data signal.

[0059] The delay amount setting unit 23 adjusts the delay amount given to the clock in the clock delay unit 21 from the initial value to the final value by a certain amount (adjustment step Δt min ) to set each set value in sequence. Then, the delay amount setting section 23 acquires the data sequence output by the sampling section 22 after sampling the training data signal at each set value of the delay amount.

[0060] After the training period ends, the delay amount setting unit 23 sets the amount of delay to be given to the clock in the clock delay unit 21 thereafter within a matching range in which the data sequence acquired at each delay amount setting value during the training period is consistent with the training data signal.

[0061] The processing contents of the delay amount setting unit 23 during the training period are specifically as follows. The delay amount that the clock delay unit 21 gives to the clock is adjusted by an adjustment width MΔt min In the range of adjustment steps Δt min The delay adjustment amount ΔT can be set in (M+1) steps. m is ΔT m =mΔt min The initial value of the delay adjustment amount ΔT 0 is 0, and the end value of the delay adjustment amount ΔT M is MΔt min It is.

[0062] 8 is a flowchart for explaining the process of the delay amount setting unit 23 during the training period. In step S1, the delay amount setting unit 23 sets m to 0. In step S2, the delay amount setting unit 23 sets the delay adjustment amount ΔT m In step S3, the delay amount setting unit 23 sets the delay adjustment amount ΔT m With m set, the sampling unit 22 samples and acquires a data string output from the sampling unit 22. In step S4, the delay amount setting unit 23 increments the value of m by 1. In step S5, the delay amount setting unit 23 determines whether or not m exceeds M. If the delay amount setting unit 23 determines in step S5 that m exceeds M, it assumes that the end value of the delay adjustment amount has been reached and ends the process. If the delay amount setting unit 23 determines in step S5 that m does not exceed M, it returns to step S2. In this manner, the processes of steps S2 and S3 are performed for each m value in the range from m=0 to m=M.

[0063] Specifically, the processing contents of the delay amount setting unit 23 after the training period is completed are as follows. The delay amount setting unit 23 judges whether or not the data sequence acquired at each delay amount setting during the training period is consistent with the training data signal. This judgment may be made if the training data signal contains a data sequence of the same pattern as the acquired data sequence at each delay amount setting, and the two are deemed to be consistent.

[0064] For example, when a training data signal is used in which the logical value is inverted every 1 UI (i.e., the logical value of each bit is repeated as 10101010...), if the data sequence output from the sampling unit 22 has a pattern in which the logical value is inverted every 1 UI (10101010... or 01010101...), then the data sequence output from the sampling unit 22 is consistent with the training data signal, and a delay amount sufficient to enable appropriate deskew has been given to the clock in the clock delay unit 21.

[0065] When a training data signal whose logical value is inverted every 1 UI is used, if the pattern obtained by taking the bit-wise exclusive OR of the data sequence output from the sampling unit 22 and the pattern of the training data signal is 00000000... or 11111111..., then the data sequence output from the sampling unit 22 is consistent with the training data signal, and a delay amount sufficient to enable appropriate deskew has been given to the clock in the clock delay unit 21.

[0066] Therefore, the delay amount setting unit 23 counts the number of bits for which the bit-by-bit exclusive OR value between the data string of number K of bits output from the sampling unit 22 and the pattern of the training data signal is 1 for each set value of the delay amount, and if the count value C is 0 or K, it can determine that a delay amount sufficient to enable appropriate deskew has been given to the clock in the clock delay unit 21.

[0067] FIG. 9 is a diagram for explaining the processing contents of the delay amount setting unit 23 after the training period ends. FIG. 9(a) shows the relationship between the m value and the count value C. FIG. 9(b) shows the waveform of the training data signal input to the sampling unit 22. The horizontal axis of FIG. 9(b) represents the sampling timing in the sampling unit 22 by the m value. In the example shown in this figure, in the first matching range from m=0 to m=2, the second matching range from m=4 to m=8, and the third matching range from m=9 to m=15, the data string acquired at each setting value of the delay amount is matched with the training data signal, and a delay amount that enables appropriate deskew is given to the clock in the clock delay unit 21.

[0068] The delay amount setting unit 23 sets the delay amount to be subsequently given to the clock in the clock delay unit 21 to any one of the first to third matching ranges. It is preferable that the delay amount setting unit 23 sets the delay amount to be subsequently given to the clock in the clock delay unit 21 to the center of any one of the first to third second matching ranges. It is also preferable that the delay amount setting unit 23 sets the delay amount to be subsequently given to the clock in the clock delay unit 21 to within the third matching range, which is the widest of the first to third. In this example, ΔT corresponding to m=12, which is the center of the third matching range, is set to 1. 12 It is most preferable to set it to

[0069] Since the length of the training period is limited, the delay amount setting unit 23 changes the delay amount given to the clock in the clock delay unit 21 from the initial value to the end value by a fixed amount at a time to set each set value in sequence, but there are cases where the set value of the delay amount does not reach the end value within the training period. In such a case, if there are multiple training periods, the delay amount setting unit 23 can perform the following processing.

[0070] When the set value of the delay amount has not reached the end value at the end of a first training period among the multiple training periods, the delay amount setting unit 23 sets the delay amount to each value in sequence following the first training period in the next second training period, and acquires a data sequence output by the sampling unit 22 by sampling the training data signal at each set value of the delay amount. Then, after the end of the second training period, the delay amount setting unit 23 sets the delay amount to be given to the clock in the clock delay unit 21 thereafter within a matching range in which the data sequence acquired at each set value of the delay amount in the past training periods including the first training period and the second training period is matched with the training data signal. In this case as well, if there are multiple matching ranges after the end of each training period, it is most suitable to set the delay amount corresponding to the m value that is the center of the widest matching range among these multiple matching ranges.

[0071] FIG. 10 is a diagram for explaining the processing contents of the delay amount setting unit 23 when there are multiple training periods. FIG. 10(a) shows the relationship between the m value and the count value C. FIG. 10(b) shows the transition of the optimal m value after the end of each training period. In this figure, it is assumed that training periods A to F are provided in order. The delay amount setting unit 23 sets the delay amount to each value from m=0 to m=2 in training period A in order, sets the delay amount to each value from m=3 to m=5 in training period B in order, sets the delay amount to each value from m=6 to m=8 in training period C in order, sets the delay amount to each value from m=9 to m=11 in training period D in order, sets the delay amount to each value from m=12 to m=14 in training period E in order, and sets the delay amount to each value from m=15 to m=17 in training period F in order. The delay amount setting section 23 acquires the data sequence output by the sampling section 22 after sampling the training data signal at each delay amount setting value during each training period.

[0072] In this case, after the end of the training period A, the delay amount setting unit 23 sets ΔT 1 After the end of the training period C, the matching period from m=4 to m=8 is longer than the matching period from m=0 to m=2, so the delay amount setting unit 23 sets ΔT 6 After the end of the training period E, the matching period from m=9 to m=14 is the longest, so the delay amount setting unit 23 sets ΔT 11 (Or, ΔT corresponding to m=12 12 )

[0073] In this way, even if the delay amount setting value does not reach the end value within a certain training period, the delay amount setting unit 23 continues to set the delay amount to each value in sequence within the next training period, and obtains the data sequence output by the sampling unit 22 after sampling the training data signal at each delay amount setting value, thereby making it possible to optimally set the delay amount to be given to the clock in the clock delay unit 21 thereafter.

[0074] As described above, the receiving device of this embodiment has a deskew function that can estimate an accurate skew amount in a short time at a wide range of data rates. Furthermore, even if the training period is short, the receiving device has a function of pausing training and resuming training when a training pattern is input again, so that the receiving device can estimate an accurate skew amount and has the deskew function. [Explanation of symbols]

[0075] 1...transmission / reception system, 10...transmission device, 11...selection unit, 20...reception device, 21, 21A to 21D...clock delay unit, 22...sampling unit, 23...delay amount setting unit, 31, 32...transmission path, 41 to 44...flip-flops, 45...conversion unit, 50, 50 1 ~50 N ...delay element, 51...first inverter section, 52...second inverter section, 61...PMOS transistor, 62...NMOS transistor, 63...first resistance circuit, 64...second resistance circuit, 70...drive buffer, 80...inverter, 81...voltage adjustment section, 82...selection section.

Claims

1. A receiving device that receives a data signal and a clock transmitted from a transmitting device, and samples the received data signal based on the received clock, comprising: a clock delay unit that delays the received clock and outputs the delayed clock; a sampling unit that samples a received data signal at a timing indicated by the clock output from the clock delay unit and outputs the sampled data; a delay amount setting unit that sets the amount of delay that the clock delay unit applies to the clock; Equipped with The delay amount setting unit is during a training period in which a known training data signal and a clock are transmitted from the transmitting device, the delay amount is set to each value in sequence from an initial value to an end value, and a data string output by the sampling unit sampling the training data signal at each set value of the delay amount is obtained; After the training period is completed, the delay amount is set within a matching range in which the data sequence acquired during the training period at each set value of the delay amount is matched with the training data signal. Receiving device.

2. The delay amount setting unit is When the set value of the delay amount has not reached an end value at the end of a first training period among the plurality of training periods, In a next second training period, the delay amount is set to each value in sequence following the first training period, and a data sequence output by the sampling unit sampling the training data signal at each set value of the delay amount is obtained; after the second training period is completed, the delay amount is set within a matching range in which the data sequence acquired at each set value of the delay amount during a past training period including the first training period and the second training period is matched with the training data signal; 2. The receiving device according to claim 1.

3. the delay amount setting unit sets the delay amount to the center of the matching range after the training period ends.

2. The receiving device according to claim 1.

4. the delay amount setting unit, after the end of the training period, when there are a plurality of matching ranges, sets the delay amount within the widest matching range among the plurality of matching ranges.

2. The receiving device according to claim 1.

5. the clock delay unit includes a delay element including a first inverter unit and a second inverter unit connected in series; Each of the first inverter unit and the second inverter unit is a PMOS transistor and an NMOS transistor, the drains of which are connected to each other; a first resistor circuit having a variable resistance value, the first resistor circuit being provided between the source of the PMOS transistor and a high potential supply terminal; a second resistor circuit having a variable resistance value, the second resistor circuit being provided between the source of the NMOS transistor and a low potential supply terminal; Including, a clock obtained by logically inverting a clock input to each of the gates of the PMOS transistor and the NMOS transistor is output from each of the drains of the PMOS transistor and the NMOS transistor; imparting a delay to a clock in accordance with a resistance value of each of the first resistance circuit and the second resistance circuit; 2. The receiving device according to claim 1.

6. The clock delay unit includes a plurality of the delay elements connected in series.

6. The receiving device according to claim 5.

7. the clock delay unit further includes a driving buffer that receives the clock delayed by the delay element and outputs the clock to the sampling unit; 6. The receiving device according to claim 5.

8. 2. The receiving device according to claim 1, which is compliant with the MIPI standard.

9. A transmitting device that transmits a data signal and a clock; A receiving device according to any one of claims 1 to 8, which receives a data signal and a clock transmitted from the transmitting device and samples the received data signal based on the received clock; A transmitting and receiving system comprising:

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