Semiconductor device

Abstract

To provide a semiconductor device that reduces on-resistance.SOLUTION: A semiconductor device 100 includes a drain electrode 21, an n+ type drain region 5, an n- type drift region 1, a pair of gate electrodes 10, a p-type base region 2, an n+ type source region 3, and a source electrode 22. The n+ type drain region is provided on the drain electrode, and the n- drift region is provided on the n+ drain region. The pair of gate electrodes are provided on the drain electrode via a gate insulating layer 11. A distance between the gate insulating layers in an X direction perpendicular to a Z direction is 150 nm or more and 450 nm or less. The p-type base region is provided between the pair of gate electrodes. The n+ type source region is provided on the p-type base region. The source electrodes are provided on the pair of gate electrodes via insulating layers, and include contact portions 22a that contact a part of the p-type base region and the source n+ type region in the X direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs) are used for applications such as power conversion, etc. It is desirable for the on-resistance of the semiconductor device to be low. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-12647 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a pair of gate electrodes, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode. The pair of gate electrodes are provided on the first semiconductor region via a gate insulating layer. The distance between the gate insulating layers in a second direction perpendicular to the first direction from the first electrode to the first semiconductor region is 150 nm or more and 450 nm or less. The second semiconductor region is provided between the pair of gate electrodes. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the pair of gate electrodes via an insulating layer. The second electrode includes a contact portion that contacts a part of the second semiconductor region and the third semiconductor region in the second direction. The length of the bottom of the contact portion in the second direction is longer than 28 nm and is 206 nm or less. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is an enlarged cross-sectional view of a portion of FIG. [Diagram 3] FIG. 3 is an enlarged cross-sectional view of a portion of FIG. [Figure 4] FIG. 4 shows the results of a simulation showing the characteristics of the semiconductor device. [Diagram 5] FIG. 5 shows the results of a simulation showing the characteristics of the semiconductor device. [Figure 6] FIG. 6 shows the results of a simulation showing the characteristics of the semiconductor device. [Figure 7] FIG. 7 shows the results of a simulation showing the characteristics of the semiconductor device. [Figure 8] FIG. 8 shows the results of a simulation showing the characteristics of the semiconductor device. [Figure 9] 9(a) and 9(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] 10(a) and 10(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 11] 11A and 11B are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 12] 12A and 12B are cross-sectional views showing a method for manufacturing a semiconductor device according to the embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. In this specification and each drawing, elements similar to those already explained are given the same reference numerals, and detailed explanations are omitted as appropriate. In the following description, n + , n - , p + The notation p indicates the relative impurity concentration in each conductivity type. + is - This indicates that the n-type impurity concentration is relatively higher than that of p + indicates that the p-type impurity concentration is relatively higher than that of p. Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0008] FIG. 1 is a perspective cross-sectional view showing a part of a semiconductor device according to an embodiment. The semiconductor device 100 according to the embodiment is a MOSFET. - p-type (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) base region 2 (second semiconductor region), n +Source region 3 (third semiconductor region), p + contact region 4 (fourth semiconductor region), n + The semiconductor device includes a drain region 5, a gate electrode 10, a gate insulating layer 11, an insulating layer 12, a drain electrode 21 (first electrode), and a source electrode 22 (second electrode). In FIG. 1, the source electrode 22 is indicated by a dashed line.

[0009] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction toward the drift region 1 is defined as the Z direction (first direction). Two directions that are perpendicular to the Z direction and perpendicular to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction toward the n-type drift region 1 is called "up" and the opposite direction is called "down." These directions are - The shape is based on the relative position to the drift region 1 and is independent of the direction of gravity.

[0010] A drain electrode 21 is provided on the bottom surface of the semiconductor device 100. + The drain region 5 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. - The drift region 1 is n + The n-type drain region 5 is provided on the n-type drain region 5. - The drift region 1 is n + The n-type drain region 5 is electrically connected to the drain electrode 21. - The n-type impurity concentration of the n-type drift region 1 is + The n-type impurity concentration of the n-type drain region 5 is lower than that of the n-type drain region 5 .

[0011] The gate electrode 10 is - A p-type base region 2 is provided on the n-type drift region 1 via a gate insulating layer 11. A plurality of gate electrodes 10 are provided in the X direction, and these gate electrodes 10 are spaced apart from each other. A p-type base region 2 is provided between adjacent gate electrodes 10. The p-type base region 2 has an n-type - Located above the drift region 1.+ The p-type source region 3 is provided on the p-type base region 2. The gate electrode 10 has an n-type - A part of the p-type drift region 1, the p-type base region 2, and the n + The gate insulating layer 11 faces a part of the source region 3 .

[0012] The source electrode 22 is provided on each of the gate electrodes 10 via an insulating layer 12. The source electrode 22 is located on the upper surface of the semiconductor device 100 and is connected to the p-type base region 2 and the n-type base region 3. + The source electrode 22 includes a contact portion 22a. The contact portion 22a extends downward and is electrically connected to a part of the p-type base region 2 and the n-type source region 3 in the X direction. + It borders on the source region 3. + The p-type contact region 4 is provided between the p-type base region 2 and the contact portion 22a. + The p-type impurity concentration of the p-type contact region 4 is higher than the p-type impurity concentration of the p-type base region 2 .

[0013] p-type base region 2, n + Shape source area 3, p + The contact region 4, the gate electrode 10, and the contact portion 22a each extend in the Y direction and are provided in a stripe pattern.

[0014] The operation of the semiconductor device 100 will be described. With a positive voltage applied to the drain electrode 21 with respect to the source electrode 22, a voltage equal to or higher than the threshold is applied to the gate electrode 10. As a result, a channel (inversion layer) is formed in the p-type base region 2. Electrons pass through the channel and are transferred from the source electrode 22 to the n-type - The current flows to the p-type drift region 1, turning on the semiconductor device 100. When the voltage applied to the gate electrode 10 thereafter becomes lower than the threshold, the channel in the p-type base region 2 disappears, turning the semiconductor device 100 off.

[0015] An example of the material for each component is explained below. - p-type drift region 1, p-type base region 2, n+ Shape source area 3, p + shaped contact region 4, and n + The n-type drain region 5 includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 12 include an insulating material such as silicon oxide. The drain electrode 21 and the source electrode 22 include a metal such as titanium, gold, or aluminum. As long as the drain electrode 21 and the source electrode 22 can be in ohmic contact with the semiconductor region, the specific material and composition of the drain electrode 21 and the source electrode 22 can be changed as appropriate.

[0016] The preferred ranges of impurity concentrations for each semiconductor region are as follows: - The n-type impurity concentration in the drift region 1 is 1.0×10 16 atom / cm 3 Above 1.0×10 18 atom / cm 3 The n-type impurity concentration in the p-type base region 2 is 1.0×10 17 atom / cm 3 Above 1.0×10 19 atom / cm 3 The following is true: + The n-type impurity concentration in the source region 3 is 5.0×10 18 atom / cm 3 Above 5.0×10 20 atom / cm 3 The following is the result. + The n-type impurity concentration in the contact region 4 is 5.0×10 18 atom / cm 3 Above 5.0×10 20 atom / cm 3 The following is true: + The n-type impurity concentration in the n-type drain region 5 is 1.0×10 19 atom / cm 3 Above 1.0×10 21atom / cm 3 The following is the result.

[0017] 2 and 3 are enlarged cross-sectional views of a portion of FIG. 2 and 3 are enlarged cross-sectional views of the same portion of the semiconductor device 100. The detailed structure and specific dimensions of each element of the semiconductor device 100 will be described with reference to FIGS.

[0018] The p-type base regions 2 and the gate electrodes 10 are alternately provided in the X direction. The distance D between a pair of adjacent gate insulating layers 11 in the X direction is preferably 150 nm or more and 450 nm or less. The width W of the gate electrodes 10 is preferably 160 nm or more and 240 nm or less. For example, the thickness of the gate insulating layer 11 is 20 nm. The thickness of the gate insulating layer 11 is preferably 10 nm or more and 30 nm or less. The sum of the distance D, the width W, and twice the thickness of the gate insulating layer 11 is also referred to as the pitch of the gate electrodes 10. The pitch of the gate electrodes 10 is preferably 450 nm or more and 650 nm or less.

[0019] The width W1 of the contact portion 22a is greater than 28 nm and less than or equal to 206 nm. "Width" refers to the length in the X direction. The length L1 of the contact portion 22a in the Z direction is preferably greater than or equal to 250 nm and less than or equal to 450 nm. The side surface of the contact portion 22a may be inclined with respect to the Z direction. The inclination of the side surface of the contact portion 22a with respect to the Z direction is preferably greater than or equal to 0 degrees and less than or equal to 5 degrees.

[0020] When the side surface of the contact portion 22a is inclined, the width W1 corresponds to the width of the lower end of the contact portion 22a. In that case, the width W2 of the upper end of the contact portion 22a is preferably greater than 50 nm and equal to or less than 270 nm. More specifically, the contact portion 22a refers to a portion of the source electrode 22 that is located between the gate insulating layers 11 and between the insulating layers 12 in the X direction and has a substantially constant width in the Y direction. The upper end of the contact portion 22a refers to the upper end of the portion with a constant width. When the side surface of the contact portion 22a is not inclined, the width W2 is equal to the width W1.

[0021] In addition, when the side surface of the contact portion 22a is inclined, the width W and the distance D refer to the dimensions in the X direction at the depth where the bottom of the contact portion 22a is provided. Specifically, first, the position (depth) where the bottom of the contact portion 22a exists in the Z direction is identified. Next, at the depth where the bottom of the contact portion 22a exists, the end of the gate electrode 10 in the X direction, the interface between the p-type base region 2 and the gate insulating layer 11, etc. are identified. Based on these ends, interfaces, etc., the distance D and the width W are measured.

[0022] 3, the source electrode 22 includes a contact portion 22b in addition to the contact portion 22a. The contact portion 22b is provided on the contact portion 22a and is located between the insulating layers 12 in the X direction. The width of the contact portion 22b is wider than the width of the contact portion 22a. For example, the width of the contact portion 22b changes stepwise from the width of the contact portion 22a.

[0023] As shown in Figure 2, n + The upper surface US of the source region 3 may include a first region US1 and a second region US2. The inclination of the first region US1 with respect to the X direction is 0 degrees or more and 15 degrees or less. The inclination of the second region US2 with respect to the X direction is 30 degrees or more and 90 degrees or less. The position of the first region US1 in the X direction is between the position of the second region US2 in the X direction and the position of the contact portion 22a in the X direction. The width W3 of the first region US1 is 87 nm or more. The width W4 of the second region US2 is 5 nm or more and 20 nm or less. The upper limit of the width W3 is not particularly limited and is appropriately designed according to the width W1 of the contact portion 22a, the pitch P of the gate electrode 10, etc.

[0024] As shown in FIG. 3, in the semiconductor device 100, +The source region 3 may include a first portion 3a and a second portion 3b. The first portion 3a has a first region US1 shown in FIG. 2. The second portion 3b is located between the first region US1 and the insulating layer 12 in the X direction. For example, the n-type impurity concentration of the second portion 3b is lower than the n-type impurity concentration of the first portion 3a. Therefore, the electrical resistivity of the second portion 3b is higher than the electrical resistivity of the first portion 3a.

[0025] As shown in Figure 2, n - A first junction J1 is formed between the p-type drift region 1 and the p-type base region 2. + A second junction J2 is formed between the first junction J1 and the second junction J2. A bottom surface LS of the contact portion 22a is located above the first junction J1 and below the second junction J2. A distance D1 (first distance) in the Z direction from the first junction J1 to the bottom surface LS is 0.5 times or more a distance D2 (second distance) in the Z direction from the first junction J1 to the second junction J2. That is, the bottom surface LS is located above the center between the first junction J1 and the second junction J2.

[0026] 4 to 8 show simulation results showing the characteristics of the semiconductor device. FIG. 4 shows a simulation result showing the relationship between the pitch P and the on-resistance Ron. FIG. 5 shows a simulation result showing the relationship between the pitch P and the threshold voltage Vth. FIG. 6 shows a simulation result showing the relationship between the pitch P and the breakdown voltage Vdss. In FIG. 4 to FIG. 6, the numerical values ​​of the on-resistance Ron, the threshold voltage Vth, and the breakdown voltage Vdss are expressed in relative ratios. The threshold voltage Vth is a voltage applied to the gate electrode 10 required to turn on the semiconductor device 100. The breakdown voltage Vdss means a maximum voltage that can be applied between the drain electrode 21 and the source electrode 22 when the gate electrode 10 and the source electrode 22 are short-circuited. In the simulation, the width W is set to 160 nm. The length L1 is set to 390 nm. The width W1 is set to 70 nm.

[0027] It can be seen from the simulation results in FIG. 4 that the on-resistance Ron increases as the pitch P becomes wider. This is because the number of gate electrodes 10 per unit area decreases as the pitch P becomes wider. The fewer the number of gate electrodes 10 per unit area, the smaller the channel area per unit area becomes. In other words, the channel density decreases. When the channel density decreases, the on-resistance Ron increases. On the other hand, it can be seen from the simulation results in FIG. 4 that the on-resistance Ron increases even when the pitch P is too narrow. When the pitch P is narrow, p + The p-type impurities are more likely to diffuse from the contact region 4 to the vicinity of the interface between the p-type base region 2 and the gate insulating layer 11. As the p-type impurity concentration at the interface increases, the resistance to electrons increases, and the on-resistance Ron increases. When the pitch P is 400 nm or less, the effect of the increase in on-resistance Ron due to the diffusion of p-type impurities becomes greater, and the on-resistance Ron increases. However, since the increase is slight, from the viewpoint of on-resistance Ron, it is sufficient for the pitch P to be 650 nm or less.

[0028] According to the simulation results in Fig. 5, the narrower the pitch P, the higher the threshold voltage Vth. Specifically, when the pitch P is 400 nm or less, the threshold voltage Vth increases significantly. This is because, as described above, when the pitch P is narrow, the p-type impurity concentration at the interface between the p-type base region 2 and the gate insulating layer 11 increases. Therefore, from the viewpoint of the threshold voltage Vth, it is preferable that the pitch P is 450 nm or more.

[0029] 6, when the pitch P is narrow or wide, the breakdown voltage Vdss decreases. + The ratio of the area of ​​the contact region 4 and the area of ​​the contact portion 22a are reduced. If the pitch P is too wide, holes are not efficiently discharged when breakdown occurs in the semiconductor device 100, and the breakdown voltage Vdss decreases. On the other hand, if the pitch P is too narrow, +The p-type impurity concentration of the p-type base region 2 increases due to the influence of the p-type contact region 4. As a result, the depletion layer in the p-type base region 2 becomes less likely to extend in the X direction, and the breakdown voltage Vdss decreases. Therefore, from the viewpoint of the breakdown voltage Vdss, it is preferable that the pitch P is 450 nm or more and 650 nm or less.

[0030] According to the simulation results of FIGS. 4 to 6, the pitch P is preferably not less than 450 nm and not more than 650 nm.

[0031] FIG. 7 shows the results of a simulation showing the relationship between the width W1 of the contact portion 22a and the on-resistance Ron. In FIG. 7, the numerical value of the on-resistance Ron is expressed as a relative ratio. In the simulation, the width W is set to 160 nm. The length L1 is set to 390 nm. The pitch P is set to 600 nm. From the results shown in FIG. 7, it can be seen that the on-resistance Ron is almost constant when the width W1 is 160 nm or less. When the width W1 exceeds 160 nm, the on-resistance Ron gradually increases. This is considered to be because the width W1 becomes wider and the p-type impurity becomes more likely to diffuse near the interface between the p-type base region 2 and the gate insulating layer 11. When the width W1 exceeds 206 nm and reaches 230 nm, the on-resistance Ron increases by more than 10% compared to when the width W1 is less than 100 nm. For this reason, it is preferable that the width W1 is 206 nm or less. In order to further suppress the increase in the on-resistance Ron, it is more preferable that the width W1 is 160 nm or less.

[0032] The width W1 is preferably 28 nm or more. When the width W1 is less than 28 nm, the occurrence of impact ionization has been confirmed near the lower end of the gate insulating layer 11, although the cause is unknown. If impact ionization occurs near the lower end of the gate insulating layer 11, the gate insulating layer 11 may be destroyed, and the semiconductor region and the gate electrode 10 may become conductive. In order to reduce the possibility of the gate insulating layer 11 being destroyed and to improve the reliability of the semiconductor device 100, the width W1 is preferably 28 nm or more.

[0033] According to the simulation results of FIG. 7, the width W1 is preferably not less than 28 nm and not more than 206 nm.

[0034] Fig. 8 shows the experimental results showing the change in on-resistance Ron when the width W3 shown in Fig. 2 is changed. In the semiconductor device used in this experiment, the distance D shown in Fig. 2 is designed to be 295 nm. The width W1 of the contact portion 22a is designed to be 64 nm. The width W4 is designed to be 20 nm.

[0035] From the experimental results shown in FIG. 8, when the width W3 is less than 73 nm, the on-resistance Ron increases significantly. This is because when the width W3 is narrow, n + The contact area between the source region 3 and the source electrode 22 is reduced, and n + This is because the electrical resistance between the source region 3 and the source electrode 22 increases. There is no particular limit to the upper limit of the width W3. As long as the width W3 is 87 nm or more, the width W3 may be set appropriately depending on the width W1 of the contact portion 22a, the distance D, the pitch P, and the like. For example, the width W3 is preferably 87 nm or more and 200 nm or less. More preferably, the width W3 is 87 nm or more and 150 nm or less.

[0036] Furthermore, for the bottom of the contact portion 22a, the distance D1 in the Z direction from the first junction J1 to the bottom surface LS is preferably 100 nm or more and 400 nm or less. The distance D2 in the Z direction from the first junction J1 to the second junction J2 is preferably 200 nm or more and 500 nm or less. The distance D3 in the Z direction from the second junction J2 to the bottom surface LS is preferably 100 nm or more and 400 nm or less.

[0037] Advantages of the embodiment will be described. In the semiconductor device 100, the distance D shown in FIG. 2 is preferably short. The shorter the distance D, the higher the channel density and the lower the on-resistance of the semiconductor device 100. On the other hand, if the distance D is too short, the threshold voltage of the gate electrode 10 increases. Also, the p-type impurity concentration in the region where the channel is formed increases. There is a possibility that the effect of increasing the on-resistance due to the increase in the p-type impurity concentration in the channel region exceeds the effect of reducing the on-resistance due to the increase in the channel density. As a result, the on-resistance of the semiconductor device 100 may increase.

[0038] As a result of verification by the present inventors, it was found that the pitch P is preferably 450 nm or more and 650 nm or less, as shown in Figures 4 to 6. In the simulation shown in Figures 4 to 6, the width W of the gate electrode 10 shown in Figure 2 is set to 160 nm. The thickness of the gate insulating layer 11 is set to 20 nm. In this case, the distance D is preferably 250 nm or more and 450 nm or less.

[0039] The width W of the gate electrode 10 is preferably set within a range of 160 nm to 240 nm. The gate electrode 10 is formed by filling an opening formed in a semiconductor layer with a conductive material, as described later. If the width W is less than 160 nm, it becomes difficult to fill the conductive material uniformly, and voids may occur in the gate electrode 10. As a result, the formation of a channel in the p-type base region 2 becomes unstable, and the on-resistance may increase. On the other hand, if the width W exceeds 240 nm, the increase in the on-resistance due to the decrease in channel density becomes significant. When the pitch P is 450 nm to 650 nm, the thickness of the gate insulating layer 11 is 20 nm, and the width W is 240 nm, the distance D is preferably 150 nm to 450 nm. That is, when the width W is set within a range of 160 nm to 240 nm, the distance D is preferably 150 nm to 450 nm. By setting the distance D within this range, the on-resistance of the semiconductor device 100 can be reduced while suppressing an increase in the threshold voltage of the gate electrode 10.

[0040] When the distance D is short, ie, 150 nm or more and 450 nm or less, the source electrode 22 preferably includes a contact portion 22a. By providing the contact portion 22a, the contact area between the p-type base region 2 and the source electrode 22 and the n + The contact area between the p-type source region 3 and the source electrode 22 can be increased. Increasing the contact area between the p-type base region 2 and the source electrode 22 promotes the discharge of holes from the p-type base region 2 to the source electrode 22. For example, when an avalanche breakdown occurs in the semiconductor device 100, the rise in potential of the p-type base region 2 can be suppressed. As a result, the semiconductor device 100 can be prevented from operating as a bipolar transistor. In other words, latch-up of the semiconductor device 100 can be suppressed, and the avalanche resistance of the semiconductor device 100 can be improved. In addition, + By increasing the contact area between the source region 3 and the source electrode 22, + The electrical resistance between the source region 3 and the source electrode 22 is reduced, and the on-resistance of the semiconductor device 100 can be reduced.

[0041] When the contact portion 22a is provided, the width W1 of the contact portion 22a also affects the characteristics of the semiconductor device 100. In particular, when the distance D is short, such as 150 nm to 450 nm, the characteristics of the semiconductor device 100 can vary significantly depending on the width W1. Specifically, as shown in FIG. 7, when the width W1 is expanded to 230 nm or more, the on-resistance Ron increases by 10% or more compared to when the width W1 is 100 nm or less. Furthermore, when the width W1 is 28 nm or less, impact ionization occurs frequently near the gate insulating layer 11, and the reliability of the semiconductor device 100 decreases. Therefore, the width W1 is preferably 28 nm or more and 206 nm or less.

[0042] In addition, the n-type insulating layer 11 is located between the gate insulating layer 11 and the contact portion 22a. + As described above, the wider the width W3 of the source region 3, the smaller the n +This increases the contact area between the source region 3 and the source electrode 22. On the other hand, as the width W3 increases, the width W1 of the contact portion 22a decreases, which may decrease the reliability of the semiconductor device 100. In this regard, according to the experimental results shown in FIG. 8, the width W3 shown in FIG. 2 is preferably 87 nm or more. By setting the width W3 to 87 nm or more, it is possible to reduce the on-resistance of the semiconductor device 100 while suppressing a decrease in the reliability of the semiconductor device 100.

[0043] In particular, in the semiconductor device 100 illustrated in FIGS. + The upper surface US of the source region 3 includes a first region US1 and a second region US2. The second region US2 is generated when the contact portion 22a is formed by a manufacturing method described later. When the second region US2 exists, the width W3 of the first region US1 becomes narrow. Therefore, more precise control of the width W3 is required.

[0044] Furthermore, as a result of the inventors' verification, n + It was found that the electrical resistivity of the second portion 3b is considered to be higher than that of the first portion 3a in the n-type source region 3. This is considered to be because the width W4 of the second portion 3b is shorter than the width W3 of the first portion 3a, and therefore the n-type impurity in the second portion 3b diffuses to the surroundings. Therefore, when the second portion 3b exists and the width of the first portion 3a becomes narrow, the n + The contact resistance between the source region 3 and the source electrode 22 is likely to increase. However, even when the second portion 3b is present, by setting the width W3 to 87 nm or more as described above, it is possible to reduce the on-resistance of the semiconductor device 100 while suppressing a decrease in the reliability of the semiconductor device 100.

[0045] In addition, by providing the second portion 3b, it is possible to adjust the current density of the semiconductor device 100. That is, from the viewpoint of reducing the on-resistance, the second portion 3b is not preferable. On the other hand, the electrical resistivity of the second portion 3b is higher than that of the first portion 3a. Therefore, the voltage drop when a current flows through the second portion 3b is larger than the voltage drop when a current flows through the first portion 3a. For example, when the semiconductor device 100 is short-circuited, a large current flows through the semiconductor device 100. At this time, the voltage drop is increased by the second portion 3b, so that the current flowing through the semiconductor device 100 can be suppressed. By providing the second portion 3b and setting the width W3 to 87 nm or more, it is possible to reduce the on-resistance of the semiconductor device 100 while reducing the current density during a short circuit.

[0046] 9(a), 9(b), 10(a), 10(b), 11(a), 11(b), 12(a), 12(b), and 13 are cross-sectional views showing a manufacturing method of a semiconductor device according to an embodiment. First, n + Semiconductor layers 5x and n - A semiconductor substrate including a semiconductor layer 1x is prepared. - The semiconductor layer 1x is + The n-type semiconductor layer 5x is formed by photolithography and reactive ion etching (RIE). - An opening OP1 is formed in the upper surface of the shaped semiconductor layer 1x. As shown in Fig. 9(a), a plurality of openings OP1 are formed in the X direction, and each opening OP1 extends in the Y direction.

[0047] Thermal oxidation causes n - An insulating layer 11x is formed along the surface of the semiconductor layer 1x. A conductive layer is formed on the insulating layer 11x by chemical vapor deposition (CVD). The conductive layer includes, for example, polysilicon. The opening OP1 is filled with the conductive layer. The upper surface of the conductive layer is recessed by wet etching. As a result, as shown in FIG. 9(b), the conductive layer is divided into multiple pieces, and a gate electrode 10 is formed inside each opening OP1.

[0048] An insulating layer 12x is formed on the gate electrode 10. The opening OP1 is filled with the insulating layer 12x. - Chemical dry etching (CDE) is performed until the top surface of the crystalline semiconductor layer 1x is exposed. As a result, as shown in FIG. 10(a), a part of the insulating layer 11x and a part of the insulating layer 12x are removed, and n - The top surface of the semiconductor layer 1x is exposed.

[0049] CDE provides the n - A part of the semiconductor layer 12x is removed. In CDE, a gas is selected that has a higher etching rate for the semiconductor than for the insulating layer. For example, HBr (hydrogen bromide) is used as the gas. When CDE is performed, a difference in etching rate occurs between a portion near the insulating layer 12x and a portion away from the insulating layer 12x. In the vicinity of the insulating layer 12x, n - 10(b), the upper surface of the portion near the insulating layer 12x is inclined and the position of the upper surface becomes higher than the position of the upper surface of the portion away from the insulating layer 12x.

[0050] n - The upper surface of the p-type semiconductor layer 1x is ion-implanted with p-type impurities and n-type impurities to form p-type semiconductor regions 2x and n-type semiconductor regions 2x. + The n-type semiconductor region 3x is formed by CVD as shown in FIG. + An insulating layer 13x is formed to cover the semiconductor region 3x and the insulating layer 12x. For example, the insulating layer 13x includes an insulating material such as silicon oxide or silicon nitride. As described later, the material of the insulating layer 13x can be changed as appropriate as long as it can be used as a mask when etching the semiconductor layer.

[0051] A part of the insulating layer 13x is n + The insulating layer 13x is located above both ends of the n-type semiconductor region 3x in the X direction. + The n-type semiconductor region 3x is located above the center in the X direction. +A part of the insulating layer 13x is removed until a part of the top surface of the shaped semiconductor region 3x is exposed. The thickness (dimension in the Z direction) of the part of the insulating layer 13x is greater than the thickness of the other part of the insulating layer 13x. Therefore, as shown in FIG. 11(b), the part of the insulating layer 13x with a smaller thickness is removed, and the part with a larger thickness remains. Specifically, the side (n) of the insulating layer 12x is removed. + The insulating layer 13x remains on both ends of the semiconductor region 3x, and the other parts of the insulating layer 13x are removed. + The central portion of the semiconductor region 3x in the X direction is exposed. + A mask 13y is formed to cover only the vicinity of the insulating layer 12x of the semiconductor region 3x.

[0052] Using the mask 13y, + A part of the p-type semiconductor region 3x and a part of the p-type semiconductor region 2x are removed. This forms an opening OP2. As shown in FIG. 12(a), p-type impurities are ion-implanted into the bottom surface of the opening OP2 through the opening OP2 to form a p + A contact region 4 is formed.

[0053] The mask 13y is removed. The surface of the p-type semiconductor region 2x and the n + A metal layer 22x and a metal layer 22y are formed along the surface of the semiconductor region 3x. The metal layer 22x includes titanium nitride. The metal layer 22y includes titanium. A metal layer 22z filling the opening OP2 is formed on the metal layer 22y by sputtering, as shown in FIG. 12(b). The metal layer 22z includes aluminum.

[0054] n + The semiconductor layer 5x is then heated to a predetermined thickness. + The bottom surface of the n-type semiconductor layer 5x is ground. As shown in FIG. + Metal layers 21x and 21y are formed on the lower surface of the shaped semiconductor layer 5x by sputtering. The metal layer 21x contains titanium. The metal layer 21y contains aluminum. Through the above steps, the semiconductor device 100 according to the embodiment is manufactured.

[0055] The n shown in Figure 13 - The semiconductor layer 1x is a n-type semiconductor layer shown in FIG. - The p-type drift region 1 corresponds to the p-type semiconductor region 2x. + The semiconductor region 3x is n + It corresponds to the source region 3. + The portion of the semiconductor region 3x adjacent to the insulating layer 12x corresponds to the first portion 3a. + The portion of the semiconductor region 3x that is away from the insulating layer 12x corresponds to the second portion 3b. + The semiconductor layer 5x is n + OP2. The opening OP2 is formed on the opening OP3 and corresponds to the drain region 5. The insulating layer 11x corresponds to the gate insulating layer 11. The insulating layer 12x corresponds to the insulating layer 12. The metal layer 21x corresponds to the drain electrode 21. The metal layers 22x to 22z correspond to the source electrode 22. A part of the metal layer 22x, a part of the metal layer 22y, and a part of the metal layer 22z are located in the opening OP2. The part of the metal layer 22x, the part of the metal layer 22y, and the part of the metal layer 22z correspond to the contact portion 22a.

[0056] When the semiconductor device 100 is manufactured, it is preferable that the positional deviation of the contact portion 22a in the X direction is small. For example, if the position of the contact portion 22a is deviated, the distance between one of the insulating layers 11x and the contact portion 22a becomes short. + When the p-type contact region 4 is formed, the p-type impurity is likely to diffuse near the insulating layer 11x. As a result, the threshold voltage of the gate electrode 10 increases. Furthermore, if the position of the contact portion 22a is shifted, the distance between the other insulating layer 11x and the contact portion 22a increases. The position where impact ionization occurs changes, and the reliability of the semiconductor device 100 may decrease.

[0057] In the manufacturing method according to the embodiment, when the opening OP2 is formed, as shown in FIG. 12(a), a mask 13y is used. The position of the mask 13y is determined based on the difference in thickness of each portion of the insulating layer 13x. Specifically, the mask 13y is formed only on the side of the insulating layer 12x, and is not formed at a position distant from the insulating layer 12x. That is, the position of the mask 13y is determined in an accident-matching manner based on the position of the insulating layer 12x. Therefore, even if the interval between the insulating layers 12x is narrow, the positional deviation of the mask 13y can be suppressed. As a result, the positional deviation of the opening OP2 formed using the mask 13y is also suppressed.

[0058] The embodiment of the present invention is suitable for a semiconductor device in which a conductor (a so-called field plate electrode) is not provided below the gate electrode 10. In general, a field plate electrode has a width of n - The field plate electrode is located between the drift region 1 and the gate electrode 10 and is electrically connected to the gate electrode 10 or the source electrode 22. When a field plate electrode is provided, - A thick insulating layer must be provided between the drift region 1 and the field plate electrode. This makes it difficult to set the pitch of the gate electrodes 10 to 450 nm to 650 nm. By applying the above configuration to a semiconductor device that does not have a field plate electrode, it is possible to effectively reduce the on-resistance of the semiconductor device 100 while suppressing an increase in the threshold voltage of the gate electrodes 10.

[0059] Embodiments of the invention include the following features. (Feature 1) A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a pair of gate electrodes provided on the first semiconductor region via a gate insulating layer, the pair of gate electrodes having a distance between the gate insulating layers in a second direction perpendicular to a first direction from the first electrodes toward the first semiconductor region of not less than 150 nm and not more than 450 nm; a second semiconductor region of a second conductivity type provided between the pair of gate electrodes; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on each of the pair of gate electrodes via an insulating layer, the second electrode including a contact portion in contact with a part of the second semiconductor region and the third semiconductor region in the second direction, the second electrode having a bottom portion of the contact portion having a length in the second direction that is longer than 28 nm and not longer than 206 nm; A semiconductor device comprising: (Feature 2) The top surface of the third semiconductor region is A first region having an inclination with respect to the second direction of 0 degrees or more and 15 degrees or less; a second region having an inclination of 30 degrees or more with respect to the second direction; Including, The semiconductor device of feature 1, wherein a position of the first region in the second direction is between a position of the second region in the second direction and a position of the contact portion in the second direction. (Feature 3) The length of the first region in the second direction is 87 nm or more, 3. The semiconductor device according to feature 2, wherein the length of the second region in the second direction is 5 nm or more and 20 nm or less. (Feature 4) The third semiconductor region is a first portion in contact with the contact portion and including the first region; a second portion having the second region and located between the second region and the insulating layer; Including, 4. The semiconductor device according to feature 2 or 3, wherein a concentration of an impurity of the first conductivity type in the second portion is lower than a concentration of an impurity of the first conductivity type in the first portion. (Feature 5) The semiconductor device according to any one of features 1 to 4, wherein a first distance from a first junction between the first semiconductor region and the second semiconductor region to a bottom surface of the contact portion is longer than 0.5 times a second distance from the first junction to a second junction between the second semiconductor region and the third semiconductor region. (Feature 6) a fourth semiconductor region of a second conductivity type provided between the second semiconductor region and the contact portion; 6. The semiconductor device according to any one of features 1 to 5, wherein a concentration of the second conductive type impurity in the fourth semiconductor region is higher than a concentration of the second conductive type impurity in the second semiconductor region. (Feature 7) The semiconductor device according to any one of features 1 to 6, wherein the sum of the distance between the gate insulating layers, the length of one of the pair of gate electrodes in the second direction, and twice the thickness of the gate insulating layer is 450 nm or more and 650 nm or less.

[0060] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed, for example, by using a scanning capacitance microscope (SCM). The carrier concentration in each semiconductor region can be considered to be equal to the concentration of the activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed by using the SCM. The impurity concentration in each semiconductor region can also be measured, for example, by secondary ion mass spectrometry (SIMS).

[0061] Although some embodiments of the present invention have been illustrated above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims. In addition, the above-mentioned embodiments can be implemented in combination with each other. [Explanation of symbols]

[0062] 1:n - Shape drift region, 1x:n - 2: p-type base region; 2x: p-type semiconductor region; 3: n +shape source area, 3a: first part, 3b: second part, 3x:n + Semiconductor area, 4:p + Shape contact area, 5:n + Shaped drain region, 5x:n + semiconductor layer, 10: gate electrode, 11: gate insulating layer, 11x: insulating layer, 12: insulating layer, 12x, 13x: insulating layer, 13y: mask, 21: drain electrode, 21x, 21y: metal layer, 22: source electrode, 22a, 22b: contact portion, 22x to 22z: metal layer, 100: semiconductor device, D, D1 to D3: distance, J1: first junction, J2: second junction, LS: bottom surface, OP1, OP2: opening, P: pitch, US: top surface, US1: first region, US2: second region, W, W1 to W4: width

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a pair of gate electrodes provided on the first semiconductor region via a gate insulating layer, the pair of gate electrodes having a distance between the gate insulating layers in a second direction perpendicular to a first direction from the first electrodes toward the first semiconductor region of not less than 150 nm and not more than 450 nm; a second semiconductor region of a second conductivity type provided between the pair of gate electrodes; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on each of the pair of gate electrodes via an insulating layer, the second electrode including a contact portion in contact with a part of the second semiconductor region and the third semiconductor region in the second direction, the second electrode having a bottom portion of the contact portion having a length in the second direction that is longer than 28 nm and not longer than 206 nm; A semiconductor device comprising:

2. The top surface of the third semiconductor region is A first region having an inclination with respect to the second direction of 0 degrees or more and 15 degrees or less; a second region having an inclination of 30 degrees or more with respect to the second direction; Including, 2 . The semiconductor device according to claim 1 , wherein a position of the first region in the second direction is between a position of the second region in the second direction and a position of the contact portion in the second direction.

3. The length of the first region in the second direction is 87 nm or more, The semiconductor device according to claim 2 , wherein the length of the second region in the second direction is not less than 5 nm and not more than 20 nm.

4. The third semiconductor region is a first portion in contact with the contact portion and including the first region; a second portion having the second region and located between the second region and the insulating layer; Including, 4. The semiconductor device according to claim 2, wherein a concentration of the impurity of the first conductivity type in said second portion is lower than a concentration of the impurity of the first conductivity type in said first portion.

5. The semiconductor device according to any one of claims 1 to 3, wherein a first distance from a first junction between the first semiconductor region and the second semiconductor region to a bottom surface of the contact portion is longer than 0.5 times a second distance from the first junction to a second junction between the second semiconductor region and the third semiconductor region.

6. a fourth semiconductor region of a second conductivity type provided between the second semiconductor region and the contact portion; 4. The semiconductor device according to claim 1, wherein a concentration of the second conductive type impurity in said fourth semiconductor region is higher than a concentration of the second conductive type impurity in said second semiconductor region.

7. The semiconductor device according to any one of claims 1 to 3, wherein the sum of the distance between the gate insulating layers, the length of one of the pair of gate electrodes in the second direction, and twice the thickness of the gate insulating layer is 450 nm or more and 650 nm or less.

Images