Semiconductor device

Abstract

To provide a semiconductor device with a built-in control circuit.SOLUTION: A main element includes a first electrode, a second electrode located away from the first electrode in a first direction along a first surface of a support, a first semiconductor layer provided between the first and second electrodes in the first direction and forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction in a second direction. A control element includes a third electrode, a fourth electrode located away from the third electrode in a fourth direction, a second semiconductor layer provided between the third and fourth electrodes in the fourth direction and forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction in a fifth direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] There is a demand for chips with built-in control circuits in power semiconductor devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-22074 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device incorporating a control circuit. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a support having a first surface, a main element provided on the support, and a control element provided on the support and controlling the main element, the main element having a first electrode, a second electrode positioned apart from the first electrode in a first direction along the first surface, a first semiconductor layer provided between the first electrode and the second electrode in the first direction and forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction in a second direction intersecting the first direction along the first surface, and the control element has a third electrode, a fourth electrode positioned apart from the third electrode in a fourth direction along the first surface, a second semiconductor layer provided between the third electrode and the fourth electrode in the fourth direction and forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction in a fifth direction intersecting the fourth direction along the first surface. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is a schematic perspective view of a main element of the semiconductor device according to the embodiment. [Diagram 3] FIG. 2 is a schematic perspective view of a main element of the semiconductor device according to the embodiment. [Figure 4] 2 is a schematic cross-sectional view of a main element of the semiconductor device according to the embodiment; [Diagram 5] 2A and 2B are schematic perspective views of a main element of a semiconductor device according to an embodiment. [Figure 6] FIG. 2 is a schematic perspective view of a control element of the semiconductor device according to the embodiment. [Figure 7] 2 is a schematic cross-sectional view of a control element of the semiconductor device according to the embodiment; [Figure 8] FIG. 2A is a circuit diagram of a control circuit of a semiconductor device according to an embodiment, and FIG. 2B is a schematic cross-sectional view of a control element that forms the control circuit. [Figure 9] FIG. 2A is a circuit diagram of a control circuit of a semiconductor device according to an embodiment, and FIG. 2B is a schematic cross-sectional view of a control element that forms the control circuit. [Figure 10] FIG. 2A is a circuit diagram of a control circuit of a semiconductor device according to an embodiment, and FIG. 2B is a schematic cross-sectional view of a control element that forms the control circuit. [Figure 11] FIG. 2A is a circuit diagram of a control circuit of a semiconductor device according to an embodiment, and FIG. 2B is a schematic cross-sectional view of a control element that forms the control circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Furthermore, the same reference numbers are used to refer to the same or similar elements.

[0008] 1, a semiconductor device 1 according to an embodiment includes a main element 110 and a control element 120. The main element 110 is a power semiconductor element that controls or converts power. The control element 120 controls the main element 110. For example, a control circuit that controls the main element 110 is formed by a plurality of control elements 120.

[0009] The semiconductor device 1 further includes a support 100. As shown in Fig. 2, the main element 110 is provided on the support 100. As shown in Fig. 6, the control element 120 is provided on the support 100.

[0010] As shown in FIG. 2, the support 100 has a first surface 100A. One direction parallel to the first surface 100A is the X-axis direction. A direction parallel to the first surface 100A and perpendicular to the X-axis direction is the Y-axis direction. A direction perpendicular to the X-axis direction and the Y-axis direction is the Z-axis direction. The first surface 100A is perpendicular to the Z-axis direction. For example, in this specification, the direction along the Y-axis is the first direction Y, the direction along the X-axis is the second direction X, and the direction along the Z-axis is the third direction Z.

[0011] 2 to 5(b), the main element 110 will be described. In Fig. 3, the main element 110 is illustrated in a state in which the second conductive portion 22b and the second insulating member 42 have been removed.

[0012] The support 100 has a substrate 101. For example, a silicon substrate can be used as the substrate 101. The main element 110 has a first semiconductor layer 11 provided on the substrate 101 in the third direction Z. The support 100 may further have an insulating layer 102 provided between the substrate 101 and the first semiconductor layer 11 in the third direction Z. In this example, the upper surface of the insulating layer 102 becomes the first surface 100A of the support 100. For example, a silicon oxide layer can be used as the insulating layer 102.

[0013] The conductivity type of the first semiconductor layer 11 is a first conductivity type. The first conductivity type is one of n-type and p-type. Hereinafter, the first conductivity type is defined as n-type. The first semiconductor layer 11 is, for example, a silicon layer. The first semiconductor layer 11 may be a silicon carbide layer or a gallium nitride layer.

[0014] The main element 110 further includes a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are located apart from each other in the first direction Y. The first semiconductor layer 11 is provided between the first electrode 21 and the second electrode 22 in the first direction Y, and is electrically connected to the first electrode 21 and the second electrode 22. The first electrode 21, the second electrode 22, and the first semiconductor layer 11 extend in the third direction Z above the first surface 100A. The upward direction is the direction from the substrate 101 toward the first semiconductor layer 11. The upward direction is the direction from the second surface 101B toward the first surface 100A. The downward direction is the opposite direction to the upward direction. The upward and downward directions are independent of the direction of gravity. With this configuration, the density of the main elements 110 on the first surface 100A of the support 100 can be increased, and for example, the on-resistance per unit area can be reduced.

[0015] The first electrode 21 may include, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0016] The second electrode 22 has a first conductive portion 22a and a second conductive portion 22b. The first conductive portion 22a is in contact with the first semiconductor layer 11. The first semiconductor layer 11 and the first conductive portion 22a form a first Schottky junction S1. The first conductive portion 22a is located between the first semiconductor layer 11 and the second conductive portion 22b in the first direction Y. The second conductive portion 22b is electrically connected to the first conductive portion 22a.

[0017] The first conductive portion 22a may include at least one selected from the group consisting of, for example, Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf. The second conductive portion 22b may include at least one selected from the group consisting of, for example, Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0018] The main element 110 further includes a first gate electrode 31. A plurality of first gate electrodes 31 are arranged in the second direction X. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X. For example, polycrystalline silicon can be used as the material of the first gate electrode 31. As shown in FIG. 3, the first gate electrode 31 extends in the third direction Z. With this configuration, transistors can be provided at high density on the first surface 100A of the support 100, and the channel area per unit area can be increased. This can reduce, for example, the on-resistance. In the main element 110, since no current flows through the support 100, the on-resistance does not increase even if the thickness of the support 100 in the third direction Z is increased to increase the mechanical strength.

[0019] A potential higher than the potential of the second electrode 22 is applied to the first electrode 21, and a potential lower than the potential of the first electrode 21 (for example, ground potential) is applied to the second electrode 22. The first electrode 21 functions as a drain electrode, and the second electrode 22 functions as a source electrode. Note that the n-type impurity concentration of the region in contact with the first electrode 21 in the first semiconductor layer 11 may be made higher than the n-type impurity concentration of the other regions. This can reduce the contact resistance between the first electrode 21 and the first semiconductor layer 11.

[0020] The thickness (distance in the first direction Y) of the Schottky barrier at the first Schottky junction S1 can be controlled by the potential of the first gate electrode 31. When the Schottky barrier is thick, substantially no current flows between the second electrode 22 and the first semiconductor layer 11. This provides an off state. In the off state, a depletion layer spreads from the first Schottky junction S1 into the first semiconductor layer 11, making it possible to maintain a breakdown voltage.

[0021] By controlling the potential of the first gate electrode 31, the Schottky barrier becomes thinner, and for example, a tunnel current flows between the second electrode 22 and the first semiconductor layer 11. The flow of the tunnel current provides an on state.

[0022] The main element 110 may further include a field plate electrode 51, a first insulating member 41, and a second insulating member .

[0023] The field plate electrode 51 is provided in a trench formed in the first semiconductor layer 11, and extends in the first direction Y and the third direction Z. The field plate electrode 51 is electrically connected to, for example, the second electrode 22. The field plate electrode 51 can reduce the electric field applied to the first semiconductor layer 11 in the first direction Y, and can increase the withstand voltage. The field plate electrode 51 can be made of, for example, polycrystalline silicon.

[0024] The first insulating member 41 is provided between the first gate electrode 31 and the first semiconductor layer 11, between the field plate electrode 51 and the first semiconductor layer 11, between the first gate electrode 31 and the field plate electrode 51, and between the first gate electrodes 31 adjacent to each other in the second direction X, and extends in the third direction Z. The first insulating member 41 has a first gate insulating portion 41a. The first gate insulating portion 41a is provided between the first gate electrode 31 and the first semiconductor layer 11, between the first gate electrode 31 and the first Schottky junction S1, and between the first gate electrode 31 and the first conductive portion 22a. The first gate electrode 31 faces the first Schottky junction S1 in the second direction X via the first gate insulating portion 41a. For example, silicon oxide can be used as the material of the first insulating member 41.

[0025] The second insulating member 42 is provided between the first gate electrode 31 and the second conductive portion 22b and between the first insulating member 41 and the second conductive portion 22b, and extends in the third direction Z. The second insulating member 42 may be made of, for example, silicon oxide.

[0026] As shown in FIG. 5(a), the substrate 101 has a second surface 101B located on the opposite side of the first surface 100A in the third direction Z. An interlayer insulating layer (indicated by a two-dot chain line) 300 is provided so as to be in contact with the upper side of the first semiconductor layer 11. A first wiring portion D electrically connected to the first electrode 21 is provided on the second surface 101B of the substrate 101. The first electrode 21 can be electrically connected to an external circuit via the first wiring portion D. A part of the first wiring portion D is located below the semiconductor device 1 and exposed. A part of the first wiring portion D extends parallel to the first direction Y and the second direction X. The substrate 101 is located between the first wiring portion D and the first semiconductor layer 11. In the third direction Z, a second wiring portion S can be provided above the first semiconductor layer 11, above the first gate electrode 31, and above the field plate electrode 51 via an interlayer insulating layer. The second wiring portion S is electrically connected to the second conductive portion 22b of the second electrode 22. The second electrode 22 can be electrically connected to an external circuit via the second wiring portion S. A part of the second wiring portion S is located above the semiconductor device 1 and is exposed. A part of the second wiring portion S extends parallel to the first direction Y and the second direction X. An interlayer insulating layer 300 is located between a part of the second wiring portion S and the first semiconductor layer 11. "Exposed" refers to being present on the surface of the semiconductor element, and is not necessarily present on the surface of a package material such as resin or ceramic. A first gate wiring G1 extending in the second direction X is provided on a plurality of first gate electrodes 31 arranged in the second direction X, and the plurality of first gate electrodes 31 can be electrically connected to the first gate wiring G1. The first gate wiring G1 is located in the interlayer insulating layer 300. The first gate wiring G1 may be located above the semiconductor device 1 and exposed. The semiconductor device 1 can be placed, for example, with the second wiring portion S in contact with an electrode of an external circuit. The wiring portions of the semiconductor device 1 other than the second wiring portion S are exposed from above the semiconductor device 1 and are connected to an external circuit by means of wire bonding or the like. In the semiconductor device 1, the exposed area of ​​the first wiring portion D and the second wiring portion S, which are the main current paths, i.e., the contact area with the external circuit, can be increased.

[0027] Alternatively, as shown in FIG. 5(b), a second wiring portion S electrically connected to the second conductive portion 22b of the second electrode 22 may be provided on the second surface 101B of the substrate 101. In the third direction Z, a first wiring portion D electrically connected to the first electrode 21 via an interlayer insulating layer may be provided above the first semiconductor layer 11, above the first gate electrode 31, and above the field plate electrode 51. A part of the first wiring portion D is located above the semiconductor device 1 and exposed. A part of the first wiring portion D extends parallel to the first direction Y and the second direction X. A part of the second wiring portion D is located below the semiconductor device 1 and exposed. A part of the second wiring portion S extends parallel to the first direction Y and the second direction X.

[0028] As shown in FIG. 1, the area of ​​the region where the main element 110 is provided is larger than the area of ​​the region where the control element 120 is provided. In the region of the semiconductor device 1 where the main element 110 is provided, a plurality of cell groups (first to fourth cell groups 71 to 74) are provided. The cell group refers to a group of cells of the main element 110 that share the first semiconductor layer 11. In the first direction Y, the second cell group 72 is located between the first cell group 71 and the fourth cell group 74, and the third cell group 73 is located between the second cell group 72 and the fourth cell group 74. In each cell group, the structures shown in FIGS. 2 to 4 described above are repeatedly arranged in the second direction X.

[0029] The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is opposite to the direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72. The direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73 is opposite to the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74. The direction from the first electrode 21 of the first cell group 71 to the second electrode 22 of the first cell group 71 is the same as the direction from the first electrode 21 of the third cell group 73 to the second electrode 22 of the third cell group 73. The direction from the first electrode 21 of the second cell group 72 to the second electrode 22 of the second cell group 72 is the same as the direction from the first electrode 21 of the fourth cell group 74 to the second electrode 22 of the fourth cell group 74.

[0030] The first electrode 21 is shared between the second cell group 72 and the third cell group 73. The second electrode 22 is shared between the first cell group 71 and the second cell group 72. The second electrode 22 is shared between the third cell group 73 and the fourth cell group 74.

[0031] The main element 110 may, for example, constitute a high-side switching element and a low-side switching element in a voltage converter.

[0032] Next, the control element 120 will be described with reference to FIGS.

[0033] For example, the control element 120 is provided on the same substrate 101 as the primary element 110, and the fourth direction in the control element 120 coincides with the first direction Y in the primary element 110, the fifth direction in the control element 120 coincides with the second direction X in the primary element 110, and the sixth direction in the control element 120 coincides with the third direction Z in the primary element 110. The control element 120 is located away from the primary element 110 in the XY plane. The control element 120 has a second semiconductor layer 12 provided on the substrate 101 in the third direction (sixth direction) Z. The conductivity type of the second semiconductor layer 12 is the first conductivity type. The material of the second semiconductor layer 12 can be the same as the material of the first semiconductor layer 11 of the primary element 110.

[0034] The control element 120 further has a third electrode 23 and a fourth electrode 24. The third electrode 23 and the fourth electrode 24 are located apart from each other in one direction on the XY plane, for example, in the first direction (fourth direction) Y. The second semiconductor layer 12 is provided between the third electrode 23 and the fourth electrode 24 in the first direction (fourth direction) Y, and is electrically connected to the third electrode 23 and the fourth electrode 24. The third electrode 23, the fourth electrode 24, and the second semiconductor layer 12 extend in the third direction (sixth direction) Z above the first surface 100A of the support 100.

[0035] The fourth electrode 24 has a third conductive portion 24a and a fourth conductive portion 24b. The third conductive portion 24a is in contact with the second semiconductor layer 12. The second semiconductor layer 12 and the third conductive portion 24a form a second Schottky junction S2. The third conductive portion 24a is located between the second semiconductor layer 12 and the fourth conductive portion 24b in the first direction (fourth direction) Y. The fourth conductive portion 24b is electrically connected to the third conductive portion 24a.

[0036] The material of the third electrode 23 may be the same as the material of the first electrode 21 of the main element 110. The material of the third conductive portion 24a may be the same as the material of the first conductive portion 22a of the main element 110. The material of the fourth conductive portion 24b may be the same as the material of the second conductive portion 22b of the main element 110.

[0037] The control element 120 further includes a second gate electrode 32. The multiple second gate electrodes 32 are arranged in one direction on the XY plane, for example, in the second direction (fifth direction) X. The second gate electrode 32 faces the second Schottky junction S2 in the second direction (fifth direction) X. The second gate electrode 32 extends in the third direction (sixth direction) Z. The material of the second gate electrode 32 can be the same as that of the first gate electrode 31 of the main element 110.

[0038] The thickness (distance in the first direction (fourth direction) Y) of the Schottky barrier in the second Schottky junction S2 can be controlled by the potential of the second gate electrode 32. When the Schottky barrier is thick, substantially no current flows between the fourth electrode 24 and the second semiconductor layer 12, thereby obtaining an off state. By controlling the potential of the second gate electrode 32, the Schottky barrier becomes thin, and for example, a tunnel current flows between the fourth electrode 24 and the second semiconductor layer 12. The flow of the tunnel current obtains an on state.

[0039] The control element 120 may further include a third insulating member 43 and a fourth insulating member 44.

[0040] The third insulating member 43 is provided between the second gate electrode 32 and the second semiconductor layer 12, and extends in the third direction (sixth direction) Z. As shown in FIG. 7, the third insulating member 43 has a second gate insulating portion 43a. The second gate insulating portion 43a is provided between the second gate electrode 32 and the second semiconductor layer 12, between the second gate electrode 32 and the second Schottky junction S2, and between the second gate electrode 32 and the third conductive portion 24a. The second gate electrode 32 faces the second Schottky junction S2 in the second direction (fifth direction) X via the second gate insulating portion 43a. The material of the third insulating member 43 can be the same as that of the first insulating member 41 of the main element 110.

[0041] The fourth insulating member 44 is provided between the second gate electrode 32 and the fourth conductive portion 24b and between the third insulating member 43 and the fourth conductive portion 24b, and extends in the third direction (sixth direction) Z. The material of the fourth insulating member 44 can be the same as that of the second insulating member 42 of the main element 110.

[0042] According to this embodiment, the main element 110 and the control element 120 can be formed in the same process simply by changing the mask patterns for film formation and etching for forming each component of the main element 110 and the control element 120 between the main element 110 and the control element 120. For example, the first semiconductor layer 11 and the second semiconductor layer 12 can be formed on the same substrate 101, and the main element 110 and the control element 120 can be configured as a single chip. This allows a power semiconductor device with the built-in control element 120 to be integrated into a single chip at low cost. When the main element 110 and the control element 120 are integrated into a single chip, it is possible to reduce the parasitic inductance of the wiring electrically connecting the main element 110 and the control element 120.

[0043] 1, a fifth insulating member 60 can be provided between the main element 110 and the control element 120 on the substrate 101. The fifth insulating member 60 can also be provided between a plurality of control elements 120. The fifth insulating member 60 can be made of, for example, silicon oxide.

[0044] Alternatively, the first semiconductor layer 11 and the second semiconductor layer 12 may be formed on the same substrate 101, and then the chip of the main element 110 and the chip of the control element 120 may be separated. In this case, the chip of the main element 110 and the chip of the control element 120 may be mounted on the same wiring substrate and packaged. In this case, the wiring substrate may be included as a support for supporting the main element 110 and the control element 120.

[0045] The third electrode 23 of the control element 120 can be electrically connected to an external circuit via a third wiring portion provided above the second semiconductor layer 12 in the third direction (sixth direction) Z. The fourth electrode 24 can be electrically connected to an external circuit via a fourth wiring portion provided above the second semiconductor layer 12 in the third direction (sixth direction) Z. The second gate electrode 32 can be electrically connected to a second gate wiring G2 provided on the second gate electrode 32 and extending in the second direction (fifth direction) X. The third wiring portion, the fourth wiring portion, and the second gate wiring G2 can be connected to an external circuit by being exposed to the outside of the semiconductor device 1 at the upper part. An interlayer insulating layer is provided on the second semiconductor layer 12. The third wiring portion, the fourth wiring portion, and the second gate wiring G2 are provided in the interlayer insulating layer. The third wiring portion, the fourth wiring portion, and the second gate wiring G2 can be connected to each wiring of the main element 110 and each wiring of the other control elements 120 in the interlayer insulating layer. Compared to the case of connection by wire bonding, for example, parasitic inductance can be reduced, and the area of ​​the electrode pads of the main element 110, that is, the area of ​​each wiring portion, can be increased.

[0046] This makes it possible to suppress leakage current between the above-mentioned first wiring portion D or second wiring portion S of the main element 110 and the main electrodes (third electrode 23 and fourth electrode 24) of the control element 120.

[0047] The voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is higher than the voltage applied between the third electrode 23 and the fourth electrode 24 of the control element 120. For example, the voltage applied between the first electrode 21 and the second electrode 22 of the main element 110 is 100 V or more, and the voltage applied between the third electrode 23 and the fourth electrode 24 of the control element 120 is about several volts. Therefore, in order to increase the withstand voltage of the main element 110, it is preferable that the thickness of the first semiconductor layer 11 of the main element 110 in the first direction Y is thicker than the thickness of the second semiconductor layer 12 of the control element 120 in the first direction Y.

[0048] At least one of the third electrode 23 and the fourth electrode 24 of the control element 120 is electrically connected to the first gate electrode 31 of the main element 110. The control element 120 forms a control circuit that controls the potential of the first gate electrode 31 of the main element 110.

[0049] An example of a control circuit formed by a plurality of control elements 120 will be described with reference to FIGS. 8(a) to 11(b).

[0050] 8(a) and 8(b) show an example in which a plurality of control elements 120 form a NOT circuit 201. As an example, a case will be described in which the plurality of control elements 120 are MOSFETs in which an N-type semiconductor layer and an electrode form a Schottky junction. The plurality of control elements 120 may be MOSFETs having a MOS-type gate electrode in a semiconductor structure of an NPN junction or a PNP junction. In addition, as an example, a configuration of a logic circuit using only MOSFETs of one polarity, for example, an N-type MOSFET, will be described. The logic circuit can be replaced with a circuit including a CMOS having both an N-type MOSFET and a P-type MOSFET. The NOT circuit 201 has a first control element Q1 (120) and a second control element Q2 (120). The second electrode of the first control element Q1 and the first electrode of the second control element Q2 form a common electrode 25 shared by the first control element Q1 and the second control element Q2. The second gate wiring G2 electrically connected to the second gate electrode 32 of the first control element Q1 is electrically connected to the first electrode 21 of the first control element Q1. A power supply voltage is applied to the first electrode 21 of the first control element Q1, and the second electrode 22 of the second control element Q2 is grounded. A signal "A" is input to the second gate wiring G2 electrically connected to the second gate electrode 32 of the second control element Q2, and a signal "Y" obtained by inverting the signal "A" is output to the common electrode 25 (output terminal).

[0051] When configuring a circuit in which the third electrode 23 or the fourth electrode 24 of a certain control element Q1 (120) is connected to the third electrode 23 or the fourth electrode 24 of another control element Q2 (120), the third electrode 23 or the fourth electrode 24 to be connected is configured as an integral unit. In this case, the direction from the third electrode 23 to the fourth electrode 24 of one control element Q1 (120) is aligned with the direction from the third electrode 23 to the fourth electrode 24 of the other control element Q2 (120). The area of ​​each wiring that connects the control elements 120 to each other can be reduced. The mounting area of ​​the control element 120 itself can be reduced. The area occupied by the control element 120 on the first surface 100A of the support 100 is reduced, and the channel area of ​​the main element 110 per unit area can be increased.

[0052] 9(a) and 9(b) show an example in which a plurality of control elements 120 form a NOR circuit 202. The NOR circuit 202 has a first control element Q1 (120), a second control element Q2 (120), and a third control element Q3 (120). The second electrode of the third control element Q3 and the first electrode of the second control element Q2 form a first common electrode 26 shared by the third control element Q3 and the second control element Q2. The second electrode of the second control element Q2 and the first electrode of the first control element Q1 form a second common electrode 27 shared by the second control element Q2 and the first control element Q1. The second gate wiring G2 electrically connected to the second gate electrode 32 of the third control element Q3 is electrically connected to the first electrode 21 of the third control element Q3. A power supply voltage is applied to the first electrode 21 of the third control element Q3, and the second electrode 22 of the first control element Q1 is grounded. A signal "A" is input to the second gate wiring G2 electrically connected to the second gate electrode 32 of the second control element Q2, a signal "B" is input to the second gate wiring G2 electrically connected to the second gate electrode 32 of the first control element Q1, and a signal "Y" which is the inverse of the signal "A+B" is output to the first common electrode 26 (output terminal).

[0053] 10(a) and 10(b) show an example in which a plurality of control elements 120 form a NAND circuit 203. The NAND circuit 203 has a first control element Q1 (120), a second control element Q2 (120), and a third control element Q3 (120). The second electrode of the third control element Q3 and the first electrode of the second control element Q2 form a first common electrode 26 shared by the third control element Q3 and the second control element Q2. The second electrode of the second control element Q2 and the first electrode of the first control element Q1 form a second common electrode 27 shared by the second control element Q2 and the first control element Q1. The second gate wiring G2 electrically connected to the second gate electrode 32 of the third control element Q3 is electrically connected to the first electrode 21 of the third control element Q3. A power supply voltage is applied to the first electrode 21 of the third control element Q3, and the second electrode 22 of the first control element Q1 is grounded. A signal "A" is input to the second gate wiring G2 electrically connected to the second gate electrode 32 of the second control element Q2, a signal "B" is input to the second gate wiring G2 electrically connected to the second gate electrode 32 of the first control element Q1, and a signal "Y" which is the inverse of the signal "A·B" is output to the second common electrode 27 (output terminal).

[0054] A NOT circuit 201, a NOR circuit 202, and a NAND circuit 203 can be created separately simply by changing the mask pattern.

[0055] 11(a) and 11(b), a plurality of control elements 120 can form a delay circuit 204. The delay circuit 204 includes two NOT circuits 201 connected in series, and a capacitor C connected between the connection node of the two NOT circuits 201 and ground.

[0056] The capacitor C has a fifth electrode 121, a sixth electrode 151, a third semiconductor layer 111, and a sixth insulating member 141. The fifth electrode 121, the sixth electrode 151, the third semiconductor layer 111, and the sixth insulating member 141 extend in the third direction Z on the first surface 100A of the support 100. The fifth electrode 121 and the sixth electrode 151 are located apart in the first direction Y and the second direction X via the third semiconductor layer 111 and the sixth insulating member 141. For example, in the XY plane, the fifth electrode 121 continuously surrounds the third semiconductor layer 111, the third semiconductor layer 111 continuously surrounds the sixth insulating member 141, and the sixth insulating member 141 continuously surrounds the sixth electrode 151.

[0057] The fifth electrode 121, the sixth electrode 151, the third semiconductor layer 111, and the sixth insulating member 141 can be formed in the same process as the main element 110 and the control element 120 described above, simply by changing the mask pattern. For example, the fifth electrode 121 can be formed in the same process as any of the first to fourth electrodes 21 to 24. The sixth electrode 151 can be formed in the same process as the field plate electrode 51. The third semiconductor layer 111 can be formed in the same process as the first semiconductor layer 11 and the second semiconductor layer 12. The sixth insulating member 141 can be formed in the same process as the first insulating member 41 and the third insulating member 43.

[0058] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0059] 1...semiconductor device, 11...first semiconductor layer, 12...second semiconductor layer, 21...first electrode, 22...second electrode, 22a...first conductive portion, 22b...second conductive portion, 23...third electrode, 24...fourth electrode, 24a...third conductive portion, 24b...fourth conductive portion, 31...first gate electrode, 32...second gate electrode, 41...first insulating member, 42...second insulating member, 43...third insulating member, 44...fourth insulating member, 51...field plate electrode, 60...fifth insulating member, 100...support, 100A...first surface, 101...substrate, 101B...second surface, 110...main element, 120...control element, 201...NOT circuit, 202...NOR circuit, 203...NAND circuit, 204...delay circuit, 300...interlayer insulating layer, S1...first Schottky junction, S2...second Schottky junction, D...first wiring section, S...second wiring section, G1...first gate wiring, G2...second gate wiring

Claims

1. A support having a first surface; A main element provided on the support; A control element provided on the support and controlling the main element; Equipped with The main element is A first electrode; a second electrode positioned apart from the first electrode in a first direction along the first surface; a first semiconductor layer provided between the first electrode and the second electrode in the first direction and forming a first Schottky junction with the second electrode; a first gate electrode facing the first Schottky junction in a second direction intersecting the first direction along the first surface; having The control element is A third electrode; a fourth electrode positioned apart from the third electrode in a fourth direction along the first surface; a second semiconductor layer provided between the third electrode and the fourth electrode in the fourth direction and forming a second Schottky junction with the fourth electrode; a second gate electrode facing the second Schottky junction in a fifth direction intersecting the fourth direction along the first surface; A semiconductor device having the above structure.

2. The support has a substrate, The semiconductor device according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer are provided on the same substrate.

3. the substrate has a second surface located on an opposite side to the first surface in a third direction intersecting the first direction and the second direction; The semiconductor device according to claim 2 , wherein the third electrode and the fourth electrode of the control element are located on the first surface and not on the second surface.

4. 4. The semiconductor device according to claim 1, wherein a thickness of the first semiconductor portion in the first direction is greater than a thickness of the second semiconductor portion in the fourth direction.

5. 4. The semiconductor device according to claim 1, wherein a plurality of said control elements form a NOT circuit.

6. 4. The semiconductor device according to claim 1, wherein a plurality of said control elements form a NOR circuit.

7. 4. The semiconductor device according to claim 1, wherein a plurality of said control elements form a NAND circuit.

8. 4. The semiconductor device according to claim 1, wherein at least one of the third electrode and the fourth electrode of the control element is electrically connected to the first gate electrode of the main element.

9. The semiconductor device according to claim 3 , wherein the main element further includes an interlayer insulating layer in contact with an upper portion of the first semiconductor layer in the third direction.

10. 10. The semiconductor device according to claim 9, wherein the main element has a first gate wiring portion connected to the first gate electrode in the interlayer insulating layer.

11. A plurality of the control elements are provided, the plurality of control elements include at least a first control element and a second control element located in the fourth direction relative to the first control element, The semiconductor device according to claim 3 , wherein the fourth electrode of the first control element is integrally connected to the third electrode of the second control element.

12. The semiconductor device according to claim 11 , wherein a second gate electrode of the first control element is connected to a third electrode of the first control element.

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