Semiconductor storage device and heating method for semiconductor storage device

Abstract

To provide a semiconductor storage device and a heating method for the semiconductor storage device, in which the product life can be extended.SOLUTION: A semiconductor storage device according to an embodiment includes a substrate, a sealing member, a first memory chip, and a non-signal wire. The non-signal wires are provided at one or more places among a surface of the sealing member, inside of the sealing member, a first surface of the substrate, inside of the substrate, and a surface of the first memory chip, and overlap with the first memory chip when viewed from a first direction. The non-signal wire includes: a first end electrically connected to a power supply unit; a second end electrically connected to the ground; and a wire main body connecting the first end and the second end. The wiring main body includes: a first part extending in a second direction intersecting with the first direction; a second part folded back from an end of the first part; and a third part folded back from an end of the second part.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] 1. Field of the Invention The present invention relates to a semiconductor memory device and a heating method for a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known that has a substrate, a memory chip mounted on the substrate, and a sealing member that seals the memory chip. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2013-502647 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment provides a semiconductor memory device and a heating method for a semiconductor memory device that can extend the product life. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a sealing member, a first memory chip, and a non-signal wiring. The substrate has a first surface. The sealing member covers the first surface when viewed from a first direction, which is a thickness direction of the substrate. The first memory chip is disposed between the first surface and the sealing member in the first direction. The non-signal wiring is different from the signal wiring of the semiconductor memory device. The non-signal wiring is provided on one or more of a surface of the sealing member, an inside of the sealing member, the first surface of the substrate, an inside of the substrate, or a surface of the first memory chip, and overlaps with the first memory chip when viewed from the first direction. The non-signal wiring has a first end electrically connected to a power supply unit, a second end electrically connected to ground, and a wiring body connecting the first end and the second end. The wiring body includes a first portion extending in a second direction intersecting the first direction, a second portion folding back from an end of the first portion to a first side in the second direction and extending parallel to the first portion, and a third portion folding back from an end of the second portion to a second side in the second direction opposite the first side and extending parallel to the second portion. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a plan view showing the storage device of the first embodiment. [Diagram 2] FIG. 2 is a diagram showing a NAND package according to the first embodiment. [Diagram 3] 3A to 3C are diagrams showing a manufacturing method of the NAND package according to the first embodiment. [Figure 4] FIG. 2 is a perspective view for explaining a remanufacturing method of the NAND package according to the first embodiment. [Diagram 5] FIG. 13 is a diagram showing a NAND package according to a modified example of the first embodiment. [Figure 6] FIG. 13 is a diagram showing a NAND package according to a second embodiment. [Figure 7] FIG. 13 is a diagram showing a NAND package according to a first example of the second embodiment. [Figure 8] 10A to 10C are diagrams showing a manufacturing method of a NAND package according to a first example of the second embodiment. [Figure 9]FIG. 13 is a diagram showing a NAND package according to a second example of the second embodiment. [Figure 10] 10A to 10C are diagrams showing a method for manufacturing a NAND package according to a second example of the second embodiment. [Figure 11] FIG. 13 is a diagram showing a NAND package according to a third example of the second embodiment. [Figure 12] 10A to 10C are diagrams showing a manufacturing method of a NAND package according to a third example of the second embodiment. [Figure 13] FIG. 13 is a diagram showing a NAND package according to a third embodiment. [Figure 14] 10A to 10C are diagrams showing a manufacturing method of a NAND package according to a third embodiment. [Figure 15] FIG. 13 is a diagram showing a NAND package according to a fourth embodiment. [Figure 16] FIG. 13 is a diagram showing a NAND package according to a fifth embodiment. [Figure 17] 13A to 13C are diagrams showing a manufacturing method of a NAND package according to the fifth embodiment. [Figure 18] FIG. 13 is a diagram showing a NAND package according to a first modified example of the fifth embodiment. [Figure 19] FIG. 13 is a diagram showing a NAND package according to a second modified example of the fifth embodiment. [Figure 20] FIG. 23 is a diagram showing a NAND package according to a third modified example of the fifth embodiment. [Figure 21] FIG. 23 is a diagram showing a NAND package according to a fourth modified example of the fifth embodiment. [Figure 22] FIG. 13 is a diagram showing a NAND package according to a fifth modified example of the fifth embodiment. [Figure 23] FIG. 13 is a diagram showing a NAND package according to a sixth modified example of the fifth embodiment. [Figure 24] FIG. 23 is a diagram showing a NAND package according to a seventh modified example of the fifth embodiment. [Diagram 25] FIG. 13 is a diagram showing a NAND package according to an eighth modified example of the fifth embodiment. [Figure 26] FIG. 13 is a diagram showing a NAND package according to a sixth embodiment. [Figure 27] FIG. 13 is a perspective view for explaining a remanufacturing method of the NAND package according to the sixth embodiment. [Figure 28]FIG. 13 is a diagram showing a NAND package according to a modified example of the sixth embodiment. [Figure 29] FIG. 13 is a diagram showing a NAND package according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a semiconductor memory device and a heating method for a semiconductor memory device according to an embodiment will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Then, duplicated descriptions of those components may be omitted. Also, in some drawings, structures may be shown diagrammatically.

[0008] In this application, "parallel," "orthogonal," or "same" may include the cases of "approximately parallel," "approximately orthogonal," or "approximately the same," respectively. In this application, "overlap" means that virtual projection images of two objects overlap. In other words, "overlap" is not limited to the case where two objects are in contact, but may include the case where the two objects are not in contact (for example, when there is a space or another member between the two objects). In addition, in this application, "overlap" may include the case where parts of two objects overlap. In this application, "connection" is not limited to mechanical connection, but may include electrical connection. In other words, "connection" is not limited to the case where the object is directly connected, but may include the case where the object is connected via another member between them.

[0009] In the present application, the +X direction, the -X direction, the +Y direction, the -Y direction, the +Z direction, and the -Z direction are defined as follows. The +X direction, the -X direction, the +Y direction, and the -Y direction are parallel to the first surface 11a of the substrate 11 (see FIG. 1), which will be described later. The +X direction is a direction from the second end 11e2 to the first end 11e1 of the substrate 11 (see FIG. 1), which will be described later. The -X direction is a direction opposite to the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the "X direction". The +Y direction and the -Y direction are directions intersecting (for example, perpendicular to) the X direction. The +Y direction is a direction from the fourth end 11e4 to the third end 11e3 of the substrate 11 (see FIG. 1), which will be described later. The -Y direction is a direction opposite to the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the "Y direction". The +Z direction and the -Z direction are directions that intersect (e.g., are perpendicular to) the X direction and the Y direction, and are the thickness direction of the substrate 11. The +Z direction is the direction from the substrate 11 toward the NAND package 14 (see FIG. 2). The -Z direction is the opposite direction to the +Z direction. When there is no need to distinguish between the +Z direction and the -Z direction, they are simply referred to as the "Z direction."

[0010] The Z direction is an example of a "first direction." The X direction is an example of a "second direction." The -X direction is an example of a "first side." The +X direction is an example of a "second side." Below, the +Z direction may be referred to as "upper," and the -Z direction may be referred to as "lower." However, these expressions are used for convenience of explanation and do not define the weight direction.

[0011] (First embodiment) <1. Overall configuration of storage device> A storage device 1 according to a first embodiment will be described with reference to Fig. 1 to Fig. 4. The storage device 1 is a storage device such as an SSD (Solid State Drive). The storage device 1 is attached to a host device and used as a storage device for the host device. The host device may be, but is not limited to, a personal computer, a mobile device, a video recorder, or an in-vehicle device.

[0012] 1 is a plan view showing a storage device 1. The storage device 1 has, for example, a substrate 11, a controller 12, a dynamic random access memory (DRAM) 13, a plurality of NAND flash memories 14 (hereinafter referred to as "NAND packages 14" for convenience), and a plurality of capacitors 15. The storage device 1 may have a housing that houses the substrate 11, the controller 12, the DRAM 13, the plurality of NAND packages 14, and the plurality of capacitors 15.

[0013] The substrate 11 is a plate member extending along the X and Y directions. The substrate 11 is a printed circuit board, and includes an insulating base material and a wiring pattern provided on the insulating base material. The substrate 11 has a first surface 11a and a second surface 11b (see FIG. 2) located on the opposite side to the first surface 11a. The first surface 11a and the second surface 11b each extend in the X and Y directions.

[0014] The end of the substrate 11 in the +X direction has a connector 11c. The connector 11c is a connection part that can be connected to a connector of a host device. The connector 11c has a plurality of metal terminals that can be connected to the connector of the host device.

[0015] The controller 12 is a component that performs overall control of the entire storage device 1. The controller 12 is, for example, a semiconductor package including a SoC (System on a Chip) in which a host interface circuit for a host device, a control circuit for controlling the DRAM 13, and a control circuit for controlling a plurality of NAND packages 14 are integrated into one semiconductor chip. The controller 12 is provided on, for example, the first surface 11a of the substrate 11.

[0016] The DRAM 13 is a semiconductor package including a volatile semiconductor memory chip. The DRAM 13 is a data buffer in which data to be written received from a host device or data to be read read from the NAND package 14 is temporarily stored. The DRAM 13 is provided on the first surface 11a of the substrate 11, for example. The DRAM 13 may be provided inside the controller 12.

[0017] The NAND package 14 is a semiconductor package including a non-volatile semiconductor memory chip. The NAND package 14 is provided, for example, on the first surface 11a and the second surface 11b of the substrate 11. In this embodiment, each of the multiple NAND packages 14 has a heating wiring 30. The NAND package 14 is an example of a "semiconductor memory device."

[0018] The capacitor 15 is one of the electronic components electrically connected to the substrate 11. The capacitor 15 performs a power backup function for protecting data when, for example, power is unexpectedly cut off. In this embodiment, the capacitor 15 supplies power to the controller 12, the DRAM 13, and the multiple NAND packages 14 for a certain period of time when the power supply from the host device is unexpectedly cut off. The multiple capacitors 15 are arranged, for example, between the controller 12 and the DRAM 13 and the multiple NAND packages 14 in the X direction.

[0019] <2.NAND package configuration> Next, the configuration of the NAND package 14 will be described. 2 is a diagram showing one NAND package 14. The NAND package 14 has, for example, a substrate 21, a plurality of connection terminals 23, a plurality of memory chips 24, a plurality of adhesive films 25, a plurality of bonding wires 26, a sealing member 27, a heating wiring 30, a first pad 41, and a second pad 42. In the following, in order to distinguish the substrate 21 of the NAND package 14 from the substrate 11 described above, the substrate 21 will be referred to as a "package substrate 21."

[0020] The package substrate 21 is a plate member extending along the X and Y directions. When viewed from the Z direction, the package substrate 21 has a rectangular shape that is the same as the outer shape of the NAND package 14. The package substrate 21 has a first surface 21a and a second surface 21b located on the opposite side to the first surface 21a. The first surface 21a is a surface facing the +Z direction. The first surface 21a has a plurality of pads 22a to which bonding wires 26, which will be described later, are respectively connected. The second surface 21b is a surface facing the -Z direction. The second surface 21b has a plurality of pads 22b to which connection terminals 23, which will be described later, are respectively connected.

[0021] The package substrate 21 is a printed circuit board, and includes an insulating base material 21i and a wiring pattern 21w. The insulating base material 21i is an insulating hard member made of an insulating material such as glass epoxy resin or polyimide. The wiring pattern 21w is a conductive portion provided on the surface or inside of the insulating base material 21i.

[0022] The wiring pattern 21w includes, for example, a power supply wiring 21p and a signal wiring 21s. The power supply wiring 21p is a wiring through which a power supply current supplied from the substrate 11 to the NAND package 14 flows. The power supply wiring 21p is electrically connected to the memory chip 24 via the pad 22a, and a power supply current supplied to the memory chip 24 flows. The signal wiring 21s is a wiring through which a signal is transmitted. For example, a signal input from the substrate 11 to the NAND package 14, a signal output from the NAND package 14 to the substrate 11, or a signal transmitted within the NAND package 14 flows in the signal wiring 21s.

[0023] The connection terminals 23 are provided on the second surface 21b of the substrate 21 and exposed to the outside of the NAND package 14. The connection terminals 23 are electrical connection parts connected to pads of the substrate 11. The multiple connection terminals 23 are arranged, for example, in a grid pattern along the X direction and the Y direction. In this embodiment, the multiple connection terminals 23 are solder balls of a BGA (Ball Grid Array). However, the connection terminals 23 are not limited to the above example. The connection terminals 23 may be pads connected to the outside via a conductive paste, terminals such as a lead frame or a pin, or terminals connected to the outside in other ways.

[0024] The memory chip 24 is, for example, a non-volatile semiconductor memory chip, such as a NAND type flash memory chip. The memory chip 24 includes a plurality of memory cell transistors and a peripheral circuit for making the plurality of memory cell transistors function as memory elements. The memory chip 24 has, for example, a charge trap type memory cell transistor. However, the memory chip 24 is not limited to the above example, and may have a floating gate type memory cell transistor.

[0025] The memory chip 24 is a plate-like shape extending along the X and Y directions. The memory chips 24 are stacked in the Z direction with adhesive films 25 interposed therebetween. The adhesive films 25 are, for example, die-attach films. The memory chips 24 are stacked on the first surface 21a of the package substrate 21. The memory chips 24 are disposed between the first surface 21a of the package substrate 21 and the sealing member 27 in the Z direction. One of the memory chips 24 is an example of a "first memory chip." One of the memory chips 24 located between the first memory chip and the sealing member 27 in the Z direction is an example of a "second memory chip."

[0026] The memory chips 24 include, for example, a first group of memory chips 24A and a second group of memory chips 24B. The first group of memory chips 24A are arranged so that the memory chips 24A are shifted in the +X direction as they are farther from the package substrate 21. The second group of memory chips 24B are located on the +Z direction side with respect to the memory chips 24A. The second group of memory chips 24B are arranged so that the memory chips 24B are shifted in the -X direction as they are farther from the package substrate 21. Each memory chip 24 has a first region R1 and a second region R2. The first region R1 is an area that overlaps with the adjacent memory chip 24 located on the +Z direction side when viewed from the Z direction. The second region R2 is an area that is out of the adjacent memory chip 24 located on the +Z direction side when viewed from the Z direction (an area that does not overlap with the adjacent memory chip 24 located on the +Z direction side). The second region R2 of the memory chip 24 has pads 24s.

[0027] The bonding wire 26 is an electrical connection portion that connects the package substrate 21 and the memory chip 24. The bonding wires 26 include, for example, a first group of bonding wires 26A (only one is shown in FIG. 2) and a second group of bonding wires 26B (only one is shown in FIG. 2). The bonding wire 26A is provided at the end of the first group of memory chips 24A on the -X direction side, and connects the pads 24s of the first group of memory chips 24A to the pads 22a of the package substrate 21. On the other hand, the bonding wire 26B is provided at the end of the second group of memory chips 24B on the +X direction side, and connects the pads 24s of the second group of memory chips 24B to the pads 22a of the package substrate 21.

[0028] The sealing member 27 is an insulating part that protects the memory chips 24 and the bonding wires 26. The sealing member 27 is, for example, a molded resin. The sealing member 27 is provided on the first surface 21a of the package substrate 21, and covers the first surface 21a of the package substrate 21 when viewed from the Z direction. The sealing member 27 covers the memory chips 24 and the bonding wires 26 from the side opposite to the first surface 21a of the package substrate 21. For example, the sealing member 27 is formed in a rectangular shape that is the same as the outer shape of the NAND package 14 when viewed from the Z direction.

[0029] <3. Heating wiring and pads> Next, the heating wiring 30, the first pad 41, and the second pad 42 will be described. The heating wiring 30 is a heating wiring for heating the memory chip 24. The heating wiring 30 is a wiring different from the above-mentioned power supply wiring 21p and signal wiring 21s. The heating wiring 30 is an example of a "non-signal wiring". In this embodiment, the heating wiring 30 is provided at a position different from the surface of the multiple memory chips 24. In this embodiment, the heating wiring 30 is provided on the surface of the sealing member 27 (for example, the surface on the +Z direction side). The heating wiring 30 overlaps with each of the multiple memory chips 24 when viewed from the Z direction. For example, the heating wiring 30 overlaps with the first region R1 and the second region R2 of the multiple memory chips 24 when viewed from the Z direction.

[0030] The heating wire 30 has, for example, a first end 31, a second end 32, and a wire body 33. The first end 31 and the second end 32 are both ends of the heating wire 30. The first end 31 is electrically connected to a power supply unit PSa (see FIG. 4) of the external power supply device PS via a first pad 41 described later during heating treatment of the memory chip 24. The second end 32 is electrically connected to a ground PSb (see FIG. 4) of the external power supply device PS via a second pad 42 described later during heating treatment of the memory chip 24. The wire body 33 extends between the first end 31 and the second end 32, and connects the first end 31 and the second end 32.

[0031] The wiring body 33 includes, for example, a first portion 33a, a second portion 33b, a third portion 33c, a fourth portion 33d, and a fifth portion 33e. The first portion 33a extends linearly in the X direction. The second portion 33b is folded back from the end of the first portion 33a on the +X direction side toward the -X direction side, and extends linearly in parallel to the first portion 33a. The third portion 33c is folded back from the end of the second portion 33b on the -X direction side toward the +X direction side, and extends linearly in parallel to the second portion 33b. The fourth portion 33d is folded back from the end of the third portion 33c on the +X direction side toward the -X direction side, and extends linearly in parallel to the third portion 33c. The fifth portion 33e is folded back from the end of the fourth portion 33d on the -X direction side toward the +X direction side, and extends linearly in parallel to the fourth portion 33d. Between the first end 31 and the second end 32, the wiring main body 33 has configurations similar to the above-mentioned first portion 33a to fifth portion 33e repeated in the Y direction.

[0032] The length in the X direction of the first portion 33a, the length in the X direction of the second portion 33b, the length in the X direction of the third portion 33c, the length in the X direction of the fourth portion 33d, and the length in the X direction of the fifth portion 33e are, for example, the same as one another. The length in the X direction of each of the first portion 33a, the second portion 33b, the third portion 33c, the fourth portion 33d, and the fifth portion 33e is equal to or greater than half the length in the X direction of the sealing member 27.

[0033] The first portion 33a to the fifth portion 33e are arranged in the Y direction in the order of the first portion 33a, the second portion 33b, the third portion 33c, the fourth portion 33d, and the fifth portion 33e. The first portion 33a, the second portion 33b, the third portion 33c, the fourth portion 33d, and the fifth portion 33e are arranged, for example, at equal intervals in the Y direction. That is, the distance S in the Y direction between the first portion 33a and the second portion 33b, the distance S in the Y direction between the second portion 33b and the third portion 33c, the distance S in the Y direction between the third portion 33c and the fourth portion 33d, and the distance S in the Y direction between the fourth portion 33d and the fifth portion 33e are the same. The distance S is, for example, less than twice the wiring width W1 of the heating wiring 30 described later.

[0034] The first pad 41 is a pad exposed to the outside of the sealing member 27. In this embodiment, the first pad 41 is provided on a surface (for example, a surface on the +Z direction side) of the sealing member 27. The first pad 41 is connected to the first end 31 of the heating wire 30.

[0035] The second pad 42 is a pad exposed to the outside of the sealing member 27. In the present embodiment, the second pad 42 is provided on a surface (for example, a surface on the +Z direction side) of the sealing member 27. The second pad 42 is connected to the second end 32 of the heating wire 30.

[0036] In this embodiment, the heating wire 30, the first pad 41, and the second pad 42 are formed by spraying a conductive material onto the surface of the sealing member 27 by an inkjet method. The conductive material is, for example, silver particles, copper particles, or nickel particles, but is not limited to these. The thickness T1 in the Z direction of each of the heating wire 30, the first pad 41, and the second pad 42 is larger than the thickness T2 in the Z direction of the power supply wire 21p, and is larger than the thickness T3 in the Z direction of the signal wire 21s. In addition, the wiring width W1 of the heating wire 30 is larger than the wiring width W2 of the power supply wire 21p, and is larger than the wiring width W3 of the signal wire 21s. In this application, the "wiring width" refers to the width in the direction perpendicular to the extension direction of the wiring, and is the width of the narrowest part of the entire length of the wiring.

[0037] In this embodiment, the heating wiring 30, the first pad 41, and the second pad 42 are electrically insulated from wiring (e.g., the power supply wiring 21p or the signal wiring 21s) inside the NAND package 14. The heating wiring 30, the first pad 41, and the second pad 42 are in a floating state except during a heating process described later. Alternatively, the heating wiring 30, the first pad 41, and the second pad 42 may be electrically connected to the ground of the NAND package 14, for example, and may be at the same potential.

[0038] Next, a description will be given of an example of dimensions of the heating wiring 30. However, the dimensions of the heating wiring 30 are not limited to the example described below.

[0039] Here, a NAND package 14 having the following conditions is considered. The resistivity of the heating wiring 30 is 4 μΩ·cm (silver wiring). The chip size of the NAND package 14 is 10 mm×10 mm. The current density of the current flowing through the heating wiring 30 is 100 A / mm 2 The power supplied to the heating wiring 30 is 1 W or more. Note that the "wiring" described here means each part of the heating wiring 30 that extends in a specific direction, such as the first part 33a to the fifth part 33e described above.

[0040] The dimensions are as follows: The wiring width is 1000 μm. The minimum distance between the wirings is 50 μm. In this embodiment, the "distance between the wirings" refers to the distance S shown in FIG. 2. The wiring thickness (thickness T1) is 30 μm. The number of wirings is 9. In this embodiment, the "number of wirings" refers to the total number of multiple straight line parts arranged in parallel with a gap between them. In this embodiment, the "number of wirings" refers to the total number of the first part 33a, the second part 33b, the third part 33c, ... shown in FIG. 2. The total length of the heating wiring 30 is 90 mm. The wiring resistance of the heating wiring 30 is 0.12 Ω. The voltage is 0.36 V. The current is 3 A. The power is 1.08 W.

[0041] <4. NAND package manufacturing method> Next, a method for manufacturing the NAND package 14 will be described. 3 is a diagram showing a manufacturing method of the NAND package 14. First, a package substrate 21 provided with pads 22a is prepared. Next, a plurality of memory chips 24 are stacked in the Z direction on a first surface 21a of the package substrate 21 (see (a) in FIG. 3).

[0042] Next, a plurality of bonding wires 26 are provided to electrically connect the package substrate 21 and the plurality of memory chips 24 (see (b) in FIG. 3). Next, a sealing member 27 is provided so as to seal the plurality of memory chips 24 and the plurality of bonding wires 26 (see (c) in FIG. 3). Next, a conductive material is sprayed onto the surface of the sealing member 27 by the inkjet method to form the heating wiring 30, the first pad 41, and the second pad 42 ((d) in FIG. 3). This completes the NAND package 14.

[0043] <5. How to recycle NAND packages (heating method)> Next, a method for regenerating (heating) the NAND package 14 will be described. 4 is a perspective view for explaining a method for remanufacturing the NAND package 14. In this embodiment, for example, in a state where the NAND package 14 is mounted on the substrate 11 (or, more specifically, in a state where the storage device 1 is connected to a host device), power is supplied to the heating wiring 30 using an external power supply device PS. For example, a power supply unit PSa of the power supply device PS is connected to a first pad 41, and a ground PSb of the power supply device PS is connected to a second pad 42. Then, power is supplied from the power supply unit PSa to the first pad 41, whereby a heating process for remanufacturing the NAND package 14 is performed.

[0044] The above-mentioned heating process may involve heating the NAND package 14 at 200° C. for three hours, at 150° C. for eight hours, or at 125° C. for several days. This allows the memory cell transistors included in the memory chip 24 to recover from their degraded state, and the NAND package 14 is regenerated. In this application, "degradation" refers to characteristic degradation such as a shortened data retention time in the memory cell transistor or a wider distribution width of the threshold voltage for determining the written data value. In this application, "regeneration" refers to bringing the degraded state closer to the state before the degradation. In this application, "regeneration" is not limited to a complete return to the initial state, but also includes partial recovery of the state of the degraded memory cell transistor.

[0045] <6. Advantages> When the write and erase cycles are repeated from the initial state of the NAND package 14, characteristic degradation occurs, such as a shortening of the data retention time and a widening of the distribution width of the threshold voltage for determining the written data value. As this characteristic degradation progresses, the number of bits in which errors occur when reading data exceeds the number of bits that can be corrected by error correction, and the product life of the NAND package 14 is reached. For example, in the case of NAND packages 14 that have become increasingly multi-valued in recent years, the product life of the NAND package 14 tends to be reached due to the degradation of the memory cell transistors even when there is no defect in the peripheral circuits.

[0046] Here, according to research by the present inventors, it has been found that even if degradation occurs in the NAND package 14, if the NAND package 14 is heated under certain conditions that are met (for example, the heating temperature and heating time described above are ensured), then the degraded state of the memory cell transistors can be partially or completely restored.

[0047] However, if the entire storage device 1 is heated to restore the deteriorated state of the memory cell transistors, this heating may cause malfunctions in components other than the NAND package 14 (e.g., the controller 12 or the DRAM 13).

[0048] Therefore, in this embodiment, the NAND package 14 has a heating wire 30. The heating wire 30 is provided on the surface of the sealing member 27 and overlaps with the memory chip 24 when viewed from the Z direction. The heating wire 30 has a first end 31 electrically connected to the power supply unit PSa of the power supply device PS, a second end 32 electrically connected to the ground PSb of the external power supply device PS, and a wiring body 33 connecting the first end 31 and the second end 32. The wiring body 33 includes a first portion 33a extending in the X direction, a second portion 33b folded back from the end of the first portion 33a to the first side and extending parallel to the first portion 33a, and a third portion 33c folded back from the end of the second portion 33b to the second side opposite to the first side and extending parallel to the second portion 33b.

[0049] According to this configuration, a heating process can be performed by using the heating wiring 30 provided on the NAND package 14 to locally heat the NAND package 14 in the storage device 1. According to this heating process, compared to heating the entire storage device 1, it is possible to recover at least a part of the deteriorated state of the memory cell transistors while suppressing the influence on components such as the controller 12 or the DRAM 13. This makes it possible to extend the product life of the NAND package 14.

[0050] In this embodiment, the heating wiring 30 is a wiring formed by spraying a conductive material by an inkjet method. With this configuration, it is easier to form the heating wiring 30 on the surface of the sealing member 27 of the NAND package 14 compared to the case where other methods are used. This can improve the manufacturability of the storage device 1. Furthermore, when the heating wiring 30 is formed by the inkjet method, it is easier to arbitrarily set the thickness T1 of the heating wiring 30 in the Z direction.

[0051] In this embodiment, the package substrate 21 has a power supply wiring 21p through which a current flows to be supplied to the memory chip 24. A thickness T1 in the Z direction of the heating wiring 30 is larger than a thickness T2 in the Z direction of the power supply wiring 21p. This configuration makes it easier to pass a large current for heating the NAND package 14. This makes it easier to heat the NAND package 14 to a temperature required for regenerating the NAND package 14.

[0052] In this embodiment, the wiring width W1 of the heating wiring 30 is larger than the wiring width W2 of the power supply wiring 21p. With this configuration, it becomes easier to pass a large current for heating the NAND package 14. This makes it easier to heat the NAND package 14 to a temperature required for regenerating the NAND package 14.

[0053] In this embodiment, the heating wiring 30 is provided on the surface of the sealing member 27. With such a configuration, the internal configuration of the NAND package 14 (for example, the internal circuit configuration) can be made the same as that of the existing NAND package 14. This can improve the manufacturability of the NAND package 14.

[0054] In this embodiment, the NAND package 14 has a first pad 41 exposed to the outside of the sealing member 27 and electrically connected to a first end 31 of the heating wire 30, and a second pad 42 exposed to the outside of the sealing member 27 and electrically connected to a second end 32 of the heating wire 30. With this configuration, it is easier to supply heating power from the external power supply device PS to the heating wire 30 compared to a case where the heating wire 30 is provided inside the NAND package 14. Therefore, it is possible to simplify the internal configuration of the NAND package 14 compared to a case where a configuration related to the heating wire 30 is provided inside the NAND package 14. This can improve the manufacturability of the NAND package 14.

[0055] <7. Variations> Next, a NAND package 14A according to a modification of the first embodiment will be described. This modification is different from the first embodiment in that the heating wiring 30 is provided inside the sealing member 27. Note that the configuration other than that described below is the same as that of the first embodiment.

[0056] 5 is a diagram showing a NAND package 14A according to a modification of the first embodiment. In this modification, the sealing member 27 includes a main body 27a and a cover 27b. The main body 27a and the cover 27b are made of mold resin and have insulating properties.

[0057] The main body 27a is provided on the first surface 21a of the package substrate 21, similar to the sealing member 27 of the first embodiment, and covers the memory chips 24 and the bonding wires 26 from the opposite side of the first surface 21a of the package substrate 21. When viewed from the Z direction, the main body 27a is formed in a rectangular shape that is the same as the outer shape of the NAND package 14. The heating wiring 30, the first pad 41, and the second pad 42 are provided on the surface of the main body 27a on the +Z direction side.

[0058] The cover portion 27b is formed, for example, from the same material as the main body portion 27a, and is laminated on the surface of the main body portion 27a on the +Z direction side. The material of the cover portion 27b may be different from the material of the main body portion 27a. For example, the cover portion 27b may be formed from a resin material that has poorer heat dissipation properties than the material of the main body portion 27a in order to improve heat retention. In addition, from a different perspective from the above, for example, for the purpose of controlling heat, the material of the cover portion 27b may be different from the material of the main body portion 27a.

[0059] The cover portion 27b covers the heating wiring 30 from the side opposite to the main body portion 27a. The cover portion 27b is a protective layer that protects the heating wiring 30. The cover portion 27b has openings 27h at positions corresponding to the first pad 41 and the second pad 42. Each of the first pad 41 and the second pad 42 is exposed to the outside of the NAND package 14A through the opening 27h. The power supply unit PSa of the external power supply device PS is connected to the first pad 41 through the opening 27h. The ground PSb of the external power supply device PS is connected to the second pad 42 through the opening 27h.

[0060] Even with this configuration, the product life of the NAND package 14A can be extended by performing a heating process using the heating wire 30. In this modification, the heating wire 30 is provided inside the sealing member 27 at a position different from the surfaces of the memory chips 24. For example, the heating wire 30 is covered and protected by the cover portion 27b. This makes it possible to suppress the occurrence of defects related to the heating wire 30 and more reliably extend the product life of the NAND package 14A.

[0061] In this modification, the heating wiring 30 includes a first portion 33a, a second portion 33b folded back from an end of the first portion 33a to a first side and extending parallel to the first portion 33a, and a third portion 33c folded back from an end of the second portion 33b to a second side opposite to the first side and extending parallel to the second portion 33b. With this configuration, air is easily released between the first portion 33a and the second portion 33b and between the second portion 33b and the third portion 33c in the step of providing the cover portion 27b, and voids are unlikely to occur between the main body portion 27a and the cover portion 27b.

[0062] Second embodiment Next, a NAND package 14B according to a second embodiment will be described. This embodiment differs from the first embodiment in that electrical connection parts 51 and 52 are provided to connect the heating wiring 30 to the substrate 11. Note that the configuration other than that described below is the same as that of the first embodiment.

[0063] 6 is a diagram showing a NAND package 14B according to the second embodiment. In this embodiment, the NAND package 14B has a first electrical connection portion 51 and a second electrical connection portion 52.

[0064] The first electrical connection portion 51 is an electrical connection portion that electrically connects the first end 31 of the heating wiring 30 and the package substrate 21. When viewed from the Z direction, the first electrical connection portion 51 is disposed in a region outside the memory chip 24. The first electrical connection portion 51 is provided inside the sealing member 27. The first electrical connection portion 51 is, for example, a through-hole via provided in the sealing member 27. The first electrical connection portion 51 may be, for example, a wire including a VW (Vertical Wire) or the like, a pillar including a metal pillar or the like, or a TMV (Through Mold Via). For example, a plurality of first electrical connection portions 51 may be provided. The first electrical connection portion 51 extends through the sealing member 27 in the Z direction and penetrates the sealing member 27, and electrically connects the first end 31 of the heating wiring 30 and the package substrate 21.

[0065] The second electrical connection portion 52 is an electrical connection portion that electrically connects the second end 32 of the heating wiring 30 and the package substrate 21. When viewed from the Z direction, the second electrical connection portion 52 is disposed in a region outside the memory chip 24. The second electrical connection portion 52 is provided inside the sealing member 27. The second electrical connection portion 52 is, for example, a through-hole via provided in the sealing member 27. The second electrical connection portion 52 may be, for example, a wire including VW or the like, a pillar including a metal pillar or the like, or a TMV. For example, a plurality of second electrical connection portions 52 may be provided. The second electrical connection portion 52 extends through the sealing member 27 in the Z direction and penetrates the sealing member 27, and electrically connects the second end 32 of the heating wiring 30 and the package substrate 21.

[0066] In this embodiment, power is supplied to the heating wiring 30 from the substrate 11 of the storage device 1, instead of from an external power supply device PS, via the connection terminal 23 and the package substrate 21. The substrate 11 of the storage device 1 is an example of a "power supply unit."

[0067] Even with such a configuration, the product life of the NAND package 14B can be extended by performing a heating process using the heating wiring 30. In this embodiment, the NAND package 14B has a first electrical connection part 51 provided inside the sealing member 27 and electrically connecting the first end 31 of the heating wiring 30 to the package substrate 21, and a second electrical connection part 52 provided inside the sealing member 27 and electrically connecting the second end 32 of the heating wiring 30 to the package substrate 21. With such a configuration, power can be supplied to the heating wiring 30 from the substrate 11 of the storage device 1. Therefore, for example, even in a state where a plurality of storage devices 1 are arranged at high density, power can be easily supplied to the heating wiring 30.

[0068] (First example of the second embodiment) 7 is a diagram showing a first example of a NAND package 14B of the second embodiment. In the first example, a case will be described in which a first electrical connection portion 51A and a second electrical connection portion 52A that are VW (Vertical Wire) are provided as the first electrical connection portion 51 and the second electrical connection portion 52. In this application, "VW" refers to a wire that extends in a direction perpendicular to the first surface 21a of the package 21. In this application, "vertical direction" may include "approximately vertical direction".

[0069] In the first example, the first surface 21a of the package substrate 21 has a pad 22c to which the first electrical connection portion 51A or the second electrical connection portion 52A is connected. The first electrical connection portion 51A and the second electrical connection portion 52A are, for example, wires extending linearly from the pad 22c in the +Z direction.

[0070] The width (e.g., diameter) of each of the first electrical connection portion 51A and the second electrical connection portion 52A is, for example, 20 μm. The width (e.g., diameter) of each of the first electrical connection portion 51A and the second electrical connection portion 52A is, for example, smaller than the wiring width W1 of the heating wiring 30. The width (e.g., diameter) of each of the first electrical connection portion 51A and the second electrical connection portion 52A is, for example, smaller than the distance S between the wirings of the heating wiring 30.

[0071] In the first example, a plurality of (for example, three) first electrical connection parts 51A are provided. The plurality of (for example, three) first electrical connection parts 51A are electrically connected in parallel between the package substrate 21 and the first end 31 of the heating wiring 30. For example, the plurality of (for example, three) first electrical connection parts 51A are arranged side by side in the X direction which is the extension direction of the first end 31 of the heating wiring 30. Similarly, in the first example, a plurality of (for example, three) second electrical connection parts 52A are provided. The plurality of (for example, three) second electrical connection parts 52A are electrically connected in parallel between the package substrate 21 and the second end 32 of the heating wiring 30. For example, the plurality of (for example, three) second electrical connection parts 52A are arranged side by side in the X direction which is the extension direction of the second end 32 of the heating wiring 30.

[0072] The material of the first electrical connection portion 51A and the second electrical connection portion 52A may be, for example, a single material such as Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, or the like, a composite material of two or more of these, or an alloy of two or more of these. More preferably, the material of the first electrical connection portion 51A and the second electrical connection portion 52A may be Au, Ag, Cu, or CuPd. More preferably, the material of the first electrical connection portion 51A and the second electrical connection portion 52A may be hard material such as Cu or CuPd. The material of the first electrical connection portion 51A and the second electrical connection portion 52A may be a metal in which Cu is coated with Pd.

[0073] 8 is a diagram showing a manufacturing method of a NAND package 14B of a first example of the second embodiment. First, a package substrate 21 provided with pads 22a and 22c is prepared. Next, a plurality of memory chips 24 are stacked in the Z direction on a first surface 21a of the package substrate 21 (see (a) in FIG. 8).

[0074] Next, a plurality of bonding wires 26 are provided to electrically connect the package substrate 21 and the plurality of memory chips 24. Also, a first electrical connection portion 51A and a second electrical connection portion 52A, which are VW, are provided (see (b) in FIG. 8). The first electrical connection portion 51A and the second electrical connection portion 52A are formed, for example, by extending them upward to a height exceeding the topmost memory chip 24, and then cutting them using a known technique such as a pull-cut method.

[0075] Next, the sealing member 27 is provided so as to seal the memory chips 24, the bonding wires 26, the first electrical connection parts 51A, and the second electrical connection parts 52A (see (c) in FIG. 8). The sealing member 27 is formed, for example, by providing a sealing member 27Z that fills the first electrical connection parts 51A and the second electrical connection parts 52A, and then removing the end of the sealing member 27Z on the +Z direction side (see the black arrow in the figure). As a result, the end of the first electrical connection part 51A and the second electrical connection part 52A on the +Z direction side is exposed to the outside of the sealing member 27. At this time, for example, a part of the end of the first electrical connection part 51A and the second electrical connection part 52A on the +Z direction side may also be removed. Next, a conductive material is sprayed onto the surface of the sealing member 27 by an inkjet method to form the heating wiring 30 (see (d) in FIG. 8). This completes the first example of the NAND package 14B.

[0076] (Second example of the second embodiment) FIG. 9 is a diagram showing a NAND package 14B of a second example of the second embodiment. In the second example, a case will be described in which a first electrical connection portion 51B and a second electrical connection portion 52B that are conductive pillars are provided as the first electrical connection portion 51 and the second electrical connection portion 52. In this application, the term "pillar" refers to a columnar electrode portion that extends in a direction perpendicular to the first surface 21a of the package 21. The "pillar" may be a metal pillar or a pillar formed of a conductive material other than metal. In this application, the term "conductive pillar" is not limited to a case in which the entire pillar is conductive. For example, when the "conductive pillar" has a center portion (core portion) and a coating portion that covers the outer periphery of the center portion, only one of the center portion and the coating portion may be conductive.

[0077] The first electrical connection portion 51B and the second electrical connection portion 52B are, for example, columnar electrode portions extending linearly in the +Z direction from the pad 22c (not shown). In the second example, the width (for example, diameter) of each of the first electrical connection portion 51B and the second electrical connection portion 52B is, for example, larger than the wiring width W1 of the heating wiring 30. For example, one each of the first electrical connection portion 51B and the second electrical connection portion 52B is provided. However, a plurality of each of the first electrical connection portion 51B and the second electrical connection portion 52B may be provided. For example, the materials described in the first example can be used as the materials of the first electrical connection portion 51B and the second electrical connection portion 52B.

[0078] 10 is a diagram showing a manufacturing method of a NAND package 14B of a second example of the second embodiment. First, a package substrate 21 provided with pads 22a and 22c is prepared. Next, a plurality of memory chips 24 are stacked in the Z direction on a first surface 21a of the package substrate 21. Also, a first electrical connection portion 51B and a second electrical connection portion 52B, which are pillars, are provided (see (a) in FIG. 10). Note that the step of providing the first electrical connection portion 51B and the second electrical connection portion 52B may be performed after the step of providing the bonding wires 26.

[0079] Next, a plurality of bonding wires 26 are provided, and the package substrate 21 and the plurality of memory chips 24 are electrically connected (see (b) in FIG. 10). Next, a sealing member 27 is provided so as to seal the plurality of memory chips 24, the plurality of bonding wires 26, the first electrical connection portion 51B, and the second electrical connection portion 52B (see (c) in FIG. 8). The sealing member 27 is formed, for example, by providing a sealing member 27Z that fills the first electrical connection portion 51B and the second electrical connection portion 52B, and then removing an end portion of the sealing member 27Z on the +Z direction side (see the black arrow in the figure). As a result, the end portions of the first electrical connection portion 51B and the second electrical connection portion 52B on the +Z direction side are exposed to the outside of the sealing member 27. At this time, for example, a part of the end portions of the first electrical connection portion 51B and the second electrical connection portion 52B on the +Z direction side may also be removed. Next, a conductive material is sprayed onto the surface of the sealing member 27 by an inkjet method to form the heating wiring 30 ((d) in FIG. 10). In this way, the second example of the NAND package 14B is completed.

[0080] (Third example of the second embodiment) FIG. 11 is a diagram showing a NAND package 14B of a third example of the second embodiment. In the third example, a case will be described in which a first electrical connection portion 51C and a second electrical connection portion 52C that are TMVs (Through Mold Vias) are provided as the first electrical connection portion 51 and the second electrical connection portion 52. In this application, "TMV" means a via that extends in a direction perpendicular to the first surface 21a of the package 21 and penetrates at least a part of the sealing member 27. "TMV" may be a metallic via, or a via formed of a conductive material other than metal. In this application, "via" is not limited to a case in which the entire via is conductive. For example, when a "via" has a central portion (core portion) and a coating portion that covers the outer periphery of the central portion, only one of the central portion and the coating portion may be conductive.

[0081] The first electrical connection portion 51C and the second electrical connection portion 52C are, for example, columnar electrode portions that penetrate the sealing member 27 in the Z direction and are connected to the first surface 21a of the package substrate 21. In the third example, the width (for example, diameter) of each of the first electrical connection portion 51C and the second electrical connection portion 52C is, for example, larger than the wiring width W1 of the heating wiring 30. For example, one each of the first electrical connection portion 51C and the second electrical connection portion 52C is provided. However, a plurality of each of the first electrical connection portion 51C and the second electrical connection portion 52C may be provided. For example, the materials described in the first example can be used as the materials of the first electrical connection portion 51C and the second electrical connection portion 52C.

[0082] 12 is a diagram showing a manufacturing method of a NAND package 14B of a third example of the second embodiment. First, a package substrate 21 provided with pads 22a is prepared. Next, a plurality of memory chips 24 are stacked in the Z direction on a first surface 21a of the package substrate 21 (see (a) in FIG. 12). Next, a plurality of bonding wires 26 are provided to electrically connect the package substrate 21 and the plurality of memory chips 24. Next, a sealing member 27 is provided so as to seal the plurality of memory chips 24 and the plurality of bonding wires 26 (see (b) in FIG. 10).

[0083] Next, a through hole 27ha is provided penetrating the sealing member 27 in the Z direction. Then, materials for the first electrical connection portion 51C and the second electrical connection portion 52C are supplied into the through hole 27ha to form the first electrical connection portion 51C and the second electrical connection portion 52C (see (c) in FIG. 12). Next, a conductive material is sprayed onto the surface of the sealing member 27 by an inkjet method to form the heating wiring 30 ((d) in FIG. 12). This completes the third example of the NAND package 14B.

[0084] Third embodiment Next, a NAND package 14C according to a third embodiment will be described. This embodiment differs from the first embodiment in that a heating wiring 30 is provided on the first surface 21a of the package substrate 21. Note that the configuration other than that described below is the same as that of the first embodiment.

[0085] FIG. 13 is a diagram showing a NAND package 14C of the third embodiment. In this embodiment, the heating wiring 30 is provided on the first surface 21a of the package substrate 21. The heating wiring 30 is located, for example, between a plurality of pads 22a arranged separately on both sides of the memory chip 24 in the X direction. The memory chip 24 located furthest on the -Z direction side among the plurality of memory chips 24 is arranged on the heating wiring 30 via an adhesive film 25. Parts of the adhesive film 25 enter between the first portion 33a and the second portion 33b of the heating wiring 30, between the second portion 33b and the third portion 33c, between the third portion 33c and the fourth portion 33d, and between the fourth portion 33d and the fifth portion 33e. When viewed from the Z direction, the heating wiring 30 overlaps with each of the plurality of memory chips 24.

[0086] The shape and size of the heating wiring 30 are not limited to the above example. For example, the heating wiring 30 may extend into an area (an area located on the outer periphery of the memory chip 24) that does not overlap with the memory chip 24 when viewed from the Z direction. When the heating wiring 30 extends to the outer periphery of the memory chip 24 when viewed from the Z direction, the heating wiring 30 is disposed at a position that avoids the multiple pads 22a. For example, the first portion 33a, the second portion 33b, the third portion 33c, the fourth portion 33d, and the fifth portion 33e of the heating wiring 30 extend while being folded back in order in the -X direction and the +X direction between the multiple pads 22a that are disposed separately on both sides of the memory chip 24 in the X direction when viewed from the Z direction.

[0087] In this embodiment, the first end 31 and the second end 32 of the heating wiring 30 are electrically connected to the package substrate 21. Power is supplied to the heating wiring 30 from the substrate 11 of the storage device 1 via the connection terminal 23 and the package substrate 21.

[0088] Next, a method for manufacturing the NAND package 14C will be described. 14 is a diagram showing a manufacturing method of the NAND package 14C. First, the heating wiring 30 is provided on the first surface 21a of the package substrate 21 (see (a) in FIG. 14). The heating wiring 30 is formed, for example, by spraying a conductive material onto the first surface 21a of the package substrate 21 using an inkjet method. Alternatively, the heating wiring 30 may be formed in the same process as the pad 22a and other wiring on the first surface 21a of the package substrate 21 (for example, a process of etching a copper-clad laminate). Next, a plurality of memory chips 24 are stacked in the Z direction on the first surface 21a of the package substrate 21 (see (b) in FIG. 14).

[0089] Next, a plurality of bonding wires 26 are provided to electrically connect the package substrate 21 and the plurality of memory chips 24 (see (c) in FIG. 14). Next, a sealing member 27 is provided so as to seal the plurality of memory chips 24 and the plurality of bonding wires 26 (see (d) in FIG. 14). This completes the NAND package 14C.

[0090] Even with this configuration, the product life of the NAND package 14C can be extended. Moreover, in this embodiment, the heating wiring 30 is provided on the first surface 21a of the package substrate 21. With this configuration, power can be supplied to the heating wiring 30 from the substrate 11 of the storage device 1. Therefore, for example, power can be supplied to the heating wiring 30 even with a simpler configuration compared to the first and second embodiments.

[0091] In this embodiment, the heating wiring 30 includes a first portion 33a, a second portion 33b that is folded back from an end of the first portion 33a to the first side and extends parallel to the first portion 33a, and a third portion 33c that is folded back from an end of the second portion 33b to the second side opposite to the first side and extends parallel to the second portion 33b. With this configuration, air is easily released between the first portion 33a and the second portion 33b and between the second portion 33b and the third portion 33c in the process of stacking the memory chips 24, and voids are less likely to occur between the first surface 21a of the package substrate 21 and the adhesive film 25 of the bottom layer.

[0092] (Fourth embodiment) Next, a NAND package 14D according to a fourth embodiment will be described. This embodiment differs from the first embodiment in that a heating wiring 30 is provided inside the package substrate 21. Note that the configuration other than that described below is the same as that of the first embodiment.

[0093] 15 is a diagram showing a NAND package 14D according to the fourth embodiment. In this embodiment, the heating wiring 30 is provided in an inner layer of the package substrate 21. For example, the heating wiring 30 is disposed in the inner layer closest to the first surface 21a among the multiple inner layers of the package substrate 21. The heating wiring 30 overlaps with each of the multiple memory chips 24 when viewed from the Z direction.

[0094] Even with such a configuration, the product life of the NAND package 14D can be extended by performing a heating process using the heating wiring 30. In this embodiment, the heating wiring 30 is provided inside the package substrate 21. With such a configuration, power can be supplied to the heating wiring 30 from the substrate 11 of the storage device 1. Therefore, for example, power can be supplied to the heating wiring 30 even with a simpler configuration than the first and second embodiments.

[0095] Fifth embodiment Next, a NAND package 14E according to a fifth embodiment will be described. This embodiment differs from the first embodiment in that a heating wire 30 is provided on the surface of the memory chip 24. Note that the configuration other than that described below is the same as that of the first embodiment.

[0096] 16 is a diagram showing a NAND package 14E according to the fifth embodiment. In this embodiment, the heating wiring 30 is provided on the surfaces of a plurality of (for example, all) memory chips 24. The heating wiring 30 is provided on the surface of each memory chip 24 on the +Z direction side.

[0097] In this embodiment, each memory chip 24 has a first region R1 and a second region R2. In each memory chip 24, a plurality of pads 24s are provided in the second region R2. The plurality of pads 24s are arranged, for example, in the Y direction.

[0098] In this embodiment, the wiring body 33 of the heating wiring 30 is provided in the first region R1. Parts of the adhesive film 25 for fixing the memory chip 24 adjacent in the +Z direction enter between the first portion 33a and the second portion 33b of the heating wiring 30, between the second portion 33b and the third portion 33c, between the third portion 33c and the fourth portion 33d, and between the fourth portion 33d and the fifth portion 33e.

[0099] On the other hand, the first pad 41 and the second pad 42 are provided in the second region R2. For example, the first pad 41 and the second pad 42 are arranged separately on both sides of the multiple pads 24s in the Y direction. In this embodiment, the NAND package 14E has a bonding wire 61 and a bonding wire 62.

[0100] The bonding wire 61 is an electrical connection portion that electrically connects the first end 31 of the heating wiring 30 and the package substrate 21. The bonding wire 61 is an example of a "first electrical connection portion." The bonding wire 61 is connected to the first pad 41, and electrically connects the first end 31 of the heating wiring 30 and the pad 22a of the package substrate 21 via the first pad 41. The bonding wire 61 sequentially connects the first pads 41 of the multiple memory chips 24 so as to electrically connect the first pads 41 of the multiple memory chips 24 in series.

[0101] The bonding wire 62 is an electrical connection portion that electrically connects the second end 32 of the heating wiring 30 and the package substrate 21. The bonding wire 62 is an example of a "second electrical connection portion." The bonding wire 62 is connected to the second pad 42, and electrically connects the second end 32 of the heating wiring 30 and the pad 22a of the package substrate 21 via the second pad 42. The bonding wire 62 sequentially connects the second pads 42 of the multiple memory chips 24 so as to electrically connect the second pads 42 of the multiple memory chips 24 in series.

[0102] Next, an example of the dimensions of the heating wiring 30 will be described. However, the dimensions of the heating wiring 30 are not limited to the example described below. Here, as in the first embodiment, a NAND package 14E having the following conditions will be considered. The resistivity of the heating wiring 30 is 4 μΩ·cm (silver wiring). The chip size of the NAND package 14E is 10 mm×10 mm. The current density of the current flowing through the heating wiring 30 is 100 A / mm 2 The power supplied to the heating wiring 30 is 1 W or more. Note that the "wiring" described here means each part of the heating wiring 30 that extends in a specific direction, such as the first part 33a to the fifth part 33e described above.

[0103] Example dimensions are as follows: The wiring width is 200 μm. The minimum spacing between the wirings is 50 μm. The wiring thickness (thickness T1) is 10 μm. The number of wirings is 40. The total length of the heating wiring 30 is 400 mm. The wiring resistance of the heating wiring 30 is 8 Ω. The voltage is 1 V. The current is 0.125 A. In one memory chip 24 out of the multiple memory chips 24, 0.125 W of power is supplied. Therefore, in this embodiment, since there are eight multiple memory chips 24 as shown in FIG. 16(b), the total power in the multiple memory chips 24 is 1 W.

[0104] Next, a method for manufacturing the NAND package 14E will be described. 17 is a diagram showing a manufacturing method of a NAND package 14E. First, the heating wiring 30 is provided on the surface of the memory chip 24 before the memory chips 24 are separated into individual pieces (see (a) in FIG. 17). Next, the memory chips 24 are stacked in the Z direction on the first surface 21a of the package substrate 21 (see (b) in FIG. 17).

[0105] Next, a plurality of bonding wires 26 are provided to electrically connect the package substrate 21 and the pads 24s of the plurality of memory chips 24. Also, bonding wires 61 are provided to electrically connect the package substrate 21 and the first pads 41 of the plurality of memory chips 24. Also, bonding wires 62 are provided to electrically connect the package substrate 21 and the second pads 42 of the plurality of memory chips 24 (see (c) in FIG. 17). Next, a sealing member 27 is provided so as to seal the plurality of memory chips 24, the plurality of bonding wires 26, the bonding wires 61, and the bonding wires 62 (see (d) in FIG. 17). This completes the NAND package 14E.

[0106] Even with this configuration, the product life of the NAND package 14E can be extended by performing a heating process using the heating wires 30. In this embodiment, the heating wires 30 are provided on the surface of the memory chips 24. With this configuration, each memory chip 24 can be heated more directly.

[0107] <Modification of the Fifth Embodiment> Next, a description will be given of some modified examples of the fifth embodiment. Note that in each modified example, the configuration other than that described below is the same as that of the fifth embodiment.

[0108] (First Modification) 18 is a diagram showing a NAND package 14F of a first modified example. In this modified example, the NAND package 14F has bonding wires 61, the number of which is the same as the number of memory chips 24, and bonding wires 62, the number of which is the same as the number of memory chips 24.

[0109] The multiple bonding wires 61 are provided in one-to-one correspondence with the multiple memory chips 24, and connect first pads 41 of the corresponding memory chips 24 to the package substrate 21. In this modification, the multiple bonding wires 61 connect the first pads 41 of the multiple memory chips 24 to the package substrate 21 electrically in parallel.

[0110] The multiple bonding wires 62 are provided in one-to-one correspondence with the multiple memory chips 24, and connect second pads 42 of the corresponding memory chips 24 to the package substrate 21. In this modification, the multiple bonding wires 62 connect second pads 42 of the multiple memory chips 24 electrically in parallel to the package substrate 21.

[0111] Even with this configuration, the product life of the NAND package 14F can be extended by performing a heating process using the heating wiring 30. In this modification, since each of the bonding wires 61 and 62 is provided for each memory chip 24, it is easy to pass a large current through the heating wiring 30 of each memory chip 24.

[0112] (Second Modification) 19 is a diagram showing a NAND package 14G of a second modified example. In this modified example, in the NAND package 14G, a plurality of bonding wires 61 are provided corresponding to the first pads 41 of each memory chip 24, and a plurality of bonding wires 62 are provided corresponding to the second pads 42 of each memory chip 24.

[0113] A plurality of bonding wires 61 provided corresponding to the first pads 41 of each memory chip 24 are electrically connected in parallel to the first pads 41 of the memory chip 24. Similarly, a plurality of bonding wires 62 provided corresponding to the second pads 42 of each memory chip 24 are electrically connected in parallel to the second pads 42 of the memory chip 24.

[0114] Even with this configuration, the product life of the NAND package 14G can be extended by performing a heating process using the heating wiring 30. In this modification, a plurality of bonding wires 61 and a plurality of bonding wires 62 are provided corresponding to each memory chip 24. This makes it easier to pass a large current through the heating wiring 30 of each memory chip 24.

[0115] (Third Modification) 20 is a diagram showing a NAND package 14H of a third modified example. In this modified example, the NAND package 14H has a first electrical connection portion 71 and a second electrical connection portion 72 instead of the bonding wires 61 and 62.

[0116] In this modification, memory chip 24 has a first surface S1 and a second surface S2. The first surface S1 faces the +Z direction and extends in the X and Y directions. The second surface S2 corresponds to a side surface of memory chip 24. The second surface S2 faces the X direction and extends in the Y and Z directions.

[0117] The first electrical connection portion 71 is an electrical connection portion that electrically connects the first end 31 of the heating wiring 30 and the package substrate 21. In this modification, the first electrical connection portion 71 is provided in a stepped shape so as to be continuous with the first surfaces S1 of the multiple memory chips 24 and the second surfaces S2 of the multiple memory chips 24, and is connected to the pads 22a of the package substrate 21. The first electrical connection portion 71 sequentially connects the first pads 41 of the multiple memory chips 24 so as to electrically connect the first pads 41 of the multiple memory chips 24 in series. The first electrical connection portion 71 is formed, for example, by spraying a conductive material onto the first surfaces S1 of the multiple memory chips 24 and the second surfaces S2 of the multiple memory chips 24 by an inkjet method.

[0118] The second electrical connection portion 72 is an electrical connection portion that electrically connects the second end 32 of the heating wiring 30 and the package substrate 21. In this modification, the second electrical connection portion 72 is provided in a stepped shape so as to be continuous with the first surface S1 of the plurality of memory chips 24 and the second surface S2 of the plurality of memory chips 24, and is connected to the pad 22a of the package substrate 21. The second electrical connection portion 72 sequentially connects the second pads 42 of the plurality of memory chips 24 so as to electrically connect the second pads 42 of the plurality of memory chips 24 in series. The second electrical connection portion 72 is formed, for example, by spraying a conductive material onto the first surface S1 of the plurality of memory chips 24 and the second surface S2 of the plurality of memory chips 24 by an inkjet method.

[0119] Even with this configuration, the product life of the NAND package 14H can be extended by performing a heating process using the heating wiring 30. In this modification, the NAND package 14H has the first electrical connection portion 71 and the second electrical connection portion 72 formed by the inkjet method. The inkjet method allows the first electrical connection portion 71 and the second electrical connection portion 72 to be formed with any thickness or wiring width. This makes it easy to pass a large current through the heating wiring 30 of each memory chip 24.

[0120] (Fourth Modification) FIG. 21 is a diagram showing a NAND package 14I of a fourth modified example. In this modified example, the NAND package 14I has a plurality of electrical connection parts 73 instead of the plurality of bonding wires 26. Each of the plurality of electrical connection parts 73 is provided in a stepped shape so as to be continuous with the first surface S1 of the plurality of memory chips 24 and the second surface S2 of the plurality of memory chips 24, and is connected to the pad 22a of the package substrate 21. Each of the plurality of electrical connection parts 73 sequentially connects the pads 24s of the plurality of memory chips 24 so as to electrically connect the pads 24s of the plurality of memory chips 24 in series. The plurality of electrical connection parts 73 are formed, for example, by spraying a conductive material onto the first surface S1 of the plurality of memory chips 24 and the second surface S2 of the plurality of memory chips 24 by an inkjet method.

[0121] Even with this configuration, the life of the NAND package 14I can be extended by performing a heating process using the heating wiring 30. Furthermore, in this modification, an electrical connection portion 73 is provided that connects the pads 24s of the memory chip 24 to the package substrate 21. With this configuration, the first electrical connection portion 71, the second electrical connection portion 72, and the electrical connection portion 73 have similar structures. This allows the manufacturability of the NAND package 14I to be improved.

[0122] (Fifth Modification) 22 is a diagram showing a NAND package 14J of a fifth modified example. In this modified example, the heating wire 30 is provided only on some of the memory chips 24. For example, when the memory chips 24 are viewed as one stack SB, the heating wire 30 is provided on the surface of one memory chip 24 that is closest to the center of the stack SB in the Z direction. Even with this configuration, the product life of the NAND package 14J can be extended by performing a heating process using the heating wire 30.

[0123] (Sixth Modification) 23 is a diagram showing a NAND package 14K of a sixth modified example. In this modified example, the heating wires 30 are provided only on some of the memory chips 24. For example, the heating wires 30 are provided on the surfaces of every other memory chip 24 in the Z direction (for example, odd-numbered memory chips 24 counting from the memory chip 24 in the bottom layer) among the multiple memory chips 24. Even with this configuration, the life of the NAND package 14K can be extended by performing a heating process using the heating wires 30.

[0124] (Seventh Modification) 24 is a diagram showing a NAND package 14L of a seventh modified example. In this modified example, the heating wiring 30 is provided only in a partial region of each memory chip 24. Each memory chip 24 has a plurality of (e.g., four) memory plane regions MP. The memory plane region MP has a memory region including a plurality of memory cell transistors, a circuit region including peripheral circuits that operate the plurality of memory cell transistors, and a wiring region including wiring that connects the memory region and the peripheral circuits.

[0125] In this modification, each memory plane region MP has a memory region MPa and a wiring region MPb when viewed from the Z direction. The memory region MPa includes a plurality of word lines stacked in the Z direction and a plurality of memory pillars penetrating the plurality of word lines in the Z direction, and memory cell transistors are formed at the intersections between the word lines and the memory pillars. The above-mentioned circuit region is, for example, stacked above or below the memory region MPa in the Z direction. On the other hand, the wiring region MPb is a region outside the memory region MPa. The wiring region MPb includes a plurality of contacts extending in the Z direction to connect the memory region MPa and the above-mentioned circuit region.

[0126] In this modification, the heating circuit 30 is provided in the memory region MPa of each memory plane region MP, but is not provided in the wiring region MPb. With this configuration, the memory region including the memory cell transistor to be regenerated can be heated more efficiently.

[0127] (Eighth Modification) 25 is a diagram showing a NAND package 14M of an eighth modified example. In this modified example, the memory region MPa of each memory plane region MP includes a first region MPaa and a second region MPab. When viewed from the Z direction, the first region MPaa is a region in the memory region MPa that overlaps with the sense amplifiers and row decoders included in the circuit region. When viewed from the Z direction, the second region MPab is a region outside the first region MPaa. When viewed from the Z direction, the second region MPab is a region that does not overlap with the sense amplifiers and row decoders included in the circuit region.

[0128] In this modification, the heating circuit 30 is provided in the second region MPab of the memory region MPa in each memory plane region MP, but is not provided in the first region MPaa and wiring region MPb of the memory region MPa. With this configuration, the memory region including the memory cell transistor to be regenerated can be heated more efficiently, and the influence of the heating process on the sense amplifier and row decoder can be suppressed compared to, for example, the seventh modification.

[0129] Details of the "memory cell transistor", "contact", "sense amplifier", and "row decoder" in this application are described in, for example, Japanese Patent Application No. 2023-111719. This document is incorporated by reference in its entirety in this specification. For example, the "sense amplifier" and the "row decoder" correspond to the "sense amplifier module" and the "row decoder module" in the above document, respectively.

[0130] Sixth embodiment Next, a NAND package 14N according to a sixth embodiment will be described. This embodiment differs from the first embodiment in that electromagnetic induction heating is used. Note that the configuration other than that described below is the same as that of the first embodiment.

[0131] FIG. 26 is a diagram showing a NAND package 14N of the seventh embodiment. The NAND package 14N has a metal part 81 for electromagnetic induction heating instead of the heating wiring 30. The metal part 81 is, for example, a metal film provided on the surface of the sealing member 27 on the +Z direction side. When viewed from the Z direction, the metal part 81 covers the entire sealing member 27. When viewed from the Z direction, the metal part 81 overlaps each of the multiple memory chips 24. The thickness T4 of the metal part 81 in the Z direction is, for example, 0.3 μm or more. For example, the metal part 81 can be formed using a sputtering device. For example, by using a sputtering device, a metal film of 0.3 μm or more can be formed. From another perspective, the thickness T4 of the metal part 81 in the Z direction is several μm to several hundreds of μm. For example, the thickness T4 of the metal part 81 in the Z direction is 1.0 μm or more.

[0132] The metal part 81 for electromagnetic induction heating is not limited to a metal part dedicated to electromagnetic induction heating, and may be realized by a metal film provided for shielding. That is, the NAND package 14N may be heated by electromagnetic induction heating using a metal film provided for shielding.

[0133] Next, a refurbishment method (heating method) for the NAND package 14N will be described. 27 is a perspective view for explaining a method for regenerating (heating) the NAND package 14N. In this embodiment, for example, in a state where the NAND package 14N is mounted on the substrate 11 (or, more specifically, in a state where the storage device 1 is connected to a host device), a magnetic field (magnetic lines of force G) is applied to the metal part 81 using an external induction heating device IH. For example, the coil C of the induction heating device IH is made to face the NAND package 14N, and an alternating current is passed through the coil C. As a result, a current caused by electromagnetic induction flows through the metal part 81, and the metal part 81 generates heat due to Joule heat. This causes the NAND package 14N to be heated.

[0134] (advantage) In this embodiment, the NAND package 14N has a metal part 81 for electromagnetic induction heating that is provided on the surface of the sealing member 27 and overlaps with the memory chip 24 when viewed from the Z direction. With this configuration, the product life of the NAND package 14N can be extended by performing a heat treatment by electromagnetic induction heating using the metal part 81.

[0135] (Modification) 28 is a diagram showing a NAND package 14P according to a modification of the seventh embodiment. In this modification, the metal part 81 is provided inside the sealing member 27. For example, the metal part 81 is provided inside the sealing member 27 at a position different from the surfaces of the multiple memory chips 24.

[0136] In this modification, the sealing member 27 includes a main body portion 27a and a cover portion 27b. The metal portion 81 is provided on the surface of the main body portion 27a on the +Z direction side. The cover portion 27b is laminated on the surface of the main body portion 27a on the +Z direction side. The cover portion 27b covers the metal portion 81 from the side opposite the main body portion 27a. The cover portion 27b is a protective layer that protects the metal portion 81. Even with this configuration, the life of the NAND package 14P can be extended by performing a heat treatment by electromagnetic induction heating using the metal portion 81.

[0137] Seventh embodiment Next, a NAND package 14Q according to a seventh embodiment will be described. This embodiment differs from the sixth embodiment in that a metal part 91 for electromagnetic induction heating is stacked on the memory chip 24 inside the NAND package 14Q. Note that the configuration other than that described below is the same as that of the sixth embodiment.

[0138] FIG. 29 is a diagram showing a NAND package 14Q according to a modified example of the seventh embodiment. In this embodiment, the NAND package 14Q has a metal part 91 for electromagnetic induction heating. The metal part 91 is laminated on the uppermost memory chip 24 inside the NAND package 14Q. The metal part 91 is fixed to the uppermost memory chip 24 by, for example, an adhesive film 25. When viewed from the Z direction, the metal part 91 overlaps with at least a portion of each of the multiple memory chips 24. The thickness T4 of the metal part 91 in the Z direction is 1.0 μm or more. For example, the thickness T4 of the metal part 91 in the Z direction is several μm to several hundreds of μm. The metal part 91 is, for example, a metal plate.

[0139] Even with this configuration, by performing a heat treatment by electromagnetic induction heating using the metal part 91, the product life of the NAND package 14Q can be extended.

[0140] Some embodiments and modifications have been described above. However, the embodiments and modifications are not limited to the above-described examples. For example, the above-described embodiments and modifications may be realized in combination with each other.

[0141] In the above-described embodiment, the X direction is an example of the "second direction", and each of the first portion 33a to the fifth portion 33e of the heating wire 30 extends in the X direction. Alternatively, the Y direction may be an example of the "second direction", and each of the first portion 33a to the fifth portion 33e of the heating wire 30 may extend in the Y direction.

[0142] According to at least one of the embodiments described above, the semiconductor memory device has a non-signal wiring. The non-signal wiring is provided on one or more of the surface of the sealing member, the inside of the sealing member, the first surface of the substrate, the inside of the substrate, or the surface of the memory chip, and overlaps with the memory chip. The non-signal wiring has a first end electrically connected to the power supply unit, a second end electrically connected to the ground, and a wiring body connecting the first end and the second end. The wiring body includes a first portion, a second portion folded back from an end of the first portion, and a third portion folded back from an end of the second portion. This configuration can extend the product life of the semiconductor memory device.

[0143] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0144] 1...storage device, 14-14Q...NAND package (semiconductor memory device), 21...package substrate (substrate), 21a...first surface, 21b...second surface, 21p...power supply wiring, 21s...signal wiring, 24...memory chip, 30...heating wiring (non-signal wiring), 31...first end, 32...second end, 33...wiring body, 33a...first portion, 33b...second portion, 33c...third portion, 41...first pad, 42...second pad, 51...first electrical connection portion, 52...second electrical connection portion, 61...bonding wire (first electrical connection portion), 62...bonding wire (second electrical connection portion).

Claims

1. A semiconductor memory device, a substrate having a first surface; a sealing member that covers the first surface when viewed from a first direction that is a thickness direction of the substrate; a first memory chip disposed between the first surface and the sealing member in the first direction; a non-signal wiring different from a signal wiring of the semiconductor memory device; Equipped with the non-signal wiring is provided on one or more of a surface of the sealing member, an inside of the sealing member, the first surface of the substrate, an inside of the substrate, or a surface of the first memory chip, and overlaps the first memory chip when viewed from the first direction; the non-signal wiring has a first end electrically connected to a power supply unit, a second end electrically connected to ground, and a wiring body connecting the first end and the second end; the wiring body includes a first portion extending in a second direction intersecting the first direction, a second portion folded back from an end of the first portion to a first side in the second direction and extending parallel to the first portion, and a third portion folded back from an end of the second portion to a second side in the second direction opposite to the first side and extending parallel to the second portion, Semiconductor memory device.

2. The non-signal wiring is a wiring formed by spraying a conductive material using an inkjet method.

2. The semiconductor memory device according to claim 1.

3. the substrate has a power supply wiring through which a current flows that is supplied to the first memory chip; a thickness of the non-signal wiring in the first direction is greater than a thickness of the power supply wiring in the first direction; 3. The semiconductor memory device according to claim 1.

4. the substrate has a power supply wiring through which a current flows that is supplied to the first memory chip; The wiring width of the non-signal wiring is larger than the wiring width of the power supply wiring.

3. The semiconductor memory device according to claim 1.

5. a plurality of memory chips including the first memory chip and stacked on the substrate; the non-signal wiring is provided at a position different from the surfaces of the memory chips, on the surface of the sealing member or inside the sealing member; 3. The semiconductor memory device according to claim 1.

6. the plurality of memory chips includes a second memory chip disposed between the first memory chip and the sealing member in the first direction; the first memory chip has a first region overlapping with the second memory chip and a second region outside the second memory chip when viewed from the first direction; the non-signal wiring overlaps with the first region of the first memory chip, the second region of the first memory chip, and the second memory chip when viewed from the first direction; 6. The semiconductor memory device according to claim 5.

7. a first pad exposed to an outside of the sealing member and electrically connected to the first end; a second pad exposed to an exterior of the sealing member and electrically connected to the second end; Further equipped with 6. The semiconductor memory device according to claim 5.

8. a first electrical connection portion provided inside the sealing member and electrically connecting the first end and the substrate; a second electrical connection portion provided inside the sealing member and electrically connecting the second end and the substrate; Further equipped with 6. The semiconductor memory device according to claim 5.

9. the first electrical connection is one of a wire, a pillar, or a via; the second electrical connection being one of a wire, a pillar, or a via; 9. The semiconductor memory device according to claim 8.

10. The non-signal wiring is provided on the first surface of the substrate.

3. The semiconductor memory device according to claim 1.

11. The non-signal wiring is provided inside the substrate.

3. The semiconductor memory device according to claim 1.

12. The non-signal wiring is provided on a surface of the first memory chip.

3. The semiconductor memory device according to claim 1.

13. a second memory chip disposed between the first memory chip and the sealing member in the first direction; a first electrical connection portion electrically connecting the first end and the substrate; a second electrical connection portion electrically connecting the second end and the substrate; Further equipped with the first memory chip has a first region overlapping with the second memory chip and a second region outside the second memory chip when viewed from the first direction; the second region has a first pad electrically connected to the first end and a second pad electrically connected to the second end; the first electrical connection portion is connected to the first pad and electrically connects the first end and the substrate via the first pad; the second electrical connection portion is connected to the second pad and electrically connects the second end and the substrate via the second pad; The semiconductor memory device according to claim 12.

14. A method for heating a semiconductor memory device, comprising the steps of: The semiconductor memory device includes: a substrate having a first surface; a sealing member that covers the first surface when viewed from a first direction that is a thickness direction of the substrate; a first memory chip disposed between the first surface and the sealing member in the first direction; a non-signal wiring different from a signal wiring of the semiconductor memory device; Equipped with the non-signal wiring is provided on one or more of a surface of the sealing member, an inside of the sealing member, the first surface of the substrate, an inside of the substrate, or a surface of the first memory chip, and overlaps the first memory chip when viewed from the first direction; the non-signal wiring includes a first portion extending in a second direction intersecting the first direction, a second portion folded back from an end of the first portion to a first side in the second direction and extending parallel to the first portion, and a third portion folded back from an end of the second portion to a second side in the second direction opposite to the first side and extending parallel to the second portion, A current is passed through the non-signal wiring. A heating method for a semiconductor memory device, comprising:

15. a substrate having a first surface; a sealing member that covers the first surface when viewed from a first direction that is a thickness direction of the substrate; a first memory chip disposed between the first surface and the sealing member in the first direction; a metal portion for electromagnetic induction heating that is provided on a surface of the sealing member or inside the sealing member and overlaps with the first memory chip when viewed from the first direction; A semiconductor memory device equipped with the

16. The thickness of the metal portion in the first direction is 1.0 μm or more.

16. The semiconductor memory device according to claim 15.

17. The metal portion is provided inside the sealing member.

17. The semiconductor memory device according to claim 15.

18. A method for heating a semiconductor memory device, comprising the steps of: The semiconductor memory device includes: a substrate having a first surface; a sealing member that covers the first surface when viewed from a first direction that is a thickness direction of the substrate; a first memory chip disposed between the first surface and the sealing member in the first direction; a metal portion provided on a surface of the sealing member or inside the sealing member and overlapping the first memory chip when viewed from the first direction; Equipped with a coil is placed opposite the semiconductor memory device, and the metal portion is heated by electromagnetic induction heating; A heating method for a semiconductor memory device, comprising:

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