Solid imaging element

Abstract

To provide a solid imaging element with the degree of integration increased.SOLUTION: A pixel in a solid imaging element 10 includes a photoelectric conversion unit 21 and a counter 30 that counts pulse signals output in accordance with the amount of light incident into the photoelectric conversion unit 21. The counter 30 is divided into a lower-order bit group 31 and an upper-order bit group 32. A first aggregation circuit 40 is disposed between the lower-order bit group 31 and the upper-order bit group 32. The first aggregation circuit 40 connects the lower-order bit group and the upper-order bit group in a plurality of pixels.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a solid-state imaging device. [Background technology]

[0002] An image sensor (solid-state imaging element) receives light incident from a subject, photoelectrically converts the received light, and generates an electrical signal. In recent years, a technology has been used in which the photoelectrically converted analog signal is A / D (analog / digital) converted within the image sensor and output as digital data (for example, Patent Document 1). In Patent Document 1, a 1-bit A / D conversion circuit is provided for each pixel, and a counter counts a pulse signal that is output according to the amount of light incident on the photoelectric conversion section, thereby significantly improving the dynamic range of the image sensor without limiting the amount of light that can be input by the storage capacity of the photoelectric conversion section.

[0003] As a new technology, single-photon avalanche diodes (SPADs) are used (see, for example, Patent Document 2). In SPADs, the number of incident photons during a certain period of time is output as a count, so the output of the photoelectric conversion element itself can be handled as a digital signal.

[0004] In addition, in the image sensor of Patent Document 1, when a 16-bit counter circuit for each pixel is arranged in a planar array, the area of ​​the counter circuit is large, so that the pixel cannot be made small and high resolution cannot be achieved. In response to this problem, a technology has been proposed in which the photoelectric conversion unit of the pixel and the counter circuit are arranged on different layers in a three-dimensional integrated circuit, and the counter circuits are arranged on multiple layers to achieve high density. In this case, the technology disclosed in Patent Document 1 is configured so that the counter signal is transmitted between the counter circuits arranged on multiple layers using a common signal line (74) and output pad (75) in order to achieve higher density by reducing the number of through electrodes for transmitting counter signals between multiple layers. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2018-019276 A [Patent Document 2] JP 2023-066374 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the image sensor disclosed in Patent Document 1, a selection switch consisting of a horizontal scanning line (71) connected to the counters of the counter array and a vertical signal line (72) sequentially selects counters using a common signal line (74) and output pad (75). Therefore, when increasing the number of pixels to achieve high resolution, in order to maintain the same frame rate (shooting cycle), the selection switch must be switched at a higher speed, which places a limit on how high the resolution can be achieved. In addition, there is a problem that the charging and discharging power in the shared wiring becomes large, making it difficult to reduce power consumption.

[0007] The present invention has been made in view of the above circumstances, and has an object to provide a solid-state imaging device with an increased integration density. [Means for solving the problem]

[0008] The above object of the present invention can be achieved by the following means.

[0009] A solid-state imaging element comprising a plurality of pixels and a first aggregation circuit, wherein the pixels comprise a photoelectric conversion unit and a counter that counts a pulse signal output in accordance with the amount of light incident on the photoelectric conversion unit, the counter is divided into a lower bit group and an upper bit group, the first aggregation circuit is disposed between the lower bit group and the upper bit group, and the first aggregation circuit connects the lower bit group and the upper bit group of the plurality of pixels. Effect of the Invention

[0010] The solid-state imaging device according to the present invention includes a counter that counts pulse signals output according to the amount of light incident on a photoelectric conversion unit, the counter being divided into a lower bit group and an upper bit group, the first aggregation circuit being disposed between the lower bit group and the upper bit group, and the first aggregation circuit connecting the lower bit group and the upper bit group of a plurality of pixels. This allows circuit wiring to be consolidated, achieving high integration. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a schematic configuration of a solid-state imaging element according to a first embodiment. [Diagram 2] 1 is a block diagram showing an example of the configuration of a pixel in a solid-state imaging element; [Figure 3A] FIG. 2 is a top view showing a layered structure of the solid-state imaging element. [Figure 3B] FIG. 2 is a side view showing a layered structure of the solid-state imaging element. [Figure 3C] FIG. 2 is a perspective view showing a layered structure of a solid-state imaging element. [Figure 4] FIG. 2 is a schematic diagram showing the arrangement of each layer and the interlayer connections. [Diagram 5] FIG. 2 is a schematic diagram showing the circuitry of each layer. [Figure 6] 11 is a timing chart showing time-division signal processing in an interlayer connection section. [Figure 7] FIG. 13 is a schematic diagram showing the circuitry of each layer in the first modified example. [Figure 8] FIG. 11 is a schematic configuration diagram showing the circuits of each layer in Modification 2. [Figure 9] FIG. 11 is a schematic diagram showing an interlayer connection configuration of each layer in Modification 2. [Figure 10] FIG. 11 is a schematic configuration diagram showing circuits of each layer of a solid-state imaging element according to a second embodiment. [Figure 11] 11 is a timing chart showing time-division signal processing in an interlayer connection section. [Figure 12]FIG. 11 is a schematic configuration diagram showing circuits and interlayer connections of each layer of a solid-state imaging element according to a third embodiment. [Figure 13] FIG. 13 is a schematic configuration diagram showing circuits and interlayer connections in each layer according to a fourth embodiment. [Figure 14] FIG. 13 is a schematic configuration diagram showing circuits and interlayer connections of each layer of a solid-state imaging element according to a fifth embodiment. [Figure 15] FIG. 13 is a schematic configuration diagram showing circuits and interlayer connections in each layer in a sixth embodiment. [Figure 16] FIG. 13 is a schematic configuration diagram showing circuits and interlayer connections in each layer in a seventh embodiment. [Figure 17] FIG. 23 is a schematic configuration diagram showing circuits and interlayer connections in each layer according to the eighth embodiment. [Figure 18] FIG. 13 is a schematic configuration diagram showing circuits and interlayer connections in each layer according to a ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings. However, the scope of the present invention is not limited to the disclosed embodiment. In the description of the drawings, the same elements are given the same reference numerals, and duplicated description will be omitted. In addition, the dimensional ratios of the drawings are exaggerated for convenience of explanation, and may differ from the actual ratios. In the following, in a plane perpendicular to the incident direction of light of the solid-state imaging element, a predetermined first direction is referred to as a lateral direction, row direction, horizontal direction, or X direction, and a second direction perpendicular to this first direction is referred to as a longitudinal direction, column direction, vertical direction, or Y direction. In addition, the arrangement position of the circuit element in this XY plane in a planar view (for example, FIG. 3A, etc.) is also referred to as an XY coordinate position.

[0013] (First embodiment) Hereinafter, a solid-state imaging element 10 according to a first embodiment will be described with reference to Fig. 1 to Fig. 9. Fig. 1 is a block diagram showing a schematic configuration of the solid-state imaging element 10 according to the first embodiment. Fig. 2 is a block diagram showing an example of the configuration of a pixel 20.

[0014] 1, the solid-state imaging device 10 includes a pixel array 110, a vertical scanning section 130, a horizontal scanning section 140, and a signal output section 150. The pixel array 110 includes a plurality of pixels 20 arranged in an array in row and column directions (M×N pixels). The pixel array 110 includes all of the pixels 20 of the solid-state imaging device 10 (for example, several million or more pixels 20). Meanwhile, a pixel unit, which will be described later, includes several to several tens of pixels 20 (in the example of FIG. 3A etc., four pixels 30 are included).

[0015] A synchronization signal is input to each of the vertical scanning section 130 and the horizontal scanning section 140, and an exposure control signal is input to the pixel array 110.

[0016] The vertical scanning unit 130 selects rows (Y) in sequence, and the horizontal scanning unit 140 selects columns (X) in sequence, thereby selecting each pixel 20 in sequence using an XY addressing method, and the pixel signals (count signals) of the selected pixels 20 are output via signal lines to the signal output unit 150. The signal output unit 150 collects the pixel signals of each pixel output to the signal lines and outputs them as image data to an external recording unit or signal processing unit.

[0017] (Pixel 20) 2, each pixel 20 is composed of a photoelectric conversion unit 21 and a signal processing unit 25. Moreover, each pixel 20 is connected to interlayer connectors (40, 50, 60) of the solid-state imaging element 10. The interlayer connectors will be described later (FIGS. 3A to 3C, etc.).

[0018] (Photoelectric conversion unit 21) The photoelectric conversion unit 21 includes a photodiode (also called a photoelectric conversion element) 211, a quench element 212, and a waveform shaping element 213. The photoelectric conversion unit 21 outputs a pulse signal according to the amount of incident light. The photoelectric conversion unit 21 may be of a SPAD type. For example, the photodiode 211 uses a single-photon avalanche diode (hereinafter referred to as a SPAD) that counts the number of photons incident on the incident surface. The SPAD is a next-generation semiconductor optical element that is extremely efficient enough to detect a single photon due to the extremely high gain characteristics of the element. When a voltage higher than the breakdown voltage of the element is applied to the SPAD, a very large electric field accelerates free electrons (carriers) and causes strong collisions with atoms, which causes electrons bound to atoms to be released, and the number of free electrons increases rapidly, causing an impact ionization phenomenon. This effect is called avalanche multiplication, and it significantly increases the number of free electrons generated by a photon irradiated onto the image sensor from the outside.

[0019] The quench element 212 is composed of a cathode resistance element of the photodiode 211 or a MOS transistor. One side of the quench element 212 is connected to the cathode of the photodiode, and the other side is connected to a voltage Vh higher than the ground voltage (Vl) connected to the anode of the photodiode 211. Every time a photocurrent is output from the photodiode 211 due to the incidence of a photon, the photocurrent flows through the quench element 212, and the cathode potential of the photodiode 211 drops to a value lower than the voltage Vh.

[0020] The waveform shaping element 213 is composed of an inverter and has a pulse generating function of converting the output of the photodiode 211 into a pulse signal. When the voltage of the cathode of the photodiode 211 decreases due to the photocurrent and the output signal (also called the optical signal output) input to the waveform shaping element 213 reaches an inversion threshold voltage, the output of the waveform shaping element 213 is inverted and a high pulse signal is output.

[0021] The photoelectric conversion element used in the photoelectric conversion unit 21 is not limited to a SPAD, and a normal photodiode may also be used. In the case of a normal photodiode, electrons generated by photoelectric conversion are accumulated in the photodiode 211, causing the voltage of the cathode of the photodiode 211 to drop, and a pulse signal is output from the waveform shaping element 213 accordingly. In addition, while Fig. 2 shows an example in which each element (the quench element 212 and the waveform shaping element 213) is connected to the cathode of the photodiode 211, the anode of the photodiode 211 may be configured to be connected to each element.

[0022] (Signal processing unit 25) The signal processing unit 25 includes a counter 30. The solid-state imaging device 10 has a layered structure, and the signal processing unit 25 is disposed across a plurality of layers.

[0023] (lower bit group 31, higher bit group 32) The counter 30 of one pixel 20 is composed of several bits to a dozen bits, and is divided into a plurality of parts with a predetermined number of digits. The counter 30 is, for example, 12 bits in total, and is divided into a counter of a lower bit group 31 of 1 to 4 bits (hereinafter simply referred to as the lower bit group 31) and a counter of an upper bit group 32 of 5 to 12 bits (hereinafter simply referred to as the upper bit group 32). The lower bit group 31 is arranged in the same layer as other components (212, 213) other than the photodiode 211 of the photoelectric conversion unit 21 (first embodiment, etc.), or the lower bit group 31 is arranged in a layer immediately below the other components (212, 213) (for example, modified examples 1 and 2 described later). The lower bit group 31 is composed of consecutive bits including at least the lowest bit, and one lower bit group 31 is arranged in one layer. The upper bit group 32 is a bit other than the lower bit group 31, and may be arranged in one layer or across multiple layers (Modification 2 in FIG. 8 described later). The layer in which the lower bit group 31 is arranged is also referred to as the first layer (lower bit layer), and the layer in which the upper bit group 32 is arranged is also referred to as the second layer (upper bit layer). The first layer is one layer (for example, the L2 layer), while the second layer is one or multiple layers (for example, the L3 layer, the L4 layer).

[0024] For example, the lower bit group 31 for all pixels 20 (e.g., four pixels) belonging to the pixel unit is arranged in one layer (L2 layer (first layer)), but the upper bit group 32 is distributed and arranged in at least two or more layers. For example, the upper bit groups 32 for the four pixels 20 belonging to the pixel unit may be distributed and arranged two by two in two layers (L3 and L4 layers (second layer)), or may be distributed and arranged one by one in separate layers (L3 to L6 layers (second layer)).

[0025] Although details will be described later, at least the lower bit group 31 and the upper bit group 32 are arranged in different layers, and the layer (L2 layer) of the lower bit group 31 and the layer (L3 layer, etc.) of the upper bit group 32 are connected by interlayer connectors (40, 50, 60). Although a specific configuration will be described later, the interlayer connector is composed of an aggregation circuit 40 (also referred to as a first aggregation circuit), a through electrode 60, and a distribution circuit 50. The lower bit group 31 and the upper bit group 32 in the same pixel 20 are connected by the aggregation circuit 40 (first aggregation circuit). In addition, one aggregation circuit 40 is shared by multiple pixels of the same pixel unit, and connects the lower bit group 31 and the upper bit group 32 of the multiple pixels. In addition, one interlayer connector is shared by multiple pixels 20 (hereinafter referred to as a pixel unit). For example, a pixel unit is composed of multiple adjacent or nearby pixels 20. For example, as shown in Fig. 1, pixel units 1 to i are formed by four pixels 20 adjacent vertically and horizontally, and the pixels 20 belonging to each pixel unit share one interlayer connection section, and the lower bit group and the upper bit group of each of the multiple pixels are connected by this one interlayer connection section. Each bit of the counter 30 is connected to a signal line, and is read out by the operation of a switch element. In Fig. 2, the signal lines and switch elements are not shown.

[0026] (Interlayer connection) Hereinafter, the configuration of each layer including the interlayer connectors and signal transmission at the interlayer connectors will be described with reference to FIGS. 3A to 6.

[0027] 3A to 3C are diagrams showing the layered structure of the solid-state imaging element 10. FIG. 3A is a top view, FIG. 3B is a side view, and FIG. 3C is a perspective view. In the drawings, the holes (vias) of the through electrodes 60 are shown in different forms for ease of viewing, i.e., painted white in FIG. 3A and FIG. 3B and painted black in FIG. 3C, but they are the same. Also, in FIG. 3A to FIG. 3C, only the layered structure of one pixel unit is shown, and the other pixel units arranged in an array are omitted (the same applies to FIG. 4, FIG. 5, FIG. 7 to FIG. 10, etc. described later), but in reality, components of many pixel units 1 to i are arranged in one layer.

[0028] In the solid-state imaging device 10 according to the first embodiment, the pixel 20 has a four-layer structure of L1 to L4 layers. As described below, in the first embodiment, the lower bit group 31 is formed in the L2 layer (also referred to as the first layer), and the upper bit group is formed in the L3 layer and the L4 layer (hereinafter, these L3 and L4 layers are collectively referred to as the second layer) different from the L2 layer.

[0029] As shown in Fig. 3A etc., the upper surface of the top L1 layer is the light incidence surface. As shown in Fig. 3A, four photodiodes 211 corresponding to the first to fourth pixels 20 (hereinafter, the individual pixels will be referred to as pixels 0 to 3 etc., and will be collectively referred to as pixels 20) are arranged in the top L1 layer.

[0030] In the L2 layer next to the L1 layer, the quench element 212 and the waveform shaping element 213 of each of the four pixels 20, and the lower bit group 31 are arranged. The photodiode 211 of the L1 layer and the quench element 212 and the waveform shaping element 213 of the L2 layer in the same pixel 20 are CtoC-connected (Cu to Cu-connected) by a CtoC-type interlayer connection part 219 at the same position of the XY coordinate. The interlayer connection part 219 is not shared, but is provided for each of the multiple pixels 20. More specifically, for example, when a back-illuminated CMOS image sensor is applied as the photodiode 211, the wiring layer of the photodiode 211 (the lower surface side (opposite side to the incident surface) in the case of a back-illuminated type) is located below the L1 layer. The wiring layer of the L1 layer and the wiring layer (upper surface side) of the L2 layer are CtoC-connected.

[0031] Furthermore, the four lower bit groups 31 corresponding to the four pixels 20 belonging to one pixel unit are connected to one aggregation circuit 40. The aggregation circuit 40 is connected to distribution circuits 50 in the lower layers L3 and L4 by hole-type interlayer connectors 60 (hereinafter also referred to as through electrodes 60).

[0032] Fig. 4 is a schematic diagram showing the arrangement of each layer and the interlayer connections. Fig. 5 is a schematic diagram showing the circuit of each layer. Figs. 4 and 5 show the solid-state imaging device 10 according to the first embodiment, which is the same as the example shown in Figs. 3A to 3C, in a different representation.

[0033] 4 and 5, a photodiode 211 is arranged in the L1 layer. A quench element 212, a waveform shaping element 213, a lower bit group 31, and an aggregation circuit 40 are arranged in the L2 layer. The 4-bit counter of the lower bit group 31 is a ripple counter in which four flip-flops are connected. In the same pixel 20, the photodiode 211 in the L1 layer and the quench element 212 and waveform shaping element 213 in the L2 layer immediately below it are connected by a CtoC type interlayer connector 219.

[0034] (Time division switching function by aggregation circuit 40 and distribution circuit 50) One aggregation circuit 40 is provided for one pixel unit, and count signals of the lower bit group 31 of the multiple pixels 20 belonging to the pixel unit are input to this aggregation circuit 40. Fig. 6 is a timing chart showing time-division signal processing in the interlayer connection section. Fig. 6 shows a control signal (G_LAT_L2 pixels 0-3) to the aggregation circuit 40 and a counter signal flowing through the output side (symbol A in Fig. 5) of the aggregation circuit 40 corresponding to the control signal (both are surrounded by dashed lines in Fig. 5).

[0035] A plurality of pixels constituting one pixel unit share one Through Electrode 60 as a transmission path for the counter signal. The aggregation circuit 40 and distribution circuit 50 have a time-division switching function that allocates the use of one Through Electrode 60 in a time-division manner. The aggregation circuit 40 combines the counter signals input from the lower bit groups 31 of the four pixels and transmits them to the Through Electrode 60. The distribution circuit 50 on the output side identifies these according to the timing of each counter signal, decodes them into the original counter signal for each pixel, and transmits them to the respective upper bit groups 32.

[0036] Specifically, the aggregation circuit 40 performs a logical AND operation between a control signal having a predetermined period with a timing shift corresponding to the four input lower bit groups 31 and the count signal of the lower bit group 31, thereby switching the count signal to be output to the output side (A) of the aggregation circuit 40 in a time-division manner. The distribution circuit 50 transmits the counter signal decoded at a timing according to the time slot to the connected upper bit group 32.

[0037] The predetermined period for switching the four pixels 20 once is set as follows. Each photoelectric conversion unit 21 outputs a pulse signal with a period (interval) according to the amount of incident light. The period becomes shorter as the amount of light increases, but is divided by the number of counter bits of the lower bit group 31. For example, if the lower bit group 31 is 4 bits, the frequency is divided by 1 / 16 (the period becomes 16 times). The period of the control signal to the aggregation circuit 40 is set to a period equal to or less than 1 / 2 of the period after the frequency of the pulse signal from the photoelectric conversion unit 21 is divided. In this example, since the period is 16 times, a sufficient period can be secured for transmitting the counter signal for four pixels in a time-division manner from the lower bit group 31 to the upper bit group 32.

[0038] 4 and 5 are referred to again. A through electrode 60 is formed in each pixel unit from the L2 layer to the L4 layer. A distribution circuit 50 and a high-order bit group 32 are also arranged in the L3 layer. A distribution circuit 50 and a high-order bit group 32 are also arranged in the L4 layer. The distribution circuit 50 transmits a counter signal via the through electrode 60 to the high-order bit group 32 in the L3 layer, which is a counter for approximately half of the pixels 20 belonging to the pixel unit, and the high-order bit group 32 in the L4 layer, which is a counter for the remaining pixels 20. Each high-order bit group 32 is, for example, an 8-bit counter, which is a ripple counter in which eight flip-flops are connected. For example, the high-order bit group 32 for pixel 0 and pixel 1 of the four pixels 20 (pixels 0 to 3) belonging to one pixel unit is arranged in the L3 layer, and the high-order bit group 32 for the remaining pixels 2 and 3 is arranged in the L4 layer. 4, 5, etc., only the stacked structure of one pixel unit is illustrated, and the other pixel units arranged in an array are omitted (similarly to FIGS. 4 to 6, etc.), but in reality, components of many pixel units 1 to i are arranged on one layer. For example, in addition to pixels 0 and 1, the L3 layer is arranged with the upper bit group 32 of pixels 4, 5, 8, and 9, and a distribution circuit 50.

[0039] The distribution circuits 50 in the L3 and L4 layers have the through electrodes 60 connected to their input sides, and the upper bit groups 32 of the pixels 20 connected to their output sides. A control signal substantially synchronized with the control signal shown in FIG. 6 is input to the two distribution circuits 50 in the L3 and L4 layers, and the distribution destination of the counter signal is switched to one of the upper bit groups 32 of pixels 0 to 3 by the control signal. This allows the transmission of the counter signal between the lower bit group 31 and the upper bit group 32 of the same pixel 20. That is, the distribution circuit 50 distributes the counter signal from the lower bit group 31 through the through electrodes 60 to the corresponding upper bit group 32. For example, during a period in which the counter signal of the lower bit group 31 of pixel 0 flows through the through electrodes 60 due to the output from the aggregation circuit 40, the distribution circuit 50 in the L3 layer sets the distribution and transmission destination to the upper bit group 32 of pixel 0. During this period, the distribution circuit 50 in the L4 layer does not transmit the counter signal to any of the upper bit groups 32. Similarly, during the period when the counter signal of the lower bit group 31 of the pixel 3 flows through the through electrode 60, the distribution circuit 50 of the L4 layer sets the distribution and transmission destination to the upper bit group 32 of the pixel 3. In this manner, the aggregation circuit 40 of the interlayer connection section, the through electrode 60, and the distribution circuit 50 cooperate to control the connection timing, thereby transmitting the counter signal of the lower bit group 31 of each pixel 20 to the upper bit group 32.

[0040] In addition, since the circuit components arranged in the L3 layer and the L4 layer and their arrangement positions in the XY coordinates are the same as those in the L3 layer and the L4 layer as described above, when manufacturing the solid-state imaging device 10, the L3 layer and the L4 layer can be formed using a common mask or a mask with a small change scale can be used, which leads to cost reduction.

[0041] In this way, only the photodiodes 211 are arranged in the L1 layer. This allows the area of ​​each photodiode 211 to be increased, or the photodiodes 211 can be arranged at a higher density even if they have the same area. In addition, the remaining components of the photoelectric conversion unit 21 (quench element 212, waveform shaping element 213) have a low degree of freedom in the arrangement of XY coordinates because analog signals flow and because of CtoC connection. Therefore, it is desirable that the arrangement of the XY coordinates of the quench element 212 and waveform shaping element 213 in the L2 layer be an array arrangement that matches the array arrangement of the photodiodes 211 in the L1 layer. On the other hand, the arrangement of each element of the signal processing unit 25 through which digital signals flow can be arranged relatively freely. For example, the signal processing unit 25 through which digital signals flow may be arranged in other layers (L3 layer, L4 layer) instead of being arranged in the layer (L2 layer) directly below the photodiode 211. For example, the lower bit group 31 of the signal processing unit 25 may be arranged in an L3 layer separate from the L2 layer in which the photoelectric conversion unit 21 (the quench element 212 and the waveform shaping element 213) are arranged. In this case, the element of the L2 layer (the downstream node of the waveform shaping element 213) and the lower bit group 31 of the L3 layer in the same pixel 20 are connected by through electrodes formed by penetrating the silicon substrate.

[0042] The number of bits (number of flip-flops) of the lower bit group 31 arranged in the L2 layer is preferably as large as possible in terms of lengthening the switching period in the time division switching function, but is restricted by the size of the pixel unit. Therefore, in the first embodiment, the number of bits of the counter of the lower bit group 31 arranged in the same L2 layer as the components of the photoelectric conversion unit 21 (quench element 212, waveform shaping element 213) is set to four.

[0043] In the first embodiment, the number of bits (number of flip-flops) arranged in the L2 layer, L3 layer, and L4 layer is 4 / 8 / 8, but is not limited to this and may be set to any number of bits. For example, the number of bits arranged in the L2 layer, L3 layer, and L4 layer may be 4 / 4 / 4, 4 / 12 / 12, etc. As another example, the number of bits in the L2 layer is not limited to 4 and may be another number, and the number of bits in the L3 layer and the L4 layer does not have to be the same.

[0044] In the first embodiment, the counters of the same pixel are not divided and arranged for the L3 layer and the L4 layer, that is, the bit group of 5 to 8 bits is distributed and arranged for the L3 layer and the bit group of 9 to 12 bits is not distributed and arranged for the L4 layer (hereinafter referred to as the comparative example), but are divided by pixel. That is, the L3 layer is arranged with the upper bit group of 5 to 12 bits of two pixels (pixels 0 and 1) out of the four pixels belonging to the pixel unit, and the L4 layer is arranged with the upper bit group of 5 to 12 bits of the remaining two pixels (pixels 2 and 3). In the above comparative example, the counter signal must be transmitted across layers twice in a chain shape from the L2 layer, the L3 layer, and the L4 layer. In contrast, in the first embodiment, the transmission across layers is only required once, such as between the L2 layer and the L3 layer or between the L2 layer and the L4 layer.

[0045] Also, as described above, when the number of pixels constituting one pixel unit is an even number, and the L3 layer and the L4 layer are equally divided as in the first embodiment, the L3 layer and the L4 layer can be made to have the same configuration. Therefore, since it is possible to manufacture using a common mask, it is possible to reduce costs and shorten the manufacturing preparation period. Also, when the number of pixels constituting one pixel unit is an odd number of 9, the L3 to L5 layers can be divided into groups of three pixels and arranged in the L3 to L5 layers, so that the L3 to L5 layers can have the same configuration. As another example, the number of pixels constituting one pixel unit does not have to be divisible by the number of layers to be distributed. In this case, it is dealt with by providing a redundant portion. For example, even if the number of pixels constituting a pixel unit is 16 and distributed to three layers L3 to L5, it is manufactured using a common mask with a redundant portion. Specifically, out of the 16, the upper bit groups of pixels 0 to 5, pixels 6 to 11, and pixels 12 to 15 are arranged in the L3 to L5 layers, respectively. In this case, in the L5 layer, the upper bit group of two pixels becomes an unused area (redundant wasted area), but in terms of mask costs and manufacturing costs, this may be advantageous overall.

[0046] In the first embodiment, the solid-state imaging device 10 has one pixel unit composed of four pixels 20, and the four pixels 20 belonging to this pixel unit share one set of interlayer connectors (40, 50, 60). However, the number of pixels 20 sharing an interlayer connector is not limited to four, and may be two or three (corresponding to the following modification 1), or five or more. In addition, the pixels constituting the pixel unit are preferably adjacent pixels 20, but are not limited thereto, and may be composed of a plurality of pixels 20 spaced apart (for example, every other pixel).

[0047] (Variation 1) Next, referring to FIG. 7, a solid-state imaging device 10b according to Modification 1 will be described. FIG. 7 is a schematic diagram showing the circuitry of each layer in Modification 1. The solid-state imaging device 10b according to Modification 1 described below is an example in which one pixel unit is composed of three pixels, and one set of interlayer connectors (40, 50, 60) is shared within the pixel unit. In addition, compared with the first embodiment in which both the photoelectric conversion unit 21 and the signal processing unit 25 are arranged in the L2 layer in the first embodiment, in Modification 1 shown in FIG. 7, the quench element 212 of the photoelectric conversion unit 21, the waveform shaping element 213, the lower bit group 31 of the signal processing unit 25, and the aggregation circuit 40 are arranged in the L2 layer. The aggregation circuit 40 in the L2 layer is connected to the through electrode 60 that penetrates from the L2 layer to the L5 layer, and is connected to the upper bit group 32 on the layer by the distribution circuit 50 of each layer.

[0048] In the L2 layer, a lower bit group 31 of 1 to 4 bits of three pixels 0 to 2 is arranged.

[0049] An upper bit group 32 of 5 to 16 bits for pixel 0 is arranged in the L3 layer. An upper bit group 32 of 5 to 16 bits for pixel 1 is arranged in the L4 layer. An upper bit group 32 of 5 to 16 bits for pixel 2 is arranged in the L5 layer. Similarly, in the first modification, a counter signal from the lower bit group 31 in the L2 layer is transmitted to the corresponding upper bit groups 32 in the L3 to L5 layers by the time division switching function of the aggregation circuit 40 and the distribution circuit 50.

[0050] (Variation 2) Next, a solid-state imaging device 10c according to Modification 2 will be described with reference to FIG. 8 and FIG. 9. FIG. 8 is a schematic diagram showing the circuit of each layer in Modification 2, and FIG. 9 is a schematic diagram showing the interlayer connection configuration of each layer. FIG. 9 is a side view. In FIG. 9, flip-flops constituting each bit (5 to 16) of the counter 30 below the L3 layer are shown together with the bit number. For example, in FIG. 9, FF-05 indicates the counter element of the 5th bit. In the solid-state imaging devices 10 and 10b according to the first embodiment and Modification 1, one through electrode 60 penetrating multiple layers is used as an interlayer connection part, but the solid-state imaging device 10c according to Modification 2 described below uses multiple through electrodes 601 to 603 penetrating only between adjacent layers. In Modification 2, one pixel unit is composed of three pixels, which is the same as Modification 1, but this is not limited thereto, and it may be composed of two or four or more pixels. In addition, in the second modification, the counter of one pixel 20 is configured with 16 bits, which is divided into one lower bit group 31 and three upper bit groups 32, each of which has four bits, and these are arranged in four layers (layers L2 to L5). However, the number of bits to be arranged in each layer can be set to any number, without being limited to the embodiment shown in FIG. 8 and FIG. 9. Similarly, in the second modification, the counter signals between adjacent layers are sent to the bit groups of the corresponding counters by the time division switching function of the aggregation circuit 40 and the distribution circuit 50. For example, in the case of the L2 layer and the L3 layer, the counter signals of the corresponding lower bit groups 31 of the same pixel 20 are transmitted to the upper bit group (5 to 8 bits) by the aggregation circuit 40 and the distribution circuit 50 via the through electrode 601.

[0051] In the second modification, by adopting such a configuration, the number of through electrodes 601 to 603 in each layer can be made smaller than the number of pixels 20. That is, it can be made one-third. In addition, the XY coordinate positions of the electrodes for interlayer connection (the through electrodes 601 to 603 and the interlayer connection portion 219) can be made the same in the L2 to L5 layers. Furthermore, the number of counter elements (flip-flops) to be arranged in the L2 to L5 layers can be made the same and arranged in the same XY coordinate positions. Thus, in the second modification, the components of the circuit to be arranged in the L2 to L5 layers and their arrangement positions in the XY coordinates are the same. Therefore, in manufacturing the solid-state imaging device 10, the L2 to L5 layers can be formed using a common mask, which can reduce costs and shorten the manufacturing preparation period.

[0052] Second Embodiment Next, a solid-state imaging device 10d according to a second embodiment will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a schematic diagram showing the circuits of each layer, and Fig. 11 is a timing chart showing time-division signal processing in the interlayer connection section. In the solid-state imaging device 10d according to the second embodiment shown in Fig. 10, a distribution circuit 71 is added to the L2 layer, and an aggregation circuit 70 is added to each of the L3 and L4 layers, compared to the solid-state imaging device 10 according to the first embodiment shown in Fig. 5.

[0053] The solid-state imaging device 10d according to the second embodiment has a function of sending an event signal related to a specific event occurring in the upper bit group 32 from the second layer (such as L3 or L4 layer) to the first layer (L2 layer) via an electrode for interlayer connection (through electrode 60). The function of sending this event signal from the lower layer to the upper layer by a time division function is realized by an aggregation circuit 70 and a distribution circuit 71, which are added as described below.

[0054] For example, the event signal is related to an event in which a counter carryover of the most significant bit group 32 occurs due to too much light being incident on the photodiode 211 .

[0055] When a specific event occurs, the upper bit group 32 generates an event signal and sends the signal to the aggregation circuit 70 in the same layer. The aggregation circuit 70 aggregates signals from two pixels in the same layer. For example, the aggregation circuit 70 in the L3 layer aggregates the event signals from pixels 0 and 1 and transmits them to the distribution circuit 71 in the L2 layer via the through electrode 60. The distribution circuit 71 then sends the signal to one of the pixels corresponding to the source pixel. The pixel that receives the signal performs processing according to the event signal. For example, if the event signal is a counter carryover, the photodiode stops receiving light. This processing stops light reception (exposure) even during the exposure period, for example, by performing a logical OR between the exposure control signal and the event signal.

[0056] (Time division switching function by aggregation circuit 70 and distribution circuit 71) As shown in FIG. 10, two aggregation circuits 70 corresponding to the number of layers (L3 and L4 layers) in which the upper bit groups 32 are arranged are provided in one pixel unit. The event signals of the upper bit groups 32 of each of the multiple pixels 20 in each layer are input to the aggregation circuits 70. FIG. 11 shows control signals (G_LAT_L2pix0-3) to the aggregation circuits 70 and the distribution circuits 71, as well as control signals (G_L2-L3_IO) to the gates upstream of the aggregation circuits 70 and the gates downstream of the distribution circuits 71 (all surrounded by dashed lines in FIG. 11), and counter signals and event signals flowing through the paths (symbol B in FIG. 11) of the aggregation circuits 70 and the distribution circuits 71 accordingly. The counter signals are transmitted from the upper layers to the lower layers (hereinafter referred to as the forward direction), and the event signals are transmitted from the lower layers to the upper layers (hereinafter referred to as the reverse direction).

[0057] The aggregation circuit 70 and the distribution circuit 71 have a time division switching function. In Fig. 11, the time division function for the counter signal flowing in the forward direction is the same as that in Fig. 6, and therefore a description thereof will be omitted. In the embodiment shown in Fig. 10 and Fig. 11, in order to switch the signal flowing through one through electrode 60 in a time division manner, a time slot for the event signal as well as the counter signal is reserved in advance.

[0058] In a predetermined cycle in which the switching of the four pixels 20 goes around once, in the first half, the counter signals of pixels 0 to 3 flow in the forward direction from the L2 layer to the L3 or L4 layer in sequence. In the second half of the predetermined cycle, the event signals of pixels 0 and 1 flow in the reverse direction from the L3 layer to the L2 layer, and then the event signals of pixels 2 and 3 flow in the reverse direction from the L4 layer to the L2 layer in sequence. In this way, when sharing one through electrode 60, the aggregation circuit 70 and the distribution circuit 71 switch the direction and transmission path of the signal flow of the through electrode 60 in a time-division manner.

[0059] As a modified example, signal transmission between the L3 layer and the L4 layer may be possible. For example, in Fig. 11, a time slot for transmitting a signal from the L3 layer to the L4 layer (or vice versa) is assigned, and the signal is transmitted from the aggregation circuit 70 in the L3 layer to the distribution circuit 50 in the L4 layer through the through electrode 60. As shown in the second embodiment, the transmission direction of the signal flowing through the through electrode 60 is not limited to the forward direction and may be the reverse direction due to the time division switching function.

[0060] (Binning mode) Next, the binning mode process will be described with reference to FIGS.

[0061] (Third and fourth embodiments) 12 and 13 are schematic diagrams showing the circuits and interlayer connections of the layers of the solid-state imaging devices 10e and 10f according to the third and fourth embodiments, respectively. In the third and fourth embodiments, in the binning mode, the aggregation circuit 40 adds or averages the counter signals of the lower bit group 31 of multiple pixels belonging to one pixel unit, and transmits the result as data for one pixel to the upper bit group 32. In addition, in the normal mode other than the binning mode, the aggregation circuit 40 and the like operate as shown in the first embodiment. That is, compared to the binning mode in which the counter signals of multiple pixels are added or averaged and output, in the normal mode, the counter signal for each pixel is output.

[0062] In the third embodiment shown in FIG. 12, in the binning mode, the solid-state imaging device 10e adds or averages the counter signals of the lower bit groups 31 of four adjacent pixels 20 arranged vertically and horizontally in a 2×2 matrix, and transmits the sum to the upper bit group 32 of the L3 layer through the through-electrode 60. In addition, in the binning mode, only the upper bit group 32 for pixel 0 of the L3 layer is enabled. The upper bit groups for the other pixels 1 to 3 are disabled and not used. By disabling the upper bit groups, the signal information required for transmission to these circuits can be reduced, thereby reducing the power consumption of the circuits at the subsequent stages. In addition, when the solid-state imaging device 10e is configured to be dedicated to the binning mode, these circuits at the subsequent stages may be eliminated.

[0063] In the fourth embodiment shown in Fig. 13, all the counters for four pixels are used as a counter for one pixel. That is, four 8-bit counters for the upper bit group 32 are concatenated and used as one 32-bit counter for the upper bit group 32, which is combined with the 4-bit counter for the lower bit group 31 to form a total of 36-bit counter. For example, the upper bit groups for pixels 0, 1, 2, and 3 are concatenated in this order.

[0064] In the binning mode, the solid-state imaging element 10e adds the lower bit groups 31 of the four pixels 20 and transmits the sum to the upper bit group 32 for pixel 0 in the L3 layer through the through electrode 60. Thereafter, each time a counter signal is input, the counter signal is transmitted to the downstream upper bit group 32. In this case, the through electrode 60 includes a counter signal flowing from the L2 layer to the L3 layer and a counter signal flowing from the L3 layer to the L4 layer. The multiple counter signals flowing through these through electrodes 60 are switched by a time-division switching function of the aggregation circuit 40 and the distribution circuit 50.

[0065] In the fourth embodiment, the four most significant bit groups 32 in the latter stage are connected (in series) to be used, and together with the least significant bit group 31, a 36-bit counter can be realized, so that the dynamic range can be expanded. Note that the number of bits of the counter to be used and the layer to be used may be freely changeable. For example, by connecting only the two most significant bit groups 32 in the L3 layer, it can function as a 16-bit counter.

[0066] In this way, in the solid-state imaging elements 10d and 10e according to the third and fourth embodiments, by executing the binning mode, data for four pixels belonging to one pixel unit is treated as extended data for one pixel without reducing the pixel information, and therefore the pixel resolution is reduced to one-quarter, but the light receiving area per pixel is four times larger, resulting in higher sensitivity and enabling imaging even in dark environments with low light levels.

[0067] (Fifth and Sixth Embodiments) 14 and 15 are schematic diagrams showing the circuits and interlayer connections of the layers of the solid-state imaging devices 10g and 10h according to the fifth and sixth embodiments, respectively. In the third and fourth embodiments, the binning process is performed in the signal processing unit 25 through which the digital signals flow. However, in the solid-state imaging devices 10g and 10h according to the fifth and sixth embodiments described below, a summarizing circuit 42 (also called a second summarizing circuit) is provided in the photoelectric conversion unit 21, and the summarizing circuit 42 summarises analog signals before the signal processing unit 25. The summarizing circuit 42 is connected to the photodiodes 211 (and the quenching elements 212) of a plurality of pixels (pixels 0 to 3), and optical signal outputs from the plurality of photodiodes 211 are input to the input side of the summarizing circuit 42. The summarizing circuit 42 performs an addition process or an averaging process on the optical signal outputs of the plurality of pixels, and outputs the result to the lower bit group 31 as a pulse signal for one pixel. In the solid-state imaging devices 10g and 10h according to the fifth and sixth embodiments, it is preferable to use a normal photodiode that outputs an analog signal, rather than a SPAD, as the photodiode 211. In the normal mode, the aggregation circuit 42 functions as a waveform shaping element 213 provided in each pixel 20 (see FIG. 2).

[0068] In the fifth embodiment shown in FIG. 14, in the binning mode, the optical signal outputs of four adjacent pixels 20 in a 2×2 matrix are added by the aggregation circuit 42 and transmitted as a pulse signal to the lower bit group 31. In addition, in the binning mode, only the lower bit group 31 for pixel 0 in the L2 layer and the upper bit group 32 for pixel 0 in the L3 layer are enabled, and the counters of the lower bit group 31 and the upper bit group 32 for the other pixels 1 to 3 are disabled and not used. By disabling them, the signal information required for propagation to these circuits can be reduced, thereby reducing the power consumption of the counter circuit in the subsequent stage. In addition, when the solid-state imaging element 10e is configured to be dedicated to the binning mode, these counter circuits may be eliminated.

[0069] In the sixth embodiment shown in FIG. 15, like the example shown in FIG. 13, the counters of four pixels are all used as a counter for one pixel by utilizing the counter circuit that was disabled. Specifically, the lower bit group 31 connects four pixels and functions as a 16-bit counter. The upper bit group 32 also connects four pixels and functions as a 32-bit counter. These are connected to function as a total of 48-bit counter. In the sixth embodiment, like the fourth embodiment, the through electrode 60 has a counter signal flowing from the L2 layer to the L3 layer and a counter signal flowing from the L3 layer to the L4 layer. The multiple counter signals flowing through these through electrodes 60 are switched by the time-division switching function of the aggregation circuit 40 and the distribution circuit 50.

[0070] Seventh embodiment FIG. 16 is a schematic configuration diagram showing the circuits and interlayer connections of each layer of a solid-state imaging device 10i according to the seventh embodiment.

[0071] The solid-state imaging device 10i according to the seventh embodiment rearranges pixel units between normal mode and binning mode. For example, in a Bayer array, adjacent pixels 0 to 3 in a 2×2 matrix are provided with R, G, G, and B optical filters, respectively. In normal mode, the pixel unit is composed of four pixels (pixels 0 to 3) in a 2×2 matrix, as in the first embodiment. On the other hand, in the binning mode, the solid-state imaging device 10i treats four pixel units 1 to 4 (see FIG. 1) in a 2×2 matrix as a large-size pixel unit (to which a total of 16 pixels 0 to 15, which are the four small-size pixel units, belong). Among the pixels belonging to this large-size pixel unit, four pixels 0, 4, 8, and 12 to which R filters are attached are treated as one set, and the counter signals of these pixels are added or averaged by the aggregation circuit 40. In addition, in Fig. 16, only an example of binning processing in pixels of an R filter is illustrated, and examples of binning processing configurations in other G1, G2, and B filters are omitted. By using a configuration like the solid-state imaging device 10i shown in Fig. 16, signals for each color can be handled. The configuration or processing capable of rearranging the pixel units in the seventh embodiment can also be applied to other embodiments. For example, the configuration or processing capable of rearranging the pixel units may be used in combination with each of the embodiments in Figs. 13 to 15.

[0072] (Eighth and ninth embodiments) 17 and 18 are schematic configuration diagrams showing the circuits and interlayer connections of each layer of the solid-state imaging devices 10j and 10k according to the eighth and ninth embodiments.

[0073] In the first to seventh embodiments and each modification, a case where a flip-flop is used as a counter circuit is described as an example. In the following, an example is shown in which a storage circuit of an SRAM (Static Random-Access Memory) is used as the latter-stage upper bit group 321 instead of a flip-flop. Note that in FIG. 17 and FIG. 18, a counter value for one pixel unit is shown to be stored, but in reality, one SRAM stores upper bits of several hundred to several tens of thousands of pixels (for example, pixel 0 to pixel 16383 corresponding to pixels of 128×128 in length and width). The SRAM layers may be arranged in a plurality of layers as shown in FIG. 18. In the solid-state imaging devices 10j and 10k according to the eighth and ninth embodiments, as in the other embodiments, the transmission of the counter signal between layers is switched by the time-division switching function of the aggregation circuit 40 and the distribution circuit 50 via the through electrode 60. By using an SRAM, the area per bit can be reduced and the integration degree can be increased. As another example, instead of the SRAM, at least one of other storage circuits such as a latch circuit, a dynamic random-access memory (DRAM), and a synchronous DRAM (SDRAM) may be applied as the upper bit group.

[0074] This embodiment has the following advantages due to the following configuration.

[0075] (1) In this embodiment, a first aggregation circuit is disposed between the lower bit group and the upper bit group, and the first aggregation circuit connects the lower bit group and the upper bit group of a plurality of pixels. This allows wiring circuits to be consolidated in the solid-state imaging device, enabling higher integration.

[0076] (2) In addition, in the solid-state imaging element according to the present embodiment, the photoelectric conversion unit can be of the SPAD type, thereby providing a solid-state imaging element with higher sensitivity.

[0077] (3) In addition, in the solid-state imaging device according to the present embodiment, the lower bit group is formed in one layer, and the upper bit group is formed in a layer different from the layer in which the lower bit group is formed. This makes it possible to reduce the area of ​​one pixel, thereby providing a solid-state imaging device with higher resolution.

[0078] (4) The first aggregation circuit has a time-division switching function, and transmits a counter signal from the lower bit group to the upper bit group by switching the connection between the lower bit group and the upper bit group corresponding to the same counter in time. This enables the wiring circuit to be consolidated in the solid-state imaging element, enabling higher integration.

[0079] (5) In addition, in the solid-state imaging element according to the present embodiment, an electrode for interlayer connection is provided between the layer (first layer) in which the lower bit group is formed and the layer (second layer) in which the upper bit group is formed, and the lower bit group is connected to the upper bit group via the first aggregation circuit and the electrode for interlayer connection. This allows the electrode for interlayer connection (through electrode 60) to be shared by multiple pixels, thereby reducing the number of electrodes for interlayer connection and thus the area of ​​one pixel.

[0080] (6) In addition, in the solid-state imaging device according to this embodiment, the upper bit groups corresponding to the respective pixels belonging to the pixel unit are formed in two or more different second layers (e.g., L3 and L4 layers), and the first layer (e.g., L2 layer) of the lower bit group and the electrodes for interlayer connection in the multiple second layers are arranged in substantially the same XY coordinate positions in the plane direction of the layers. In this way, when manufacturing the solid-state imaging device, the masks can be shared in L2 to L3, or a mask with a small change scale can be used. This allows for cost reduction and shortening of the manufacturing preparation period.

[0081] (7) In the solid-state imaging device according to the present embodiment, the high-order bit groups corresponding to the respective pixels belonging to the pixel unit are formed in two or more different second layers, and the different second layers have substantially the same layer structure. This allows a common mask to be used when manufacturing the solid-state imaging device, thereby reducing costs and shortening the manufacturing preparation time.

[0082] (8) In addition, in the solid-state imaging device according to the present embodiment, a distribution circuit is provided in the second layer, and distributes the counter signal received from the interlayer connection electrode to the corresponding upper bit group. This allows the wiring circuit to be consolidated in the solid-state imaging device, thereby enabling higher integration.

[0083] (9) In addition, in the solid-state imaging device according to the present embodiment, a plurality of upper bit groups corresponding to each of a plurality of pixels belonging to a pixel unit are formed in one second layer for each pixel, and a distribution circuit is provided in the second layer, and the distribution circuit distributes a counter signal from the lower bit group sent from the first aggregation circuit to the corresponding upper bit group. This makes it possible to consolidate wiring circuits in the solid-state imaging device and achieve higher integration.

[0084] (10) In addition, in the solid-state imaging device according to the present embodiment, the photoelectric conversion unit, the lower bit group, and the upper bit group are formed in different layers, and the photoelectric conversion unit layer and the lower bit group layer, and the lower bit group layer and the upper bit group layer are connected to each other via interlayer connection electrodes. This allows the interlayer connection electrode (through electrode 60) to be shared by multiple pixels, thereby reducing the number of interlayer connection electrodes and thus the area of ​​one pixel.

[0085] (11) In addition, the solid-state imaging element according to this embodiment has a function of sending an event signal related to a specific event occurring in the upper bit group from the second layer to the first layer via an electrode for interlayer connection. This allows processing according to the event to be performed after the event occurs. For example, if the event signal is a counter carryover event, the power consumption during imaging in the circuit can be reduced by processing to stop the photodiode from receiving light.

[0086] (12) In addition, in the solid-state imaging device according to the present embodiment, the solid-state imaging device can switch between a normal mode and a binning mode, and in the binning mode, the first aggregation circuit adds or averages the counter signals of the lower bit groups of the multiple pixels connected to the first aggregation circuit, and sends the counter signal obtained by adding or averaging to at least one upper bit group. This allows the binning mode to be executed, and high-sensitivity shooting can be performed. For example, shooting can be performed even in a dark environment.

[0087] (13) In addition, in the solid-state imaging device according to the present embodiment, the solid-state imaging device includes a second aggregation circuit that shares and aggregates the optical signal output of the photoelectric conversion unit of a plurality of pixels. The solid-state imaging device can switch between a normal mode in which a counter signal is output for each pixel and a binning mode in which the counter signals of a plurality of pixels are added or averaged and output. In the binning mode, the second aggregation circuit adds or averages the optical signal output of the photoelectric conversion unit of the plurality of pixels, and sends a counter signal based on the added or averaged optical signal output to at least one lower bit group. This also makes it possible to execute the binning mode and perform high-sensitivity shooting. For example, shooting can be performed even in a dark environment.

[0088] The configuration of the solid-state imaging device 10 etc. described above is a main configuration for explaining the features of the above-mentioned embodiment, and is not limited to the above-mentioned configuration, and can be modified in various ways within the scope of the claims. In addition, the configuration of a general solid-state imaging device 10 etc. is not excluded. For example, the number of pixels belonging to one pixel unit, the number of pixels distributed, the layer distribution method of the pixels, the number of layers, and the number of divisions of the counter bits (particularly the number of divisions of the upper bit group and the number of layers arranged) are not limited to the contents of this embodiment. [Explanation of symbols]

[0089] 10 Solid-state imaging element 20 pixels 21 Photoelectric conversion unit 211 Photodiode 212 Quench element 213 Waveform shaping section 30 Counter 31 Low-order bit group 32 High order bits 321 SRAM type upper bit group 40 First Aggregation Circuit 42 Second Aggregation Circuit 50 distribution circuit 219 CtoC type interlayer connection 60 Through-electrode type interlayer connection (through-electrode)

Claims

1. A solid-state imaging device comprising a plurality of pixels and a first aggregation circuit, The pixel is A photoelectric conversion unit; a counter that counts a pulse signal output in accordance with an amount of light incident on the photoelectric conversion unit; Equipped with The counter is divided into a lower bit group and an upper bit group, the first aggregation circuit is disposed between the lower bit group and the upper bit group; The first aggregation circuit connects the lower bit group of a plurality of pixels and the upper bit group of a plurality of pixels.

2. The solid-state imaging device according to claim 1 , wherein the photoelectric conversion portion is of a SPAD type.

3. the solid-state imaging device has a laminated structure, 2. The solid-state imaging device according to claim 1, wherein the lower bit group is formed in one layer, and the upper bit group is formed in a layer different from the layer in which the lower bit group is formed.

4. 2. The solid-state imaging element of claim 1, wherein the first aggregation circuit has a time division switching function and transmits a counter signal from the lower bit group to the upper bit group by switching and connecting the corresponding lower bit group and the upper bit group of the same counter in time.

5. the solid-state imaging device has a laminated structure, the lower bit group is formed in one layer, and the upper bit group is formed in one or more layers different from the layer in which the lower bit group is formed; an electrode for interlayer connection is provided between the layer in which the lower bit group is formed and the layer in which the upper bit group is formed; The solid-state imaging device according to claim 4 , wherein the lower bit group is connected to the upper bit group via the first summing circuit and the interlayer connection electrode.

6. In a pixel unit including a plurality of pixels sharing the first aggregation circuit, 6. The solid-state imaging element of claim 5, wherein the upper bit groups corresponding to each of the plurality of pixels belonging to the pixel unit are formed in two or more different layers, and the arrangement of the electrodes for interlayer connection in the layer in which the lower bit group is formed and in the plurality of layers in which the upper bit group is formed is substantially the same in XY coordinate positions in the surface direction of the layer.

7. 7. The solid-state imaging element of claim 6, wherein the upper bit groups corresponding to each of the plurality of pixels belonging to the pixel unit are formed in two or more different layers, and the layer structures of the two or more different layers in which the upper bit groups are arranged are substantially the same.

8. A solid-state imaging element as described in claim 5 or claim 6, wherein a distribution circuit is provided in each of the layers in which the upper bit group is formed, and the distribution circuit distributes a counter signal from the lower bit group via the electrode for interlayer connection to the corresponding upper bit group.

9. a plurality of the most significant bit groups corresponding to a plurality of pixels belonging to the pixel unit are formed in one of the layers for each pixel, and a distribution circuit is provided in the layer; 9. The solid-state imaging device according to claim 8, wherein the distribution circuit distributes the counter signal from the lower bit group sent from the first aggregation circuit to the corresponding upper bit group.

10. 2. The solid-state imaging element of claim 1, wherein the photoelectric conversion unit, the lower bit group, and the upper bit group are each formed in a different layer, and the layer between the photoelectric conversion unit and the layer of the lower bit group, and the layer between the lower bit group and the layer of the upper bit group are each connected via an electrode for interlayer connection.

11. 6. The solid-state imaging element according to claim 5, further comprising a function of transmitting an event signal relating to a specific event occurring in the upper bit group from the layer in which the upper bit group is formed to the layer in which the lower bit group is formed via the interlayer connection electrode.

12. the solid-state imaging device is capable of switching between a normal mode in which a counter signal for each pixel is output and a binning mode in which counter signals of a plurality of pixels are added or averaged and output; In the binning mode, the first aggregation circuit 2. The solid-state imaging device according to claim 1, further comprising: a first aggregation circuit that adds or averages the counter signals of the lower bit groups of a plurality of pixels connected to the first aggregation circuit; and sends the added or averaged counter signal to at least one of the upper bit groups.

13. The solid-state imaging device according to claim 1 , further comprising a second consolidation circuit that shares and consolidates optical signal outputs of the photoelectric conversion units of a plurality of pixels.

14. the solid-state imaging device is capable of switching between a normal mode in which a counter signal for each pixel is output and a binning mode in which counter signals of a plurality of pixels are added or averaged and output; 14. The solid-state imaging element of claim 13, wherein in the binning mode, the second aggregation circuit adds or averages the optical signal outputs of the photoelectric conversion units of a plurality of pixels, and sends a counter signal based on the added or averaged optical signal outputs to at least one of the lower bit groups.

15. 2. The solid-state imaging device according to claim 1, wherein the counter is a ripple counter.

16. 2. The solid-state imaging element according to claim 1, wherein the lower bit group is a ripple counter, and the upper bit group is composed of at least one type of memory circuit selected from the group consisting of SRAM, DRAM, Latch, and SDRAM.

Images