Optical semiconductor element

Abstract

To provide an optical semiconductor element whose characteristic can be evaluated with high accuracy.SOLUTION: An optical semiconductor element 1 includes a substrate having a first main surface whose plane orientation is {100} and a second main surface on the opposite side of the first main surface, and a first semiconductor layer provided on the first main surface and including a mesa 31. The mesa includes a laser part 40 and an optical amplifier unit 50. The laser part includes a first surface 111 perpendicular to the first main surface, and a second surface 112 perpendicular to the first main surface and parallel to the first surface. The optical amplifier unit includes a third surface 113 perpendicular to the first main surface and continuing to the first surface, a fourth surface 114 perpendicular to the first main surface and continuing to the second surface, a fifth surface 115 perpendicular to the first main surface and continuing to the third surface, a sixth surface 116 perpendicular to the first main surface, continuing to the fourth surface, and parallel to the fifth surface, and an end surface 31A perpendicular to the first main surface, continuing to the fifth surface and the sixth surface, and emitting light.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to an optical semiconductor device. [Background technology]

[0002] 2. Description of the Related Art An optical semiconductor device in which a distributed feedback (DFB) laser and a semiconductor optical amplifier (SOA) are integrated is known.

[0003] Also known is an optical semiconductor device in which the optical axis between the DFB laser and the SOA is shifted. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2012 / 0243074 [Non-patent literature]

[0005] [Non-Patent Document 1] M. Faugeron et al., "High power three-section integrated master oscillator power amplifier at 1.5μm", IEEE Photon. Technol. Lett., vol. 27, no. 13, pp. 1449-1452, Jul. 2015 Summary of the Invention [Problem to be solved by the invention]

[0006] In conventional optical semiconductor devices with the optical axis shifted between the DFB laser and the SOA, the characteristics of the optical semiconductor device cannot be evaluated with high accuracy due to the influence of the radiation light emitted from the DFB laser to the outside of the SOA. For example, even if an attempt is made to evaluate the divergence angle in the far-field pattern, the far-field pattern is likely to contain vibration components, which reduces the accuracy of the half-width, etc. This makes it difficult to estimate the coupling efficiency with optical fibers with high accuracy.

[0007] An object of the present disclosure is to provide an optical semiconductor element whose characteristics can be evaluated with high accuracy. [Means for solving the problem]

[0008] The optical semiconductor element of the present disclosure comprises a substrate having a first principal surface oriented in {100} direction and a second principal surface opposite to the first principal surface, and a first semiconductor layer provided on the first principal surface and having a mesa formed thereon, the mesa having a laser section and an optical amplifier section, the laser section having a first surface perpendicular to the first principal surface and a second surface perpendicular to the first principal surface and parallel to the first surface, the optical amplifier section having a third surface perpendicular to the first principal surface and connected to the first surface, a fourth surface perpendicular to the first principal surface and connected to the second surface, and a fourth surface perpendicular to the first principal surface and connected to the third surface. a fifth surface perpendicular to the first main surface, connected to the fourth surface and parallel to the fifth surface; and an end surface perpendicular to the first main surface, connected to the fifth surface and the sixth surface, from which light is emitted, wherein a first distance between the first surface and the second surface is smaller than a second distance between the fifth surface and the sixth surface, the first surface and the second surface are parallel to a {01-1} plane of the substrate, the end surface is perpendicular to the {01-1} plane, and the third surface and the fourth surface are inclined in the same direction from the {01-1} plane within a plane parallel to the first main surface. the third surface is inclined from the {01-1} plane more than the fourth surface in a plane parallel to the first main surface, the fifth surface and the sixth surface are inclined from the {01-1} plane in the same direction as the third surface and the fourth surface in a plane parallel to the first main surface, and a first electrode pad is provided at a position sandwiching the laser unit between a second semiconductor layer in contact with the first surface, the second surface, the third surface, the fourth surface, the fifth surface and the sixth surface and the substrate, the first electrode pad including a first metal and electrically connected to the laser unit, and the optical element is disposed between the substrate and the first semiconductor layer. The laser diode has a second electrode pad provided on either side of the amplifier section, containing a second metal and electrically connected to the optical amplifier section, and a third electrode pad provided on the second main surface, electrically connected to the substrate, and containing a third metal. In a planar view, the laser diode has a first region on an extension of the laser section on the side of the propagation direction of light propagating linearly through the laser section, outside the first electrode pad, and a second region overlapping with the optical amplifier section, and in the first region, the proportion of metal film covering the first semiconductor layer or the second semiconductor layer is lower than in the second region. Effect of the Invention

[0009] According to the present disclosure, characteristics can be evaluated with high accuracy. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing the optical semiconductor element according to the first embodiment. [Diagram 2] FIG. 2 is a plan view showing the configuration of the first semiconductor layer in the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view (part 1) illustrating the optical semiconductor element according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) illustrating the optical semiconductor element according to the first embodiment. [Diagram 5] FIG. 5 is a cross-sectional view (part 3) illustrating the optical semiconductor element according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) illustrating the optical semiconductor element according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 1) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 2) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 3) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 4) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 5) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 6) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 7) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view (part 8) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 15] FIG. 15 is a ninth cross-sectional view illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 10) illustrating the method for manufacturing the optical semiconductor device 1 according to the first embodiment. [Figure 17] FIG. 17 is a diagram showing the relationship between the inclination angle and the reflectance at the end face. [Figure 18] FIG. 18 is a diagram showing the relationship between the radius of curvature in the tapered section and the transmittance of light from the laser section to the optical amplifier section. [Figure 19] FIG. 19 is a plan view showing the optical semiconductor element according to the second embodiment. [Figure 20] FIG. 20 is a plan view showing the optical semiconductor element according to the third embodiment. [Figure 21] FIG. 21 is a plan view showing the optical semiconductor element according to the fourth embodiment. [Figure 22] FIG. 22 is a plan view showing the optical semiconductor element according to the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [Description of the embodiments of the present disclosure] First, the embodiments of the present disclosure are listed and described. In the following description, the same or corresponding elements are given the same symbols, and the same description is not repeated. In the crystallographic description in this disclosure, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. In addition, a negative index in crystallography is usually expressed by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In addition, from an arbitrary point, the

[0100] side of the substrate may be referred to as the upper side, upper side, or top, and the [-100] side of the substrate may be referred to as the lower side, lower side, or bottom.

[0012] [1] An optical semiconductor element according to one aspect of the present disclosure includes a substrate having a first main surface oriented in {100} direction and a second main surface opposite to the first main surface, and a first semiconductor layer provided on the first main surface and having a mesa formed thereon, the mesa having a laser section and an optical amplifier section, the laser section having a first surface perpendicular to the first main surface and a second surface perpendicular to the first main surface and parallel to the first surface, the optical amplifier section having a third surface perpendicular to the first main surface and continuous with the first surface, a fourth surface perpendicular to the first main surface and continuous with the second surface, and a fourth surface perpendicular to the first main surface and continuous with the third surface. a fifth surface continuous with the first main surface, a sixth surface perpendicular to the first main surface, continuous with the fourth surface and parallel to the fifth surface, and an end surface perpendicular to the first main surface, continuous with the fifth surface and the sixth surface, from which light is emitted, a first distance between the first surface and the second surface being smaller than a second distance between the fifth surface and the sixth surface, the first surface and the second surface being parallel to a {01-1} surface of the substrate, the end surface being perpendicular to the {01-1} surface, and the third surface and the fourth surface being oriented in the same direction from the {01-1} surface within a plane parallel to the first main surface. the third surface is inclined from the {01-1} plane more than the fourth surface, within a plane parallel to the first main surface, the fifth surface and the sixth surface are inclined from the {01-1} plane in the same direction as the third surface and the fourth surface, within a plane parallel to the first main surface; a first electrode pad, which includes a first metal and is electrically connected to the laser portion, is provided at a position sandwiching the laser portion between a second semiconductor layer in contact with the first surface, the second surface, the third surface, the fourth surface, the fifth surface and the sixth surface and the substrate, and The laser diode has a second electrode pad provided on either side of the optical amplifier section, containing a second metal and electrically connected to the optical amplifier section, and a third electrode pad provided on the second main surface, electrically connected to the substrate, and containing a third metal. In a planar view, the laser diode has a first region on an extension of the laser section on the side of the propagation direction of light propagating in a straight line through the laser section, outside the first electrode pad, and a second region overlapping with the optical amplifier section, and in the first region, the proportion of metal film covering the first semiconductor layer or the second semiconductor layer is lower than in the second region.

[0013] The fifth and sixth faces are inclined in the same direction as the third and fourth faces from the {01-1} plane in a plane parallel to the first main face, and the optical axis of the optical amplifier section is inclined from the direction perpendicular to the end face. When the optical axis of the optical amplifier section is inclined from the direction perpendicular to the end face, the reflectance at the end face is lower than when it is not inclined. Therefore, reflection at the end face is suppressed, and high output is obtained. In addition, the optical axis is not in a straight line between the laser section and the optical amplifier section, and the light travels in different directions, but since the second semiconductor layer is provided, the light is confined within the mesa, and the radiation of light to the outside of the mesa is suppressed. Therefore, the output can be improved. In addition, since the ratio of the metal film covering the first semiconductor layer or the second semiconductor layer is lower in the first region than in the second region, this light is easily radiated to the outside before being emitted from the optical semiconductor element. Therefore, the deterioration of the evaluation accuracy of the characteristics due to the output of the light radiated to the outside of the mesa is suppressed, and the characteristics can be evaluated with high accuracy.

[0014] [2] In [1], a ratio of the first semiconductor layer or the second semiconductor layer covered by the metal film in the first region may be 60% or less in terms of area ratio, in which case light emitted to the outside of the mesa is more likely to be emitted to the outside before being emitted from the optical semiconductor element.

[0015] [3] In [2], a ratio of the first semiconductor layer or the second semiconductor layer covered by the second electrode pad in the first region may be 40% or more and 60% or less in area ratio, making it easy to connect a bonding wire to the second electrode pad and to contact a probe.

[0016] [4] In [1], a ratio of the first semiconductor layer or the second semiconductor layer covered by the metal film in the first region may be 20% or less in terms of area ratio, in which case light emitted to the outside of the mesa is more likely to be emitted to the outside, particularly before being emitted from the optical semiconductor element.

[0017] [5] In any one of [1] to [4], a frame portion may be provided that is connected to the second electrode pad, contains a fourth metal, and is provided along an edge of the first semiconductor layer in a plan view. In this case, high rigidity is easily obtained.

[0018] [6] In any one of [1] to [5], an identification mark may be provided visibly apart from the second electrode pad and containing a fifth metal. In this case, the optical semiconductor element can be distinguished from other optical semiconductor elements.

[0019] [7] In any one of [1] to [6], the substrate may be an indium phosphide substrate. In this case, high output is easily obtained.

[0020] [Details of the embodiment of the present disclosure] (First embodiment) A first embodiment will be described. The first embodiment relates to an optical semiconductor element. FIG. 1 is a plan view showing an optical semiconductor element according to the first embodiment. FIG. 2 is a plan view showing the configuration of a first semiconductor layer in the first embodiment. FIGS. 3 to 6 are cross-sectional views showing an optical semiconductor element according to the first embodiment. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIG. 1. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIG. 1. In FIG. 1, a p-type block layer 81, an n-type block layer 82, a p-type semiconductor layer 83, a contact layer 84, and an insulating film 90, which will be described later, are omitted.

[0021] As shown in FIGS. 1 to 6, the optical semiconductor device 1 according to the first embodiment mainly includes a substrate 20, a semiconductor layer 30, and a semiconductor layer 80. As shown in FIG.

[0022] The substrate 20 is, for example, an n-type indium phosphide (InP) substrate. The substrate 20 has a first main surface 20A and a second main surface 20B opposite to the first main surface 20A. The substrate 20 has, for example, a 1.0×10 18 cm -3The first main surface 20A has a surface orientation of (100), and the second main surface 20B has a surface orientation of (-100). In this disclosure, a planar view refers to viewing an object from a direction perpendicular to the first main surface 20A.

[0023] The semiconductor layer 30 is provided on the first major surface 20A. The semiconductor layer 30 has a buffer layer 32, a diffraction grating layer 33, an n-type cladding layer 34, an active layer 35, and a p-type cladding layer 36. The semiconductor layer 30 is an example of a first semiconductor layer.

[0024] The buffer layer 32 is provided on the substrate 20. The buffer layer 32 is, for example, an n-type InP layer having a thickness of about 300 nm. 17 cm -3 The buffer layer 32 inherits the crystal orientation of the substrate 20.

[0025] The diffraction grating layer 33 is provided on the buffer layer 32. The diffraction grating layer 33 is, for example, an n-type gallium indium arsenide phosphide (GaInAsP) layer having a thickness of about 50 nm. The diffraction grating layer 33 has an emission wavelength λg of about 1.15 μm at room temperature. The diffraction grating layer 33 has a 5.0×10 17 cm -3 The diffraction grating layer 33 has the same crystal orientation as the buffer layer 32.

[0026] The n-type cladding layer 34 is provided on the diffraction grating layer 33 and the buffer layer 32. The n-type cladding layer 34 covers the diffraction grating layer 33. The n-type cladding layer 34 is, for example, an n-type InP layer having a thickness of about 500 nm. The n-type cladding layer 34 is, for example, a 5.0×10 17 cm -3 The n-type cladding layer 34 inherits the crystal orientation of the diffraction grating layer 33 and the buffer layer 32.

[0027] The active layer 35 is provided on the n-type cladding layer 34. The active layer 35 has a quantum well layer and two barrier layers sandwiching the quantum well layer. The quantum well layer is, for example, a GaInAsP layer or an aluminum gallium indium arsenide (AlGaInAs) layer with a thickness of about 80 nm. The barrier layers are, for example, GaInAsP layers or AlGaInAs layers with a thickness of about 50 nm. The emission wavelength λg of the barrier layers at room temperature is about 1.15 μm. The active layer 35 inherits the crystal orientation of the n-type cladding layer 34.

[0028] The p-type cladding layer 36 is provided on the active layer 35. The p-type cladding layer 36 is, for example, a p-type InP layer having a thickness of about 300 nm. 17 cm -3 The p-type cladding layer 36 inherits the crystal orientation of the active layer 35.

[0029] The semiconductor layer 30 inherits the crystal orientation of the substrate 20. The crystal orientation in the following description is the crystal orientation of the substrate 20. A mesa 31 is formed in the semiconductor layer 30. The mesa 31 is formed so that a part of the buffer layer 32 is exposed. The height of the mesa 31 is, for example, about 1000 nm. The mesa 31 has a laser section 40 and an optical amplifier section 50. Details will be described later, but as shown in Figures 1 and 2, the laser section 40 generally extends parallel to the [0-1-1] direction, and the optical amplifier section 50 extends parallel to a direction inclined from the [0-1-1] direction toward the [01-1] direction by 6° to 8°. The optical amplifier section 50 is connected to the end of the laser section 40 on the [0-1-1] side. The dimension of the laser section 40 in a direction parallel to the [0-1-1] direction is, for example, 350 μm to 1000 μm. The dimension of the optical amplifier section 50 in a direction parallel to the [0-1-1] direction is, for example, not less than 500 μm and not more than 1800 μm.

[0030] The laser section 40 has a first surface 111 and a second surface 112 perpendicular to the first main surface 20A. The plane orientation of the first surface 111 is (01-1), and the plane orientation of the second surface 112 is (0-11). That is, the first surface 111 and the second surface 112 are parallel to the {01-1} plane. A first distance W1 between the first surface 111 and the second surface 112 is, for example, not less than 1.5 μm and not more than 2.5 μm.

[0031] The optical amplifier section 50 has a tapered section 51 and a parallel section 52. The tapered section 51 is connected to the end of the laser section 40 on the [0-1-1] side, and the parallel section 52 is connected to the end of the tapered section 51 opposite the laser section 40.

[0032] The tapered portion 51 has a third surface 113 and a fourth surface 114 perpendicular to the first main surface 20A. The third surface 113 is continuous with the first surface 111, and the fourth surface 114 is continuous with the second surface 112. The third surface 113 and the fourth surface 114 are inclined in the same direction from the (01-1) plane and the (0-11) plane, respectively, in a plane parallel to the first main surface 20A. The third surface 113 and the fourth surface 114 are inclined in a direction parallel to the (100) plane. The inclination of the third surface 113 from the (01-1) plane is larger than the inclination of the fourth surface 114 from the (0-11) plane. That is, the third surface 113 is inclined from the {01-1} plane more than the fourth surface 114 in a plane parallel to the first main surface 20A. Therefore, a third distance W3 between the third surface 113 and the fourth surface 114 gradually increases with increasing distance from the laser unit 40. The angle between the third surface 113 and the (01-1) surface is angle θ13, and the angle between the fourth surface 114 and the (0-11) surface is angle θ14, with angle θ13 being greater than angle θ14. In the present disclosure, the angle between the two surfaces is greater than or equal to 0° and less than or equal to 90°. The angle between the two surfaces can be measured, for example, through observation using a microscope.

[0033] The parallel portion 52 has a fifth surface 115 and a sixth surface 116 perpendicular to the first main surface 20A. The fifth surface 115 and the sixth surface 116 are parallel to each other. A second distance W2 between the fifth surface 115 and the sixth surface 116 is greater than the first distance W1. In other words, the first distance W1 is smaller than the second distance W2. The second distance W2 is, for example, 2.0 μm or more and 10 μm or less. The fifth surface 115 and the sixth surface 116 are inclined in the same direction as the third surface 113 and the fourth surface 114 from the (01-1) plane and the (0-11) plane, respectively, in a plane parallel to the first main surface 20A. For example, fifth surface 115 and sixth surface 116 are inclined from the (01-1) plane and the (0-11) plane, respectively, in the same direction as third surface 113 and fourth surface 114 by 6° or more and 8° or less within a plane parallel to first main surface 20A. The magnitude of the angle between fifth surface 115 and the (01-1) plane is angle θ15, and the magnitude of the angle between sixth surface 116 and the (0-11) plane is angle θ16, where angle θ15 and angle θ16 are equal to each other, for example, 6° or more and 8° or less.

[0034] In the first embodiment, the third surface 113 and the fifth surface 115 are inclined so that their normal vectors point between the [01-1] direction and the

[0011] direction, and the fourth surface 114 and the sixth surface 116 are inclined so that their normal vectors point between the [0-11] direction and the [0-1-1] direction.

[0035] The fifth surface 115 is inclined from the (01-1) plane less than the third surface 113 in a plane parallel to the first main surface 20A. From the opposite perspective, the third surface 113 is inclined from the (01-1) plane more than the fifth surface 115 in a plane parallel to the first main surface 20A. For example, the third surface 113 is inclined from the (01-1) plane more than 0° and not more than 1° more than the fifth surface 115 in a plane parallel to the first main surface 20A. The angle θ13 is larger than the angle θ15, and for example, the difference between the angle θ13 and the angle θ15 is more than 0° and not more than 1°.

[0036] The sixth surface 116 is inclined from the (0-11) plane more than the fourth surface 114 in a plane parallel to the first main surface 20A. From the opposite perspective, the fourth surface 114 is inclined from the (0-11) plane less than the sixth surface 116 in a plane parallel to the first main surface 20A. For example, the fourth surface 114 is inclined from the (0-11) plane more than 0° and not more than 1° less than the sixth surface 116 in a plane parallel to the first main surface 20A. The angle θ16 is larger than the angle θ14, and for example, the difference between the angle θ16 and the angle θ14 is more than 0° and not more than 1°.

[0037] For example, the difference between angle θ13 and angle θ15 is equal to the difference between angle θ16 and angle θ14, and the optical axis of tapered portion 51 and the optical axis of parallel portion 52 are connected to each other and are parallel to each other at the boundary between tapered portion 51 and parallel portion 52. The optical axis of parallel portion 52 is inclined, for example, by 6° to 8° from the [0-1-1] direction.

[0038] 3, in the laser section 40, a diffraction grating with a constant period is formed in the diffraction grating layer 33. On the other hand, in the optical amplifier section 50, no diffraction grating is formed in the diffraction grating layer 33, and the entire upper surface of the buffer layer 32 in the mesa 31 is covered with the diffraction grating layer 33, as shown in FIG.

[0039] The semiconductor layer 80 is provided on the side of the mesa 31 so as to embed the mesa 31. The semiconductor layer 80 has a p-type block layer 81 and an n-type block layer 82. The semiconductor layer 80 contacts a first face 111, a second face 112, a third face 113, a fourth face 114, a fifth face 115, and a sixth face 116. The semiconductor layer 80 is an example of a second semiconductor layer. At least a portion of an upper surface of the p-type cladding layer 36 is exposed from the semiconductor layer 80.

[0040] The p-type blocking layer 81 is provided on the buffer layer 32. The p-type blocking layer 81 contacts the first surface 111, the second surface 112, the third surface 113, the fourth surface 114, the fifth surface 115, and the sixth surface 116. The p-type blocking layer 81 contacts each side surface of the buffer layer 32, the diffraction grating layer 33, the n-type cladding layer 34, the active layer 35, and the p-type cladding layer 36. The p-type blocking layer 81 is, for example, a p-type InP layer having a thickness of 1000 nm or more and 1500 nm or less at its thickest portion. The p-type blocking layer 81 has a thickness of, for example, 1.0×10 17 cm -3 Above 1.0×10 18 cm -3 The p-type block layer 81 is doped with Zn at the following concentration: Chlorine (Cl) may be added to a portion of the p-type block layer 81 .

[0041] The n-type block layer 82 is provided on the p-type block layer 81. The n-type block layer 82 is, for example, an n-type InP layer having a thickness of 300 nm or more and 500 nm or less at its thickest part. The n-type block layer 82 is, for example, a 5.0×10 18 cm -3 The n-type block layer 82 is doped with Si at a concentration of about 1000 .mu.m. The n-type block layer 82 may be doped with Cl in part.

[0042] The optical semiconductor element 1 further has a p-type semiconductor layer 83, a contact layer 84, a first electrode 61, a second electrode 62, a first electrode pad 71, a second electrode pad 72, a third electrode pad 73, an insulating film 90, an anti-reflection film 93, and a highly reflective film 94.

[0043] The p-type semiconductor layer 83 is provided on the p-type cladding layer 36 and the n-type block layer 82. The p-type semiconductor layer 83 is, for example, a p-type InP layer having a thickness of 2500 nm or more and 3500 nm or less at its thickest part. 18 cm -3 Above 2.0×10 18 cm -3 The p-type semiconductor layer 83 is doped with Zn at the following concentration: The p-type semiconductor layer 83 can function as a part of the p-type cladding layer 36 .

[0044] The contact layer 84 is provided on the p-type semiconductor layer 83. The contact layer 84 has a p-type GaInAsP layer and a p-type indium gallium arsenide (InGaAs) layer. The GaInAsP layer is provided on the p-type semiconductor layer 83. For example, the thickness of the GaInAsP layer is about 200 nm, and the GaInAsP layer has a thickness of 2.0×10 18 cm -3 The InGaAs layer is doped with Zn at a concentration of about 8.0×10 18 cm -3 The contact layer 84 is doped with Zn at a concentration of about 1000 .mu.m. The band gap of the contact layer 84 is smaller than the band gap of the p-type semiconductor layer 83. The contact layer 84 provides insulation between the laser section 40 and the optical amplifier section 50.

[0045] The first electrode 61 is provided on the contact layer 84 in the laser section 40. The first electrode 61 is provided so as to overlap with the laser section 40 in a planar view. For example, the first surface 111 and the second surface 112 are located inside the contour of the first electrode 61 in a planar view.

[0046] The second electrode 62 is provided on the contact layer 84 in the optical amplifier section 50. The second electrode 62 is provided so as to overlap with the optical amplifier section 50 in a planar view. For example, a third surface 113, a fourth surface 114, a fifth surface 115, and a sixth surface 116 are located inside the contour of the second electrode 62 in a planar view.

[0047] The insulating film 90 covers the upper surface of the contact layer 84, the upper surface and side surfaces of the first electrode 61, and the upper surface and side surfaces of the second electrode 62. The insulating film 90 is made of, for example, silicon oxide (SiO 2 ) film, a silicon oxynitride (SiON) film, or a silicon nitride (SiN) film. An opening 91 through which a part of the upper surface of the first electrode 61 is exposed, and an opening 92 through which a part of the upper surface of the second electrode 62 is exposed are formed in the insulating film 90.

[0048] The first electrode pad 71 and the second electrode pad 72 are provided on the insulating film 90. The first electrode pad 71 is provided at a position where the laser unit 40 is sandwiched between the first electrode pad 71 and the substrate 20. The first electrode pad 71 contacts the first electrode 61 and is electrically connected to the laser unit 40 via the first electrode 61. The second electrode pad 72 is provided at a position where the optical amplifier unit 50 is sandwiched between the first electrode pad 71 and the substrate 20. The second electrode pad 72 contacts the second electrode 62 and is electrically connected to the optical amplifier unit 50 via the second electrode 62. The first electrode pad 71 and the second electrode pad 72 contain a metal and have, for example, a gold (Au) film. The metal contained in the first electrode pad 71 is an example of a first metal, and the metal contained in the second electrode pad 72 is an example of a second metal.

[0049] The first electrode 61 and the second electrode 62 are insulated and separated from each other, and the first electrode pad 71 and the second electrode pad 72 are insulated and separated from each other. Therefore, voltages can be applied to the laser section 40 and the optical amplifier section 50 independently of each other.

[0050] The third electrode pad 73 is provided on the second main surface 20B of the substrate 20. The third electrode pad 73 is in contact with the substrate 20 and is electrically connected to the substrate 20. The third electrode pad 73 includes a metal and has, for example, a gold (Au) film. The metal included in the third electrode pad 73 is an example of a third metal.

[0051] The mesa 31 has a first end face 31A with a plane orientation of (0-1-1) and a second end face 31B with a plane orientation of (011). An anti-reflection film 93 covers the first end face 31A, and a highly reflective film 94 covers the second end face 31B. For example, the anti-reflection film 93 is made of aluminum oxide (Al 2 O 3 ) or tantalum oxide (Ta 2 O 3 ) layer and a silicon oxide (SiO 2 ) or titanium dioxide (TiO 2 ) film, and the high refractive index film is between the first end face 31A and the low refractive index film. For example, the high reflection film 94 is made of aluminum oxide (Al 2 O 3 ) or tantalum oxide (Ta2 O 3 ) layer and a silicon oxide (SiO 2 ) or titanium dioxide (TiO 2 ) film, and the structure in which the high refractive index film is between the second end face 31B and the low refractive index film is repeated 2 to 5 times.

[0052] Here, the shape of the first electrode pad 71 in a plan view, that is, the planar shape, will be described. The planar shape of the first electrode pad 71 is rectangular. The planar shape of the first electrode pad 71 has sides 71A and 71B parallel to the

[0011] direction, and sides 71C and 71D parallel to the [01-1] direction. Side 71A is on the [01-1] side of side 71B, and side 71C is on the [0-1-1] side of side 71D. Side 71A is in the vicinity of the end of the semiconductor layer 30 on the [01-1] side. Side 71B is in the vicinity of the end of the semiconductor layer 30 on the [0-11] side. Side 71C is in the vicinity of the boundary between the laser section 40 and the optical amplifier section 50. Side 71D is in the vicinity of the end of the semiconductor layer 30 on the

[0011] side.

[0053] Next, the shape of the second electrode pad 72 in a plan view, that is, the planar shape, will be described. The planar shape of the second electrode pad 72 is trapezoidal. The planar shape of the second electrode pad 72 has a side 72A parallel to the

[0011] direction, a side 72B parallel to the sixth surface 116, and sides 72C and 72D parallel to the [01-1] direction. The side 72A is on the [01-1] side of the side 72B, and the side 72C is on the [0-1-1] side of the side 72D. The side 72A is in the vicinity of the end of the semiconductor layer 30 on the [01-1] side. The side 72B is in the vicinity of the fourth surface 114 and the sixth surface 116. The side 72C is in the vicinity of the end of the semiconductor layer 30 on the [0-1-1] side. The side 72D is between the first electrode pad 71 and the parallel part 52.

[0054] The optical semiconductor element 1 has, outside the first electrode pad 71 in a plan view, a first region 11 on an extension of the laser section 40 in the direction of propagation of light that linearly propagates through the laser section 40, and a second region 12 overlapping with the optical amplifier section 50. A part of the first region 11 and a part of the second region 12 may overlap with each other.

[0055] The second electrode pad 72 overlaps most of the optical amplifier section 50 in a plan view, and is provided in most of the second region 12. For example, the second electrode pad 72 is provided in 80% or more of the second region 12 in terms of area ratio in a plan view, and covers 80% or more of the semiconductor layer 30 in the second region 12, i.e., the optical amplifier section 50. The second electrode pad 72 may cover 90% or more, or 95% or more of the optical amplifier section 50 in terms of area ratio in a plan view.

[0056] On the other hand, the side 72B of the planar shape of the second electrode pad 72 is located near the fourth surface 114 and the sixth surface 116, and most of the first region 11 is not covered by the second electrode pad 72. Also, the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 is not covered by a metal film other than the second electrode pad 72. For example, in terms of area ratio in a plan view, the ratio of the metal film in the first region 11 is 20% or less, and the ratio of the portion of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 that is covered by the metal film is 20% or less. In terms of area ratio in a plan view, the ratio of the portion of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 that is covered by the metal film may be 10% or less, or may be 5% or less.

[0057] In this way, the proportion of the metal film covering the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 is lower than that in the second region 12.

[0058] In the optical semiconductor device 1, a portion of the mesa 31 including the laser portion 40 in a plan view functions as a DFB laser, and a portion of the mesa 31 including the optical amplifier portion 50 in a plan view functions as an SOA.

[0059] Next, a method for manufacturing the optical semiconductor element 1 according to the first embodiment will be described. Figures 7 to 16 are cross-sectional views showing the method for manufacturing the optical semiconductor element 1 according to the first embodiment. Figures 7 to 16 show changes in the cross section taken along line VV in Figure 1.

[0060] First, as shown in Fig. 7, a substrate 20 having a first main surface 20A and a second main surface 20B is prepared, and a buffer layer 32 is formed on the first main surface 20A. Next, a diffraction grating layer 33 is formed on the buffer layer 32. The diffraction grating layer 33 may be formed to be wider than its final dimensions. In the portion included in the laser section 40, a diffraction grating is formed in the diffraction grating layer 33 (see Fig. 3), and in the portion included in the optical amplifier section 50, the entire upper surface of the buffer layer 32 is covered with the diffraction grating layer 33.

[0061] 8, an n-type cladding layer 34 is formed on the diffraction grating layer 33 and the buffer layer 32. The n-type cladding layer 34 covers the diffraction grating layer 33. Next, an active layer 35 is formed on the n-type cladding layer 34, and a p-type cladding layer 36 is formed on the active layer 35.

[0062] 9, a mask 39 is formed on the p-type cladding layer 36. The mask 39 is formed on an area where the mesa 31 is to be formed. The mask 39 is made of, for example, SiO 2 It is a membrane.

[0063] 10, the p-type cladding layer 36, the active layer 35, the n-type cladding layer 34, the diffraction grating layer 33, and a part of the buffer layer 32 are dry etched using the mask 39 as an etching mask. As a result, the mesa 31 is formed. The mesa 31 has a laser section 40 and an optical amplifier section 50, and the optical amplifier section 50 has a tapered section 51 and a parallel section 52. The laser section 40 has a first surface 111 and a second surface 112, the tapered section 51 has a third surface 113 and a fourth surface 114, and the parallel section 52 has a fifth surface 115 and a sixth surface 116. For example, silicon tetrachloride (SiCl 4 ) is used for reactive ion etching (RIE).

[0064] 11 , using mask 39 as a growth mask, a p-type block layer 81 is formed on the buffer layer 32 exposed from mesa 31, and an n-type block layer 82 is formed on the p-type block layer 81. As a result, the mesa 31 is buried with a semiconductor layer 80 including the p-type block layer 81 and the n-type block layer 82. The semiconductor layer 80 is in contact with a first surface 111, a second surface 112, a third surface 113, a fourth surface 114, a fifth surface 115, and a sixth surface 116.

[0065] 12, the mask 39 is removed. The mask 39 can be removed using, for example, hydrofluoric acid (HF). Next, a p-type semiconductor layer 83 is formed on the p-type cladding layer 36 and the n-type block layer 82, and a contact layer 84 is formed on the p-type semiconductor layer 83. The p-type semiconductor layer 83 is integrated with the p-type cladding layer 36.

[0066] 13, a first electrode 61 is formed on the contact layer 84. At the same time as the first electrode 61, a second electrode 62 is also formed (see FIGS. 4 and 6).

[0067] 14, an insulating film 90 is formed to cover the upper surface of the contact layer 84, the upper and side surfaces of the first electrode 61, and the upper and side surfaces of the second electrode 62, and an opening 91 is formed in the insulating film 90 to expose a portion of the upper surface of the first electrode 61. At the same time as the opening 91, an opening 92 is also formed to expose a portion of the upper surface of the second electrode 62 (see FIG. 6).

[0068] 15, a first electrode pad 71 is formed on the insulating film 90. The first electrode pad 71 is in contact with the first electrode 61. At the same time as the opening 91, a second electrode pad 72 in contact with the second electrode 62 is also formed (see FIGS. 4 and 6).

[0069] 16, the second main surface 20B of the substrate 20 is polished. Next, a third electrode pad 73 in contact with the substrate 20 is formed on the second main surface 20B.

[0070] Next, an anti-reflection film 93 covering the first end face 31A of the mesa 31 and a highly reflective film 94 covering the second end face 31B are formed.

[0071] In this manner, the optical semiconductor device 1 according to the first embodiment can be manufactured.

[0072] In the optical semiconductor device 1, when a voltage is applied between the first electrode pad 71 and the third electrode pad 73, light is generated in the laser section 40. When a voltage is applied between the second electrode pad 72 and the third electrode pad 73, the output is amplified by the optical amplifier section 50 and laser light is emitted from the first end face 31A. The fifth face 115 and the sixth face 116 are inclined in the same direction as the third face 113 and the fourth face 114 from the (01-1) face and the (0-11) face, respectively, in a plane parallel to the first main face 20A, and the optical axis of the optical amplifier section 50 is inclined from the direction perpendicular to the first end face 31A. As shown in FIG. 17, when the optical axis of the optical amplifier section 50 is inclined from the direction perpendicular to the first end face 31A, that is, when the inclination angle α is greater than 0°, the reflectance at the first end face 31A is lower than when the optical axis is not inclined, that is, when the inclination angle α is 0°. Therefore, in the optical semiconductor device 1, reflection at the first end face 31A is suppressed and high output can be obtained. When the inclination angle α is between 6° and 8°, the reflectance is particularly low and excellent output can be obtained. Figure 17 shows the relationship between the inclination angle α and the reflectance at the first end face 31A. The reflectance is expressed in logarithm.

[0073] The optical axis is not aligned between the laser section 40 and the optical amplifier section 50, and the light travels in different directions, but the semiconductor layer 80 is provided to confine the light within the mesa 31 and suppress radiation of light outside the mesa 31. For example, radiation of light outside the mesa 31 is suppressed to 3% or less.

[0074] Even if light is emitted to the outside of the mesa 31, the light is unlikely to reach the anti-reflection film 93. This is because the second electrode pad 72 is provided locally between the laser portion 40 and the anti-reflection film 93, and most of the first region 11 is not covered by the metal film of the second electrode pad 72 or the like. The wider the area of ​​the first region 11 covered by the metal film, the more easily the light is reflected between the metal film and the third electrode pad 73 and reaches the anti-reflection film 93. On the other hand, if most of the first region 11 is not covered by the metal film, even if light is reflected by the third electrode pad 73, the light is not reflected by the opposite surface and is likely to go outside the optical semiconductor element 1. Therefore, even if light is emitted to the outside of the mesa 31, the light is unlikely to reach the anti-reflection film 93.

[0075] When the light radiated to the outside of the mesa 31 reaches the anti-reflection film 93, this light is output from the optical semiconductor element 1 in addition to the light output from the mesa 31. This can reduce the accuracy of evaluating the characteristics of the optical semiconductor element 1. In contrast, according to this embodiment, the output from the optical semiconductor element 1 of the light radiated to the outside of the mesa 31 can be suppressed, so that the characteristics can be evaluated with high accuracy. Since the proportion of the portion of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 that is covered with the metal film is 20% or less, the light radiated to the outside of the mesa 31 is particularly likely to be radiated to the outside before being emitted from the optical semiconductor element 1.

[0076] As described above, the optical axis is not aligned between the laser section 40 and the optical amplifier section 50, and the light travels in different directions. In plan view, the optical axis passes through the center of the width direction of the mesa 31 perpendicular to the light travel direction. The smaller the radius of curvature of the optical axis in the tapered section 51, etc., the easier it is to miniaturize the optical semiconductor element 1, but the more likely light radiation to occur outside the mesa 31. The radius of curvature of the optical axis does not need to be constant, but if the maximum value of the radius of curvature of the optical axis is 2500 μm or less, the optical semiconductor element 1 is easier to miniaturize. If the maximum value of the radius of curvature of the optical axis is 2000 μm or less, the optical semiconductor element 1 is easier to miniaturize. On the other hand, if the minimum value of the radius of curvature of the optical axis is 1500 μm or more, the radiation of light to the outside of the mesa 31 is easier to suppress. Therefore, the radius of curvature of the optical axis is, for example, 1500 μm or more and 2500 μm or less, and may be 1500 μm or more and 2000 μm or less. The light radiation to the outside of the mesa 31 is, for example, 5% or less, and may be 3% or less. Furthermore, when the radius of curvature of the optical axis changes continuously, it is easy to reduce the coupling loss due to mode mismatch at the connection portion between the linear region and the curved region such as the tapered portion 51.

[0077] Here, the relationship between the radius of curvature in the tapered section 51 and the transmittance of light from the laser section 40 to the optical amplifier section 50 will be described. FIG. 18 is a diagram showing the relationship between the radius of curvature in the tapered section 51 and the transmittance of light from the laser section 40 to the optical amplifier section 50. In the example shown in FIG. 18, the transmittance increases as the radius of curvature increases. This indicates that the radiation of light to the outside of the mesa 31 is suppressed as the radius of curvature increases. However, when the radius of curvature is greater than 2500 μm, the change in transmittance is small. Also, when the radius of curvature is less than 1500 μm, the transmittance is less than 95%.

[0078] For example, bonding wires are connected to the first electrode pads 71 ​​and the second electrode pads 72. The first electrode pads 71 ​​and the second electrode pads 72 may be brought into contact with a probe of an inspection device.

[0079] Although the material of the substrate 20 is not limited, when the substrate 20 is an InP substrate, high output can be easily obtained.

[0080] Second embodiment A second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the metal film on the semiconductor layer 80. Fig. 19 is a plan view showing an optical semiconductor element according to the second embodiment. In Fig. 19, the p-type block layer 81, the n-type block layer 82, the p-type semiconductor layer 83, the contact layer 84, and the insulating film 90 are omitted.

[0081] As shown in FIG. 19, the optical semiconductor element 2 according to the second embodiment has an identification mark 74 provided on an insulating film 90. The identification mark 74 is provided so as to be visible. The identification mark 74 includes a metal, and has, for example, an Au film. For example, the identification mark 74 is made of the same material as the second electrode pad 72. A part of the identification mark 74 may be in a part of the first region 11. The identification mark 74 indicates, for example, a number, a letter, or a symbol. For example, the identification mark 74 may be in a range of 10% or less of the first region 11 in terms of area ratio in a plan view. For example, in terms of area ratio in a plan view, the ratio of the metal film in the first region 11 is 30% or less, and the ratio of the part of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 that is covered by the metal film is 30% or less. As in the first embodiment, the ratio of the metal film covering the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 is lower than that in the second region 12. The metal included in the identification mark 74 is an example of a fifth metal.

[0082] Other configurations of the second embodiment are the same as those of the first embodiment. The second embodiment also provides the same effects as the first embodiment. In addition, the provision of the identification mark 74 allows the optical semiconductor element 2 to be distinguished from other optical semiconductor elements.

[0083] Third embodiment A third embodiment will be described. The third embodiment differs from the second embodiment mainly in the configuration of the second electrode pad. Fig. 20 is a plan view showing an optical semiconductor element according to the third embodiment. In Fig. 20, p-type block layer 81, n-type block layer 82, p-type semiconductor layer 83, contact layer 84, and insulating film 90 are omitted.

[0084] 20, the optical semiconductor element 3 according to the third embodiment has a second electrode pad 300 instead of the second electrode pad 72. The second electrode pad 300 has a first pad region 310 having a rectangular planar shape and a second pad region 320 having a parallelogram planar shape. The first pad region 310 and the second pad region 320 are connected to each other.

[0085] The planar shape of the first pad region 310 has sides 310A and 310B parallel to the

[0011] direction, and sides 310C and 310D parallel to the [01-1] direction. Side 310A is on the [01-1] side of side 310B, and side 310C is on the [0-1-1] side of side 310D. Side 310A is in the vicinity of the end of the semiconductor layer 30 on the [01-1] side. Side 310B is in the vicinity of the end of the semiconductor layer 30 on the [0-11] side. Side 310C is between the first electrode pad 71 and the identification mark 74. Side 310D is between the first electrode pad 71 and the parallel portion 52. For example, the length of sides 310A and 310B is 180 μm or more and 380 μm or less, and the length of sides 310C and 310D is 100 μm or more and 800 μm or less. The first pad region 310 occupies about 50% of the first region 11 in terms of area ratio in a plan view.

[0086] The planar shape of the second pad region 320 has a side 320A parallel to the fifth surface 115, a side 320B parallel to the sixth surface 116, and sides 320C and 320D parallel to the [01-1] direction. Side 320A is on the [01-1] side of side 320B, and side 320C is on the [0-1-1] side of side 320D. Side 320A is in the vicinity of the fifth surface 115. Side 320B is in the vicinity of the sixth surface 116. Side 320C is in the vicinity of the end of the semiconductor layer 30 on the [0-1-1] side. Side 320D overlaps with side 310C.

[0087] The second electrode pad 300 overlaps most of the optical amplifier section 50 in a plan view, and is provided in most of the second region 12. For example, the second electrode pad 300 is provided in 80% or more of the second region 12 in terms of area ratio in a plan view, and covers 80% or more of the semiconductor layer 30 in the second region 12, i.e., the optical amplifier section 50. The second electrode pad 300 may cover 90% or more, or 95% or more of the optical amplifier section 50 in terms of area ratio in a plan view.

[0088] On the other hand, the side 320B of the planar shape of the second pad region 320 of the second electrode pad 300 is in the vicinity of the sixth surface 116, and the first region 11 is away from the second pad region 320. In addition, the identification mark 74 and the first pad region 310 are present in a part of the first region 11, but the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 is not covered with a metal film other than the identification mark 74 or the second electrode pad 300. For example, in terms of area ratio in a plan view, the ratio of the metal film in the first region 11 is 60% or less, and the ratio of the part of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 that is covered with the metal film is 60% or less. In terms of area ratio in a plan view, the ratio of the part of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 that is covered with the metal film may be 50% or less, or may be 40% or less.

[0089] In this manner, also in the third embodiment, the proportion of the metal film covering the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 is lower than that in the second region 12.

[0090] Other configurations of the third embodiment are the same as those of the second embodiment. The third embodiment also provides the same effects as the second embodiment. Since the ratio of the portion of the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 covered with the metal film is 60% or less, the light emitted to the outside of the mesa 31 is likely to be emitted to the outside before being emitted from the optical semiconductor element 1. In addition, since the first pad region 310 having a large dimension in a direction parallel to the [01-1] direction is provided, it becomes easier to connect the bonding wire and contact the probe. In particular, if the second electrode pad 300 is 40% or more of the first region 11 in terms of area ratio in a plan view, it becomes especially easy to connect the bonding wire and contact the probe.

[0091] (Fourth embodiment) A fourth embodiment will be described. The fourth embodiment differs from the second embodiment mainly in the configuration of the metal film on the semiconductor layer 80. Fig. 21 is a plan view showing an optical semiconductor element according to the fourth embodiment. In Fig. 21, the p-type block layer 81, the n-type block layer 82, the p-type semiconductor layer 83, the contact layer 84, and the insulating film 90 are omitted.

[0092] As shown in FIG. 21, the optical semiconductor element 4 according to the fourth embodiment has a frame portion 75 provided on an insulating film 90. The frame portion 75 includes a metal, for example, an Au film. For example, the frame portion 75 is made of the same material as the second electrode pad 72. A part of the frame portion 75 may be in a part of the first region 11. The frame portion 75 is connected to the intersection of the side 72C and the side 72B of the second electrode pad 72 and the intersection of the side 72D and the side 72B in a plan view, and is arranged along the end of the semiconductor layer 30 on the [0-1-1] side and the end of the semiconductor layer 30 on the [0-11] side. The identification mark 74 is surrounded by the second electrode pad 72 and the frame portion 75. For example, the frame portion 75 may be in a range of 10% or less of the first region 11 in terms of area ratio in a plan view. As in the first embodiment, the ratio of the metal film covering the semiconductor layer 30 or the semiconductor layer 80 in the first region 11 is lower than that in the second region 12. The metal contained in frame 75 is an example of a fourth metal.

[0093] Other configurations of the fourth embodiment are the same as those of the second embodiment. The fourth embodiment also provides the same effects as the second embodiment. In addition, the provision of the frame portion 75 provides high rigidity and can suppress deformation during transportation using a suction collet.

[0094] Fifth embodiment A fifth embodiment will be described. The fifth embodiment differs from the third embodiment mainly in the configuration of the metal film on the semiconductor layer 80. Fig. 22 is a plan view showing an optical semiconductor element according to the fifth embodiment. In Fig. 22, the p-type block layer 81, the n-type block layer 82, the p-type semiconductor layer 83, the contact layer 84, and the insulating film 90 are omitted.

[0095] As shown in FIG. 22, the optical semiconductor element 5 according to the fifth embodiment has frame portions 76 and 77 provided on an insulating film 90. The frame portions 76 and 77 include a metal, for example, an Au film. For example, the frame portions 76 and 77 are made of the same material as the second electrode pad 72. A part of the frame portion 76 may be in a part of the first region 11. The frame portion 76 is connected to the intersection of the side 310C and the side 310B of the second electrode pad 72 and the intersection of the side 320B and the side 320C in a plan view, and is arranged along the end of the semiconductor layer 30 on the [0-1-1] side and the end of the semiconductor layer 30 on the [0-11] side. The identification mark 74 is surrounded by the second electrode pad 72 and the frame portion 76. For example, the frame portion 76 may be in a range of 10% or less of the first region 11 in terms of area ratio in a plan view. The frame portion 77 is connected to an intersection of the side 310C and the side 310A of the second electrode pad 72 and an intersection of the side 320A and the side 320C of the second electrode pad 72 in a plan view, and is disposed along the end portion on the [0-1-1] side and the end portion on the [01-1] side of the semiconductor layer 30. As in the first embodiment, the proportion of the metal film covering the semiconductor layer 30 or the semiconductor layer 80 is lower in the first region 11 than in the second region 12. The metal contained in the frame portion 76 is another example of the fourth metal.

[0096] Other configurations of the fifth embodiment are the same as those of the third embodiment. The fifth embodiment also provides the same effects as the third embodiment. In addition, by providing the frames 76 and 77, high rigidity is obtained, and deformation during transportation using the suction collet can be suppressed.

[0097] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0098] 1, 2, 3, 4, 5: Optical semiconductor element 11:First area 12:Second area 20: Substrate 20A: First main surface 20B: 2nd main surface 30, 80: Semiconductor layer 31: Mesa 31A: 1st end surface 31B: 2nd end face 32: Buffer layer 33: Diffraction grating layer 34: n-type cladding layer 35:Active layer 36: p-type cladding layer 39: Mask 40: Laser section 50: Optical amplifier section 51: Tapered section 52: Parallel section 61: 1st electrode 62:Second electrode 71: First electrode pad 71A, 71B, 71C, 71D: Sides 72: Second electrode pad 72A, 72B, 72C, 72D: Sides 73: 3rd electrode pad 74: Identification sign 75, 76, 77: Frame 81: p-type block layer 82: n-type blocking layer 83: p-type semiconductor layer 84: Contact layer 90: Insulating film 91, 92: Opening 93: Anti-reflection film 94: High reflective film 111: 1st page 112:Second side 113:Side 3 114:Side 4 115:Side 5 116:Side 6 300: Second electrode pad 310: First pad area 310A, 310B, 310C, 310D: Sides 320: Second pad area 320A, 320B, 320C, 320D: Sides W1: 1st distance W2: Second distance W3: Third distance θ13, θ14, θ15, θ16: Angle

Claims

1. A substrate having a first main surface having a {100} orientation and a second main surface opposite to the first main surface; a first semiconductor layer provided on the first major surface and having a mesa formed therein; having the mesa has a laser portion and an optical amplifier portion; The laser unit includes: a first surface perpendicular to the first main surface; a second surface perpendicular to the first main surface and parallel to the first surface; having The optical amplifier section includes: a third surface that is perpendicular to the first main surface and is continuous with the first main surface; a fourth surface perpendicular to the first main surface and connected to the second main surface; a fifth surface perpendicular to the first main surface and connected to the third surface; a sixth surface perpendicular to the first main surface, connected to the fourth surface, and parallel to the fifth surface; an end surface perpendicular to the first main surface, connected to the fifth surface and the sixth surface, through which light exits; having a first distance between the first surface and the second surface is smaller than a second distance between the fifth surface and the sixth surface; the first surface and the second surface are parallel to a {01-1} plane of the substrate; the end face is perpendicular to the {01-1} plane, the third surface and the fourth surface are inclined in the same direction from the {01-1} surface within a plane parallel to the first main surface, the third surface is inclined from the {01-1} plane more than the fourth surface in a plane parallel to the first main surface, the fifth plane and the sixth plane are inclined in a plane parallel to the first main surface in the same direction as the third plane and the fourth plane from the {01-1} plane, a second semiconductor layer in contact with the first surface, the second surface, the third surface, the fourth surface, the fifth surface, and the sixth surface; a first electrode pad provided at a position sandwiching the laser portion between the substrate and the first electrode pad, the first electrode pad including a first metal and electrically connected to the laser portion; a second electrode pad provided at a position sandwiching the optical amplifier section between the substrate and the second electrode pad, the second electrode pad including a second metal and electrically connected to the optical amplifier section; a third electrode pad provided on the second main surface, electrically connected to the substrate, and including a third metal; having In a plan view, on the outer side of the first electrode pad, a first region on a line extending from the laser section in a direction in which light linearly propagates through the laser section; a second region overlapping the optical amplifier section; having An optical semiconductor element, wherein a ratio of a metal film covering the first semiconductor layer or the second semiconductor layer is lower in the first region than in the second region.

2. 2 . The optical semiconductor element according to claim 1 , wherein a ratio of the first semiconductor layer or the second semiconductor layer covered by the metal film in the first region is 60% or less in terms of area ratio.

3. 3 . The optical semiconductor element according to claim 2 , wherein a ratio of the first semiconductor layer or the second semiconductor layer covered by the second electrode pad in the first region is equal to or greater than 40% and equal to or less than 60% in terms of area ratio.

4. 2 . The optical semiconductor element according to claim 1 , wherein a ratio of the first semiconductor layer or the second semiconductor layer covered by the metal film in the first region is 20% or less in terms of area ratio.

5. The optical semiconductor element according to claim 1 , further comprising a frame portion connected to the second electrode pad, containing a fourth metal, and provided along an end portion of the first semiconductor layer in a plan view.

6. The optical semiconductor element according to claim 1 , further comprising an identification mark that is provided visibly apart from the second electrode pad and contains a fifth metal.

7. The optical semiconductor device according to claim 1 , wherein the substrate is an indium phosphide substrate.

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