Semiconductor memory device and memory system

Abstract

To provide a semiconductor memory device and a memory system which can shorten time between each operation in a writing operation, a reading operation or an erasure operation.SOLUTION: A semiconductor memory device includes a first memory cell MT capable of storing data, a control circuit for controlling first operation and second operation to the first memory cell, and a voltage generation circuit 17A for outputting a first voltage used in the first operation and a second voltage used in the second operation. The control circuit is configured to maintain the first voltage output from the voltage generation circuit 17A, on the basis of the first command input from outside, to the start of the second operation from the end of the first operation.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device and a memory system. [Background technology]

[0002] As a semiconductor memory device, for example, a NAND flash memory in which memory cells are arranged two-dimensionally or three-dimensionally is known, and a memory system including a NAND flash memory and a memory controller that controls the NAND flash memory is also known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-192338 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device and a memory system capable of shortening the time between write, read, or erase operations. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a first memory cell capable of storing data, a control circuit for controlling a first operation and a second operation for the first memory cell, and a voltage generating circuit for outputting a first voltage used in the first operation and a second voltage used in the second operation. The control circuit is configured to maintain the first voltage output from the voltage generating circuit from the end of the first operation to the start of the second operation based on a first command input from outside. [Brief description of the drawings]

[0006] [Figure 1]1 is a block diagram showing a configuration of a memory system according to a first embodiment. [Diagram 2] 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment. [Diagram 3] 2 is a circuit diagram of a block in the memory cell array according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing a part of a planar layout of the memory cell array according to the first embodiment. [Diagram 5] 5 is a diagram showing a cross section taken along line VV in FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] 2 is a diagram illustrating an example of a configuration of a voltage generating circuit according to the first embodiment. FIG. [Figure 8] 4 is a diagram showing the relationship between possible threshold voltage distributions of the memory cell transistor according to the first embodiment and data. FIG. [Figure 9] FIG. 4 is a diagram showing internal voltages during continuous operation according to the first embodiment. [Figure 10] FIG. 13 is a diagram showing internal voltages during continuous operation in the comparative example. [Figure 11] FIG. 4 is a diagram showing a first example of a command sequence in a write operation according to the first embodiment. [Figure 12] FIG. 11 is a diagram showing a second example of a command sequence in a write operation according to the first embodiment. [Figure 13] FIG. 4 is a diagram showing internal voltages and write voltages in a write operation according to the first embodiment. [Figure 14] FIG. 11 is a diagram showing an internal voltage and a write voltage in a write operation of the comparative example. [Figure 15] FIG. 4 is a diagram showing a first example of a command sequence in a read operation according to the first embodiment. [Figure 16] FIG. 11 is a diagram showing a second example of a command sequence in a read operation according to the first embodiment. [Figure 17] 5 is a diagram showing an internal voltage and a read voltage in a read operation according to the first embodiment. FIG. [Figure 18] FIG. 11 is a diagram showing an internal voltage and a read voltage in a read operation of the comparative example. [Figure 19] FIG. 4 is a diagram showing a first example of a command sequence in an erase operation according to the first embodiment. [Figure 20] FIG. 11 is a diagram showing a second example of a command sequence in an erase operation according to the first embodiment. [Figure 21] FIG. 4 is a diagram showing an internal voltage and an erase voltage in an erase operation according to the first embodiment. [Figure 22] FIG. 11 is a diagram showing an internal voltage and an erase voltage in an erase operation of a comparative example. [Diagram 23] 13 is a diagram showing a first example of command sequences in an erase operation, a write operation, and a read operation according to the second embodiment. FIG. [Figure 24] 13 is a diagram showing a second example of command sequences in an erase operation, a write operation, and a read operation according to the second embodiment. FIG. [Diagram 25] 13A and 13B are diagrams showing internal voltages, erase voltages, write voltages, and read voltages in erase, write, and read operations according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] In the following description, components having the same functions and configurations are given the same reference numerals. Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0008] The functional blocks can be realized as either hardware or computer software, or a combination of both. It is not essential that the functional blocks are differentiated as in the following example. For example, some functions may be performed by a functional block other than the illustrated functional block. Furthermore, the illustrated functional blocks may be further divided into smaller functional subblocks.

[0009] A memory system including a semiconductor memory device and a memory controller according to an embodiment will be described below. As an example of the semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked three-dimensionally above a semiconductor substrate will be taken.

[0010] For example, in a memory system, when a semiconductor memory device is to execute operations such as writing, reading, and erasing data, a memory controller transmits operation commands instructing the semiconductor memory device to write, read, and erase.

[0011] Upon receiving an operation command, the semiconductor memory device uses a voltage generation circuit (or a boost circuit) to generate a voltage required for the operation instructed by the operation command. Hereinafter, the voltage generated by the voltage generation circuit is referred to as an internal voltage, and the process in which the voltage generation circuit boosts the initial voltage to generate the internal voltage is referred to as a boost process.

[0012] Next, the semiconductor memory device performs an operation according to the operation command using the internal voltage. When the operation using the internal voltage is completed, a process (hereinafter referred to as recovery) of lowering the internal voltage to an initial voltage by the voltage generating circuit is performed.

[0013] Thereafter, when the semiconductor memory device receives the next operation command, the semiconductor memory device again uses the voltage generating circuit to generate the internal voltage required for the operation instructed by the operation command, i.e., a boost process is executed in which the initial voltage is boosted again by the voltage generating circuit to generate the internal voltage.

[0014] In this way, the internal voltage recovery and boosting process is repeated between the previous operation and the next operation, so that the time from when the semiconductor memory device receives an operation command to when it starts the operation, and the time from when the previous operation ends to when it is able to start the next operation, become longer. Also, when the period between the previous operation and the next operation is short, repeating the internal voltage recovery and boosting process between each operation may consume more power than maintaining the voltage level (or voltage value) of the internal voltage between each operation.

[0015] In the embodiment described below, the recovery and boost process of the internal voltage is not performed after the end of the previous operation, i.e., the voltage level of the internal voltage is maintained between the previous operation and the subsequent operation, thereby shortening the time between the previous operation and the subsequent operation and suppressing power consumption. Hereinafter, maintaining the voltage level of the internal voltage is also referred to as maintaining the internal voltage.

[0016] 1. First embodiment A memory system including a semiconductor memory device and a memory controller according to a first embodiment will be described.

[0017] 1.1 Memory system configuration The configuration of a memory system according to the first embodiment will be described. Fig. 1 is a block diagram showing the configuration of the memory system according to the first embodiment. The memory system 1 is connected to an external host device 2, and executes various operations in response to commands from the host device 2. The memory system 1 includes a semiconductor memory device 10 and a memory controller 20.

[0018] The semiconductor memory device 10 includes, for example, a NAND flash memory, and stores data in a non-volatile manner. The details of the semiconductor memory device 10 will be described later.

[0019] The memory controller 20 is connected to the semiconductor memory device 10 via a NAND bus. The memory controller 20 controls the semiconductor memory device 10. The NAND bus transmits and receives signals in accordance with a NAND interface. The memory controller 20 is also connected to a host device 2 via a host bus. The memory controller 20 accesses the semiconductor memory device 10 in response to a command received from the host device 2.

[0020] The semiconductor memory device 10 and the memory controller 20 may be combined to form a single semiconductor device, for example. TM Examples of such a memory controller include a memory card including a card, a solid state drive (SSD), etc. Furthermore, the memory controller 20 may be, for example, a system-on-a-chip (SoC) or the like.

[0021] The host device 2 is, for example, a digital camera or a personal computer, and the host bus is, for example, an SD TM It is a bus that conforms to the interface.

[0022] 1.1.1 Memory Controller The configuration of the memory controller 20 will be described with reference to Fig. 1. The memory controller 20 includes a CPU (central processing unit) (or processor) 21, a RAM (random access memory) 22, a ROM (read only memory) 23, an ECC (error checking and correcting) circuit 24, a NAND interface circuit (NAND I / F) 25, and a host interface circuit (host I / F) 26.

[0023] The CPU 21 controls the overall operation of the memory controller 20. For example, when the CPU 21 receives a write command from the host device 2, it responds by issuing a write command to the NAND interface circuit 25. Similarly, when the CPU 21 receives a read command and an erase command, it responds by issuing a read command and an erase command to the NAND interface circuit 25, respectively.

[0024] Furthermore, the CPU 21 executes various processes, such as wear leveling, for managing the semiconductor memory device 10. Note that the operation of the memory controller 20 described below may be realized by the CPU 21 executing software (or firmware), or may be realized by hardware.

[0025] The RAM 22 is used as a working area for the CPU 21. The RAM 22 also temporarily stores firmware for managing the semiconductor memory device 10, various management tables, data, etc. The RAM 22 is, for example, a semiconductor memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0026] The ROM 23 stores, for example, firmware executed by the CPU 21.

[0027] The ECC circuit 24 performs processing related to error detection and correction on write data written to the semiconductor memory device 10 and on read data read from the semiconductor memory device 10 .

[0028] The NAND interface circuit 25 is connected to the semiconductor memory device 10 via a NAND bus and controls communication with the semiconductor memory device 10. The NAND interface circuit 25 transmits various signals, commands, and data to the semiconductor memory device 10 based on instructions received from the CPU 21. The NAND interface circuit 25 also receives various signals and data from the semiconductor memory device 10.

[0029] The host interface circuit 26 is connected to the host device 2 via a host bus and controls communication with the host device 2. The host interface circuit 26 transfers commands and data received from the host device 2 to the CPU 21 and RAM 22, respectively. In addition, the host interface circuit 26 outputs data in the RAM 22 to the host device 2 in response to a command from the CPU 21.

[0030] 1.1.2 Semiconductor memory devices Next, a description will be given of the configuration of the semiconductor memory device 10. Fig. 2 is a block diagram showing the configuration of the semiconductor memory device 10 of the first embodiment.

[0031] The semiconductor memory device 10 includes a memory cell array 11, an input / output circuit 12, a logic control circuit 13, a ready / busy circuit 14, a register group 15, a sequencer (or a control circuit) 16, a voltage generating circuit 17A, a driver 17B, a row decoder 18, a column decoder 19A, a data register 19B, and a sense amplifier 19C. The register group 15 includes a status register 15A, an address register 15B, and a command register 15C.

[0032] The memory cell array 11 includes one or more blocks BLK0, BLK1, BLK2, ..., BLKn (n is an integer equal to or greater than 0). Each of the blocks BLK0 to BLKn includes a plurality of memory cell transistors (hereinafter also referred to as memory cells) associated with rows and columns. The memory cell transistors are non-volatile memory cells that can be electrically erased and programmed. The memory cell array 11 includes a plurality of word lines, a plurality of bit lines, and a source line for applying voltages to the memory cell transistors. A specific configuration of the block BLKn will be described later.

[0033] The input / output circuit 12 and the logic control circuit 13 are connected to the memory controller 20 via input / output terminals (or a NAND bus).

[0034] The input / output circuit 12 transmits / receives input / output signals (I / O signals) DQ (for example, DQ0, DQ1, DQ2, . . . , DQ7) via input / output terminals to / from the memory controller 20. The I / O signals DQ communicate commands, addresses, data, and the like.

[0035] The logic control circuit 13 receives control signals from the memory controller 20 via input / output terminals. The control signals include, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn. The "n" added to the signal name indicates that the signal is active low.

[0036] The chip enable signal CEn is asserted when selecting one of the multiple semiconductor memory devices 10. The command latch enable signal CLE enables a command transmitted as the signal DQ to be latched in the command register 15C. The address latch enable signal ALE enables an address transmitted as the signal DQ to be latched in the address register 15B. The write enable signal WEn enables data transmitted as the signal DQ to be stored in the data register 19B. The read enable signal REn enables data read from the memory cell array 11 to be output as the signal DQ. The write protect signal WPn is asserted when prohibiting a write operation and an erase operation on the semiconductor memory device 10.

[0037] The ready / busy circuit 14 generates a ready / busy signal R / Bn in response to control from the sequencer 16. The ready / busy signal R / Bn indicates whether the semiconductor memory device 10 is in a ready state or a busy state. The ready state indicates that the semiconductor memory device 10 is in a state where it can accept commands from the memory controller 20. The busy state indicates that the semiconductor memory device 10 is in a state where it cannot accept commands from the memory controller 20. By receiving the ready / busy signal R / Bn from the semiconductor memory device 10, the memory controller 20 can know whether the semiconductor memory device 10 is in a ready state or a busy state.

[0038] The status register 15A stores status information STS necessary for the operation of the semiconductor memory device 10. The status register 15A transfers the status information STS to the input / output circuit 12 in accordance with an instruction from the sequencer 16.

[0039] The address register 15B stores an address ADD transferred from the input / output circuit 12. The address ADD includes a row address and a column address. The row address includes, for example, a block address that specifies a block BLKn to be operated, and a page address that specifies a word line WL (e.g., a page) to be operated in the specified block.

[0040] The command register 15C stores the command CMD transferred from the input / output circuit 12. The command CMD includes, for example, a write command that commands the sequencer 16 to perform a write operation, a read command that commands a read operation, and an erase command that commands an erase operation.

[0041] The status register 15A, the address register 15B, and the command register 15C may be implemented by, for example, a static random access memory (SRAM).

[0042] The sequencer 16 receives a command from the command register 15C and performs overall control of the semiconductor memory device 10 in accordance with a sequence based on this command.

[0043] The sequencer 16 controls the voltage generating circuit 17A, the driver 17B, the row decoder 18, the column decoder 19A, the data register 19B, the sense amplifier 19C, etc. to execute the write operation, the read operation, and the erase operation. Specifically, the sequencer 16 controls the voltage generating circuit 17A, the driver 17B, the row decoder 18, and the sense amplifier 19C based on a write command received from the command register 15C to write data to a plurality of memory cell transistors specified by the address ADD. The sequencer 16 also controls the voltage generating circuit 17A, the driver 17B, the row decoder 18, the column decoder 19A, and the sense amplifier 19C based on a read command received from the command register 15C to read data from a plurality of memory cell transistors specified by the address ADD. The sequencer 16 also controls the voltage generation circuit 17A, the driver 17B, the row decoder 18, the column decoder 19A, and the sense amplifier 19C based on the erase command received from the command register 15C, and erases the data stored in the block specified by the address ADD.

[0044] The functions of sequencer 16 described herein may be implemented by sequencer 16 executing software (or firmware), or may be implemented in hardware (or dedicated circuitry).

[0045] The voltage generating circuit 17A receives a power supply voltage VDD and a ground voltage VSS via a power supply terminal from outside the semiconductor memory device 10. The power supply voltage VDD is an external voltage supplied from outside the semiconductor memory device 10. The ground voltage VSS is an external voltage supplied from outside the semiconductor memory device 10, and is, for example, 0 V.

[0046] The voltage generating circuit 17A generates a plurality of voltages required for write, read, and erase operations using a power supply voltage VDD. The voltage generating circuit 17A supplies the generated voltages to the memory cell array 11, the row decoder 18, the sense amplifier 19C, and the like via a driver 17B. A specific configuration of the voltage generating circuit 17A will be described later.

[0047] The driver 17B receives a plurality of voltages from the voltage generating circuit 17A. The driver 17B selects a plurality of voltages from the plurality of voltages supplied from the voltage generating circuit 17A according to a read operation, a write operation, and an erase operation, and supplies the selected voltages to the row decoder 18, the memory cell array 11, and the sense amplifier 19C via a plurality of signal lines. For example, during a write operation, the driver 17B supplies the internal voltages supplied from the voltage generating circuit 17A to the word lines as a write voltage VPGM and a write pass voltage VPASS. For example, during a read operation, the driver 17B supplies the internal voltages supplied from the voltage generating circuit 17A to the word lines as a read voltage VCGRV and a read pass voltage VREAD. Furthermore, for example, during an erase operation, the driver 17B supplies the internal voltages supplied from the voltage generating circuit 17A to the source lines as an erase voltage VERA.

[0048] The row decoder 18 receives a row address from the address register 15B and decodes the row address. Based on the result of decoding the row address, the row decoder 18 selects one of the blocks, and further selects a word line WL in the selected block BLKn. Furthermore, the row decoder 18 transfers a plurality of voltages supplied from the driver 17B to the selected block BLKn.

[0049] The column decoder 19A receives a column address from the address register 15B, decodes the column address, and selects a latch circuit in the data register 19B based on the result of decoding the column address.

[0050] The data register 19B includes a plurality of latch circuits, which temporarily store write data and read data during write and read operations, respectively.

[0051] During a data read operation, the sense amplifier 19C senses and amplifies data read from the memory cell transistor to the bit line. Furthermore, the sense amplifier 19C temporarily stores the read data read from the memory cell transistor and transfers the stored read data to the data register 19B. During a data write operation, the sense amplifier 19C temporarily stores write data transferred from the input / output circuit 12 via the data register 19B. Furthermore, the sense amplifier 19C transfers the write data to the bit line.

[0052] 1.1.2.1 Memory Cell Array Next, the circuit configuration and structure of the memory cell array 11 in the semiconductor memory device 10 of the first embodiment will be described.

[0053] As described above, the memory cell array 11 has a plurality of blocks BLK0 to BLKn. The circuit configuration of the block BLKn will be described below. FIG.

[0054] The block BLKn includes, for example, four string units SU0, SU1, SU2, and SU3. Hereinafter, when a string unit SU is written, this refers to each of the string units SU0 to SU3.

[0055] The string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0, BL1, BL2, ..., BLm (m is an integer equal to or greater than 0). Each NAND string NS includes, for example, memory cell transistors MT0, MT1, MT2, ..., MT7, and select transistors ST1 and ST2. Hereinafter, when a bit line BL is mentioned, it refers to each of the bit lines BL0 to BLm, and when a memory cell transistor MT is mentioned, it refers to each of the memory cell transistors MT0 to MT7.

[0056] The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0057] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. A select transistor ST1 is connected between one end of the series-connected memory cell transistors MT0 to MT7 and the associated bit line BL. The drain of a select transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. A source line SL and a well line CPWELL (not shown) are connected to the source of the select transistor ST2.

[0058] In the same block BLKn, the gates of the multiple selection transistors ST1 included in the string units SU0 to SU3 are commonly connected to the selection gate lines SGD0 to SGD3, respectively. The control gates of the multiple memory cell transistors MT0 to MT7 are commonly connected to the word lines WL0 to WL7, respectively. The gates of the multiple selection transistors ST2 are commonly connected to the selection gate lines SGS0 to SGS3, respectively. Hereinafter, when a selection gate line SGD is mentioned, it refers to each of the selection gate lines SGD0 to SGD3, and when a selection gate line SGS is mentioned, it refers to each of the selection gate lines SGS0 to SGS3.

[0059] The bit lines BL0 to BLm are shared among the multiple blocks BLK0 to BLKn. The same bit line BL is connected to the NAND strings NS corresponding to the same column address. Each of the word lines WL0 to WL7 is provided for each block BLKn. The source line SL is shared among, for example, the multiple blocks BLK0 to BLKn. That is, the source line SL is connected to the sources of the multiple selection transistors ST2 included in the block BLKn.

[0060] The block BLKn is, for example, a unit of data erasure. That is, the data in the multiple blocks BLK0 to BLKn is erased sequentially for each block BLKn. The data stored in the memory cell transistors MT included in the block BLKn is erased all at once.

[0061] A set of multiple memory cell transistors MT connected to a common word line WL in one string unit SU is referred to as a cell unit CU, for example. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." The cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0062] The circuit configuration of the memory cell array 11 described above is merely an example, and is not limited thereto. For example, the number of string units SU included in the block BLKn can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0063] Next, an example of the structure of the memory cell array 11 in the semiconductor memory device 10 of the first embodiment will be described. In the following, a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked three-dimensionally above a semiconductor substrate will be taken as an example of the memory cell array 11.

[0064] In the drawings referred to below, the X direction corresponds to the extension direction of the word lines WL, and the Y direction corresponds to the extension direction of the bit lines BL. Furthermore, the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate on which the semiconductor memory device 10 is formed, in other words, the direction in which the word lines WL are stacked with respect to the surface of the semiconductor substrate. Hatching added to the plan view does not necessarily relate to the material or characteristics of the components to which the hatching is added. In this specification, components such as wiring, contacts, and insulating layers are appropriately omitted to make the drawings easier to understand.

[0065] First, there will be described an example of a planar layout of the memory cell array 11. Fig. 4 is a diagram showing a part of the planar layout of the memory cell array 11 in the first embodiment.

[0066] The memory cell array 11 includes, for example, a plurality of slits SLT, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL.

[0067] The multiple slits SLT are arranged in the Y direction. At least a portion of each slit SLT extends along the X direction. The slits SLT are provided in the same wiring layer and separate adjacent conductive layers via the slits SLT. Specifically, the slits SLT separate multiple wiring layers corresponding to, for example, the word lines WL0 to WL7 and the select gate lines SGD and SGS.

[0068] Each slit SLT includes, for example, a spacer SP and a contact LI. In each slit SLT, at least a part of the contact LI extends in the X direction. The spacer SP is provided on a side surface of the contact LI. The contact LI and a plurality of wiring layers adjacent to the slit SLT are separated and insulated by the spacer SP. The contact LI is used as a source line SL. The contact LI may be a semiconductor or a metal. The spacer SP is an insulating layer and includes, for example, silicon oxide (SiO2).

[0069] Each of the memory pillars MP functions as, for example, one NAND string NS. The memory pillars MP are arranged, for example, in a staggered pattern of four rows in the region between two adjacent slits SLT. This is not limiting, and the number and arrangement of the memory pillars MP between two adjacent slits SLT can be changed as appropriate.

[0070] At least one bit line BL is arranged to overlap each memory pillar MP. The multiple bit lines BL are arranged in the X direction. At least a portion of each bit line BL extends along the Y direction. One of the multiple bit lines BL overlapping a memory pillar MP is electrically connected to the memory pillar MP via a contact CV.

[0071] The planar layout of the memory cell array 11 described above is repeatedly arranged in the Y direction. Each of the regions separated by the slits SLT corresponds to one string unit SU. That is, a set of string units SU0 to SU3 each extending in the X direction is arranged in the Y direction. For example, one contact CV is connected to one bit line BL in each of the spaces separated by the slits SLT.

[0072] Next, a description will be given of an example of a cross-sectional structure of the memory cell array 11. Fig. 5 shows a cross section taken along line VV in Fig. 4, including the memory pillars MP and the slits SLT, and shows a cross section taken along the Y direction.

[0073] The memory cell array 11 includes a semiconductor substrate 30, insulating layers 31 to 35, conductive layers 40 to 44, memory pillars MP, contacts CV, and slits SLT.

[0074] A conductive layer 40 is provided on the semiconductor substrate 30. The conductive layer 40 is formed, for example, in a plate shape extending along the XY plane, and is used as the source line SL. The conductive layer 40 includes, for example, polysilicon doped with phosphorus.

[0075] An insulating layer 31 is provided on the conductive layer 40. A conductive layer 41 is provided on the insulating layer 31. The conductive layer 41 is formed, for example, in a plate shape extending along the XY plane, and is used as a select gate line SGS. The conductive layer 41 includes, for example, polysilicon doped with phosphorus. The select gate line SGS may be composed of a plurality of conductive layers 41. When the select gate line SGS is composed of a plurality of conductive layers 41, the plurality of conductive layers 41 may be composed of conductors different from each other.

[0076] An insulating layer 32 is provided on the conductive layer 41. A conductive layer 42 and an insulating layer 33 are alternately laminated on the insulating layer 32. Each of the plurality of conductive layers 42 is formed, for example, in a plate shape extending along the XY plane. The plurality of conductive layers 42 are used as word lines WL0 to WL7, in order from the conductive layer 40 side. The conductive layer 42 includes, for example, tungsten.

[0077] An insulating layer 34 is provided on the uppermost conductive layer 42. A conductive layer 43 is provided on the insulating layer 34. The conductive layer 43 is formed, for example, in a plate shape extending along the XY plane, and is used as a select gate line SGD. The select gate line SGD may be composed of a plurality of conductive layers 43. The conductive layer 43 includes, for example, tungsten.

[0078] An insulating layer 35 is provided on the conductive layer 43. A conductive layer 44 is provided on the insulating layer 35. The conductive layer 44 is formed, for example, in a line shape extending in the Y direction and is used as a bit line BL. In a region not shown, a plurality of conductive layers 44 are arranged in the X direction. The conductive layer 44 contains, for example, copper.

[0079] Each memory pillar MP extends along the Z direction. Each memory pillar MP penetrates the insulating layers 31 to 34 and the conductive layers 41 to 43. The lower part of the memory pillar MP contacts the conductive layer 40. The upper part of the memory pillar MP reaches the insulating layer 35.

[0080] Each memory pillar MP includes, for example, a semiconductor layer 50, a tunnel insulating layer (also referred to as a tunnel insulating film) 51, a charge storage layer (for example, an insulating layer) 52, and a block insulating layer 53.

[0081] The semiconductor layer 50 extends along the Z direction. For example, the lower end of the semiconductor layer 50 is in contact with the conductive layer 40. The upper end of the semiconductor layer 50 is included in a layer including the insulating layer 35. The tunnel insulating layer 51 is disposed on a side surface of the semiconductor layer 50. The charge storage layer 52 is disposed on a side surface of the tunnel insulating layer 51. The block insulating layer 53 is disposed on a side surface of the charge storage layer 52.

[0082] A portion where the memory pillar MP intersects with the conductive layer 41 (i.e., the select gate line SGS) functions as a select transistor ST2. A portion where the memory pillar MP intersects with a plurality of conductive layers 42 (i.e., the word lines WL) functions as memory cell transistors MT0 to MT7. A portion where the memory pillar MP intersects with the conductive layer 43 (i.e., the select gate line SGD) functions as a select transistor ST1. The semiconductor layer 50 functions as the channel layers of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. A current path of the NAND string NS is formed inside the semiconductor layer 50. The charge storage layer 52 functions as a layer that stores the charge of the memory cell transistor MT.

[0083] A columnar contact CV is provided on the semiconductor layer 50 of each memory pillar MP. In the illustrated region, a contact CV corresponding to one of the two memory pillars MP is shown. A contact CV is connected to the memory pillar MP to which the contact CV is not connected in the corresponding region in a region not shown. One conductive layer 44 (i.e., a bit line BL) is in contact with the contact CV.

[0084] The slit SLT includes, for example, a spacer SP and a contact LI. At least a part of the slit SLT is formed in a plate shape extending along the XZ plane, and divides the insulating layers 31 to 34 and the conductive layers 41 to 43. The lower end of the slit SLT contacts, for example, the conductive layer 40. The upper end of the slit SLT is included in a layer including the insulating layer 35. In the slit SLT, at least a part of the contact LI extends in the X direction. The spacer SP is provided on a side surface of the contact LI. The contact LI and the multiple conductive layers 41 to 43 are separated and insulated by the spacer SP.

[0085] Next, a description will be given of the cross-sectional structure of the memory pillar MP in the memory cell array 11. Fig. 6 shows a cross section taken along line VI-VI in Fig. 5, illustrating a cross section of the memory pillar MP in a layer parallel to the surface of the semiconductor substrate 30 and including the conductive layer 42.

[0086] As described above, the memory pillar MP has, for example, a semiconductor layer 50, a tunnel insulating layer 51, a charge storage layer 52, and a block insulating layer 53. Specifically, the semiconductor layer 50 is provided, for example, in the center of the memory pillar MP. The tunnel insulating layer 51 surrounds the side surface of the semiconductor layer 50. The charge storage layer 52 surrounds the side surface of the tunnel insulating layer 51. The block insulating layer 53 surrounds the side surface of the charge storage layer 52. The conductive layer 42 surrounds the side surface of the block insulating layer 53. Note that the memory pillar MP may have a structure in which a core insulating layer is provided inside the semiconductor layer 50.

[0087] The tunnel insulating layer 51 functions as a potential barrier when charges are injected from the semiconductor layer 50 to the charge storage layer 52, or when charges stored in the charge storage layer 52 diffuse to the semiconductor layer 50. The tunnel insulating layer 51 includes, for example, silicon oxide (SiO2).

[0088] The charge storage layer 52 has a function of storing charges injected into the memory cell transistors MT0 to MT7 from the semiconductor layer 50. The charge storage layer 52 includes, for example, silicon nitride (SiN).

[0089] The block insulating layer 53 prevents the charge stored in the charge storage layer 52 from diffusing to the conductive layer 42 (word line WL). The block insulating layer 53 includes, for example, an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0090] 1.1.2.2 Voltage Generation Circuit Next, the configuration of the voltage generating circuit 17A in the semiconductor memory device 10 of the first embodiment will be described.

[0091] As described above, the voltage generating circuit 17A generates a plurality of voltages required for the write operation, read operation, and erase operation using the power supply voltage VDD. Fig. 7 is a diagram showing an example of the configuration of the voltage generating circuit 17A.

[0092] The voltage generating circuit 17A includes boosting circuits 171, 172, 173, 174, and 175. The boosting circuits 171, 172, 173, 174, and 175 generate a plurality of internal voltages used in, for example, a write operation, a read operation, or an erase operation.

[0093] The boost circuit 171 generates and outputs an internal voltage VI1 used during a write operation. The boost circuit 172 generates and outputs an internal voltage VI2 used during a write operation. In a write operation, the internal voltage VI1 output from the boost circuit 171 is supplied as a write voltage VPGM to a word line (or a selected word line) WLsel to be written to via the driver 17B and the row decoder 18. The internal voltage VI2 output from the boost circuit 172 is supplied as a write pass voltage VPASS to a word line (or a non-selected word line) WLusel to be not to be written to via the driver 17B and the row decoder 18.

[0094] The boost circuit 173 generates and outputs an internal voltage VI3 used during a read operation. The boost circuit 174 generates and outputs an internal voltage VI4 used during a read operation. In a read operation, the internal voltage VI3 output from the boost circuit 173 is supplied to a word line to be read (or a selected word line) WLsel as a read voltage VCGRV via the driver 17B and the row decoder 18. The internal voltage VI4 output from the boost circuit 174 is supplied to a word line not to be read (or a non-selected word line) WLusel as a read pass voltage VREAD via the driver 17B and the row decoder 18.

[0095] The boost circuit 175 generates and outputs an internal voltage VI5 used during an erase operation. During an erase operation, the internal voltage VI5 output from the boost circuit 175 is supplied as an erase voltage VERA to the source line SL of the block to be erased (or the selected block) via the driver 17B.

[0096] 1.1.3 Threshold voltage distribution of memory cell transistors Next, the relationship between the possible threshold voltage distribution of the memory cell transistor MT and data will be described below. Fig. 8 is a diagram showing the relationship between the possible threshold voltage distribution of the memory cell transistor MT and data.

[0097] Here, an example is shown in which a triple-level cell (TLC) method capable of storing three bits of data in one memory cell transistor MT is applied as the storage method for the memory cell transistor MT. Note that this embodiment can also be applied to cases where other storage methods are used, such as a single-level cell (SLC) method capable of storing one bit of data in one memory cell transistor MT, a multi-level cell (MLC) method capable of storing two bits of data in one memory cell transistor MT, or a quad-level cell (QLC) method capable of storing four bits of data in one memory cell transistor MT.

[0098] The three bits of data that the memory cell transistor MT can store are defined by a lower bit, a middle bit, and an upper bit. When the memory cell transistor MT stores three bits, the memory cell transistor MT can take one of eight states corresponding to a plurality of threshold voltages. The eight states are called states "Er", "A", "B", "C", "D", "E", "F", and "G" in order from the lowest. The multiple memory cell transistors MT belonging to each of the states "Er", "A", "B", "C", "D", "E", "F", and "G" form a threshold voltage distribution as shown in FIG. 6.

[0099] States "Er", "A", "B", "C", "D", "E", "F", and "G" are assigned data "111", "110", "100", "000", "010", "011", "001", and "101", for example. The bit arrangement is "Z, Y, X", with lower bit "X", middle bit "Y", and upper bit "Z". The allocation of threshold voltage distributions and data can be set arbitrarily.

[0100] In order to read data stored in the memory cell transistor MT to be read, the state to which the threshold voltage of the memory cell transistor MT belongs is determined. To determine the state, read voltages AR, BR, CR, DR, ER, FR, and GR are used. Hereinafter, the voltages applied to the memory cell transistor MT to be read to determine the level, including the read voltages AR, BR, CR, DR, ER, FR, and GR, may be referred to as read voltages VCGRV.

[0101] The state "Er" corresponds to, for example, a state in which data is erased (erased state). The threshold voltage of the memory cell transistor MT belonging to the state "Er" is lower than the voltage AR and has, for example, a negative value.

[0102] States "A" to "G" correspond to states in which charges are injected into the charge storage layer and data is written to the memory cell transistor MT, and the threshold voltages of the memory cell transistors MT belonging to states "A" to "G" have, for example, positive values. The threshold voltage of the memory cell transistor MT belonging to state "A" is higher than the read voltage AR and is lower than the read voltage BR. The threshold voltage of the memory cell transistor MT belonging to state "B" is higher than the read voltage BR and is lower than the read voltage CR. The threshold voltage of the memory cell transistor MT belonging to state "C" is higher than the read voltage CR and is lower than the read voltage DR. The threshold voltage of the memory cell transistor MT belonging to state "D" is higher than the read voltage DR and is lower than the read voltage ER. The threshold voltage of the memory cell transistor MT belonging to state "E" is higher than the read voltage ER and is lower than the read voltage FR. The threshold voltage of the memory cell transistor MT belonging to state "F" is higher than the read voltage FR and is lower than the read voltage GR. The threshold voltage of the memory cell transistor MT belonging to state "G" is higher than the read voltage GR and is lower than the voltage VREAD.

[0103] The voltage VREAD is applied to the word line WL connected to the memory cell transistor MT of the cell unit CU that is not the target of reading, and is higher than the threshold voltage of the memory cell transistor MT in any state. Therefore, the memory cell transistor MT to which the voltage VREAD is applied is turned on regardless of the data it holds.

[0104] In addition, verify voltages used in the write operation are set between adjacent threshold distributions. Specifically, verify voltages AV, BV, CV, DV, EV, FV, and GV are set corresponding to states "A", "B", "C", "D", "E", "F", and "G", respectively. For example, the verify voltages AV, BV, CV, DV, EV, FV, and GV are set slightly higher than the read voltages AR, BR, CR, DR, ER, FR, and GR, respectively.

[0105] As described above, each memory cell transistor MT can be set to one of eight states and store three-bit data. Moreover, writing and reading are performed in units of pages in one cell unit CU. When the memory cell transistor MT stores three-bit data, the lower bit, the middle bit, and the upper bit are respectively assigned to three pages in one cell unit CU. The pages in which the lower bit, the middle bit, and the upper bit are written in one write operation or the pages in which the upper bit is read in one read operation, that is, the set of the lower bit, the set of the middle bit, and the set of the upper bit held by the cell unit CU, are called the lower page, the middle page, and the upper page, respectively.

[0106] When the above data mapping is applied, the lower page is determined by a read operation using read voltages AR and ER, the middle page is determined by a read operation using read voltages BR, DR and FR, and the upper page is determined by a read operation using read voltages CR and GR.

[0107] 1.2 Memory System Operation The operation of the semiconductor memory device 10 and the operation of the memory system 1 according to the first embodiment will be described.

[0108] First, an overview of the operation of the semiconductor memory device 10 of the first embodiment will be described.

[0109] Here, it is assumed that the semiconductor memory device 10 knows that writing, reading, or erasing is performed consecutively. For example, the semiconductor memory device 10 may know that the operations are performed consecutively by a command sent from the memory controller 20, or may know by using another means. Hereinafter, the two operations performed consecutively in the semiconductor memory device 10 are referred to as a first operation and a second operation.

[0110] Fig. 9 is a diagram showing the internal voltage during continuous operation in the first embodiment, in which the horizontal axis represents time and the vertical axis represents voltage.

[0111] Before the start of the first operation, the voltage generation circuit 17A boosts an initial voltage (e.g., power supply voltage VDD) to generate an internal voltage. The internal voltage is boosted to an operating voltage. The semiconductor memory device 10 executes the first operation using the internal voltage. When the first operation ends, the semiconductor memory device 10 does not step down the internal voltage generated by the voltage generation circuit 17A, i.e., does not execute recovery, and maintains the voltage level (or voltage value) of the internal voltage. Subsequently, the semiconductor memory device 10 executes the second operation using the internal voltage generated by the voltage generation circuit 17A after the end of the first operation.

[0112] The continuous operation of the comparative example will be described below, and the first embodiment and the comparative example will be compared.

[0113] FIG. 10 shows the internal voltage in successive operations of the comparative example. In the comparative example, the semiconductor memory device executes a first operation using the internal voltage. When the first operation is completed, the semiconductor memory device recovers the internal voltage generated by the voltage generating circuit and reduces the internal voltage to the initial voltage. Thereafter, the semiconductor memory device again executes a boost process in which the voltage generating circuit boosts the initial voltage to the internal voltage, thereby generating the internal voltage. Next, the semiconductor memory device 10 executes a second operation using the internal voltage generated through the recovery and boost processes after the first operation is completed.

[0114] As described above, in the embodiment, the recovery and boost process performed in the comparative example can be omitted. This makes it possible to shorten the time between the first operation and the second operation. That is, it is possible to shorten the time from the end of the first operation to the start of the second operation. In addition, when the period from the first operation to the second operation is short, it is also possible to suppress the power consumption that occurs when the first operation and the second operation are executed consecutively.

[0115] Hereinafter, the operating mode in which the semiconductor memory device 10 is set so that after performing the first operation using the internal voltage, the internal voltage used in the first operation output from the voltage generating circuit 17A is not lowered and the voltage level of the internal voltage is maintained is referred to as the voltage suspension mode.

[0116] Next, a description will be given of the operation of the memory system 1 of the first embodiment. The following describes the operation when a write operation, a read operation, and an erase operation are each performed consecutively.

[0117] 1.3 When performing continuous write operations The operation when the write operations are performed continuously will be described.

[0118] For example, we will consider a case where a memory cell transistor MT can store 3-bit data, and a lower page, a middle page, and an upper page are written to one cell unit CU, i.e., memory cell transistors connected to one word line.

[0119] 1.3.1 First Example In the first example, before transmitting a command related to a write operation from the memory controller 20 to the semiconductor memory device 10, a command instructing the semiconductor memory device 10 to enter the voltage suspension mode is transmitted from the memory controller 20 to the semiconductor memory device 10. As a result, the semiconductor memory device 10 is set to the voltage suspension mode.

[0120] When the voltage suspension mode is set, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage generated during the successive write operations commanded by the command, even after one write operation is completed, until the successive write operations are completed. After that, after the successive write operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released, and the voltage generation circuit 17A reduces the internal voltage to the initial voltage.

[0121] FIG. 11 is a diagram showing a first example of a command sequence in a write operation in the first embodiment.

[0122] Before transmitting a command related to a write operation from the memory controller 20 to the semiconductor memory device 10, a predetermined prefix command "XXh" is transmitted. This prefix command "XXh" is a command commanding a voltage suspension mode, and commands the voltage generating circuit 17A to generate (or output) the same internal voltage that it generated (or output) during a write operation until the successive write operations by the commands transmitted thereafter are completed, even after one write operation is completed. Note that X in the prefix command "XXh" is a predetermined hexadecimal number, and h indicates that XX is a hexadecimal number. The same applies to X and h in other commands.

[0123] 11, first, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the prefix command "XXh" to the semiconductor memory device 10. The prefix command "XXh" is a command that instructs the semiconductor memory device 10 to enter the voltage suspension mode.

[0124] Upon receiving the prefix command "XXh", the sequencer 16 of the semiconductor memory device 10 maintains the internal voltage output from the voltage generating circuit 17A as it is from the end of the first write operation to the start of the subsequent second write operation based on the prefix command "XXh". That is, the internal voltage output from the voltage generating circuit 17A is maintained as it is for a predetermined time from the end of the first write operation to the start of the second write operation.

[0125] Next, the memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit the commands "01h" and "80h" to the semiconductor memory device 10. The command "01h" is a page selection command, and is a command that notifies that the command, address, and data transmitted following the command "01h" are related to the lower page. The command "80h" is a command that notifies of a write operation and input of data.

[0126] Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit addresses "CA1, CA2, RA1, RA2, and RA3" and data "WD1" to the semiconductor memory device 10. The data "WD1" is lower page data as data to be written. The addresses "CA1, CA2, RA1, RA2, and RA3" are addresses that specify a memory location to which the data "WD1" is written. The addresses "CA1 and CA2" are column addresses that specify a memory location on the column side. The addresses "RA1, RA2, and RA3" are row addresses that specify a memory location on the row side. That is, the addresses "CA1, CA2, RA1, RA2, and RA3" specify memory cell transistors connected to the word lines to which the lower page data is to be written. Here, the addresses are shown in five cycles, but the number of cycles is arbitrary.

[0127] Next, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the command "1Ah" to the semiconductor memory device 10. The command "1Ah" is a command to instruct the semiconductor memory device 10 to store the data "WD1" in the first latch circuit in the sense amplifier 19C. Upon receiving the command "1Ah", the sequencer 16 of the semiconductor memory device 10 temporarily stores the data "WD1" in the first latch circuit in the sense amplifier 19C at time tDC.

[0128] Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit commands "02h" and "80h" to the semiconductor memory device 10. The command "02h" is a page selection command, and is a command notifying that the command, address, and data transmitted following the command "02h" are related to the middle page. The command "80h" is a command notifying a write operation and input of data.

[0129] Next, the memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit the addresses "CA1, CA2, RA1, RA2, and RA3" and the data "WD2" to the semiconductor memory device 10. The data "WD2" is the middle page data as the data to be written. The addresses "CA1, CA2, RA1, RA2, and RA3" are addresses that specify the memory location to which the data "WD2" is written. The addresses "CA1 and CA2" are column addresses that specify the memory location on the column side. The addresses "RA1, RA2, and RA3" are row addresses that specify the memory location on the row side. In other words, the addresses "CA1, CA2, RA1, RA2, and RA3" specify the memory cell transistors connected to the word line to which the middle page data is to be written. Note that, although the addresses are shown in five cycles here, the number of cycles is arbitrary.

[0130] Next, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the command "1Ah" to the semiconductor memory device 10. The command "1Ah" is a command to instruct the semiconductor memory device 10 to store the data "WD2" in the second latch circuit in the sense amplifier 19C. Upon receiving the command "1Ah", the sequencer 16 temporarily stores the data "WD2" in the second latch circuit in the sense amplifier 19C at time tDC.

[0131] Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit commands "03h" and "80h" to the semiconductor memory device 10. The command "03h" is a page selection command, and is a command that notifies that the command, address, and data transmitted following the command "03h" are related to the upper page. The command "80h" is a command that notifies of a write operation and input of data.

[0132] Next, the memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit the addresses "CA1, CA2, RA1, RA2, and RA3" and the data "WD3" to the semiconductor memory device 10. The data "WD3" is the upper page data as the data to be written. The addresses "CA1, CA2, RA1, RA2, and RA3" are addresses that specify the memory location to which the data "WD3" is written. The addresses "CA1 and CA2" are column addresses that specify the memory location on the column side. The addresses "RA1, RA2, and RA3" are row addresses that specify the memory location on the row side. That is, the addresses "CA1, CA2, RA1, RA2, and RA3" specify the memory cell transistors connected to the word line to which the upper page data is to be written. Here, the addresses are shown as five cycles, but the number of cycles is arbitrary.

[0133] Next, the memory controller 20 uses the signals DQ0 to DQ7 to send the command "10h" to the semiconductor memory device 10. The command "10h" is a command to instruct the execution of a write operation, that is, the start of a program operation described later. Upon receiving the command "10h", the sequencer 16 writes data "WD1, WD2, and WD3", that is, the lower page data, the middle page data, and the upper page data, to the memory cell transistors specified by the addresses at time tPR.

[0134] 1.3.2 Second Example In the second example, before a command related to a write operation is sent from the memory controller 20 to the semiconductor memory device 10, the semiconductor memory device 10 is set to the voltage suspension mode using a "Set Feature" command. When the semiconductor memory device 10 is set to the voltage suspension mode by the "Set Feature" command, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage that was generated during the write operation even after the write operation is completed. After that, after the successive write operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released using the "Set Feature" command again.

[0135] FIG. 12 is a diagram showing a second example of a command sequence in a write operation in the first embodiment.

[0136] The memory controller 20 transmits commands, addresses, and data as shown in (1), (2), (3), and (4) in FIG.

[0137] First, (1) parameters are set using the "Set Feature" command to set the semiconductor memory device 10 in voltage suspension mode. Next, (2) parameters are acquired using the "Get Feature" command. Note that the purpose of acquiring parameters using the "Get Feature" command is to check whether the parameters have been set correctly, and there are cases where the parameter acquisition is not performed. Next, (3) a write operation is executed. After that, (4) parameters are set using the "Set Feature" command to release the voltage suspension mode that has been set in the semiconductor memory device 10.

[0138] Below, these points (1) to (4) are described in detail.

[0139] (1) Setting the voltage suspension mode First, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN (Logical Unit Number) address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" is a command to notify that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" is an address that specifies the unit to be set by the "Set Feature" command. The feature address "XXh" indicates the address where the parameters to be set by the "Set Feature" command are stored.

[0140] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. By setting these parameters, the semiconductor memory device 10 is set to a voltage suspension mode. When set to the voltage suspension mode, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate (or output) the same internal voltage that it generated (or output) during the write operation, even after the write operation is completed.

[0141] (2) Obtaining parameters using the get feature The memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit a command “D4h”, a LUN address “XXh”, and a feature address “XXh” to the semiconductor memory device 10. The command “D4h” is a command to notify that the address transmitted following the command “D4h” is related to the acquisition of parameters by the “Get Feature” command. The LUN address “XXh” is an address that designates a unit to be acquired by the “Get Feature” command. The feature address “XXh” indicates an address where the parameters acquired by the “Get Feature” command are stored. As a result, the parameters set by the “Set Feature” command are read in the semiconductor memory device 10. Then, the read data R0, R1, R2, and R3 are transmitted from the semiconductor memory device 10 to the memory controller 20. As a result, the memory controller 20 can know whether the parameters set by the “Set Feature” command have been set correctly, i.e., whether the semiconductor memory device 10 has been set to the voltage suspension mode.

[0142] (3) Write operation The write operation is similar to that in the first example, except for the prefix command "XXh".

[0143] First, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit commands "01h" and "80h" to the semiconductor memory device 10. Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit addresses "CA1, CA2, RA1, RA2, and RA3" and data "WD1" to the semiconductor memory device 10. Furthermore, the memory controller 20 transmits command "1Ah" to the semiconductor memory device 10 using signals DQ0 to DQ7.

[0144] Next, the memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit the commands "02h" and "80h" to the semiconductor memory device 10. Next, the memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit the addresses "CA1, CA2, RA1, RA2, and RA3" and the data "WD2" to the semiconductor memory device 10. Furthermore, the memory controller 20 transmits the command "1Ah" to the semiconductor memory device 10 using the signals DQ0 to DQ7.

[0145] Next, the memory controller 20 sequentially transmits commands "03h" and "80h" to the semiconductor memory device 10 using signals DQ0 to DQ7. Next, the memory controller 20 sequentially transmits addresses "CA1, CA2, RA1, RA2, and RA3" and data "WD3" to the semiconductor memory device 10 using signals DQ0 to DQ7. Furthermore, the memory controller 20 transmits command "10h" to the semiconductor memory device 10 using signals DQ0 to DQ7. Upon receiving command "10h", the sequencer 16 writes data "WD1, WD2, and WD3", i.e., lower page data, middle page data, and upper page data, to memory cell transistors designated by the addresses at time tPR.

[0146] (4) Canceling the voltage suspension mode The memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" indicates that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" and the feature address "XXh" are the same as described above.

[0147] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. Setting these parameters cancels the voltage suspension mode set in the semiconductor memory device 10. When the voltage suspension mode is canceled, the voltage generation circuit 17A of the semiconductor memory device 10 reduces the internal voltage that was generated during the write operation to the initial voltage when the write operation is completed.

[0148] As described above, the voltage suspension mode is set and released during a write operation using the "Set Feature" command.

[0149] 1.3.3 Write operations in the first and second examples The write operation to the memory cell transistor executed in the above-mentioned first and second examples will be described.

[0150] As described above, in a write operation, the internal voltage VI1 output from the boost circuit 171 of the voltage generation circuit 17A is supplied as a write voltage VPGM to the selected word line WLsel to be written to via the driver 17B and the row decoder 18. Here, the internal voltage VI1 output from the boost circuit 171 and the write voltage VPGM supplied to the selected word line WLsel to be written to will be described as an example.

[0151] Fig. 13 is a diagram showing the internal voltage VI1 and the write voltage VPGM in the write operation of the first embodiment. In Fig. 13, the write voltage VPGM is indicated by a solid line, and the internal voltage VI1 is indicated by a dashed line.

[0152] The write operation includes a program operation and a program verify operation. The program operation is an operation in which, for example, charges are injected into the insulating layer (i.e., charge storage layer) 52 of the memory cell transistor by applying a write voltage VPGM to the gate electrode of the memory cell transistor, thereby increasing the threshold voltage of the memory cell transistor. The program verify operation is a read operation that verifies whether the threshold voltage of the memory cell transistor generated by the application of the write voltage VPGM has reached a target voltage.

[0153] A write operation is performed multiple times on multiple cell units using multiple write voltages VPGM. The Nth and (N+1)th write operations shown in FIG. 13 respectively show write operations to memory cell transistors connected to two word lines among the write operations performed on memory cell transistors connected to multiple word lines. In the Nth write operation, the internal voltage VI1 output from the boost circuit 171 is supplied to the first selected word line WLsel as the write voltage VPGM. In the (N+1)th write operation, the internal voltage VI1 is set to the write voltage VPGM and supplied to the second selected word line WLsel.

[0154] The Nth write operation is performed as follows.

[0155] 13, at time t1, a program operation is executed on the memory cell transistors using a write voltage VPGM. In this program operation, an internal voltage VI1 is output from the boost circuit 171 of the voltage generating circuit 17A, and the internal voltage VI1 is supplied to the selected word line WLsel to be written as a write voltage VPGM.

[0156] Subsequently, at time t2, a program verify operation is executed on the memory cell transistors using the verify voltage VVE In this program verify operation, the verify voltage VVE is supplied to the selected word line WLsel.

[0157] In the program verify operation, if the threshold voltage of the memory cell transistor does not reach a predetermined threshold voltage, i.e., if the program verify operation fails, the write voltage VPGM is increased by a constant voltage ΔV, the program operation is executed again, and then the program verify operation is executed. Then, the program operation and the program verify operation are repeatedly executed until the program verify operation passes.

[0158] In the program verify operation, when the threshold voltage of the memory cell transistor reaches a predetermined threshold voltage, that is, when the program verify operation passes the verify, the Nth write operation ends.

[0159] The internal voltage VI1 output from the boost circuit 171 is set to the write voltage VPGM in the first program operation in the Nth write operation. After that, every time the program operation is repeated, the voltage is boosted by a constant voltage ΔV and set to the write voltage "VPGM+R·ΔV", where R indicates the number of times the program operation is repeated.

[0160] When the Nth write operation is completed, the internal voltage VI1 (i.e., the write voltage VPGM) generated by the boost circuit 171 at the end of the Nth write operation is generated and output by the boost circuit 171 as is until the (N+1)th write operation is started.

[0161] In a write operation, multiple states are written to a memory cell transistor. In a program verify operation, multiple verify voltages are used according to the multiple written states. For example, when the seven states "A" to "G" described above are written, verify voltages AV to GV are used according to the states "A" to "G", respectively. Here, these multiple verify voltages are collectively referred to as a verify voltage VVE, or any one of the multiple verify voltages is referred to as a verify voltage VVE.

[0162] Next, the (N+1)th write operation is performed as follows.

[0163] At time t3, a program operation is executed on the memory cell transistors using the write voltage VPGM. In this program operation, the internal voltage VI1 (i.e., the write voltage VPGMa) generated by the boost circuit 171 at the end of the Nth write operation is set to the write voltage VPGM and supplied to the selected word line WLsel.

[0164] Subsequently, at time t4, a program verify operation is executed on the memory cell transistors using the verify voltage VVE In this program verify operation, the verify voltage VVE is supplied to the selected word line WLsel.

[0165] If the program verify operation fails, the write voltage VPGM is increased by a constant voltage ΔV, the program operation is executed again, and then the program verify operation is executed. Then, the program operation and the program verify operation are repeatedly executed until the program verify operation passes.

[0166] If the program verify operation passes the verify, the (N+1)th write operation is completed.

[0167] The internal voltage VI1 output from the boost circuit 171 is set to the write voltage VPGM in the first program operation in the (N+1)th write operation. After that, every time the program operation is repeated, the voltage is boosted by a constant voltage ΔV and set to the write voltage "VPGM+R·ΔV", where R indicates the number of times the program operation is repeated.

[0168] When the (N+1)th write operation is completed, the internal voltage VI1 is maintained at the write voltage VPGMa used in the last program operation in the (N+1)th write operation.

[0169] The write operation of the comparative example will be described below, and the first embodiment and the comparative example will be compared.

[0170] 14 shows the internal voltage VI1 and the write voltage VPGM in a write operation in the comparative example. In this comparative example, after the Nth write operation is completed, the internal voltage VI1 (i.e., the write voltage VPGMa) generated by the boost circuit 171 is stepped down to an initial voltage (e.g., the power supply voltage VDD). Then, in the first program operation of the (N+1)th write operation, the internal voltage VI1 of the boost circuit 171 is stepped up to the write voltage VPGM and used for the program operation. For this reason, in the comparative example, time is required to step down the internal voltage VI1 from the write voltage VPGMa to the initial voltage and then to step up from the initial voltage to the write voltage VPGM.

[0171] In contrast, in the write operation of the first embodiment, the internal voltage VI1 (i.e., the voltage VPGMa) generated by the boost circuit 171 at the end of the Nth write operation is used for the first program operation in the (N+1)th write operation. That is, the internal voltage VI1 (i.e., the voltage VPGMa) of the boost circuit 171 is set to the voltage VPGM and supplied to the selected word line WLsel.

[0172] Since the voltage difference between the write voltage VPGMa and the write voltage VPGM is small, the time required to set the internal voltage VI1 from the voltage VPGMa to the voltage VPGM is shorter than the time required to boost the internal voltage VI1 from the initial voltage to the write voltage VPGM. This makes it possible to shorten the time between the Nth write operation and the (N+1)th write operation. In other words, the time from the end of the Nth write operation to the start of the (N+1)th write operation can be shortened.

[0173] Although the write voltage VPGM and the internal voltage VI1 of the boost circuit 171 have been described above, the present invention is not limited to this. The same applies to other voltages used in the write operation and the corresponding internal voltages of the boost circuit. If the internal voltage is maintained at the end of the Nth write operation and this internal voltage is used for the (N+1)th write operation, the time from the end of the Nth write operation to the start of the (N+1)th write operation can be shortened.

[0174] 1.4 When performing continuous read operations The operation when the read operations are performed continuously will be described.

[0175] For example, when a memory cell transistor MT stores 3-bit data, multiple read operations are performed on one cell unit CU, i.e., the memory cell transistors connected to one word line, and data of the lower page, middle page, and upper page are read.

[0176] 1.4.1 First Example In the first example, before transmitting a command related to a read operation from the memory controller 20 to the semiconductor memory device 10, a command instructing the semiconductor memory device 10 to enter the voltage suspension mode is transmitted from the memory controller 20 to the semiconductor memory device 10. As a result, the semiconductor memory device 10 is set to the voltage suspension mode.

[0177] When the voltage suspension mode is set, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage generated during one read operation until the successive read operations commanded by the command are completed, even if one read operation is completed. After that, after the successive read operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released, and the voltage generation circuit 17A reduces the internal voltage to the initial voltage.

[0178] FIG. 15 is a diagram showing a first example of a command sequence in a read operation in the first embodiment.

[0179] Before transmitting a command related to a read operation from the memory controller 20 to the semiconductor memory device 10, a predetermined prefix command "XXh" is transmitted. This prefix command "XXh" is a command commanding a voltage suspension mode, and commands the voltage generating circuit 17A to generate (or output) the internal voltage that it generated (or output) during the read operation as is until the successive read operations by the commands transmitted thereafter are completed, even after one read operation is completed. Note that X in the prefix command "XXh" is a predetermined hexadecimal number, and h indicates that XX is a hexadecimal number. The same applies to X and h in other commands.

[0180] 15, first, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the prefix command "XXh" to the semiconductor memory device 10. The prefix command "XXh" is a command that commands the semiconductor memory device 10 to enter the voltage suspension mode.

[0181] Upon receiving the prefix command "XXh", the sequencer 16 of the semiconductor memory device 10 maintains the internal voltage output from the voltage generating circuit 17A as it is from the end of the first read operation to the start of the subsequent second read operation based on the prefix command "XXh". That is, the internal voltage output from the voltage generating circuit 17A is maintained as it is for a predetermined time from the end of the first read operation to the start of the second read operation.

[0182] Next, the memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit the command "PC" and the command "00h" to the semiconductor memory device 10. The command "PC" is the command "01h", or "02h", or "03h". The command "01h" is a command notifying that the command, address, and data transmitted following this command "01h" are related to the lower page. The command "02h" is a command notifying that the command, address, and data transmitted following this command "02h" are related to the middle page. The command "03h" is a command notifying that the command, address, and data transmitted following this command "03h" are related to the upper page. The command "00h" is a command notifying that a read operation and an address input are required.

[0183] Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit addresses "CA1, CA2, RA1, RA2, and RA3" to the semiconductor memory device 10. The addresses "CA1, CA2, RA1, RA2, and RA3" are addresses that specify memory locations to be read in the memory cell array 11. The addresses "CA1 and CA2" are column addresses that specify memory locations on the column side. The addresses "RA1, RA2, and RA3" are row addresses that specify memory locations on the row side. In other words, the addresses "CA1, CA2, RA1, RA2, and RA3" specify memory cell transistors that are targets for reading page data indicated by the command "PC". Although the addresses are shown here as five cycles, the number of cycles is arbitrary.

[0184] Next, the memory controller 20 uses the signals DQ0 to DQ7 to send the command "30h" to the semiconductor memory device 10. The command "30h" is a command to start a read operation on the memory cell transistor to be read. Upon receiving the command "30h", the sequencer 16 reads the data stored in the memory cell transistor specified by the address.

[0185] Next, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the command "05h" to the semiconductor memory device 10. The command "05h" is a command for notifying data output and address input.

[0186] Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit addresses “CA1, CA2, RA1, RA2, and RA3” to the semiconductor memory device 10. The addresses “CA1, CA2, RA1, RA2, and RA3” are addresses of read data to be output.

[0187] Next, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the command "E0h" to the semiconductor memory device 10. The command "E0h" is a command to instruct the memory controller 20 to output read data specified by the address. Upon receiving the command "E0h", the sequencer 16 outputs the read data specified by the address to the memory controller 20.

[0188] 1.4.2 Second Example In the second example, before a command related to a read operation is sent from the memory controller 20 to the semiconductor memory device 10, the semiconductor memory device 10 is set to the voltage suspension mode using a "Set Feature" command. When the semiconductor memory device 10 is set to the voltage suspension mode by the "Set Feature" command, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage that was generated during the read operation even after the read operation is completed. After that, after the successive read operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released using the "Set Feature" command again.

[0189] FIG. 16 is a diagram showing a second example of a command sequence in a read operation in the first embodiment.

[0190] The memory controller 20 transmits a command, an address, and data as shown in (1), (2), (3), and (4) in FIG.

[0191] First, (1) parameters are set using the "Set Feature" command to set the semiconductor memory device 10 in voltage suspension mode. Next, (2) parameters are acquired using the "Get Feature" command. Note that the purpose of acquiring parameters using the "Get Feature" command is to check whether the parameters have been set correctly, and there are cases where the parameter acquisition is not performed. Next, (3) a read operation is executed. After that, (4) parameters are set using the "Set Feature" command to release the voltage suspension mode set in the semiconductor memory device 10.

[0192] Below, these points (1) to (4) are described in detail.

[0193] (1) Setting the voltage suspension mode First, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" is a command to notify that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" is an address that specifies the unit to be set by the "Set Feature" command. The feature address "XXh" indicates the address where the parameters to be set by the "Set Feature" command are stored.

[0194] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. By setting these parameters, the semiconductor memory device 10 is set to a voltage suspension mode. When set to the voltage suspension mode, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate (or output) the internal voltage that was generated (or output) during the read operation, even after the read operation is completed.

[0195] (2) Obtaining parameters using the get feature The memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit a command “D4h”, a LUN address “XXh”, and a feature address “XXh” to the semiconductor memory device 10. The command “D4h” is a command to notify that the address transmitted following the command “D4h” is related to the acquisition of parameters by the “Get Feature” command. The LUN address “XXh” is an address that designates a unit to be acquired by the “Get Feature” command. The feature address “XXh” indicates an address where the parameters acquired by the “Get Feature” command are stored. As a result, the parameters set by the “Set Feature” command are read in the semiconductor memory device 10. Then, the read data R0, R1, R2, and R3 are transmitted from the semiconductor memory device 10 to the memory controller 20. As a result, the memory controller 20 can know whether the parameters set by the “Set Feature” command have been set correctly, i.e., whether the semiconductor memory device 10 has been set to the voltage suspension mode.

[0196] (3) Read operation The read operation is similar to that in the first example, except for the prefix command "XXh".

[0197] First, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit the command "PC" and the command "00h" to the semiconductor memory device 10. Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit addresses "CA1, CA2, RA1, RA2, and RA3" to the semiconductor memory device 10. Furthermore, the memory controller 20 transmits the command "30h" to the semiconductor memory device 10 using signals DQ0 to DQ7.

[0198] Next, the memory controller 20 transmits the command "05h" to the semiconductor memory device 10 using the signals DQ0 to DQ7. Next, the memory controller 20 transmits the addresses "CA1, CA2, RA1, RA2, and RA3" to the semiconductor memory device 10 in order using the signals DQ0 to DQ7. Furthermore, the memory controller 20 transmits the command "E0h" to the semiconductor memory device 10 using the signals DQ0 to DQ7. Upon receiving the command "E0h", the sequencer 16 outputs the read data specified by the address to the memory controller 20.

[0199] (4) Canceling the voltage suspension mode The memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" indicates that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" and the feature address "XXh" are the same as described above.

[0200] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. Setting these parameters cancels the voltage suspension mode set in the semiconductor memory device 10. When the voltage suspension mode is canceled, the voltage generation circuit 17A of the semiconductor memory device 10 reduces the internal voltage that was generated during the read operation to the initial voltage when the read operation is completed.

[0201] As described above, the voltage suspension mode is set and released during a read operation using the "Set Feature" command.

[0202] 1.4.3 Read operations in the first and second examples The read operation to the memory cell transistor executed in the above-mentioned first and second examples will be described.

[0203] As described above, in a read operation, the internal voltage VI4 output from the boost circuit 174 of the voltage generation circuit 17A is supplied as a read pass voltage VREAD to the unselected word line WLusel that is not to be read via the driver 17B and the row decoder 18. Here, the internal voltage VI4 output from the boost circuit 174 and the read pass voltage VREAD supplied to the unselected word line WLusel will be described as an example.

[0204] Fig. 17 is a diagram showing the internal voltage VI4 and the read pass voltage VREAD in the read operation of the first embodiment. In Fig. 17, the read pass voltage VREAD is indicated by a solid line, and the internal voltage VI4 is indicated by a dashed line.

[0205] The read operation is performed multiple times on multiple cell units using multiple read voltages VCGRV (not shown) and a read pass voltage VREAD. The Nth and (N+1)th read operations shown in FIG. 17 respectively show read operations on memory cell transistors connected to two word lines among the read operations performed on memory cell transistors connected to multiple word lines. In the Nth read operation, the internal voltage VI4 output from the boost circuit 174 is supplied as a read pass voltage VREAD to the unselected word lines WLusel other than the first selected word line WLsel. In the (N+1)th write operation, the internal voltage VI4 is supplied as a read pass voltage VREAD to the unselected word lines WLusel other than the second selected word line WLsel. Note that although a read operation on multiple cell units is shown here, the read operation on one cell unit, i.e., the memory cell transistor connected to one word line, is similar.

[0206] The Nth read operation is performed as follows.

[0207] 17, at time t1, a read operation is executed on the memory cell transistor using a read voltage VCGRV (not shown) and a read pass voltage VREAD. In this read operation, an internal voltage VI4 is output from the boost circuit 174 of the voltage generating circuit 17A, and the internal voltage VI4 is supplied to the unselected word line WLusel as a read pass voltage VREAD.

[0208] When the Nth read operation is completed, the internal voltage VI4 (i.e., the read pass voltage VREAD) generated by the boost circuit 174 at the end of the Nth read operation is generated and output by the boost circuit 174 as is until the (N+1)th read operation is started.

[0209] Next, the (N+1)th read operation is performed as follows.

[0210] At time t2, a read operation is executed on the memory cell transistors using the read voltage VCGRV and the read pass voltage VREAD. In this read operation, the internal voltage VI4 (i.e., the read pass voltage VREAD) generated by the boost circuit 174 at the end of the Nth read operation is supplied to the unselected word line WLusel as the read pass voltage VREAD.

[0211] When the (N+1)th read operation is completed, if this (N+1)th read operation is not the last read operation executed in response to the command, the internal voltage VI4 generated by the boost circuit 174 is generated and output as is by the boost circuit 174. On the other hand, if the (N+1)th read operation is the last read operation executed in response to the command, the internal voltage VI4 generated by the boost circuit 174 (i.e., the read pass voltage VREAD) is stepped down to the initial voltage.

[0212] The read operation of the comparative example will be described below, and the first embodiment and the comparative example will be compared.

[0213] 18 shows the internal voltage VI4 and the read pass voltage VREAD in a read operation of the comparative example. In this comparative example, after the Nth read operation is completed, the internal voltage VI4 (i.e., the read pass voltage VREAD) generated by the boost circuit 174 is stepped down to an initial voltage (e.g., the power supply voltage VDD). Then, in the (N+1)th read operation, the internal voltage VI4 of the boost circuit 174 is stepped up to the read pass voltage VREAD and used for the read operation. For this reason, in the comparative example, time is required to step down the internal voltage VI4 from the read pass voltage VREAD to the initial voltage, and then to step up from the initial voltage to the read pass voltage VREAD.

[0214] In contrast to this, in the read operation of the first embodiment, the internal voltage VI4 (i.e., the read pass voltage VREAD) generated by the boost circuit 174 at the end of the Nth read operation is used in the (N+1)th read operation. That is, the internal voltage VI4 of the boost circuit 174 is supplied to the unselected word line WLusel as the read pass voltage VREAD without being recovered and boosted in the Nth and (N+1)th read operations.

[0215] The internal voltage VI4 used in the Nth read operation is used in the (N+1)th read operation without being recovered or boosted. This makes it possible to shorten the time between the Nth read operation and the (N+1)th read operation. In other words, it is possible to shorten the time from the end of the Nth read operation to the start of the (N+1)th read operation.

[0216] In the above, the read pass voltage VREAD and the internal voltage VI4 of the boost circuit 174 have been described, but the present invention is not limited to this. The same applies to other voltages used in the read operation and the corresponding internal voltages of the boost circuit. If the internal voltage is maintained at the end of the Nth read operation and this internal voltage is used for the (N+1)th read operation, the time from the end of the Nth read operation to the start of the (N+1)th read operation can be shortened.

[0217] 1.5 When erasing operations are performed consecutively The operation when the erase operations are performed continuously will be described.

[0218] 1.5.1 First Example In the first example, before transmitting a command related to an erase operation from the memory controller 20 to the semiconductor memory device 10, a command instructing the semiconductor memory device 10 to enter the voltage suspension mode is transmitted from the memory controller 20 to the semiconductor memory device 10. As a result, the semiconductor memory device 10 is set to the voltage suspension mode.

[0219] When the voltage suspension mode is set, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage generated during one erase operation until the successive erase operations commanded by the command are completed, even if one erase operation is completed. After that, after the successive erase operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released, and the voltage generation circuit 17A reduces the internal voltage to the initial voltage.

[0220] FIG. 19 is a diagram showing a first example of a command sequence in an erase operation according to the first embodiment.

[0221] Before transmitting a command related to an erase operation from the memory controller 20 to the semiconductor memory device 10, a predetermined prefix command "XXh" is transmitted. This prefix command "XXh" is a command commanding a voltage suspension mode, and commands the voltage generating circuit 17A to generate (or output) the internal voltage that it generated (or output) during the erase operation as is until the successive erase operations by the commands transmitted thereafter are completed, even after one erase operation is completed. Note that X in the prefix command "XXh" is a predetermined hexadecimal number, and h indicates that XX is a hexadecimal number. The same applies to X and h in other commands.

[0222] 19, first, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the prefix command "XXh" to the semiconductor memory device 10. The prefix command "XXh" is a command that instructs the semiconductor memory device 10 to enter the voltage suspension mode.

[0223] Upon receiving the prefix command “XXh”, the sequencer 16 of the semiconductor memory device 10 maintains the internal voltage output from the voltage generating circuit 17A as it is from the end of the first erase operation to the start of the subsequent second erase operation based on the prefix command “XXh”. That is, the internal voltage output from the voltage generating circuit 17A is maintained as it is for a predetermined time from the end of the first erase operation to the start of the second erase operation.

[0224] Next, the memory controller 20 uses the signals DQ0 to DQ7 to transmit the command "60h" to the semiconductor memory device 10. The command "60h" is a command for notifying an erase operation and input of an address.

[0225] Next, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit addresses "RA1, RA2, and RA3" to the semiconductor memory device 10. The addresses "RA1, RA2, and RA3" are addresses that specify blocks to be erased in the memory cell array 11. Note that although the addresses are shown here as three cycles, the number of cycles is arbitrary.

[0226] Next, the memory controller 20 uses the signals DQ0 to DQ7 to send the command "D0h" to the semiconductor memory device 10. The command "D0h" is a command to start an erase operation on the block specified by the address. Upon receiving the command "D0h", the sequencer 16 starts an erase operation on the block specified by the address.

[0227] 1.5.2 Second Example In the second example, before a command related to an erase operation is sent from the memory controller 20 to the semiconductor memory device 10, the semiconductor memory device 10 is set to the voltage suspension mode using a "Set Feature" command. When the semiconductor memory device 10 is set to the voltage suspension mode by the "Set Feature" command, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage that was generated during the erase operation even after the erase operation is completed. After that, after the successive erase operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released using the "Set Feature" command again.

[0228] FIG. 20 is a diagram showing a second example of a command sequence in the erase operation of the first embodiment.

[0229] The memory controller 20 transmits commands, addresses, and data as shown in (1), (2), (3), and (4) in FIG.

[0230] First, (1) parameters are set using the "Set Feature" command to set the semiconductor memory device 10 in voltage suspension mode. Next, (2) parameters are acquired using the "Get Feature" command. Note that the purpose of acquiring parameters using the "Get Feature" command is to check whether the parameters have been set correctly, and there are cases where this is not performed. Next, (3) an erase operation is executed. After that, (4) parameters are set using the "Set Feature" command to release the voltage suspension mode that has been set in the semiconductor memory device 10.

[0231] Below, these points (1) to (4) are described in detail.

[0232] (1) Setting the voltage suspension mode First, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" is a command to notify that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" is an address that specifies the unit to be set by the "Set Feature" command. The feature address "XXh" indicates the address where the parameters to be set by the "Set Feature" command are stored.

[0233] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. By setting these parameters, the semiconductor memory device 10 is set to a voltage suspension mode. When set to the voltage suspension mode, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate (or output) the same internal voltage that it generated (or output) during the erase operation, even after the erase operation is completed.

[0234] (2) Obtaining parameters using the get feature The memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit a command “D4h”, a LUN address “XXh”, and a feature address “XXh” to the semiconductor memory device 10. The command “D4h” is a command to notify that the address transmitted following the command “D4h” is related to the acquisition of parameters by the “Get Feature” command. The LUN address “XXh” is an address that designates a unit to be acquired by the “Get Feature” command. The feature address “XXh” indicates an address where the parameters acquired by the “Get Feature” command are stored. As a result, the parameters set by the “Set Feature” command are read in the semiconductor memory device 10. Then, the read data R0, R1, R2, and R3 are transmitted from the semiconductor memory device 10 to the memory controller 20. As a result, the memory controller 20 can know whether the parameters set by the “Set Feature” command have been set correctly, i.e., whether the semiconductor memory device 10 has been set to the voltage suspension mode.

[0235] (3) Erase operation The erase operation is similar to that in the first example, except for the prefix command "XXh".

[0236] First, the memory controller 20 uses signals DQ0 to DQ7 to transmit a command "60h" to the semiconductor memory device 10. Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit addresses "RA1, RA2, and RA3" to the semiconductor memory device 10 in order. Furthermore, the memory controller 20 uses signals DQ0 to DQ7 to transmit a command "D0h" to the semiconductor memory device 10. Upon receiving the command "D0h", the sequencer 16 starts an erase operation on the block specified by the address.

[0237] (4) Canceling the voltage suspension mode The memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" indicates that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" and the feature address "XXh" are the same as described above.

[0238] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. Setting these parameters cancels the voltage suspension mode set in the semiconductor memory device 10. When the voltage suspension mode setting is canceled, the voltage generation circuit 17A of the semiconductor memory device 10 reduces the internal voltage that was generated during the erase operation to the initial voltage when the erase operation is completed.

[0239] As described above, the voltage suspension mode is set and released during the erase operation using the "Set Feature" command.

[0240] 1.5.3 Erase operation in the first and second examples The erase operation on the memory cell transistor executed in the above-mentioned first and second examples will be described.

[0241] As described above, in an erase operation, the internal voltage VI5 output from the boost circuit 175 of the voltage generating circuit 17A is supplied as an erase voltage VERA to the source line SL of the selected block to be erased via the driver 17B. Here, the internal voltage VI5 output from the boost circuit 175 and the erase voltage VERA supplied to the source line SL of the selected block will be described as examples.

[0242] Fig. 21 is a diagram showing the internal voltage VI5 and the erase voltage VERA in the erase operation of the first embodiment. In Fig. 21, the erase voltage VERA is indicated by a solid line, and the internal voltage VI5 is indicated by a dashed line.

[0243] An erase operation is performed for each of a plurality of blocks in the memory cell array 11. The Nth and (N+1)th erase operations shown in FIG. 21 show two of the erase operations performed for each block. In the Nth erase operation, the internal voltage VI5 output from the boost circuit 175 is supplied to the source line SL of the selected block as the erase voltage VERA. In the (N+1)th erase operation, the internal voltage VI5 is supplied to the source line SL of the next selected block as the erase voltage VERA.

[0244] The Nth erase operation is performed as follows.

[0245] 21, at time t1, an erase operation is executed on memory cell transistors of a selected block using an erase voltage VERA. In this erase operation, an internal voltage VI5 is output from the boost circuit 175 of the voltage generating circuit 17A, and the internal voltage VI5 is supplied as the erase voltage VERA to the source line SL of the selected block to be erased.

[0246] When the Nth erase operation is completed, the internal voltage VI5 (i.e., erase voltage VERA) generated by the boost circuit 175 at the end of the Nth erase operation is generated and output by the boost circuit 175 as is until the (N+1)th erase operation is started.

[0247] Next, the (N+1)th erase operation is performed as follows.

[0248] At time t2, an erase operation is performed on the memory cell transistors of the next selected block using the erase voltage VERA. In this erase operation, the internal voltage VI5 (i.e., the erase voltage VERA) generated by the boost circuit 175 at the end of the Nth erase operation is supplied to the source line SL of the selected block as the erase voltage VERA.

[0249] When the (N+1)th erase operation is completed, if this (N+1)th erase operation is not the last erase operation executed in response to a command, the internal voltage VI5 is generated and output as is by the boost circuit 175. On the other hand, if the (N+1)th erase operation is the last erase operation executed in response to a command, the internal voltage VI5 generated by the boost circuit 175 is stepped down to the initial voltage.

[0250] The erase operation of the comparative example will be described below, and the first embodiment and the comparative example will be compared.

[0251] 22 shows the internal voltage VI5 and the erase voltage VERA in an erase operation of the comparative example. In this comparative example, after the Nth erase operation is completed, the internal voltage VI5 (i.e., the erase voltage VERA) generated by the boost circuit 175 is stepped down to an initial voltage (e.g., the power supply voltage VDD). Then, in the (N+1)th erase operation, the internal voltage VI5 of the boost circuit 175 is stepped up to the erase voltage VERA and used for the erase operation. For this reason, in the comparative example, time is required to step down the internal voltage VI5 from the erase voltage VERA to the initial voltage, and then to step up from the initial voltage to the erase voltage VERA.

[0252] In contrast, in the erase operation of the first embodiment, the internal voltage VI5 (i.e., the voltage VERA) generated by the boost circuit 175 at the end of the Nth erase operation is used in the (N+1)th erase operation. That is, the internal voltage VI5 of the boost circuit 175 is supplied to the source line SL of the selected block as the erase voltage VERA without being recovered and boosted in the Nth and (N+1)th erase operations.

[0253] The internal voltage VI5 used in the Nth erase operation is used in the (N+1)th erase operation without being recovered or boosted. This makes it possible to shorten the time between the Nth erase operation and the (N+1)th erase operation. In other words, it is possible to shorten the time from the end of the Nth erase operation to the start of the (N+1)th erase operation.

[0254] Although the erase voltage VERA and the internal voltage VI5 of the boost circuit 175 have been described above, the present invention is not limited to these. The same applies to other voltages used in the erase operation and the corresponding internal voltages of the boost circuit. If the internal voltage is maintained at the end of the Nth erase operation and this internal voltage is used for the (N+1)th erase operation, the time from the end of the Nth erase operation to the start of the (N+1)th erase operation can be shortened.

[0255] 1.6 Effects of the First Embodiment According to the semiconductor memory device and memory system of the first embodiment, the time between successive write operations (or successive read operations, or successive erase operations) can be shortened.

[0256] In the semiconductor memory device of the first embodiment, in successive write operations (or successive read operations, successive erase operations), recovery of the internal voltage of the voltage generating circuit 17A is not executed after the end of the first operation (or the previous operation), and the internal voltage is maintained until the start of the second operation (or the subsequent operation). That is, after the end of the first operation, the voltage level of the internal voltage is maintained until the start of the second operation. Then, the internal voltage maintained after the end of the first operation is used as it is or is set as the operating voltage in the second operation. This makes it possible to shorten the time from the end of the first operation to the start of the second operation. In addition, when the period from the first operation to the second operation is short, it is also possible to suppress the power consumption that occurs when the first operation and the second operation are executed successively.

[0257] In the memory system of the first embodiment, by sending a preset prefix command “XXh” or a “Set Feature” command from the memory controller 20 to the semiconductor memory device 10, the semiconductor memory device 10 can be informed that the internal voltage generated by the voltage generation circuit 17A will be maintained after each of the successive write operations (or successive read operations, or successive erase operations) is completed.

[0258] When the prefix command “XXh” or the “Set Feature” command is received, the semiconductor memory device 10 does not execute recovery of the internal voltage generated by the voltage generating circuit 17A even after the first operation is completed in the successive write operations (or the successive read operations, or the successive erase operations), and maintains the internal voltage until the second operation is started. That is, after the first operation is completed, the voltage level of the internal voltage is maintained until the second operation is started. Then, the internal voltage maintained after the first operation is completed is used as the operating voltage in the second operation as it is or is set as the operating voltage. This makes it possible to shorten the time from the end of the first operation to the start of the second operation. Also, when the period from the first operation to the second operation is short, it is also possible to suppress the power consumption that occurs when the first operation and the second operation are performed consecutively.

[0259] 2. Second embodiment A memory system according to a second embodiment will be described. In the second embodiment, an operation in the case where erase, write, and read operations are executed consecutively will be described. In the second embodiment, differences from the first embodiment will be mainly described.

[0260] 2.1 Memory system configuration The circuit configurations of the memory controller 20 and the semiconductor memory device 10 in the second embodiment are similar to those in the first embodiment.

[0261] 2.2 Memory System Operation The operation of the memory system 1 of the second embodiment will be described below. The operation when an erase operation, a write operation, a read operation, and an erase operation are executed consecutively will be described below.

[0262] 2.2.1 First Example In the first example, before the memory controller 20 transmits commands related to the erase operation, the write operation, and the read operation to the semiconductor memory device 10, a command instructing the semiconductor memory device 10 to enter the voltage suspension mode is transmitted from the memory controller 20 to the semiconductor memory device 10. As a result, the semiconductor memory device 10 is set to the voltage suspension mode in each of the erase operation, the write operation, and the read operation.

[0263] When the voltage suspension mode is set, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltage that was generated during the erase operation, write operation, or read operation commanded by a command, even after that operation is completed. After that, for example, after the last operation is completed and a certain amount of time has passed, the voltage suspension mode of the semiconductor memory device 10 is released, and the voltage generation circuit 17A reduces the internal voltage to the initial voltage.

[0264] FIG. 23 is a diagram showing a first example of a command sequence in an erase operation, a write operation, and a read operation in the second embodiment.

[0265] For example, before transmitting a command related to an erase operation from the memory controller 20 to the semiconductor memory device 10, a predetermined prefix command "XXh" is transmitted. This prefix command "XXh" is a command for instructing a voltage suspension mode, and is a command for instructing the voltage generating circuit 17A to continue to generate (or output) the internal voltage that it generated (or output) during the erase operation even after the erase operation based on the command transmitted thereafter is completed. Next, the memory controller 20 transmits a command related to the erase operation to the semiconductor memory device 10 using the signals DQ0 to DQ7. The above-mentioned prefix command "XXh" and the command related to the erase operation are the same as those shown in FIG. 19.

[0266] Next, before transmitting a command related to a write operation from the memory controller 20 to the semiconductor memory device 10, a predetermined prefix command "XXh" is transmitted. This prefix command "XXh" is a command for instructing a voltage suspension mode, and is a command for instructing the voltage generating circuit 17A to continue generating (or outputting) the internal voltage that it generated (or output) during the write operation even after the write operation based on the command transmitted thereafter is completed. Next, the memory controller 20 transmits a command related to the write operation to the semiconductor memory device 10 using the signals DQ0 to DQ7. The above-mentioned prefix command "XXh" and the command related to the write operation are the same as those shown in FIG. 11.

[0267] Next, before transmitting a command related to a read operation from the memory controller 20 to the semiconductor memory device 10, a predetermined prefix command "XXh" is transmitted. This prefix command "XXh" is a command for instructing a voltage suspension mode, and is a command for instructing the voltage generating circuit 17A to continue generating (or outputting) the internal voltage that it generated (or output) during the read operation even after the read operation based on the command transmitted thereafter is completed. Next, the memory controller 20 transmits a command related to the read operation to the semiconductor memory device 10 using the signals DQ0 to DQ7. The above-mentioned prefix command "XXh" and the command related to the read operation are the same as those shown in FIG. 15.

[0268] As described above, an erase operation, a write operation, and a read operation are performed consecutively by sending the prefix command “XXh” and a command related to an erase operation, the prefix command “XXh” and a command related to a write operation, and the prefix command “XXh” and a command related to a read operation, respectively.

[0269] Thereafter, each operation can be executed successively by sending the prefix command "XXh" and a command for each operation.

[0270] 2.2.2 Second Example In the second example, before commands related to erase, write, and read operations are sent from the memory controller 20 to the semiconductor memory device 10, the semiconductor memory device 10 is set to the voltage suspension mode using a "Set Feature" command. When the semiconductor memory device 10 is set to the voltage suspension mode by the "Set Feature" command, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate and output the internal voltages generated during each operation even after the erase, write, and read operations are completed. After that, after the consecutive erase, write, and read operations are completed, the voltage suspension mode of the semiconductor memory device 10 is released again using the "Set Feature" command.

[0271] FIG. 24 is a diagram showing a second example of command sequences in the erase operation, write operation, and read operation of the second embodiment.

[0272] The memory controller 20 transmits a command, an address, and data as shown in (1), (2), (3), and (4) in FIG.

[0273] First, (1) parameters are set using the "Set Feature" command to set the semiconductor memory device 10 in voltage suspension mode. Next, (2) parameters are acquired using the "Get Feature" command. Note that the purpose of acquiring parameters using the "Get Feature" command is to check whether the parameters have been set correctly, and there are cases where this is not performed. Next, (3) an erase operation is executed. After that, (4) parameters are set using the "Set Feature" command to release the voltage suspension mode that has been set in the semiconductor memory device 10.

[0274] Below, these points (1) to (4) are described in detail.

[0275] (1) Setting the voltage suspension mode First, the memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" is a command to notify that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" is an address that specifies the unit to be set by the "Set Feature" command. The feature address "XXh" indicates the address where the parameters to be set by the "Set Feature" command are stored.

[0276] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. By setting these parameters, the semiconductor memory device 10 is set to a voltage suspension mode. When set to the voltage suspension mode, the voltage generation circuit 17A of the semiconductor memory device 10 continues to generate (or output) the internal voltage that was generated (or output) during each operation, even after each of the erase operation, write operation, and read operation is completed.

[0277] (2) Obtaining parameters using the get feature The memory controller 20 uses the signals DQ0 to DQ7 to sequentially transmit a command “D4h”, a LUN address “XXh”, and a feature address “XXh” to the semiconductor memory device 10. The command “D4h” is a command to notify that the address transmitted following the command “D4h” is related to the acquisition of parameters by the “Get Feature” command. The LUN address “XXh” is an address that designates a unit to be acquired by the “Get Feature” command. The feature address “XXh” indicates an address where the parameters acquired by the “Get Feature” command are stored. As a result, the parameters set by the “Set Feature” command are read in the semiconductor memory device 10. Then, the read data R0, R1, R2, and R3 are transmitted from the semiconductor memory device 10 to the memory controller 20. As a result, the memory controller 20 can know whether the parameters set by the “Set Feature” command have been set correctly, i.e., whether the semiconductor memory device 10 has been set to the voltage suspension mode.

[0278] (3) Erase, write, and read operations The erase operation, write operation, and read operation are the same as those in the first example, except for the prefix command "XXh".

[0279] (4) Canceling the voltage suspension mode The memory controller 20 uses signals DQ0 to DQ7 to sequentially transmit a command "D5h", a LUN address "XXh", and a feature address "XXh" to the semiconductor memory device 10. The command "D5h" indicates that the address and data transmitted following this command "D5h" are related to the setting of parameters by the "Set Feature" command. The LUN address "XXh" and the feature address "XXh" are the same as described above.

[0280] Next, the memory controller 20 uses signals DQ0 to DQ7 to transmit data "D0, D1, D2, and D3" to the semiconductor memory device 10. The data "D0, D1, D2, and D3" are parameters set by the "Set Feature" command. Setting these parameters cancels the voltage suspension mode set in the semiconductor memory device 10. When the voltage suspension mode is canceled, the voltage generation circuit 17A of the semiconductor memory device 10 reduces the internal voltage generated during each operation to the initial voltage when the successive erase, write, and read operations are completed.

[0281] As described above, the voltage suspension mode is set and released during successive erase, write, and read operations using the "Set Feature" command.

[0282] 2.2.3 Erase, write, and read operations in the first and second examples The erase operation, write operation, and read operation to the memory cell transistors executed in the above-mentioned first and second examples will be described.

[0283] Here, as an example, it is assumed that the internal voltage VI5 output from the boost circuit 175 of the voltage generating circuit 17A is supplied as the erase voltage VERA in an erase operation, as the write voltage VPGM in a write operation, and as the read pass voltage VREAD in a read operation. That is, the internal voltage VI5 generated by one boost circuit 175 is supplied as the erase voltage VERA, or the write voltage VPGM, or the read pass voltage VREAD.

[0284] 25 is a diagram showing the internal voltages, the erase voltage, the write voltage, and the read pass voltage in the erase operation, the write operation, and the read operation of the second embodiment. In FIG. 25, the erase voltage VERA, the write voltage VPGM, and the read pass voltage VREAD are shown by solid lines, and the internal voltage VI5 is shown by dashed lines.

[0285] 25, the semiconductor memory device 10 is not set to the voltage suspension mode, and is set to the voltage suspension mode during the period from the end of the operation prior to the erase operation to the start of the erase operation. Therefore, before the start of the erase operation, the internal voltage VI5 output from the boost circuit 175 of the voltage generating circuit 17A is set to an initial voltage.

[0286] 25, when an erase operation is started, the internal voltage VI5 output from the boost circuit 175 is boosted from an initial voltage to the erase voltage VERA. Then, at time t1, an erase operation is performed on the memory cell transistors of the selected block using the erase voltage VERA. In this erase operation, the internal voltage VI5 is output from the boost circuit 175 of the voltage generating circuit 17A, and the internal voltage VI5 is supplied as the erase voltage VERA to the source line SL of the selected block to be erased.

[0287] When the erase operation is completed, the internal voltage VI5 (i.e., the erase voltage VERA) generated by the boost circuit 175 at the time the erase operation is completed is generated and output by the boost circuit 175 as is until the next operation (e.g., a write operation) is started.

[0288] Next, at time t2, a program operation is executed on the memory cell transistors using the write voltage VPGM. In this program operation, the internal voltage VI5 generated by the boost circuit 175 at the end of the erase operation is set as the write voltage VPGM and supplied to the selected word line WLsel.

[0289] Then, a program verify operation is performed on the memory cell transistor using a verify voltage VVE. If the program verify operation fails, the write voltage VPGM is increased by a constant voltage ΔV, the program operation is performed again, and then a program verify operation is performed. Then, the program operation and the program verify operation are repeatedly performed until the program verify operation passes.

[0290] If the program verify operation passes, the write operation ends. When the write operation ends, the internal voltage VI5 (i.e., the write voltage VPGMa) generated by the boost circuit 175 at the end of the write operation continues to be generated and output by the boost circuit 175 until the next operation (e.g., a read operation) starts.

[0291] Next, at time t3, a read operation is executed on the memory cell transistors using a read voltage VCGRV (not shown) and a read pass voltage VREAD. In this read operation, the internal voltage VI5 (i.e., the write voltage VPGMa) generated by the boost circuit 175 at the end of the write operation is set to the read pass voltage VREAD and supplied to the unselected word lines WLusel.

[0292] When the read operation is completed, the internal voltage VI5 (i.e., the read pass voltage VREAD) generated by the boost circuit 175 at the time of completion of the read operation is generated and output by the boost circuit 175 as is until the next operation is started.

[0293] 2.3 Effects of the second embodiment According to the semiconductor memory device and memory system of the second embodiment, the time between successive erase, write, and read operations can be reduced.

[0294] In the semiconductor memory device of the second embodiment, in the successive erase, write, and read operations, recovery of the internal voltage of the voltage generating circuit 17A is not performed after the end of the first operation (or the previous operation), and the internal voltage is maintained until the start of the second operation (or the subsequent operation). That is, after the end of the first operation, the voltage level of the internal voltage is maintained until the start of the second operation. Then, the internal voltage maintained after the end of the first operation is used as it is or is set as the operating voltage in the second operation. This makes it possible to shorten the time from the end of the first operation to the start of the second operation. In addition, when the period from the first operation to the second operation is short, it is also possible to suppress the power consumption that occurs when the first operation and the second operation are executed successively.

[0295] In the memory system of the second embodiment, by sending a preset prefix command “XXh” or a “Set Feature” command from the memory controller 20 to the semiconductor memory device 10, the semiconductor memory device 10 can be informed that the internal voltage generated by the voltage generation circuit 17A will be maintained after each of the successive erase operations, write operations, and erase operations is completed.

[0296] When the prefix command “XXh” or the “Set Feature” command is received, the semiconductor memory device 10 does not execute recovery of the internal voltage generated by the voltage generating circuit 17A even after the first operation is completed in the consecutive erase, write, and erase operations, and maintains the internal voltage until the second operation is started. That is, after the first operation is completed, the voltage level of the internal voltage is maintained until the second operation is started. Then, the internal voltage maintained after the first operation is used as it is or is set as the operating voltage as the operating voltage in the second operation. This makes it possible to shorten the time from the end of the first operation to the start of the second operation. Also, when the period from the first operation to the second operation is short, it is also possible to suppress the power consumption that occurs when the first operation and the second operation are performed consecutively.

[0297] 3.Other Furthermore, in the above embodiment, a NAND type flash memory is used as an example of a semiconductor memory device, but the present invention is not limited to a NAND type flash memory and can be applied to other semiconductor memory devices in general, and can also be applied to various memory devices other than semiconductor memory devices.

[0298] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0299] 1...memory system, 2...host device, 10...semiconductor memory device, 11...memory cell array, 12...input / output circuit, 13...logic control circuit, 14...ready / busy circuit, 15...register group, 15A...status register, 15B...address register, 15C...command register, 16...sequencer, 17A...voltage generation circuit, 17B...driver, 18...row decoder, 19A...column decoder, 19B...data register, 19C...sense amplifier, 20...memory controller, 21...CPU , 22...RAM, 23...ROM, 24...ECC circuit, 25...NAND interface circuit, 26...host interface circuit, 30...semiconductor substrate, 31-35...insulating layer, 40-44...conductive layer, 50...semiconductor layer, 51...tunnel insulating layer, 52...charge storage layer, 53...block insulating layer, 171...boost circuit, 172...boost circuit, 173...boost circuit, 174...boost circuit, 175...boost circuit, VI1...internal voltage, VI2...internal voltage, VI3...internal voltage, VI4...internal voltage, VI5...internal voltage.

Claims

1. a first memory cell capable of storing data; a control circuit for controlling a first operation and a second operation for the first memory cell; a voltage generating circuit that outputs a first voltage used in the first operation and a second voltage used in the second operation; Equipped with The control circuit includes: A semiconductor memory device configured to maintain the first voltage output from the voltage generating circuit from the end of the first operation to the start of the second operation based on a first command input from outside.

2. 2. The semiconductor memory device according to claim 1, wherein the first voltage is maintained for a first time period after the first operation ends.

3. 3. The semiconductor memory device according to claim 2, wherein the first voltage is maintained for the first time period, and then is set to the second voltage and used for the second operation.

4. a word line connected to the first memory cell; the first and second operations are write operations, In the first operation, the first voltage is supplied to the word line; 2. The semiconductor memory device according to claim 1, wherein in the second operation, the second voltage is supplied to the word line.

5. a word line connected to the first memory cell; the first and second operations are read operations, In the first operation, the first voltage is supplied to the word line; 2. The semiconductor memory device according to claim 1, wherein in the second operation, the second voltage is supplied to the word line.

6. a second memory cell capable of storing data; a first source line connected to the first memory cell; a second source line connected to the second memory cell; Further equipped with the first and second operations are erase operations, In the first operation, the first voltage is supplied to the first source line; 2. The semiconductor memory device according to claim 1, wherein in the second operation, the second voltage is supplied to the second source line.

7. 2 . The semiconductor memory device according to claim 1 , wherein each of the first operation and the second operation is one of a write operation, a read operation, and an erase operation.

8. the control circuit controls the first operation and the second operation based on a second command input from an external device; 2. The semiconductor memory device according to claim 1, wherein the first command is input before the second command.

9. 2. The semiconductor memory device according to claim 1, wherein the first command is a command instructing the control circuit to maintain the first voltage from the end of the first operation to the start of the second operation.

10. The first command is a "Set Feature" command, and a parameter is set by the "Set Feature" command; 2 . The semiconductor memory device according to claim 1 , wherein the control circuit is configured to maintain the first voltage from the end of the first operation to the start of the second operation based on the parameter.

11. 2. The semiconductor memory device according to claim 1, wherein the maintaining of the first voltage comprises maintaining a voltage value of the first voltage.

12. the voltage generating circuit boosts a second voltage to generate the first voltage; 2 . The semiconductor memory device according to claim 1 , wherein the voltage generating circuit maintains the first voltage without stepping down the first voltage to the second voltage.

13. A semiconductor memory device according to claim 1 , a controller that transmits the first command to the semiconductor memory device; A memory system comprising:

14. A semiconductor memory device according to claim 8 , a controller that transmits the first command to the semiconductor memory device and then transmits the second command to the semiconductor memory device; A memory system comprising:

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