Data receiver and clock frequency adjustment method

Abstract

To provide a data receiver capable of synchronizing clocks between a data transmitter and a data receiver.SOLUTION: A packet receiving unit 31 receives a data packet sampled with the first clock. A clock generator 36 generates a second clock based on a reference clock supplied from a frequency variation oscillator 35. A data buffer 32 writes and reads data packets using the second clock. The packet receiving unit 31 obtains a count value C31 by counting the number of samples in a measurement period using the reference clock. A frequency control unit 34 obtains a frequency difference between the first and second clocks based on the difference between the number of samples of the data packet by the first clock in the measurement period and the count value. When a flag F32 indicating an overflow or underflow of the data buffer 32 is supplied, the frequency control unit 34 supplies a frequency adjustment value to the frequency variation oscillator 35.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a data receiver and a clock frequency adjustment method. [Background technology]

[0002] A data transmitter and a data receiver at different locations may transmit and receive data via a wide area network (WAN). At this time, it may be necessary to synchronize the clocks between the data transmitter and the data receiver. Patent Document 1 describes the need to synchronize the clocks between a master device and a slave device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-31334 A Summary of the Invention [Problem to be solved by the invention]

[0004] One method for synchronizing clocks is the Precision Time Protocol (PTP), but PTP cannot be used in a WAN. Another method for synchronizing clocks is to use time information transmitted from satellites for the Global Navigation Satellite System (GNSS), such as the Global Positioning System (GPS). However, using time information transmitted from satellites for the GNSS is not desirable because it results in high costs for data transmitters and data receivers.

[0005] An object of the present invention is to provide a data receiver and a clock frequency adjustment method capable of achieving clock synchronization between a data transmitter and a data receiver with a simple configuration in the data receiver. [Means for solving the problem]

[0006] The present invention includes a packet receiving unit that receives a data packet sampled with a first clock and transmitted from a data transmitter via a network, a frequency fluctuation oscillator that oscillates a reference clock and fluctuates the oscillation frequency of the reference clock according to an input frequency adjustment value, a clock generator that generates a second clock having a frequency corresponding to the frequency of the first clock based on the reference clock supplied from the frequency fluctuation oscillator, and a data buffer that writes and reads out a data packet received by the packet receiving unit using the second clock, and the packet receiving unit calculates the number of samples of the received data packet in a predetermined measurement period using the reference clock. a count value counted by counting the number of samples taken by the first clock and the first clock, and the data buffer generates a flag if the data packets are written to a capacity exceeding a predetermined upper limit of the total capacity or if the data packets are written to a capacity less than a predetermined lower limit of the total capacity; a frequency difference indicating how much higher or lower the frequency of the second clock is than the frequency of the first clock is determined based on a difference between the number of samples taken by the first clock of the data packets during the measurement period and the count value; and a frequency control unit that supplies a frequency adjustment value to the frequency variable oscillator to correct the frequency difference when the flag is supplied from the data buffer.

[0007] The present invention provides a clock frequency adjustment method, which includes receiving a data packet sampled with a first clock and transmitted from a data transmitter via a network, generating a second clock having a frequency equivalent to the frequency of the first clock based on a reference clock supplied from a frequency fluctuation oscillator, writing the received data packet to a data buffer using the second clock and reading it out, determining a count value obtained by counting the number of samples of the received data packet in a predetermined measurement period using the reference clock, generating a flag when the data packet has been written to the data buffer exceeding a predetermined upper limit capacity of the total capacity or when the data packet has been written to a capacity less than a predetermined lower limit capacity of the total capacity, determining a frequency difference indicating how much higher or lower the frequency of the second clock is than the frequency of the first clock based on the difference between the number of samples of the data packet by the first clock in the measurement period and the count value, and supplying a frequency adjustment value for correcting the frequency difference to the frequency fluctuation oscillator when the flag is generated, thereby varying the oscillation frequency of the reference clock. Effect of the Invention

[0008] According to the data receiver and clock frequency adjustment method of the present invention, clock synchronization can be achieved between the data transmitter and the data receiver with a simple configuration in the data receiver. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing a data transmission / reception system including a data receiver according to an embodiment, the system including a data transmitter and a data receiver. [Diagram 2] FIG. 2 is a diagram showing the relationship between the timing of writing data to and reading data from an audio data buffer in a data receiver according to an embodiment. [Diagram 3] FIG. 3 is a flowchart showing the operation of an audio packet receiving unit in a data receiver according to an embodiment. [Figure 4] FIG. 4 is a flowchart showing the operation of the frequency control unit in the data receiver according to one embodiment. [Diagram 5] FIG. 5 is a diagram showing a preferred example of the structure of a packet transmitted and received by the data transmission and reception system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A data receiver and a clock frequency adjustment method according to an embodiment will be described below with reference to the accompanying drawings. In Fig. 1, a data transmitter 10 and a data receiver 30 are connected via a network 20. The data transmitter 10 and the data receiver 30 connected via the network 20 constitute a data transmission / reception system. Typically, the network 20 is the Internet.

[0011] The data transmitter 10 and the data receiver 30 may be data transceivers having the same configuration. In this case, the data transmitter 10 is a data transceiver that describes only the transmission function, and the data receiver 30 is a data transceiver that describes only the reception function.

[0012] As an example, the data transmitted and received between the data transmitter 10 and the data receiver 30 is assumed to be audio data. The data transmitted and received between the data transmitter 10 and the data receiver 30 may be video data, or video data and audio data. The data transmitted and received between the data transmitter 10 and the data receiver 30 may be any data.

[0013] The data transmitter 10 includes a source oscillator 11, an audio clock generator 12, and an audio packet transmitting unit 13. The source oscillator 11 oscillates a reference clock of, for example, 27 MHz. The frequency of the reference clock may be a free-running frequency of the source oscillator 11. The audio clock generator 12 generates an audio clock (first clock) of, for example, 48 kHz based on the reference clock supplied from the source oscillator 11.

[0014] The audio packet transmitting unit 13 transmits packets of audio data (audio packets) sampled at the audio clock generated by the audio clock generator 12 to the data receiver 30 via the network 20. The audio packets are an example of data packets.

[0015] The data receiver 30 includes an audio packet receiving unit 31 (packet receiving unit), an audio data buffer 32 (data buffer), an audio processing unit 33, a frequency control unit 34, a frequency variation oscillator 35, and an audio clock generator 36 (clock generator). The audio packet receiving unit 31 receives audio packets transmitted from the data transmitter 10.

[0016] The audio data buffer 32 uses an audio clock (second clock) supplied from an audio clock generator 36 to write audio packets received by the audio packet receiving unit 31 and reads them out at a timing to be described later.

[0017] The audio processing unit 33 generates audio data representing audio to be output from a speaker (not shown) based on the audio packets read from the audio data buffer 32. The audio data is converted into an analog signal by a D / A converter (not shown) and supplied to the speaker. The frequency variation oscillator 35 is an oscillator that can vary the oscillation frequency of the reference clock with an adjustment accuracy of ±100 ppm, with a center frequency of 27 MHz. The frequency variation oscillator 35 varies the oscillation frequency of the reference clock according to an input frequency adjustment value. The frequency control unit 34 controls the oscillation frequency of the reference clock generated by the frequency variation oscillator 35, as described below.

[0018] The audio clock generator 36 generates an audio clock with a frequency of about 48 kHz based on the reference clock supplied from the frequency variable oscillator 35. The frequency of the audio clock generated by the audio clock generator 36 corresponds to the frequency of the audio clock generated by the audio clock generator 12, but the two frequencies may not match perfectly.

[0019] Next, a description will be given of the operation of the data receiver 30 for synchronizing the audio clocks between the data transmitter 10 and the data receiver 30. The operation performed by the data receiver 30 corresponds to a clock frequency adjustment method according to one embodiment.

[0020] The audio packet receiving unit 31 counts the number of samples of the received audio packets during a predetermined measurement period using a reference clock supplied by the frequency variation oscillator 35. The measurement period is, for example, one second. The audio packet receiving unit 31 obtains a count value by counting the number of samples during multiple measurement periods. The audio packet receiving unit 31 may obtain a count value for one measurement period, but it is preferable to obtain an average value of multiple count values ​​to eliminate errors. The average value may be a moving average value.

[0021] The count value is a concept including an average value of the count values. The audio packet receiving unit 31 supplies the count value C31 calculated as above to the frequency control unit .

[0022] Assume that the audio data buffer 32 has a capacity of, for example, 10 MB. As shown in Fig. 2, the audio data buffer 32 starts writing audio packets, and then starts reading audio packets when, for example, 5 MB, which is half the capacity, has been written. If the audio clocks of the data transmitter 10 and the data receiver 30 are not synchronized, an overflow or underflow may occur in the audio data buffer 32.

[0023] The audio data buffer 32 generates a flag (overflow flag) indicating an overflow state when audio packets are written to the buffer exceeding, for example, 90% (upper limit capacity) of the total capacity. The audio data buffer 32 generates a flag (underflow flag) indicating an underflow state when audio packets are written to the buffer exceeding, for example, 10% (lower limit capacity) of the total capacity. The audio data buffer 32 supplies a flag F32, which is an overflow flag or underflow flag, to the frequency control unit 34.

[0024] The frequency control section 34 determines a frequency adjustment value for adjusting the oscillation frequency of the reference clock generated by the frequency variable oscillator 35 in the following manner. If the audio clock generated by the audio clock generator 12 in the data transmitter 10 and the audio clock generated by the audio clock generator 36 in the data receiver 30 are the same, the actual count value per second indicated by the count value C31 input to the frequency control section 34 will be 48,000. If the latter is lower than the former, the actual count value will be more than 48,000, and if the latter is higher than the former, the actual count value will be less than 48,000.

[0025] Suppose that the count value C31 input to the frequency control section 34 is 48004. In this case, the frequency of the audio clock generated by the audio clock generator 36 is lower than the frequency of the audio clock generated by the audio clock generator 12 by 83.3 ppm, based on (1-48000 / 48004)×1000000.

[0026] In this way, the frequency control unit 34 determines a frequency difference indicating how much higher or lower the frequency of the audio clock generated by the audio clock generator 36 is than the frequency of the audio clock generated by the audio clock generator 12, based on the difference between the number of samples (48,000) based on the 48 kHz audio clock of the audio packet during the measurement period and the count value C31.

[0027] Since the adjustment accuracy in the frequency fluctuation oscillator 35 is ±100 ppm, the frequency control section 34 supplies the frequency fluctuation oscillator 35 with a frequency adjustment value that increases the frequency of the reference clock by 100 ppm, which is greater than 83.3 ppm, so that the frequency difference of 83.3 ppm can be corrected.

[0028] The process executed by the audio packet receiving unit 31 will be described with reference to the flowchart shown in Fig. 3. In Fig. 3, when the process of the audio packet receiving unit 31 starts, the audio packet receiving unit 31 counts the number of samples in step S1. In step S2, the audio packet receiving unit 31 determines whether or not the measurement period (1 second) has elapsed. If the measurement period has not elapsed (NO), the audio packet receiving unit 31 repeats the processes of steps S1 and S2.

[0029] If the measurement period has elapsed in step S2 (YES), the audio packet receiving unit 31 stores the count value in step S3. Then, in step S4, the audio packet receiving unit 31 determines whether or not multiple count values ​​have been acquired. If multiple count values ​​have not been acquired (NO), the audio packet receiving unit 31 repeats the processes of steps S1 to S3. If multiple count values ​​have been acquired (YES), the audio packet receiving unit 31 calculates the average value of the count values ​​in step S5.

[0030] In step S6, the audio packet receiving unit 31 supplies the average value of the count values ​​to the frequency control unit 34. In step S7, the audio packet receiving unit 31 determines whether or not to end data reception. If data reception is not to end (NO), the audio packet receiving unit 31 repeats the processes of steps S1 to S7. If data reception is to end (YES), the audio packet receiving unit 31 ends the process.

[0031] The process executed by the frequency control unit 34 will be described with reference to the flowchart shown in Fig. 4. In Fig. 4, when the process of the frequency control unit 34 starts, the frequency control unit 34 acquires the average value of the count values ​​supplied from the audio packet receiving unit 31 in step S11. The frequency control unit 34 calculates a frequency adjustment value in step S12. The frequency control unit 34 determines whether or not a flag F32 that is an overflow flag or an underflow flag has been input in step S13.

[0032] If flag F32 is not input in step S13 (NO), frequency control unit 34 repeats the processing of steps S11 to S13. If flag F32 is input (YES), frequency control unit 34 supplies frequency adjustment value for correcting the oscillation frequency in frequency variation oscillator 35 to frequency variation oscillator 35 in step S14, and shifts the processing to step S15. In step S15, frequency control unit 34 determines whether or not to end data reception. If data reception is not to end (NO), frequency control unit 34 repeats the processing of steps S11 to S15. If data reception is to end (YES), frequency control unit 34 ends the processing.

[0033] As shown in Fig. 5(b), generally, the packet size of each audio packet transmitted from the data transmitter 10 to the data receiver 30 is the same. As shown in Fig. 5(a), it is preferable to set the packet size so that the packet size is large at the start of the measurement period and small at the end of the measurement period. In the example shown in Fig. 5, groups Gp1 to Gp10 with different packet sizes are set.

[0034] Groups Gp1 and Gp2 each contain 12 packets, groups Gp3 and Gp4 each contain 6 packets, groups Gp5 and Gp6 each contain 3 packets, groups Gp7 and Gp8 each contain 2 packets, groups Gp9 and Gp10 each contain 1 packet. Packets in group Gp10 may be further divided into smaller packets.

[0035] As shown in (a) of Figure 5, the packet size should be set so that it gradually decreases from the start point to the end point within the measurement period. Although the packet size is set to be gradually decreased for each group of packets, the packet size may be set to be gradually decreased for each individual packet.

[0036] 5(a), the measurement period can be set from the time when a packet of the maximum packet size is received, and a command to notify the start time of the measurement period is not required. Also, even if the data received by the data receiver 30 contains jitter and the timing of reception is delayed, the packets affected by the delayed reception are the smaller packets near the end, so the effect of jitter can be minimized.

[0037] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention. [Explanation of symbols]

[0038] 10 Data transmitter 11 Source Oscillator 12 Audio Clock Generator 13 Audio packet transmitter 20 Network 30 Data Receiver 31 Audio packet receiver 32 Audio Data Buffers 33 Audio Processing Section 34 Frequency Control Section 35 Frequency-Variable Oscillator 36 Audio Clock Generator

Claims

1. a packet receiving unit that receives a data packet sampled by a first clock and transmitted from a data transmitter via a network; a frequency variable oscillator that oscillates a reference clock and varies the oscillation frequency of the reference clock in response to an input frequency adjustment value; a clock generator that generates a second clock having a frequency corresponding to a frequency of the first clock based on the reference clock provided by the frequency variable oscillator; a data buffer for writing and reading data packets received by the packet receiving unit using the second clock; Equipped with the packet receiving unit obtains a count value by counting the number of samples of the received data packet during a predetermined measurement period using the reference clock; the data buffer generates a flag when the data packets are written exceeding a predetermined upper limit capacity of the total capacity or when the data packets are written to a capacity less than a predetermined lower limit capacity of the total capacity; a frequency control unit that calculates a frequency difference indicating how much higher or lower the frequency of the second clock is than the frequency of the first clock based on a difference between the number of samples of the data packet by the first clock during the measurement period and the count value, and that supplies a frequency adjustment value for correcting the frequency difference to the frequency variable oscillator when the flag is supplied from the data buffer. Data receiver.

2. the packet receiving unit calculates an average value of the count values ​​calculated over a plurality of the measurement periods; The frequency control unit calculates the frequency difference based on a difference between the number of samples of the data packet by the first clock and an average value of the count value.

2. The data receiver of claim 1.

3. 3. The data receiver according to claim 1, wherein the packet size of the data packet transmitted by the data transmitter is set so that the packet size is larger at the start of the measurement period and smaller at the end of the measurement period.

4. receiving a data packet sampled by a first clock and transmitted by a data transmitter over a network; generating a second clock having a frequency corresponding to a frequency of the first clock based on a reference clock provided by a frequency variable oscillator; using the second clock to write and read received data packets into a data buffer; A count value is obtained by counting the number of samples of the received data packet during a predetermined measurement period using the reference clock; generating a flag when the data packets are written in the data buffer in an amount exceeding a predetermined upper limit of the total capacity or when the data packets are written in an amount less than a predetermined lower limit of the total capacity; determining a frequency difference indicating how much higher or lower the frequency of the second clock is than the frequency of the first clock based on a difference between the count value and the number of samples of the data packet by the first clock during the measurement period; When the flag is generated, a frequency adjustment value for correcting the frequency difference is supplied to the frequency variation oscillator, thereby varying the oscillation frequency of the reference clock. Clock frequency adjustment method.

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