Semiconductor chip and semiconductor device

Abstract

To provide a semiconductor chip and a semiconductor device, which can be miniaturized while having an alignment mark indicating a high recognition property.SOLUTION: A semiconductor chip 1 comprises: a semiconductor substrate 2 which has a first surface 2A, and in which a semiconductor element is formed; and a plurality of pads 3 that is electrically connected to the semiconductor element, and is arranged while having an interval each other onto a first surface. The plurality of pads contains: a first control pad 6; and a second control pad 7. In a plan view, the second control pad contains an irregular shape part 7A of which an outer shape is an abnormal shape in a comparison with the first control pad.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor chip and a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art There is known a semiconductor device including an individual semiconductor chip and a mounting substrate on which the semiconductor chip is mounted. The semiconductor chip is provided with an alignment mark for positioning the semiconductor chip in the semiconductor device.

[0003] Generally, alignment marks are formed as two or more patterns in an area of ​​a semiconductor chip that is different from wiring areas such as pads that are electrically connected to external components (see, for example, International Publication No. 2002 / 082540). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2002 / 082540 Summary of the Invention [Problem to be solved by the invention]

[0005] In order to properly position a semiconductor chip in a semiconductor device, it is necessary that a relatively large alignment mark exhibiting high recognition ability is formed on the semiconductor chip.

[0006] Therefore, when an alignment mark that exhibits high recognizability is formed in an area other than a wiring area such as a pad as described above, it is difficult to realize miniaturization of a semiconductor chip.

[0007] In particular, power semiconductor chips made of silicon carbide (SiC) and the like have been increasingly miniaturized in recent years, making it difficult to form alignment marks that are highly recognizable on power semiconductor chips.

[0008] A primary object of the present disclosure is to provide a semiconductor chip and a semiconductor device that are provided with alignment marks that are highly recognizable and can be miniaturized. [Means for solving the problem]

[0009] The semiconductor chip according to the present disclosure includes a semiconductor substrate having a first surface on which a semiconductor element is formed, and a plurality of pads electrically connected to the semiconductor element and arranged at intervals from one another on the first surface. The plurality of pads include a first pad and a second pad. In a plan view, the second pad includes an irregularly shaped portion whose outer shape is different from that of the first pad. Effect of the Invention

[0010] The semiconductor chip and semiconductor device according to the present disclosure can be miniaturized while still being provided with an alignment mark that exhibits high recognizability. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a plan view for explaining the semiconductor chip according to the first embodiment. [Diagram 2] 2 is a partial enlarged plan view for explaining the semiconductor chip according to the first embodiment. [Diagram 3] FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment. [Figure 4] FIG. 11 is a plan view for explaining a first modified example of the semiconductor chip according to the first embodiment. [Diagram 5] FIG. 11 is a partially enlarged plan view for explaining a second modified example of the semiconductor chip according to the first embodiment. [Figure 6] FIG. 11 is a partially enlarged plan view for explaining a third modified example of the semiconductor chip in accordance with the first embodiment. [Figure 7] FIG. 13 is a partial enlarged plan view for explaining a fourth modified example of the semiconductor chip according to the first embodiment. [Figure 8]FIG. 11 is a plan view for explaining a semiconductor chip according to a second embodiment. [Figure 9] FIG. 11 is a plan view for explaining a semiconductor chip according to a third embodiment. [Figure 10] FIG. 13 is a plan view for explaining a semiconductor chip according to a fourth embodiment. [Figure 11] FIG. 11 is a partially enlarged cross-sectional view taken along the line indicated by arrows XI-XI in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following, the same or corresponding parts are denoted by the same reference characters, and overlapping descriptions will not be repeated.

[0013] Embodiment 1 <Semiconductor chip configuration> As shown in FIGS. 1 and 2, a semiconductor chip 1 according to the first embodiment includes a semiconductor substrate 2 and a plurality of pads 3. The semiconductor chip 1 includes a semiconductor substrate 2 and a plurality of pads 3. The semiconductor substrate 2 and the pads 3 are made of a material such as aluminum.

[0014] The semiconductor substrate 2 has a first surface 2A and a second surface 2B located on the opposite side to the first surface 2A. In this specification, a plan view means a viewpoint seen from a direction perpendicular to the first surface 2A. The semiconductor substrate 2 is a semiconductor substrate having a first surface 2A and a second surface 2B on which an arbitrary element structure is formed. In a plan view, the outer shape of the semiconductor substrate 2 is, for example, rectangular. The semiconductor substrate 2 includes, for example, silicon carbide (SiC) as a base material.

[0015] The semiconductor element is, for example, a vertical semiconductor element. The semiconductor element is, for example, a power semiconductor element. The semiconductor element is, for example, a switching element such as an IGBT (Insulated Gate Bipolar Transistor), a GCT (Gate Commutated Turn-off thyristor), or a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). The semiconductor element is, for example, provided to control a main current flowing through the main pad 4 in response to signals input to a first control pad 6 and a second control pad 7 described later.

[0016] In addition, in a plan view, the outer shape of the semiconductor substrate 2 is not limited to a rectangular shape. The semiconductor substrate 2 is not limited to a vertical semiconductor element. The semiconductor substrate 2 may contain a compound semiconductor material other than silicon (Si) or SiC as a base material. The semiconductor substrate 2 is not limited to a switching element, and may be a rectifying element such as a diode.

[0017] The multiple pads 3 are arranged at intervals from one another on the first surface 2A of the semiconductor substrate 2. Each of the multiple pads 3 is electrically connected to a semiconductor element. The multiple pads 3 include, for example, a main pad 4, a first control pad 6, and a second control pad 7. A main current of the semiconductor element flows through the main pad 4. A signal for controlling the main current is input to and output from the first control pad 6 and the second control pad 7.

[0018] In a plan view, each of the first control pad 6 and the second control pad 7 is arranged next to the main pad 4 at a distance in a first direction X along the first surface 2A. In a plan view, each of the first control pad 6 and the second control pad 7 is arranged next to the main pad 4 at a distance in a second direction Y along the first surface 2A and perpendicular to the first direction X. In a plan view, each of the first control pad 6 and the second control pad 7 is arranged within a rectangular region corresponding to a field of view FV described later. The distance between the first control pad 6 and the second control pad 7 is, for example, equal to or greater than the width of the first control pad 6 in the Y direction.

[0019] In plan view, the second control pad 7 includes an irregularly shaped portion 7A whose outer shape is different from that of the first control pad 6. From a different perspective, in plan view, the first control pad 6 includes an irregularly shaped portion 6A whose outer shape is different from that of the second control pad 7.

[0020] The irregularly shaped portion 7A is, for example, a part of the outer edge of the second control pad 7. From a different perspective, in a plan view, each of the first control pad 6 and the second control pad 7 further includes congruent portions 6B, 7B that are located at corresponding positions between the first control pad 6 and the second control pad 7 and have congruent outer shapes. Note that the entire outer edge of the second control pad 7 may be configured as the irregularly shaped portion 7A.

[0021] The irregularly shaped portions 6A and 7A are formed at positions corresponding to each other between the first control pad 6 and the second control pad 7 in a plan view.

[0022] In this specification, when two irregularly shaped portions are formed at positions corresponding to each other between two pads in a plan view, it means that, in a plan view, the directions from the center of each of the two pads toward the irregularly shaped portions are equal to each other. In a plan view, the relative positions of the congruent portion and the irregularly shaped portion in each of the two pads are equal to each other. In a plan view, imaginary lines connecting the center and the irregularly shaped portion in each of the two pads are, for example, parallel to each other.

[0023] In a plan view, the direction from the center toward the irregularly shaped portion 6A in the first control pad 6 is equal to the direction from the center toward the irregularly shaped portion 7A in the second control pad 7. In a plan view, the relative positions of the congruent portions 6B, 7B and the irregularly shaped portions 6A, 7A in the first control pad 6 and the second control pad 7 are equal to each other. In a plan view, an imaginary line A connecting the center and the irregularly shaped portion 6A in the first control pad 6 is parallel to an imaginary line B connecting the center and the irregularly shaped portion 7A in the second control pad 7, for example.

[0024] When recognized together with at least the irregularly shaped portion 6A, the irregularly shaped portion 7A can indicate the position and orientation of the semiconductor chip 1 in a planar view. For example, in the semiconductor chip 1 shown in Fig. 1, the irregularly shaped portion 7A can indicate that the direction in which the imaginary straight lines A and B are aligned is the Y direction, and that the direction facing the side on which the irregularly shaped portion 7A is formed with respect to the center of the second control pad 7 in a direction perpendicular to the Y direction in a planar view is the X direction, by being recognized together with the irregularly shaped portion 6A and the congruent portions 6B and 7B.

[0025] In a plan view, the outer shape of the first control pad 6 is, for example, a rectangular shape with four rounded corners. The first control pad 6 has a plurality of corners 61, 62, 63, 64 and a plurality of sides connecting two adjacent corners. In a plan view, the first control pad 6 has, for example, rotational symmetry around the center of the first control pad 6.

[0026] In a plan view, the second control pad 7 has a plurality of corners 71, 72, 73, and 74, and a plurality of sides connecting two adjacent corners. The corner 71 is, for example, composed of a plurality of corners 75, 76, and 77, and a plurality of sides connecting these. In a plan view, each of the plurality of corners 71, 72, 73, and 74 is located at a position corresponding to the plurality of corners 61, 62, 63, and 64. In a plan view, the second control pad 7 does not have rotational symmetry around the center of the second control pad 7.

[0027] The second control pad 7 includes, for example, one irregularly shaped portion 7A. The irregularly shaped portion 7A is formed, for example, at a corner 71 of the second control pad 7. From a different perspective, the irregularly shaped portion 6A is formed, for example, at a corner 61 of the first control pad 6. In a plan view, the corner 71 is located, for example, at a position among the multiple corners of the second control pad 7 that is closest to the corner of the semiconductor substrate 2.

[0028] The irregularly shaped portion 7A has a recess whose outer shape is concave in comparison with the first control pad 6, for example. The irregularly shaped portion 7A includes multiple corners 75, 76, 77. The number of corners of the second control pad 7 is greater than the number of corners of the first control pad 6. The shape of the recess is not particularly limited. The dimensions of the recess are not particularly limited as long as they can be recognized as an alignment mark by a mounting device used in the process of mounting the semiconductor chip 1 on a mounting substrate in the manufacturing method of the semiconductor device 100 described later.

[0029] The joint parts 6B, 7B are formed by the remaining outer peripheries of the first control pad 6 and the second control pad 7 excluding the irregularly shaped parts 6A, 7A. The joint part 7B includes corners 72, 73, 74 other than corner 71 and multiple sides of the outer periphery of the second control pad 7. The joint part 6B includes corners 62, 63, 64 other than corner 61 and multiple sides of the outer periphery of the first control pad 6.

[0030] In plan view, the outer shape of the main pad 4 is, for example, a rectangular shape with four rounded corners. In plan view, the outer shape of the first control pad 6 main pad 4 is, for example, a rectangular shape with four rounded corners.

[0031] In a plan view, the occupation area of ​​the main pad 4 is larger than each of the occupation areas of the first control pad 6 and the second control pad 7. In a plan view, the occupation area of ​​the main pad 4 is larger than, for example, the sum of the occupation areas of the first control pad 6 and the second control pad 7.

[0032] The plurality of pads 3 may further include a third control pad 8. The third control pad 8 is, for example, arranged side by side with a space from the main pad 4 in the first direction X, and arranged with a space from the first control pad 6 in the second direction Y.

[0033] The semiconductor chip 1 does not have, on the first surface 2A, any alignment marks that are not electrically connected to the semiconductor element, that is, any patterns that function only as alignment marks.

[0034] The semiconductor chip 1 further includes a protective film (not shown) formed so as to surround the periphery of the plurality of pads 3 on the first surface 2A, for example.

[0035] <Method of manufacturing semiconductor chips> The semiconductor chip 1 can be manufactured in the same manner as a conventional semiconductor chip. The second control pad 7 having the irregularly shaped portion 7A can be formed by any method, for example, by patterning a conductive film formed on the first surface 2A using a mask corresponding to the irregularly shaped portion 7A.

[0036] <Configuration of Semiconductor Device> As shown in FIG. 3, the semiconductor device 100 of the first embodiment comprises a semiconductor chip 1, a mounting substrate 110, a first connecting member 111, a second connecting member 112, a third connecting member 113, a fourth connecting member 114, and a sealing member (not shown).

[0037] The semiconductor chip 1 is mounted on a mounting substrate 110. An area on the mounting substrate 110 where the semiconductor chip 1 is to be mounted is designated in advance, and the semiconductor chip 1 is bonded to that area with a bonding material. The mounting substrate 110 may be a substrate made of a metal such as copper or aluminum. The mounting substrate 110 may also be a substrate whose base material is ceramic, resin, or the like.

[0038] The first connection member 111 is electrically connected to the first control pad 6. The second connection member 112 is electrically connected to the second control pad 7. The third connection member 113 is electrically connected to the main pad 4. The fourth connection member 114 is electrically connected to the third control pad 8. Each of the first connection member 111, the second connection member 112, the third connection member 113, and the fourth connection member 114 is electrically connected to another member (not shown) included in the semiconductor device 100, for example. The first connection member 111, the second connection member 112, and the fourth connection member 114 are, for example, wires or ribbons. The third connection member 113 is, for example, a lead terminal.

[0039] In the semiconductor device 100, the semiconductor chip 1 is sealed with a sealing member.

[0040] <Method of Manufacturing Semiconductor Device> The semiconductor device 100 can be manufactured in the same manner as a conventional semiconductor device. The manufacturing method of the semiconductor device 100 includes a first step of preparing a semiconductor chip 1 and a second step of mounting the semiconductor chip 1 prepared in the first step on a mounting substrate 110.

[0041] In the second step, the first control pad 6 and the second control pad 7 are simultaneously recognized by the mounting device and used as alignment marks. The mounting device can grasp the position and orientation of the semiconductor chip 1 in a plan view by simultaneously recognizing the irregular portions 6A and 7A within its field of view FV (see FIG. 3).

[0042] The manufacturing method of the semiconductor device 100 further includes, after the second step, a third step of electrically connecting each of the first connecting member 111, the second connecting member 112, the third connecting member 113 and the fourth connecting member 114 to each of the first control pad 6, the second control pad 7, the third control pad 8 and the main pad 4.

[0043] <Effects> In the semiconductor chip 1, the second control pad 7 (second pad) includes an irregularly shaped portion 7A whose outer shape is different from that of the first control pad 6 (first pad). Therefore, the first control pad 6 and the second control pad 7 are wiring components for electrically connecting the semiconductor element in the semiconductor chip 1 to an external component in the semiconductor device 100, but can also function as an alignment mark. Therefore, the occupied area of ​​the first control pad 6 and the second control pad 7 is smaller than the total occupied area of ​​a pad having an equivalent occupied area and an alignment mark formed in a region different from the pad. As a result, the semiconductor chip 1 can be miniaturized while being provided with an alignment mark that shows a high recognizability equivalent to or higher than that of a conventional semiconductor chip provided with a pad electrically connected to an external component and an alignment mark formed in a region different from the pad.

[0044] Furthermore, the first control pad 6 and the second control pad 7 that can function as alignment marks are wiring components as described above, and therefore can be configured to be larger than alignment marks formed separately from pads in conventional semiconductor chips. Therefore, the semiconductor chip 1 can be made smaller while being provided with alignment marks that show higher recognition compared to the conventional semiconductor chips described above. Such a semiconductor chip 1 is suitable for power semiconductor chips, the chip size of which is being reduced, for example, power semiconductor chips whose base material is silicon carbide (SiC).

[0045] In the semiconductor chip 1, each of the first control pad 6 and the second control pad 7 further includes a congruent portion 6B, 7B. In this case, the orientation of the semiconductor chip 1 can be recognized from relative position information of the irregularly shaped portion 7A with respect to each of the irregularly shaped portion 6A and the congruent portion 7B. Furthermore, in this case, the second control pad 7 including the irregularly shaped portion 7A and the congruent portion 7B can be easily formed as including at least one recess in comparison with the first control pad 6.

[0046] In the semiconductor chip 1, the first control pad 6 and the second control pad 7 are adjacent to each other among the multiple pads 3. In this way, the field of view FV required to simultaneously recognize the first control pad 6 and the second control pad 7 of the semiconductor chip 1 can be smaller than that when the first control pad 6 and the second control pad 7 are not adjacent to each other. Therefore, the first control pad 6 and the second control pad 7 can be observed at a higher magnification, so that the recognition of the irregular portion 7A is improved, and the above-mentioned mounting of the semiconductor chip 1 can be performed more efficiently. In addition, the above-mentioned conventional semiconductor chip generally has one alignment mark formed at one end of the chip in a plan view and another alignment mark formed at the other end of the chip in a plan view. Therefore, in the process of mounting a conventional semiconductor chip on a mounting board, the mounting device generally recognizes the two alignment marks individually and sequentially, thereby aligning the semiconductor chip. In contrast, according to the semiconductor chip 1, the first control pad 6 and the second control pad 7 can be aligned by being recognized simultaneously, so that the mounting can be performed more efficiently than in the conventional semiconductor chip described above.

[0047] Since the semiconductor device 100 includes the semiconductor chip 1, it can be made smaller than a semiconductor device including a conventional semiconductor chip. Furthermore, in the manufacturing method of the semiconductor device 100, the semiconductor chip 1 is mounted on the mounting substrate 110 using the first control pad 6 and the second control pad 7 as alignment marks. Therefore, the manufacturing efficiency of the semiconductor device 100 is higher than that of the conventional semiconductor device.

[0048] <Modification> 4, a third control pad 8 may be disposed between the first control pad 6 and the second control pad 7. The first control pad 6 and the second control pad 7 do not have to be adjacent to each other. The second control pad 7 may be disposed adjacent to the third control pad 8. In this case, the first control pad 6 and the second control pad 7 can be configured as an alignment mark that is larger than the alignment mark of the conventional semiconductor chip described above and exhibits high recognition ability.

[0049] In the semiconductor chip 1, the irregularly shaped portion 7A may be formed at any position on the outer edge of the second control pad 7 and have any shape. As shown in FIG. 5, the irregularly shaped portion 7A may be formed at a corner 72. In this case, the corner 71 may be included in the joint portion 7B. As shown in FIG. 6, the irregularly shaped portion 7A may be formed on one side. In this case, multiple corners may be included in the joint portion 7B.

[0050] 7, the irregularly shaped portion 7A may have a convex portion whose outer shape is convex in comparison with the first control pad 6. In a plan view, the outer shape of the second control pad 7 has an outer shape that is realized when, for example, one relatively large rounded rectangular corner is overlapped with one relatively small rounded rectangular corner. The corner 71 is, for example, composed of a plurality of corners 75, 76, 77, 78, 79 and a plurality of sides connecting these corners.

[0051] The irregularly shaped portion 7A may have both the recessed portion and the protruding portion. For example, at least one of the corners 77, 78, and 79 shown in FIG.

[0052] Preferably, the irregularly shaped portion 7A is formed on at least one of the multiple corners 71, 72, 73, and 74 of the second control pad 7. In this way, even when the area that the irregularly shaped portion 7A can occupy is limited, the degree of freedom in the shape and arrangement of the irregularly shaped portion 7A can be increased compared to when the irregularly shaped portion 7A is formed on one of the multiple sides.

[0053] Embodiment 2 Unless otherwise specified, the semiconductor chip and the semiconductor device according to the second embodiment have the same configuration and the same action and effect as those of the first embodiment. Therefore, the same configuration as that of the first embodiment is given the same reference numerals and the description will not be repeated.

[0054] 8, in the semiconductor chip 12 according to the second embodiment, the distance between the second control pad 7 and the first control pad 6 in the first direction X is narrower than the width of the second control pad 7 in the first direction X. The distance between the second control pad 7 and the first control pad 6 in the first direction X is, for example, the smallest distance between two pads adjacent to each other in the first direction X or the second direction Y among the multiple pads 3.

[0055] According to the semiconductor chip 12, the distance between the second control pad 7 and the first control pad 6 in the first direction X can be shorter than that of the semiconductor chip 1, and therefore the visual field FV required to simultaneously recognize the first control pad 6 and the second control pad 7 of the semiconductor chip 12 can be smaller than the visual field FV required to simultaneously recognize the first control pad 6 and the second control pad 7 of the semiconductor chip 1. Therefore, according to the semiconductor chip 12, the visibility of the irregular-shaped portion 7A is further improved compared to the semiconductor chip 1, and the above-mentioned mounting of the semiconductor chip 1 can be performed more efficiently.

[0056] Semiconductor chip 12 according to the second embodiment can also be modified in the same manner as semiconductor chip 1 according to the first embodiment.

[0057] Embodiment 3 Unless otherwise specified, the semiconductor chip and the semiconductor device according to the third embodiment have the same configuration and the same action and effect as those of the first embodiment. Therefore, the same configuration as that of the first embodiment is given the same reference numerals and the description will not be repeated.

[0058] 9, in the semiconductor chip 13 according to the third embodiment, the multiple pads 3 include a first main pad 4 (first pad), a second main pad 5 (second pad), and multiple control pads 8. The second main pad 5 is disposed at a distance from the first main pad 4 in the first direction X. The first main pad 4 and the second main pad 5 are disposed at a distance from the multiple control pads 8 in the second direction Y. The area occupied by each of the first main pad 4 and the second main pad 5 is larger than the area occupied by each of the multiple control pads 8.

[0059] In plan view, the second main pad 5 includes an irregularly shaped portion 5A whose outer shape is different from that of the first main pad 4. From a different perspective, in plan view, the first main pad 4 includes an irregularly shaped portion 4A whose outer shape is different from that of the second main pad 5.

[0060] The irregularly shaped portion 5A is formed, for example, at a corner of the second main pad 5. In a plan view, the irregularly shaped portion 5A is formed, for example, at one corner of the multiple corners of the second main pad 5 that is located on the multiple control pads 8 side.

[0061] The irregularly shaped portion 5A has a recess whose outer shape is concave in comparison with the first main pad 4, for example.

[0062] The irregularly shaped portion 5A is, for example, a part of the outer edge of the second main pad 5. From a different point of view, in a plan view, each of the first main pad 4 and the second main pad 5 further includes congruent portions 4B, 5B that are located at corresponding positions between the first main pad 4 and the second main pad 5 and have congruent outer shapes.

[0063] The irregularly shaped portions 4A, 5A may have a configuration similar to that of the irregularly shaped portions 6A, 7A of the semiconductor chip 1. The joint portions 4B, 5B may have a configuration similar to that of the joint portions 6B, 7B of the semiconductor chip 1. The entire outer edge of the second main pad 5 may be configured as the irregularly shaped portion 5A.

[0064] In the semiconductor chip 13, the first main pad 4 and the second main pad 5 are simultaneously recognized by a mounting device and are used as alignment marks. The first main pad 4 and the second main pad 5 are larger than the first control pad 6 and the second control pad 7, and therefore can be configured as alignment marks that exhibit higher recognition than the first control pad 6 and the second control pad 7.

[0065] Semiconductor chip 13 according to the third embodiment can also be modified in the same manner as semiconductor chip 1 according to the first embodiment.

[0066] Embodiment 4 Unless otherwise specified, the semiconductor chip and the semiconductor device according to the fourth embodiment have the same configuration and the same action and effect as those of the first embodiment. Therefore, the same configuration as that of the first embodiment is given the same reference numerals and the description will not be repeated.

[0067] 10 and 11, the semiconductor chip 14 according to the fourth embodiment further includes an outer edge portion 9 arranged so as to surround the second control pad 7 (first pad) on the first surface 2A of the semiconductor substrate 2. The outer edge portion 9 can be seen simultaneously with the second control pad 7 and its irregular shaped portion 7A in a plan view. The outer edge portion 9 is arranged at least within the field of view FV.

[0068] The visible light reflectance of the material constituting the outer edge portion 9 is lower than the visible light reflectance of the material constituting the second control pad 7. The material constituting the second control pad 7 is a conductive material, and includes at least one selected from the group consisting of gold (Au), copper (Cu), nickel (Ni), and aluminum (Al). The material constituting the outer edge portion 9 may be any material as long as it has a visible light reflectance lower than that of the material constituting the second control pad 7, but is preferably a material having electrical insulation properties. The material constituting the outer edge portion 9 is, for example, a polyimide or nitride film. In this case, the outer edge portion 9 may be configured as a part of a protective film around each of the multiple pads 3, for example.

[0069] The semiconductor chip 14 may further include a protective film disposed so as to surround each of the pads 3 and the outer edge portion 9.

[0070] According to the semiconductor chip 14, since there is a large difference in color between the irregular portion 7A of the second control pad 7 and the outer edge 9, the first control pad 6, the second control pad 7, and the outer edge 9 can function as alignment marks with high recognition ability.

[0071] Although the embodiment of the present disclosure has been described above, the above-mentioned embodiment can be modified in various ways. The scope of the present disclosure is not limited to the above-mentioned embodiment. The scope of the present disclosure is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0072] 1, 12, 13, 14 semiconductor chip, 2 semiconductor substrate, 2A first surface, 2B second surface, 3 pad, 4, 5 main pad, 4A, 5A, 6A, 7A irregular portion, 4B, 5B, 6B, 7B joint portion, 6 first control pad, 7 second control pad, 8 third control pad, 9 outer edge portion, 61, 62, 63, 64, 71, 72, 73, 74, 75, 76, 77, 78, 79 corner portion, 100 semiconductor device, 110 mounting substrate, 111 first connecting member, 112 second connecting member, 113 third connecting member, 114 fourth connecting member.

Claims

1. a semiconductor substrate having a first surface and a semiconductor element formed thereon; a plurality of pads electrically connected to the semiconductor element and spaced apart from one another on the first surface; the plurality of pads includes a first pad and a second pad; A semiconductor chip, wherein, in a plan view, the second pad includes an irregularly shaped portion whose outer shape is irregular in comparison with the first pad.

2. 2. The semiconductor chip according to claim 1, wherein, in the planar view, each of the first pad and the second pad further includes a congruence portion that is located at a corresponding position between the first pad and the second pad and has an outer shape that is congruent to each other.

3. In the plan view, each of the first pad and the second pad has a corner portion located at a corresponding position between the first pad and the second pad, The semiconductor chip according to claim 1 , wherein the irregularly shaped portion is provided at the corner of the second pad.

4. 2. The semiconductor chip according to claim 1, wherein said irregularly shaped portion of said second pad has a concave portion or a convex portion, the outer shape of which is concave or convex in comparison with said first pad.

5. The semiconductor chip according to claim 1 , wherein the first pad and the second pad are adjacent to each other among the plurality of pads.

6. The plurality of pads further includes a third pad through which a main current of the semiconductor device flows; 2. The semiconductor chip according to claim 1, wherein a signal for controlling the main current is input to and output from the first pad and the second pad.

7. A main current of the semiconductor element flows through the first pad and the second pad, 2. The semiconductor chip according to claim 1, wherein the plurality of pads further include a third pad and a fourth pad for inputting and outputting a signal for controlling the main current.

8. an outer edge portion that is arranged around the second pad on the first surface and that can be seen in the plan view; The semiconductor chip according to claim 1 , wherein the visible light reflectance of a material constituting said outer edge portion is lower than the visible light reflectance of a material constituting said second pad.

9. The semiconductor chip of claim 1 , wherein the semiconductor element comprises silicon carbide.

10. A semiconductor chip according to any one of claims 1 to 9, a mounting substrate on which the semiconductor chip is mounted; a first connection member electrically connected to the first pad; a second connection member electrically connected to the second pad.

Images