Use of material layer containing molybdenum to protect gate dielectric

Abstract

To provide a method for forming an integrated circuit having a gate electrode that includes at least one layer containing molybdenum.SOLUTION: A semiconductor device 101 includes a gate structure that includes a gate electrode, on a gate dielectric 110, made up of a conductive fill 108 and one or more metal work function layers 109. The gate structure extends around a fin or any number of nanowires, nanoribbons, or nanosheets of a semiconductor material. The gate electrode includes one or more conductive layers on the gate dielectric, and at least one of those conductive layers contains molybdenum (e.g., molybdenum nitride). The conductive layer containing molybdenum may be used during the formation of the gate dielectric (e.g., during an annealing process), thus resulting in a higher quality gate dielectric.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] As the size of integrated circuits continues to shrink, numerous challenges arise. For example, it becomes increasingly more difficult to reduce the size of memory and logic cells in interconnect structures as device spacing in device layers decreases. Maintaining a particular level of quality among various transistor elements can be a challenge due to the number of different manufacturing processes that these transistors may undergo. Thus, numerous non-trivial challenges remain with regard to the formation of such high density semiconductor devices. [Brief description of the drawings]

[0002] [Figure 1A] 1 is a cross-sectional view of an integrated circuit including a gate structure including at least one layer including molybdenum, according to one embodiment of the present disclosure. [Figure 1B] 1 is a cross-sectional view of an integrated circuit including a gate structure including at least one layer including molybdenum, according to one embodiment of the present disclosure.

[0003] [Figure 2A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit constructed with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 2B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit constructed with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0004] [Figure 3A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 3B]1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0005] [Figure 4A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 4B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0006] [Figure 5A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 5B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0007] [Figure 6A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 6B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0008] [Figure 7A]1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 7B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0009] [Figure 8A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 8B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0010] [Figure 9A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 9B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0011] [Figure 10A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 10B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0012] [Figure 11A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 11B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0013] [Figure 12A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 12B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0014] [Figure 13A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 13B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0015] [Figure 14A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 14B]1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0016] [Figure 15A] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure. [Figure 15B] 1A-1C are cross-sectional views illustrating different stages in an exemplary process for forming an integrated circuit configured with a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0017] [Figure 16] 2 is a cross-sectional view of another exemplary semiconductor device configured with a gate structure including at least one layer including molybdenum, according to an embodiment of the present disclosure.

[0018] [Figure 17] 1 illustrates a cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure.

[0019] [Figure 18] 1 is a flow chart of a manufacturing process for an integrated circuit including a gate structure that includes at least one layer that includes molybdenum, according to one embodiment of the present disclosure.

[0020] [Figure 19] 1 illustrates a computing system including one or more integrated circuits, variously described herein, according to one embodiment of the present disclosure.

[0021] The following detailed description will proceed with reference to exemplary embodiments, many alternatives, modifications and variations of which will become apparent in light of this disclosure. It will be further understood that these figures are not necessarily drawn to scale or intended to limit the disclosure to the specific configurations shown. For example, while some figures generally show perfect straight lines, right angles and smooth surfaces, given real-world limitations of the processing equipment and techniques used, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), some features may have surface topologies or may not be otherwise smooth. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Techniques are provided herein for forming integrated circuits having gate electrodes that include at least one layer that includes molybdenum. These techniques can be used in any number of integrated circuit applications and are particularly useful for logic and memory cells, such as cells that use FinFETs or gate-all-around transistors (e.g., ribbon FETs and nanowire FETs). In one such example, a FET (field effect transistor) includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend between source and drain regions in a first direction, while the gate structure extends over the semiconductor material in a second direction that is substantially perpendicular to the first direction. The gate electrode includes one or more conductive layers on the gate dielectric, at least one of which includes molybdenum and nitrogen (e.g., molybdenum nitride). The conductive layer that includes molybdenum may be used during the formation of the gate dielectric to protect the gate dielectric during an annealing step, thus resulting in a higher quality gate dielectric. Numerous variations and embodiments will become apparent in light of this disclosure. [overview]

[0023] As mentioned above, numerous non-trivial challenges remain with respect to integrated circuit fabrication. More specifically, the gate dielectric of a FET is a critical element that separates the gate electrode from the semiconductor material of the transistor. Any degradation in the quality of the gate dielectric can negatively impact the performance of the transistor. A given gate dielectric may undergo an annealing process to enhance the integrity of the gate dielectric and to incorporate certain desired elements into the gate dielectric. Additional layers of material may be deposited on the gate dielectric prior to the annealing, which may provide some degree of protection to the gate dielectric during the annealing process. However, the deposition of these additional layers may actually damage the underlying gate dielectric, causing it to be partially removed later during fabrication. For example, a layer of titanium nitride is often deposited on the gate dielectric prior to the annealing step. However, the deposition of titanium nitride requires the use of high temperature chlorine-based precursors (TiCl 4 ) is used, which can create by-products that attack the gate dielectric and increase the likelihood that the gate dielectric will be removed during subsequent gate patterning processes.

[0024] Therefore, and according to one embodiment of the present disclosure, a technique is provided herein for protecting a gate dielectric during device fabrication. This technique can be used, for example, to replace a layer of titanium nitride (TiN) or other layer that may cause damage to the underlying gate dielectric. Such potentially damaging layers (e.g., TiN) can be replaced with a layer containing molybdenum. For example, a layer containing molybdenum can be deposited on top of the gate dielectric to effectively protect the gate dielectric during annealing. The layer containing molybdenum can then remain on top of the gate dielectric as one of the conductive layers in the gate electrode. According to some embodiments, the gate dielectric includes at least one high-k dielectric layer (e.g., a material having a dielectric constant higher than that of silicon dioxide or higher than 3.9), such as hafnium dioxide. The conductive layer used on the gate dielectric can include, for example, molybdenum nitride. During the formation of the gate electrode, an additional conductive layer can be formed on the layer of molybdenum nitride to create a work function metal layer and a metal fill on the work function metal layer. The material types and relative thicknesses of the various work function metal layers may vary depending on whether the transistor is n-type or p-type and the desired threshold voltage of the transistor. Generally, the threshold voltage of a device decreases with increasing thickness of a given work function layer. In some embodiments, a p-type FET includes multiple work function layers including a material layer including molybdenum nitride, a material layer including tantalum nitride, and a material layer including titanium nitride. In some embodiments, an n-type FET includes multiple work function layers including a material layer including molybdenum nitride, and a material layer including tantalum nitride (e.g., no titanium nitride). In some embodiments, the layer including molybdenum nitride is removed for some n-type FET devices, so that those n-type FET devices do not include a work function layer including molybdenum, but still benefit from the improved gate dielectric. An exemplary fill metal on the work function layer is tungsten. The quality of the gate dielectric may be determined using measurements of parameters such as gate leakage, threshold voltage, and maximum voltage before transistor breakdown (VMAX).

[0025] According to one embodiment, a method of forming an integrated circuit includes forming a fin including one or more semiconductor layers, the fin extending above a substrate in a first direction; forming a sacrificial gate, the sacrificial gate extending above the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming source or drain regions from edges of the one or more semiconductor layers and within the recess; removing the sacrificial gate from a periphery of the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, where the conductive layer comprises molybdenum and nitrogen; after forming the conductive layer, annealing the one or more dielectric layers; and forming one or more additional conductive layers above the conductive layer.

[0026] According to another embodiment, an integrated circuit includes a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers over the semiconductor region and one or more conductive layers over the one or more dielectric layers. The one or more conductive layers include a conductive layer including molybdenum and nitrogen. The source or drain region may include, for example, silicon, germanium, or silicon germanium (SiGe) doped with an n-type dopant.

[0027] According to another embodiment, an electronic device includes a chip package including one or more dies. At least one of the one or more dies includes a semiconductor device having a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers over the semiconductor region and one or more conductive layers over the one or more dielectric layers. The one or more conductive layers include a conductive layer including molybdenum and nitrogen. The source or drain region may include, for example, silicon, germanium, or SiGe doped with an n-type dopant.

[0028] These techniques may be used with any type of planar or non-planar transistor, including FinFETs (sometimes referred to as double-gate or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes referred to as gate-all-around transistors) or fork-sheet transistors, to name a few. More generally, the techniques described herein may benefit any transistor architecture having a gate dielectric layer that undergoes a relatively high temperature anneal (e.g., 500° C. to 700° C.). The source and drain regions may be, for example, doped portions of a given fin or substrate, or epitaxial regions that are deposited during an etch-and-replace source / drain formation process. The dopant type in the source and drain regions depends on the polarity of the corresponding transistor. The gate structures may be implemented using a gate-first or gate-last process (sometimes referred to as a replacement metal gate (i.e., RMG) process) or any other gate formation process. Any number of semiconductor materials may be used in forming transistors, such as Group IV materials (eg, silicon, germanium, silicon germanium) or Group III-V materials (eg, gallium arsenide, indium gallium arsenide).

[0029] Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable exemplary analytical tools. For example, in some exemplary embodiments, such tools may indicate the presence of a metal layer comprising molybdenum as part of the gate electrode of a transistor. In some embodiments, the layer comprising molybdenum also comprises nitrogen and is disposed between the gate dielectric and one or more other metal layers that are part of the gate electrode. The layer comprising molybdenum may be observed directly on the gate dielectric.

[0030] It should be readily understood that the meaning of "above" and "over" in this disclosure should be interpreted in the broadest way, such that "above" and "over" do not only mean "directly above" something, but also mean above something when there is an intermediate feature or layer between them. Furthermore, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," "top," and "bottom," may be used herein to facilitate explanation to describe the relationship of one element or feature to another element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and therefore the spatially relative descriptors used herein may be interpreted similarly.

[0031] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over an entire underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Additionally, a layer may be a region of a uniform or non-uniform continuous structure, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved) with a relatively uniform thickness throughout the layer.

[0032] "Compositionally distinct" or "compositionally distinct" materials as used herein refer to two materials that have different chemical compositions. This compositional difference can be due, for example, to elements that are present in one material but not the other (e.g., SiGe is compositionally distinct from silicon), or one material has all the same elements as a second material, but at least one of those elements is intentionally provided in one material at a different concentration than the other (e.g., SiGe with 70 atomic percent germanium is compositionally distinct from SiGe with 25 atomic percent germanium). In addition to such chemical compositional diversity, the materials can also have distinct dopants (e.g., gallium and magnesium), or dopants that are the same but at different concentrations. In yet other embodiments, compositionally distinct materials can further refer to two materials that have different crystallographic orientations. For example, (110) silicon is compositionally distinct from or distinct from (100) silicon. Creation of stacks of different orientations can be accomplished, for example, using blanket wafer layer transfer. If two materials are elementally dissimilar, then one of the materials has an element that is not present in the other material. [architecture]

[0033] FIG. 1A is a cross-sectional view through various semiconductor devices 101 along the "fin direction" according to one embodiment of the present disclosure, showing a semiconductor body extending between the source or drain regions of each semiconductor device 101. FIG. 1B shows a cross-sectional view into the page (or out of the page, as the case may be) that is parallel to the cross-section of FIG. 1A, such that the cross-sectional view cuts across a gate structure that is away from the semiconductor body of the transistor but still extends above the semiconductor body. Each of the semiconductor devices may be a non-planar metal-oxide-semiconductor (MOS) transistor, such as, for example, a tri-gate (e.g., FinFET) or a gate-all-around (GAA) transistor, although other transistor topologies and types may also benefit from the techniques provided herein. Examples herein show semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires or nanosheets extending between source and drain regions). Other examples may have a fork-sheet structure with p-type and n-type devices separated by a dielectric spine or structure.

[0034] The semiconductor materials used in each of the semiconductor devices may be formed from a semiconductor substrate 102. The substrate 102 may be a bulk substrate including, for example, a Group IV semiconductor material (such as silicon, germanium, or SiGe), a Group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which a transistor may be formed. Alternatively, the substrate may be a semiconductor-on-insulator substrate having a desired semiconductor layer (e.g., silicon on silicon dioxide) on a buried insulator layer. Alternatively, the substrate may be a multilayer substrate or superlattice suitable for the formation of nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates may be used. In some embodiments, the substrate 102 is removed and replaced with one or more backside interconnect layers to form backside signal and power routing.

[0035] The semiconductor region or regions of these devices may include fins that may be intrinsic to the substrate 102 (formed from the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed of material deposited onto the substrate 102. In one such exemplary case, a blanket layer of SiGe may be deposited onto a silicon substrate and then patterned and etched to form a number of SiGe fins extending from the substrate. In yet other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons and nanosheets during gate formation processing, where one type of alternating layer is selectively etched away to free the other type of alternating layer in the channel region, such that a gate-all-around or fork-sheet gate process may then be performed. Again, in some examples, these alternating layers may be blanket deposited and then etched into a fin, or deposited into a fin-shaped trench.

[0036] According to some embodiments, the semiconductor device 101 further includes a sub-fin region 103 extending below the semiconductor device 101 in a first direction. According to some embodiments, the sub-fin region 103 is a portion of a corresponding semiconductor fin that remains after formation of the various transistors, and may be formed from the substrate 102. Thus, the sub-fin region 103 may include the same semiconductor material as the substrate 102 (or any semiconductor material in situations where the substrate 102 is removed).

[0037] Each semiconductor device 101 includes one or more semiconductor regions (also referred to as channel regions), such as one or more nanoribbons 104 extending between epitaxial source or drain regions 106 in a first direction. A gate structure extends in a second direction (e.g., into and out of the page) over the one or more semiconductor regions (e.g., nanoribbons 104) of a given semiconductor device 101 to form a transistor gate. A sub-fin region 103 may extend along the first direction beneath the one or more nanoribbons 104 and may be flanked by a dielectric fill 105 in areas not beneath the one or more nanoribbons 104, as shown in FIG. 1B. Thus, the dielectric fill 105 may function as a shallow trench isolation (STI) between adjacent sub-fins along the second direction (e.g., into and out of the page).

[0038] Either of the source or drain regions 106 may function as either the source or drain region, depending on the application and dopant profile. Any semiconductor material suitable for source and drain regions (e.g., Group IV and III-V semiconductor materials) may be used for either of the source or drain regions 106 shown. In any such case, the composition and doping of the source or drain regions 106 may be the same or different, depending on the polarity of the transistor. For example, any semiconductor device that is a p-channel transistor includes a high concentration of p-type dopant in the associated source or drain region 106, and any semiconductor device that is an n-channel transistor includes a high concentration of n-type dopant in the associated source or drain region 106. An exemplary p-type dopant includes boron, and an exemplary n-type dopant includes phosphorus. Any number of source and drain configurations and materials may be used. In some examples, the n-type source or drain region includes silicon doped with phosphorus, and the p-type source or drain region includes silicon germanium doped with boron.

[0039] According to some embodiments, the gate structure may include a gate electrode composed of a conductive fill 108 and one or more metal work function layers 109. The gate structure also includes a gate dielectric 110, which may represent any number of dielectric layers. The conductive fill 108 may include any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some examples, the conductive fill 108 includes tungsten (W), but other metals or conductive materials may be used, such as aluminum (Al), ruthenium (Ru), cobalt (Co), or doped polysilicon. In some embodiments, one or both of the semiconductor devices 101 are p-channel devices in which one or more work function layers 109 include a layer of molybdenum nitride (MoN). The other metal work function layers 109 of the p-channel device may include tantalum nitride (TaN) and titanium nitride (TiN). In some embodiments, one or both of the semiconductor devices 101 are n-channel devices in which one or more work function layers 109 include a layer of molybdenum nitride (MoN). The other metal work function layer 109 for n-channel devices may include tantalum nitride (TaN). According to some embodiments, a MoN layer may be deposited on the gate dielectric 110 before the annealing procedure and remain on the gate dielectric 110 to function as one of the gate electrode work function metals.

[0040] The gate dielectric 110 may include any suitable gate dielectric material. In some embodiments, the gate dielectric 110 includes a layer of an intrinsic oxide material (e.g., silicon dioxide, germanium dioxide, or SiGe oxide) on the nanoribbons 104 or other semiconductor regions, and a layer of a high-k dielectric material (e.g., hafnium oxide or aluminum oxide) on the intrinsic oxide. According to some embodiments, spacer structures 112 and internal spacers 114 are present along the sidewalls of the gate structure. The spacer structures 112 and internal spacers 114 may be any suitable dielectric material, such as silicon nitride, and may provide isolation between a given gate structure and adjacent source or drain regions 106. The internal spacers 114 may separate adjacent nanoribbons 104 from one another along a third direction (e.g., vertically).

[0041] According to some embodiments, a dielectric capping layer 116 may be present over the gate electrode in the gate trench of the semiconductor device 101. A top surface of the dielectric capping layer 116 may be substantially coplanar with a top surface of the spacer structure 112. In some examples, the dielectric capping layer 116 may include the same dielectric material as the spacer structure 112.

[0042] According to some embodiments, a conductive contact 118 is provided on the source or drain region 106. The conductive contact 118 may comprise any suitable conductive material, such as tungsten, molybdenum, ruthenium, cobalt, or other metals. The conductive contacts 118 may be formed together such that they all comprise the same conductive material.

[0043] 1B, according to some embodiments, a dielectric plug 120 may be present in the source / drain trench to separate the source or drain region 106 from other source or drain regions along a second direction (e.g., into and out of the page). The dielectric plug 120 may be any suitable dielectric material, such as silicon dioxide, silicon oxynitride, or silicon oxycarbide. [Manufacturing method]

[0044] 2A-15A and 2B-15B include cross-sectional views collectively illustrating an exemplary process for forming an integrated circuit configured with a molybdenum-containing work function layer according to one embodiment of the present disclosure. 2A-15A represent cross-sectional views similar to that of FIG. 1A through a series of semiconductor devices, while 2B-15B represent cross-sectional views similar to that of FIG. 1B parallel to the views in FIGS. 2A-15A and away from the semiconductor devices. Since each set of figures sharing the same letter illustrates an exemplary structure resulting from the process flow up to that point, the illustrated structures evolve as the process flow continues, ultimately resulting in the structures illustrated in FIGS. 15A and 15B, which are similar to the structures illustrated in FIGS. 1A and 1B. Such structures may be part of an overall integrated circuit (e.g., a processor or memory chip, etc.) including, for example, digital logic cells and / or memory cells and analog mixed signal circuitry. Thus, the illustrated integrated circuit structure may be part of a larger integrated circuit including other integrated circuits not shown. Although example materials and process parameters are provided, other materials and process parameters may be used, as will be understood in light of this disclosure.

[0045] 2A and 2B each show a cross-sectional view through a substrate 201 having a series of material layers formed thereon, according to one embodiment of the present disclosure. Alternating material layers may be deposited on the substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating sacrificial layers 202 and semiconductor layers 204 may be deposited on the substrate 201. The substrate 201 may be substantially similar to the substrate 102 described above.

[0046] According to some embodiments, the semiconductor layer 204 has a different material composition than the sacrificial layer 202. In some embodiments, the semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material such as indium phosphide (InP) or gallium arsenide (GAA). The sacrificial layer 202 includes a material that can be selectively removed relative to the semiconductor layer 204. In some examples, for example, the semiconductor layer 204 is silicon and the sacrificial layer 202 is SiGe, or vice versa. In some other examples where SiGe is used in each of the semiconductor layers 204 and in the sacrificial layer 202, the germanium concentration differs between the semiconductor layer 204 and the sacrificial layer 202 to enable etch selectivity. For example, the semiconductor layer 204 can include a higher germanium content compared to the sacrificial layer 202.

[0047] Although dimensions may vary from one exemplary embodiment to the next, in some examples, the thickness of each semiconductor layer 204 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each semiconductor layer 204 is substantially the same (e.g., within 1-2 nm). The thickness of each of the sacrificial layers 202 may be about the same as the thickness of each semiconductor layer 204 (e.g., about 5-20 nm). Each of the semiconductor layers 204 and the sacrificial layers 202 may be deposited using any material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) or epitaxial growth.

[0048] 3A and 3B show cross-sectional views of the structure shown in FIGS. 2A and 2B, respectively, after formation of a cap layer 302 and subsequent formation of fins below the cap layer 302, according to one embodiment. The cap layer 302 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 302 is patterned into multiple rows to form corresponding multiple rows of fins from an alternating layer stack of sacrificial layers 202 and semiconductor layers 204. As seen in FIG. 3A, the cap layer 302 extends along the top of each fin in a first direction.

[0049] According to some embodiments, the anisotropic etching process continues through at least a portion of the substrate 201. The portions of the substrate 201 below the fins are not etched, resulting in the sub-fin region 304 as shown in FIG. 3A. The etched portions of the substrate 201 that are not below the fins may be filled with a dielectric fill 306 that acts as a shallow trench isolation (STI) between adjacent fins as shown in FIG. 3B. The dielectric fill 306 may be any suitable dielectric material, such as silicon dioxide. According to some embodiments, the sub-fin region 304 represents the remaining portion of the substrate 201 that is flanked by the dielectric fill 306.

[0050] 4A and 4B show cross-sectional views of the structure shown in FIG. 3A and 3B after formation of a sacrificial gate 402 and spacer structures 404, according to some embodiments. The gate masking layer may first be patterned in strips extending orthogonally across each of the fins (e.g., in a second direction) to form corresponding sacrificial gates 402 in strips below the gate masking layer. The gate masking layer may then be removed or may remain as a cap layer above each sacrificial gate 402. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate masking layer. The sacrificial gate 402 may be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 402 includes polysilicon.

[0051] According to some embodiments, spacer structures 404 are formed along the sidewalls of the sacrificial gate 402. The spacer structures 404 may be conformally deposited (e.g., CVD or ALD) and then etched back or otherwise removed (e.g., via anisotropic or directional etching) from horizontal surfaces, so that the spacer structures 404 remain mostly only on the sidewalls of any exposed structures. The width of the spacer structures 404 (along the first direction) may vary from one example to the next, but in some cases is in the range of 3 nm to 20 nm. According to some embodiments, the spacer structures 404 may be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon oxycarbonitride. In one such embodiment, the spacer structures 404 include nitride and the dielectric fill 306 includes oxide to provide some etch selectivity during final gate processing. Other etch-selective dielectric schemes (e.g., oxide / carbide, carbide / nitride) may also be used for the spacer structures 404 and the dielectric fill 306. In other embodiments, the spacer structures 404 and the dielectric fill 306 are compositionally the same or otherwise similar and etch selectivity is not used.

[0052] 5A and 5B show cross-sectional views of the structure shown in FIG. 4A and 4B after removal of exposed portions of the fin not protected by the sacrificial gate 402 and spacer structure 404, according to some embodiments. The exposed fin portions may be removed using any anisotropic etching process, such as reactive ion etching (RIE), or other directional etching process. According to some embodiments, removal of the exposed fin portions creates source or drain trenches alternating with gate trenches (now filled with the sacrificial gate 402) along a first direction. In some embodiments, at least a portion of the sub-fin region 304 is also removed such that a top surface of the sub-fin region 304 is recessed below a top surface of the dielectric fill 306. The recessed areas above the sub-fin region 304 may be filled with one or more dielectric materials.

[0053] 6A and 6B show cross-sectional views of the structure shown in Figures 5A and 5B after removal of portions of the sacrificial layers 202, according to one embodiment of the present disclosure. An isotropic etching process may be used to selectively recess the exposed ends of each sacrificial layer 202 (e.g., while etching a relatively small amount of the semiconductor layer 204).

[0054] 7A and 7B show cross-sectional views of the structure shown in FIG. 6A and 6B after formation of an inner spacer 702 according to an embodiment of the present disclosure. The inner spacer 702 may have a material composition similar or exactly the same as the spacer structure 404. Thus, the inner spacer 702 may be any suitable dielectric material that exhibits high etch selectivity with respect to semiconductor materials such as silicon and / or silicon germanium. The inner spacer 702 may be conformally deposited on the side of the fin structure using a conformal deposition process such as, for example, CVD or ALD, and then etched back using an isotropic etching process to expose the end of the semiconductor layer 204. According to some embodiments, the inner spacer 702 has a similar width (e.g., along a first direction) as the spacer structure 404. It should be noted that according to some embodiments, the inner spacer 702 may be formed only around the end of the semiconductor layer 204, and not along other edges of the gate trench away from the semiconductor layer 204 (as shown in FIG. 7B).

[0055] 8A and 8B show cross-sectional views of the structures shown in FIGS. 7A and 7B, respectively, after formation of source or drain regions 802 in source / drain trenches, according to some embodiments. The source or drain regions 802 may be formed in areas previously occupied by the exposed fins between the spacer structures 404. According to some embodiments, the source or drain regions 802 are epitaxially grown from exposed semiconductor material at the edge of the semiconductor layer 204. In some exemplary embodiments, the source or drain regions 802 are n-channel source or drain regions (e.g., epitaxial silicon with n-type dopants) or p-channel source or drain regions (e.g., epitaxial SiGe with p-type dopants). A contact 804 may be formed on a top surface of the source or drain regions 802. The contact 804 may include any suitable conductive material, such as tungsten, cobalt, molybdenum, or ruthenium, to make electrical contact with the underlying source or drain regions 802. In some embodiments, the area above the source or drain region 802 is filled with a dielectric that is replaced with a contact 804 after replacement of the sacrificial gate 402 with a gate structure.

[0056] According to some embodiments, a dielectric fill 806 is provided between adjacent source or drain regions 802 along a given source / drain trench running in the second direction. In some examples, the dielectric fill 806 occupies the remaining volume in the source drain trench around, and possibly above, portions of the source or drain regions 802. The dielectric fill 806 may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric fill 806 extends to and is coplanar with the top surface of the spacer structure 404 (e.g., after a polishing procedure).

[0057] 9A and 9B show cross-sectional views of the structures shown in FIGS. 8A and 8B, respectively, after removal of the sacrificial gate 402 and the sacrificial layer 202, according to some embodiments. In instances where the gate masking layer is still present, the gate masking layer may be removed at this point. Once the sacrificial gate 402 is removed, the fins extending between the spacer structures 404 are exposed.

[0058] In examples where the fin includes alternating semiconductor layers 202 and 204, the sacrificial layer 202 is selectively removed to leave behind nanoribbons 902 that extend between corresponding source or drain regions 802. Each vertical set of nanoribbons 902 represents a semiconductor region (also called a channel region) of a different semiconductor device. It should be understood that the nanoribbons 902 may be nanowires or nanosheets. The sacrificial gate 402 and the sacrificial layer 202 may be removed using the same isotropic etching process or different isotropic etching processes.

[0059] 10A and 10B show cross-sectional views of the structures shown in FIGS. 9A and 9B, respectively, after formation of a gate dielectric 1002, according to some embodiments. The gate dielectric 1002 can be formed around the nanoribbons 902 and along any exposed surfaces within the gate trench, such as along the sidewalls of the spacer structures 404. The gate dielectric 1002 can include any suitable dielectric material, such as silicon dioxide and / or high-k dielectric materials. To provide some examples, examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. According to some embodiments, the gate dielectric 1002 includes a layer of hafnium oxide having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 1002 can include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and other transition metal silicates). In some cases, the gate dielectric 1002 includes a first layer on the nanoribbons 902 and a second layer on the first layer. The first layer can be, for example, an oxide of the semiconductor material of the nanoribbons 902 (e.g., silicon dioxide), and the second layer can be a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). Any excess gate dielectric can be removed from the top surface of the structure, for example, via a polishing process (e.g., chemical mechanical planarization, CMP).

[0060] 11A and 11B show cross-sectional views of the structures shown in FIGS. 10A and 10B, respectively, after formation of a material layer 1102 over all surfaces of the gate dielectric 1002 in the gate trench, according to some embodiments. According to some embodiments, the material layer 1102 includes molybdenum, such as molybdenum nitride (MoN). The material layer 1102 is formed by oxidizing molybdenum and ammonia (NH 3) precursor. In some examples, material layer 1102 has a thickness between about 1 nm and 2 nm (e.g., between 12 Angstroms (1.2 nanometers) and about 16 Angstroms (1.6 nanometers)). According to some embodiments, the deposition conditions used to form material layer 1102 do not damage the underlying gate dielectric 1002.

[0061] 12A and 12B show cross-sectional views of the structures shown in FIGS. 11A and 11B, respectively, after formation of a protective layer 1202 over the material layer 1102, according to some embodiments. The protective layer 1202 may include, for example, amorphous silicon or amorphous silicon germanium, and may be provided to protect the gate dielectric 1002 during an annealing process. After the formation of the protective layer 1202, an annealing procedure is performed to improve the quality of the gate dielectric 1002. The temperature and duration of the annealing may vary from one example to the next, but in some cases is within the range of about 550° C. to about 650° C. for about 30 seconds to about 90 seconds.

[0062] 13A and 13B show cross-sectional views of the structures shown in FIGS. 12A and 12B, respectively, after formation of one or more additional conductive layers to form a work function layer 1302 over the gate dielectric 1002, according to some embodiments. After the annealing process, the protective layer 1202 may be removed, and one or more additional conductive layers (e.g., one or more metal layers) may be formed over the material layer 1102 to provide a stack of work function layers 1302. In some embodiments, the work function layers 1302 fill the areas between adjacent nanoribbons 902. The work function layers 1302 may be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD, to name a few.

[0063] The type and thickness of the different work function layers 1302 depend on the type of transistor (n or p type) and the desired threshold voltage of the transistor. For example, an n-channel transistor may have a work function layer 1302 including a material layer 1102 directly on the gate dielectric 1002 and a first work function layer 1304 on the material layer 1102, as shown in the upper enlarged portion of FIG. 13B. The first work function layer 1304 may include, for example, tantalum nitride. In another example, a p-channel transistor may have a work function layer 1302 including a material layer 1102 directly on the gate dielectric 1002, a first work function layer 1304 on the material layer 1102, and a second work function layer 1306 on the first work function layer 1304, as shown in the lower enlarged portion of FIG. 13B. The second work function layer 1306 may include, for example, titanium nitride. Other work function materials may also be used for each of the first work function layer 1304 and the second work function layer 1306. In some examples, an additional work function metal layer including aluminum doped titanium carbide (TiAlC) is provided within the work function layer 1302. According to some embodiments, the thickness of the second work function layer 1306 can be used to adjust the threshold voltage of a p-channel transistor. For example, the threshold voltage of a p-channel transistor generally decreases as the thickness of the second work function layer 1306 increases.

[0064] 14A and 14B show cross-sectional views of the structures shown in FIGS. 13A and 13B, respectively, after the formation of a conductive fill 1402 in the remaining volume of the gate trench, according to some embodiments. The conductive fill 1402 may include any suitable conductive metal material, such as tungsten, cobalt, or ruthenium. According to some embodiments, the conductive fill 1402 also includes one or more conductive adhesion layers to promote better adhesion to the underlying work function layer 1302. An exemplary adhesion layer includes titanium nitride. According to some embodiments, the conductive fill 1402 and the work function layer 1302 together constitute a gate electrode provided on the gate dielectric 1002. Another example may not include any conductive fill 1402, where the work function layer 1302 consumes the entire space remaining after deposition of either the first work function layer 1304 or the second work function layer 1306.

[0065] 15A and 15B show cross-sectional views of the structures shown in FIGS. 14A and 14B, respectively, after formation of a gate cap 1502, according to some embodiments. A top portion of the gate electrode may be recessed using any suitable metal etching process, and the recessed area is filled with a dielectric material to form the gate cap 1502. Thus, the gate cap 1502 may be any suitable dielectric material, such as silicon nitride. In some examples, the gate cap 1502 comprises the same dielectric material as the spacer structure 404. Other examples may not include the gate cap 1502.

[0066] FIG. 16 shows another exemplary integrated circuit having a finFET architecture as opposed to a GAA architecture. Thus, the semiconductor region extending between the source and drain regions is in the form of a fin 1602 extending above the substrate 201. The cross section of FIG. 16 crosses the gate trench (along the second direction) through the different fins 1602. The same procedure described above for the GAA architecture can be used in the finFET architecture to form a gate structure having a gate dielectric 1002, a work function layer 1302 and a conductive fill 1402 on the fin 1602. The work function layer 1302 can include different metal layers as described above depending on whether the fin 1602 is part of an n-channel or p-channel device. In either case, however, the work function layer 1302 includes a layer including molybdenum.

[0067] 17 illustrates an exemplary embodiment of a chip package 1700 according to one embodiment of the present disclosure. As can be seen, the chip package 1700 includes one or more dies 1702. The one or more dies 1702 may include at least one integrated circuit having a semiconductor device, such as any of the semiconductor devices disclosed herein. In some exemplary configurations, the one or more dies 1702 may include any other circuitry used to interface with other devices formed on the die or connected to the chip package 1700.

[0068] As can be further seen, the chip package 1700 includes a housing 1704 bonded to a package substrate 1706. The housing 1704 may be any standard or proprietary housing and may provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 1700. The one or more dies 1702 may be conductively coupled to the package substrate 1706 using connections 1708 that may be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonds, to name a few. The package substrate 1706 may be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and traces) extending through the dielectric material between faces of the package substrate 1706 or between different locations on each face. In some embodiments, the package substrate 1706 may have a thickness of less than 1 millimeter (e.g., between 0.1 and 0.5 millimeters), although any number of package geometries may be used. Additional conductive contacts 1712 may be disposed on an opposing surface of the package substrate 1706, for example to conductively contact a printed circuit board (PCB). One or more vias 1710 extend through the thickness of the package substrate 1706 to provide a conductive path between one or more of the connections 1708 to one or more of the contacts 1712. The vias 1710 are shown as a single linear row through the package substrate 1706 for ease of illustration, although other configurations (e.g., damascene, dual damascene, through silicon vias, or interconnect structures that meander through the thickness of the substrate 1706 to contact one or more intermediate locations therein) may be used. In still other embodiments, the vias 1710 are fabricated by a number of smaller stacked vias, or are staggered at different locations across the package substrate 1706.In the embodiment shown, the contacts 1712 are solder balls (e.g., bump-based connections or a ball grid array arrangement), although any suitable package attachment mechanism may be used (e.g., pins in a pin grid array arrangement, or lands in a land grid array arrangement). In some embodiments, solder resist is placed between the contacts 1712 to prevent shorting.

[0069] In some embodiments, a molding material 1714 may be disposed around one or more dies 1702 contained within the housing 1704 (e.g., between the die 1702 and the package substrate 1706 as an underfill material, and between the die 1702 and the housing 1704 as an overfill material). While the dimensions and qualities of the molding material 1714 may vary from one embodiment to the next, in some embodiments, the molding material 1714 is less than one millimeter thick. Exemplary materials that may be used for the molding material 1714 include epoxy molding materials, as appropriate. In some cases, the molding material 1714 is thermally conductive in addition to being electrically insulating. [method]

[0070] FIG. 18 is a flow chart of a method 1800 of forming at least a portion of an integrated circuit, according to one embodiment. Various steps of the method 1800 may be illustrated in FIGS. 2A-15A and 2B-15B. However, the correlation of various steps of the method 1800 with specific components illustrated in the aforementioned figures is not intended to suggest any structural and / or use limitations. Rather, the aforementioned figures provide one exemplary embodiment of the method 1800. Other steps may be performed before, during, or after any of the steps of the method 1800. For example, the method 1800 does not explicitly describe various standard processes that are typically performed to form a transistor structure. Some of the steps of the method 1800 may be performed in a different order than shown.

[0071] According to some embodiments, the method 1800 begins at step 1802 where a plurality of parallel semiconductor fins are formed. The semiconductor material in the fins may be formed from the substrate (e.g., etched from a bulk silicon substrate) such that the fins become an integral part of the substrate. Alternatively, the fins may be formed of material deposited onto an underlying substrate. In one such exemplary case, a blanket layer of SiGe may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-native fins may be formed in a so-called aspect ratio trapping based process where the intrinsic fins are etched away to leave fin-shaped trenches that may then be filled with an alternative semiconductor material (e.g., group IV or III-V material). In yet other embodiments, the fins include alternating layers of materials (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during gate formation processing, where one type of alternating layer is selectively etched away to free the other type of alternating layer in the channel region, so that a gate-all-around (GAA) process can then be performed. Again, according to some examples, these alternating layers can be blanket deposited and then etched into the fins, or deposited into fin-shaped trenches. The fins can also include a cap structure on top of each fin, used to define the location of the fin during, for example, a RIE process. The cap structure can be a dielectric material, such as silicon nitride.

[0072] According to some embodiments, a dielectric fill is formed around a sub-fin portion of one or more fins. In some embodiments, the dielectric fill extends between each pair of adjacent parallel fins and runs vertically in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate, and the dielectric fill may be formed within the recessed portion of the substrate. Thus, the dielectric fill acts as a shallow trench isolation (STI) between adjacent fins. The dielectric fill may be any suitable dielectric material, such as silicon dioxide. The lower portion of the fin adjacent the dielectric fill may be identified as the sub-fin.

[0073] The method 1800 continues at step 1804 where a dynamic sacrificial gate is formed over the fin. The sacrificial gate may be patterned with a gate masking layer in strips running orthogonally and parallel to one another over the fin (e.g., a cross-hatch pattern is formed). The gate masking layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate itself may be formed from any suitable material that may be selectively removed at a later time without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon.

[0074] According to some embodiments, spacer structures are also formed on at least the sidewalls of the sacrificial gate. The spacer structures may be deposited and then etched back such that the spacer structures remain mostly only on the sidewalls of any exposed structures. In some cases, the spacer structures may also be formed along the sidewalls of exposed fins that run orthogonally between the strips of the sacrificial gate. According to some embodiments, the spacer structures may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0075] The method 1800 continues at step 1806 where exposed portions of the fin are removed to form source / drain trenches. None of the exposed portions of the fin are covered by a sacrificial gate or spacer structure may be removed using any anisotropic etching process, such as reactive ion etching (RIE). As described above, the sacrificial layer of the fin may be recessed (e.g., via an isotropic etching process) after which an inner spacer (e.g., silicon nitride) is deposited.

[0076] The method 1800 continues with step 1808 where source or drain regions are formed at opposing ends of the fins in the source / drain trenches. The source or drain regions may be formed in areas previously occupied by the exposed fins between the spacer structures. According to some embodiments, the source or drain regions are epitaxially grown from the exposed semiconductor material of the fins (or nanoribbons, nanowires or nanosheets, as the case may be) along the outer walls of the spacer structures. In some exemplary embodiments, the source or drain regions are NMOS source or drain regions (e.g., epitaxial silicon with n-type dopants) or PMOS source or drain regions (e.g., epitaxial SiGe with p-type dopants). A dielectric fill may be formed between and over the source or drain regions along a given source / drain trench. The dielectric fill may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric fill extends over the source or drain regions to and flush with the top surface of the spacer structures. The dielectric fill also acts as an electrical insulator between adjacent source or drain regions, although some adjacent source or drain regions may merge together during their growth.

[0077] The method 1800 continues at step 1810 where the sacrificial gate is removed. According to some embodiments, the sacrificial gate may be removed along with any sacrificial layers in the exposed fins between the spacer structures (in the case of a GAA structure). The sacrificial gate and / or sacrificial layers may be removed using any suitable isotropic etching process.

[0078] The method 1800 continues at step 1812 where a gate dielectric is formed in the gate trench (e.g., the area previously occupied by the sacrificial gate). The gate dielectric may include any number of dielectric layers deposited using an oxidation process and / or a conformal deposition process such as ALD. The gate dielectric may include at least one layer of high-k dielectric material, such as a layer including hafnium oxide or aluminum oxide.

[0079] The method 1800 continues at step 1814 where a conductive layer comprising molybdenum is formed on the gate dielectric. According to some embodiments, the conductive layer comprises molybdenum nitride and is formed by ionizing molybdenum and ammonia (NH) at a temperature between about 380° C. and about 390° C. 3 ) precursor. In some examples, the conductive layer comprising molybdenum nitride has a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers). The precursors and temperatures used during the formation of the molybdenum nitride layer do not cause any appreciable damage to the gate dielectric. In some embodiments, a protective layer is deposited over the conductive layer comprising molybdenum. The protective layer may comprise amorphous silicon or any other similar amorphous semiconductor material.

[0080] The method 1800 continues at step 1816 where an anneal is performed on the molybdenum nitride layer on the gate dielectric. The anneal may be performed to strengthen the gate dielectric and improve its electrical properties. For example, the anneal may reduce charge traps in the gate dielectric. The temperature and duration of the anneal may vary from one example to the next, but in some cases is in the range of about 550° C. to 650° C. for about 30 seconds to 90 seconds. After the anneal, the protective layer, if present, may be removed.

[0081] The method 1800 continues with step 1818, where one or more additional conductive layers are formed on the molybdenum-containing layer to complete the formation of the gate electrode on the gate dielectric. According to some embodiments, the one or more additional conductive layers include a metal work function layer and a metal fill on the metal work function layer. The metal work function layer may vary depending on whether the transistor is to be an n-channel device or a p-channel device. The metal fill may be any suitable conductive material, such as tungsten. In some examples, the metal work function layer includes at least one layer of tantalum nitride and at least one layer of titanium nitride for p-channel devices, and at least one layer of tantalum nitride for n-channel devices. In some examples, the metal work function layer also includes a layer of TiAlC.

[0082] In some embodiments, step 1818 includes removal of the molybdenum-containing layer prior to forming one or more additional conductive layers. Some n-channel devices (e.g., those with relatively low threshold voltages) may not use a molybdenum-containing layer as one of their work function layers. According to some embodiments, n-channel devices without a molybdenum-containing layer may instead include a titanium nitride work function layer. N-channel devices with a removed molybdenum-containing layer still benefit from an improved gate dielectric due to the presence of the molybdenum-containing layer during the annealing process in step 1816. [Example System]

[0083] 19 is an exemplary computing system implemented with one or more of the integrated circuit structures disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 1900 houses a motherboard 1902. The motherboard 1902 may include multiple components, including, but not limited to, a processor 1904 and at least one communication chip 1906, each of which may be physically and electrically coupled to the motherboard 1902 or otherwise integrated within the motherboard 1902. As will be appreciated, the motherboard 1902 may be, for example, any printed circuit board (PCB), whether it is a main board, a daughter board mounted on a main board, the only board of the system 1900, etc.

[0084] Depending on its application, the computing system 1900 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1902. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs) and digital versatile discs (DVDs), etc.). Any of the components included in the computing system 1900 may include one or more integrated circuit structures or devices configured in accordance with an exemplary embodiment (e.g., a module including an integrated circuit device on a substrate having one or more semiconductor devices including a gate structure including at least one layer including molybdenum, as variously provided herein). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communications chip 1906 may be part of the processor 1904 or may otherwise be integrated into the processor 1904).

[0085] The communications chip 1906 enables wireless communication for the transfer of data to and from the computing system 1900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not include any wiring, although in some embodiments this may not be the case. The communications chip 1906 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing system 1900 may include multiple communications chips 1906. For example, a first communications chip 1906 may be dedicated to short-range wireless communications, such as Wi-Fi and Bluetooth, and a second communications chip 1906 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0086] The processor 1904 of the computing system 1900 includes an integrated circuit die packaged within the processor 1904. In some embodiments, the processor's integrated circuit die includes on-board circuitry implemented with one or more semiconductor devices variously described herein. The term "processor" may refer to any device or part of a device that processes electronic data from, for example, registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0087] The communications chip 1906 may also include an integrated circuit die packaged within the communications chip 1906. According to some such exemplary embodiments, the integrated circuit die of the communications chip includes one or more semiconductor devices variously described herein. As will be understood in light of the present disclosure, it should be noted that multi-standard wireless functionality may be integrated directly into the processor 1904 (e.g., rather than having separate communications chips, the functionality of any of the chips 1906 is integrated into the processor 1904). It should also be noted that the processor 1904 may be a chipset having such wireless functionality. In short, any number of processors 1904 and / or communications chips 1906 may be used. Similarly, any one chip or chipset may have multiple functions integrated therein.

[0088] In various implementations, the computing system 1900 may be a laptop, netbook, notebook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or uses one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.

[0089] It will be appreciated that in some embodiments, the various components of computing system 1900 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, these components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software. Further exemplary embodiments

[0090] The following examples relate to further embodiments, from which numerous variations and configurations will become apparent.

[0091] Example 1 is a method of forming an integrated circuit comprising: forming a fin including one or more semiconductor layers, the fin extending above a substrate in a first direction; forming a sacrificial gate, the sacrificial gate extending above the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming source or drain regions from edges of the one or more semiconductor layers and within the recess; removing the sacrificial gate from a periphery of the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, where the conductive layer comprises molybdenum and nitrogen; annealing the one or more dielectric layers after forming the conductive layer; and forming one or more additional conductive layers on the conductive layer.

[0092] Example 2 includes the method of example 1, in which forming the conductive layer includes forming the conductive layer using an atomic layer deposition (ALD) process.

[0093] Example 3 includes the method of example 2, wherein the conductive layer includes molybdenum and nitrogen, and the ALD process includes dissolving the molybdenum in ammonia (NH 3 ) precursor gas.

[0094] Example 4 includes the method of any one of Examples 1 to 3, wherein forming the conductive layer includes forming the conductive layer to a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers).

[0095] Example 5 includes the method of any one of examples 1 to 4, wherein forming the conductive layer comprises forming the conductive layer at a temperature less than 400°C.

[0096] Example 6 includes the method of any one of examples 1 to 5, wherein the one or more dielectric layers includes at least one layer including a high-k dielectric material.

[0097] Example 7 includes the method of example 6, wherein the high-k dielectric material includes hafnium and oxygen.

[0098] Example 8 includes the method of any one of Examples 1 to 7, wherein forming the one or more additional conductive layers includes forming at least one additional conductive layer including nitrogen and one of tantalum or titanium.

[0099] Example 9 includes the method of any one of Examples 1 to 8, wherein forming the sacrificial gate comprises forming spacers on sidewalls of the sacrificial gate, and removing the sacrificial gate comprises removing the sacrificial gate between the spacers to expose the one or more semiconductor layers between the spacers.

[0100] Example 10 includes the method of any one of Examples 1 to 9, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

[0101] Example 11 includes the method of example 10, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers.

[0102] Example 12 is an integrated circuit comprising a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers over the semiconductor region and one or more conductive layers over the one or more dielectric layers. The one or more conductive layers include a conductive layer including molybdenum and nitrogen. The source or drain region includes silicon, germanium, or silicon germanium (SiGe) doped with an n-type dopant.

[0103] Example 13 includes the integrated circuit of example 12, wherein the conductive layer is directly overlying the one or more dielectric layers.

[0104] Example 14 includes the integrated circuit of example 12 or 13, wherein the conductive layer further includes nitrogen and has a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers).

[0105] Example 15 includes the integrated circuit of any one of examples 12 to 14, wherein the one or more dielectric layers includes at least one layer including a high-k dielectric material.

[0106] Example 16 includes the integrated circuit of example 15, wherein the high-k dielectric material includes hafnium and oxygen.

[0107] Example 17 includes the integrated circuit of any one of examples 12 to 16, wherein the semiconductor region comprises one or more semiconductor nanoribbons.

[0108] Example 18 includes the integrated circuit of example 17, wherein the one or more semiconductor nanoribbons include germanium, silicon, or any combination thereof.

[0109] Example 19 includes the integrated circuit of any one of Examples 12 to 18, wherein the conductive layer is a first conductive layer and the one or more conductive layers include a second conductive layer on the first conductive layer comprising nitrogen and one of tantalum or titanium.

[0110] Example 20 is a printed circuit board comprising the integrated circuit of any one of Examples 12 to 19.

[0111] Example 21 is an electronic device having a chip package including one or more dies. At least one of the one or more dies includes a semiconductor device having a semiconductor region extending from a source or drain region in a first direction and a gate structure extending over the semiconductor region in a second direction different from the first direction. The gate structure includes one or more dielectric layers over the semiconductor region and one or more conductive layers over the one or more dielectric layers. The one or more conductive layers include a conductive layer including molybdenum and nitrogen. The source or drain region includes silicon, germanium, or SiGe doped with an n-type dopant.

[0112] Example 22 includes the electronic device of example 21, wherein the conductive layer is directly on the one or more dielectric layers.

[0113] Example 23 includes the electronic device of example 21 or 22, wherein the conductive layer has a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers).

[0114] Example 24 includes the electronic device of any one of Examples 21 to 23, wherein the one or more dielectric layers include at least one layer including a high-k dielectric material.

[0115] Example 25 includes the electronic device of example 24, wherein the high-k dielectric material includes hafnium and oxygen.

[0116] Example 26 includes the electronic device of any one of Examples 21 to 25, wherein the semiconductor region comprises one or more semiconductor nanoribbons.

[0117] Example 27 includes the electronic device of example 26, wherein the one or more semiconducting nanoribbons include germanium, silicon, or any combination thereof.

[0118] Example 28 includes the electronic device of any one of Examples 21 to 27, wherein the conductive layer is a first conductive layer and the one or more conductive layers include a second conductive layer on the first conductive layer comprising tantalum and nitrogen.

[0119] Example 29 includes the electronic device of any one of Examples 21 to 28, wherein the semiconductor device is a first semiconductor device, the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, the one or more dielectric layers are first one or more dielectric layers, and the one or more conductive layers are first one or more conductive layers. At least one of the one or more dies further includes a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor region in the second direction. The second gate structure includes one or more second dielectric layers on the second semiconductor region and one or more second conductive layers on the one or more second dielectric layers. The one or more second conductive layers include a conductive layer including molybdenum and nitrogen. The second source or drain region comprises silicon, germanium, or SiGe doped with a p-type dopant.

[0120] Example 30 includes the electronic device of any one of Examples 21 to 29, further comprising a printed circuit board (PCB), wherein the chip package is attached to the PCB.

[0121] Example 31 is a method of forming an integrated circuit comprising: forming a fin comprising one or more semiconductor layers, the fin extending above a substrate in a first direction; forming a sacrificial gate, the sacrificial gate extending above the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming source or drain regions comprising silicon doped with an n-type dopant from edges of the one or more semiconductor layers and in the recess; removing the sacrificial gate from a periphery of the fin; forming one or more dielectric layers on the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, where the conductive layer comprises molybdenum and nitrogen; and forming one or more additional conductive layers on the conductive layer.

[0122] Example 32 includes the method of example 31, further comprising annealing the one or more dielectric layers after forming the conductive layer.

[0123] Example 33 includes the method of example 31 or 32, wherein forming the conductive layer comprises forming the conductive layer at a temperature less than 400° C.

[0124] Example 34 includes the method of any one of Examples 31 to 33, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

[0125] Example 35 includes the method of example 34, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers.

[0126] Example 36 includes the method of any one of examples 1 to 11, wherein the annealing comprises annealing the one or more dielectric layers at about 550° C. to about 650° C. for about 30 seconds to about 90 seconds.

[0127] The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. [Other possible items] [Item 1] 1. A method of forming an integrated circuit, comprising: forming a fin including one or more semiconductor layers, said fin extending in a first direction; forming a sacrificial gate, the sacrificial gate extending over the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming a source or drain region from an edge of the one or more semiconductor layers and within the recess; removing the sacrificial gate from around the fin; forming one or more dielectric layers over the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer comprises molybdenum; annealing the one or more dielectric layers after forming the conductive layer; and forming one or more additional conductive layers over the conductive layer; A method comprising: [Item 2] 2. The method of claim 1, wherein forming the conductive layer comprises forming the conductive layer using an atomic layer deposition (ALD) process. [Item 3] The conductive layer includes molybdenum and nitrogen, and the ALD process comprises dissolving the molybdenum in ammonia (NH 3 ) The method according to item 2, wherein the precursor gas is used together with the [Item 4] 2. The method of claim 1, wherein forming the conductive layer comprises forming the conductive layer to a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers). [Item 5] 2. The method of claim 1, wherein forming the conductive layer comprises forming the conductive layer at a temperature less than 400° C. [Item 6] Item 13. The method of item 1, wherein the one or more dielectric layers include at least one layer comprising a high-k dielectric material. [Item 7] 2. The method of claim 1, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers. [Item 8] 8. The method of claim 7, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers. [Item 9] Item 1. The method of item 1, wherein the annealing step comprises annealing the one or more dielectric layers at about 550° C. to about 650° C. for about 30 seconds to about 90 seconds. [Item 10] a semiconductor region extending in a first direction from a source or drain region, where the source or drain region comprises silicon doped with an n-type dopant; and a gate structure extending over the semiconductor region in a second direction different from the first direction; Equipped with Here, the gate structure is one or more dielectric layers over the semiconductor region; and one or more conductive layers on said one or more dielectric layers, wherein said one or more conductive layers comprises a conductive layer comprising molybdenum and nitrogen. having Integrated circuits. [Item 11] Item 11. The integrated circuit of item 10, wherein the conductive layer is directly on the one or more dielectric layers. [Item 12] Item 11. The integrated circuit of item 10, wherein the conductive layer has a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers). [Item 13] Item 11. The integrated circuit of item 10, wherein the one or more dielectric layers include at least one layer comprising a high-k dielectric material. [Item 14] Item 11. The integrated circuit of item 10, wherein the conductive layer is a first conductive layer and the one or more conductive layers include a second conductive layer on the first conductive layer comprising nitrogen and one of tantalum or titanium. [Item 15] the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, the one or more dielectric layers are first one or more dielectric layers, the one or more conductive layers are first one or more conductive layers, and at least one of the one or more dies is a second semiconductor region extending in the first direction from a second source or drain region, where the second source or drain region comprises silicon doped with a p-type dopant; and a second gate structure extending over the second semiconductor region in the second direction; Further comprising: Here, the second gate structure is one or more second dielectric layers over the second semiconductor region; and one or more second conductive layers on the one or more second dielectric layers, where the one or more second conductive layers comprise a conductive layer comprising molybdenum and nitrogen. Including, Item 11. The integrated circuit according to item 10. [Item 16] 1. A method of forming an integrated circuit, comprising: forming a fin including one or more semiconductor layers, said fin extending in a first direction; forming a sacrificial gate, the sacrificial gate extending over the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming a source or drain region comprising silicon doped with an n-type dopant from an edge of the one or more semiconductor layers and within the recess; removing the sacrificial gate from around the fin; forming one or more dielectric layers over the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer comprises molybdenum; and forming one or more additional conductive layers over the conductive layer; A method comprising: [Item 17] Item 17. The method of item 16, further comprising annealing the one or more dielectric layers after forming the conductive layer. [Item 18] Item 17. The method of item 16, wherein forming the conductive layer comprises forming the conductive layer at a temperature less than 400°C. [Item 19] Item 17. The method of item 16, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers. [Item 20] 20. The method of claim 19, further comprising forming another conductive layer comprising titanium and nitrogen on the one or more dielectric layers.

Claims

1. 1. A method of forming an integrated circuit, comprising: forming a fin including one or more semiconductor layers, said fin extending in a first direction; forming a sacrificial gate, the sacrificial gate extending over the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming a source or drain region from an edge of the one or more semiconductor layers and within the recess; removing the sacrificial gate from around the fin; forming one or more dielectric layers over the one or more semiconductor layers of the fin; forming a conductive layer on said one or more dielectric layers, said conductive layer comprising molybdenum; annealing the one or more dielectric layers after forming the conductive layer; and forming one or more additional conductive layers over the conductive layer; A method comprising:

2. The method of claim 1 , wherein forming the conductive layer comprises forming the conductive layer using an atomic layer deposition (ALD) process.

3. The conductive layer includes molybdenum and nitrogen, and the ALD process comprises dissolving molybdenum in ammonia (NH ３ 3. The method of claim 2, wherein the precursor gas is a fluorine-containing gas.

4. 10. The method of claim 1, wherein forming the conductive layer comprises forming the conductive layer to a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers).

5. The method of claim 1 , wherein forming the conductive layer comprises forming the conductive layer at a temperature less than 400° C.

6. The method of claim 1 , wherein the one or more dielectric layers includes at least one layer comprising a high-k dielectric material.

7. The method of claim 6 , wherein the high-k dielectric material comprises hafnium and oxygen.

8. The method of claim 1 , wherein forming the one or more additional conductive layers comprises forming at least one additional conductive layer comprising nitrogen and one of tantalum or titanium.

9. 2. The method of claim 1 , wherein forming the sacrificial gate comprises forming spacers on sidewalls of the sacrificial gate, and removing the sacrificial gate comprises removing the sacrificial gate between the spacers to expose the one or more semiconductor layers between the spacers.

10. The method of claim 1 , further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

11. The method of claim 10 , further comprising forming another conductive layer comprising titanium and nitrogen over the one or more dielectric layers.

12. 12. The method of claim 1, wherein the annealing comprises annealing the one or more dielectric layers at about 550°C to about 650°C for about 30 seconds to about 90 seconds.

13. a semiconductor region extending in a first direction from a source or drain region, where the source or drain region comprises one or both of silicon and germanium and is doped with an n-type dopant; and a gate structure extending over the semiconductor region in a second direction different from the first direction; Equipped with Here, the gate structure is one or more dielectric layers over the semiconductor region; and one or more conductive layers on said one or more dielectric layers, wherein said one or more conductive layers include a conductive layer comprising molybdenum and nitrogen. having Integrated circuits.

14. The integrated circuit of claim 13 , wherein the conductive layer is directly above the one or more dielectric layers.

15. 14. The integrated circuit of claim 13, wherein the conductive layer has a thickness between about 12 angstroms (1.2 nanometers) and about 16 angstroms (1.6 nanometers).

16. 14. The integrated circuit of claim 13, wherein the one or more dielectric layers include at least one layer comprising a high-k dielectric material.

17. 17. The integrated circuit of claim 16, wherein the high-k dielectric material comprises hafnium and oxygen.

18. The integrated circuit of claim 13 , wherein the semiconductor region comprises one or more semiconductor nanoribbons.

19. 14. The integrated circuit of claim 13, wherein the conductive layer is a first conductive layer and the one or more conductive layers include a second conductive layer on the first conductive layer comprising nitrogen and one of tantalum or titanium.

20. the semiconductor region is a first semiconductor region, the source or drain region is a first source or drain region, the gate structure is a first gate structure, the one or more dielectric layers are first one or more dielectric layers, the one or more conductive layers are first one or more conductive layers, and at least one of the one or more dies is a second semiconductor region extending in the first direction from a second source or drain region, where the second source or drain region comprises silicon doped with a p-type dopant; and a second gate structure extending over the second semiconductor region in the second direction; Further comprising: Here, the second gate structure is one or more second dielectric layers over the second semiconductor region; and one or more second conductive layers on the one or more second dielectric layers, where the one or more second conductive layers comprise a conductive layer comprising molybdenum and nitrogen. Including, 20. An integrated circuit according to any one of claims 13 to 19.

21. 1. A method of forming an integrated circuit, comprising: forming a fin including one or more semiconductor layers, said fin extending in a first direction; forming a sacrificial gate, the sacrificial gate extending over the fin in a second direction, the second direction being different from the first direction; removing an exposed portion of the fin adjacent the sacrificial gate to form a recess through the fin; forming a source or drain region comprising silicon doped with an n-type dopant from an edge of the one or more semiconductor layers and within the recess; removing the sacrificial gate from around the fin; forming one or more dielectric layers over the one or more semiconductor layers of the fin; forming a conductive layer on the one or more dielectric layers, wherein the conductive layer comprises molybdenum; and forming one or more additional conductive layers over the conductive layer; A method comprising:

22. 22. The method of claim 21, further comprising annealing the one or more dielectric layers after forming the conductive layer.

23. 22. The method of claim 21, wherein forming the conductive layer comprises forming the conductive layer at a temperature less than 400 degrees Celsius.

24. 24. The method of any one of claims 21 to 23, further comprising removing the conductive layer and the one or more additional conductive layers to expose the one or more dielectric layers.

25. 25. The method of claim 24, further comprising forming another conductive layer comprising titanium and nitrogen over the one or more dielectric layers.

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