Semiconductor integrated circuit device and power source apparatus

Abstract

To increase the area efficiency in a semiconductor integrated circuit device.SOLUTION: A semiconductor integrated circuit device (101) includes an error amplifier (11) configured to output an error voltage corresponding to the difference between a feedback voltage based on the output voltage of a power source apparatus and a reference voltage, a first switching element (M1) and a second switching element (M2) connected in series, a first control unit (13, 14, 15, CD) configured to perform switching control of the first switching element and the second switching element on the basis of the error voltage, an output transistor (Q7), a second control unit (Q1 to Q6, 22) configured to perform linear control of the output transistor on the basis of the error voltage, and a first terminal (SW) configured to connect a connection node between the first switching element and the second switching element and an output end of the output transistor.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor integrated circuit device and a power supply device. [Background technology]

[0002] The semiconductor integrated circuit device disclosed in Patent Document 1 includes a first error amplifier that outputs a first error voltage corresponding to an error between a feedback voltage and a reference voltage, a second error amplifier that outputs a second error voltage corresponding to an error between the feedback voltage and the reference voltage, a first switching element and a second switching element connected in series, a first control unit that controls the switching of the first switching element and the second switching element based on the first error voltage, an output transistor, and a second control unit that linearly controls the output transistor based on the second error voltage.

[0003] The semiconductor integrated circuit device disclosed in Patent Document 1 can be switched between use as part of a switching power supply device and use as part of a linear power supply device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-130622 A

[0005] [overview] However, the semiconductor integrated circuit device disclosed in Patent Document 1 has poor area efficiency because the circuits related to the switching power supply device and the circuits related to the linear power supply device are configured completely separately.

[0006] The semiconductor integrated circuit device disclosed in this specification is a semiconductor integrated circuit device configured to be part of a power supply device, and includes an error amplifier configured to output an error voltage corresponding to an error between a reference voltage and a feedback voltage based on an output voltage of the power supply device, a first switching element and a second switching element connected in series, a first control unit configured to control the switching of the first switching element and the second switching element based on the error voltage, an output transistor, a second control unit configured to linearly control the output transistor based on the error voltage, and a first terminal configured to connect a connection node of the first switching element and the second switching element to an output end of the output transistor.

[0007] The power supply device disclosed in this specification includes a substrate and a semiconductor integrated circuit device having the above-described configuration mounted on the substrate. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to a reference example. [Diagram 2] FIG. 2 is a diagram showing a schematic configuration of a switching power supply device according to a reference example. [Diagram 3] FIG. 3 is a diagram showing a schematic configuration of a linear power supply device according to a reference example. [Figure 4] FIG. 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to the first embodiment. [Diagram 5] FIG. 5 is an external perspective view of the semiconductor integrated circuit device according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing a schematic configuration of the switching power supply device according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing a schematic configuration of the linear power supply device according to the first embodiment. [Figure 8] FIG. 8 is a diagram illustrating an example of a configuration of a phase compensation circuit. [Figure 9]FIG. 9 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to the second embodiment. [Figure 10] FIG. 10 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to the third embodiment.

[0009] [Detailed Description] In this specification, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0010] In this specification, the reference voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0011] <Semiconductor integrated circuit device according to reference example> 1 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to a reference example. The semiconductor integrated circuit device 100 shown in FIG. 1 includes a terminal IN, a terminal SW, a terminal OUT, and a terminal GND. The terminal IN is connected to an input voltage V IN The terminal GND is a terminal configured to be connected to a ground potential outside the semiconductor integrated circuit device 100.

[0012] The semiconductor integrated circuit device 100 further includes an output stage circuit MM, an error amplifier 11, a phase compensation circuit 12, a slope voltage generating circuit 13, a comparator 14, a clock signal generating circuit 15, a logic circuit 16, a drive circuit 17, and resistors R1 and R2.

[0013] The output stage circuit MM includes a transistor M1 configured as a P-channel MOSFET and a transistor M2 configured as an N-channel MOSFET. The transistors M1 and M2 are a pair of switching elements connected in series between the terminal IN and the terminal GND. The transistors M1 and M2 are switched to generate an input voltage V IN is switched, and a square-wave switch voltage V SW appears. The transistor M1 is provided on the higher potential side than the transistor M2. In other words, the transistor M2 is provided on the lower potential side than the transistor M1. Specifically, the source of the transistor M1 is connected to the terminal IN. The drains of the transistors M1 and M2 are commonly connected to the terminal SW. The source of the transistor M2 is connected to the terminal GND.

[0014] Gate signals G1 and G2 are supplied to the gates of the transistors M1 and M2 as drive signals, respectively, and the transistors M1 and M2 are turned on and off according to the gate signals G1 and G2. When the gate signal G1 is at a low level, the transistor M1 is in an on state, and when the gate signal G1 is at a high level, the transistor M1 is in an off state. When the gate signal G2 is at a high level, the transistor M2 is in an on state, and when the gate signal G2 is at a low level, the transistor M2 is in an off state. Basically, the transistors M1 and M2 are alternately turned on and off, but there are also cases where both the transistors M1 and M2 are maintained in an off state. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a Hi-Z state (high impedance state).

[0015] The error amplifier 11 is a current output type transconductance amplifier. The error amplifier 11 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 11 receives a feedback voltage V FB The feedback voltage V FB is the output voltage V received by the terminal OUT OUT This is the voltage obtained by dividing the voltage by resistors R1 and R2.

[0016] The non-inverting input terminal of the error amplifier 11 is connected to a predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the semiconductor integrated circuit device 100. The output terminal of the error amplifier 11 is connected to a wiring WR11.

[0017] The error amplifier 11 outputs the feedback voltage V FB and the reference voltage V REF The feedback voltage V FB and the reference voltage V REF Error voltage V according to the difference between ERR The charge generated by the current signal I11 is input to and output from the wire WR11. Specifically, the error amplifier 11 generates a feedback voltage V FB is the reference voltage V REF When the voltage of the feedback voltage V FB is the reference voltage V REF When the feedback voltage V is higher than 1 V, a current is drawn from the wire WR11 to the error amplifier 11 by the current signal I11 so that the potential of the wire WR11 decreases. FB and the reference voltage V REF As the absolute value of the difference between increases, the magnitude of the current due to current signal I11 also increases.

[0018] The phase compensation circuit 12 is provided between the wiring WR11 and the inverting input terminal of the error amplifier 11, and receives the current signal I11 to generate an error voltage V ERR The phase compensation circuit 12 has a series circuit of a capacitor 12a and a resistor 12b. Specifically, one end of the capacitor 12a is connected to the inverting input terminal of the error amplifier 11, the other end of the capacitor 12a is connected to one end of the resistor 12b, and the other end of the resistor 12b is connected to the wiring WR11. By appropriately setting the capacitance value of the capacitor 12a and the resistance value of the resistor 12b, the error voltage V ERRIt is possible to prevent oscillation of the output feedback loop by compensating for the phase.

[0019] The slope voltage generation circuit 13 generates and outputs a slope voltage V SLP . The slope voltage V SLP is a sawtooth-shaped voltage synchronized with the clock signal S1.

[0020] The comparator 14 includes an inverting input terminal that receives the voltage V1, a non-inverting input terminal that receives the voltage V2, and an output terminal. The voltage V1 is the first comparison voltage, and the voltage V2 is the second comparison voltage. The comparator 14 compares the voltages V1 and V2 and outputs a signal S2 (hereinafter referred to as the comparison result signal S2) indicating the comparison result from its output terminal. The comparison result signal S2 is a binary signal having a signal level of high level or low level. The comparator 14 outputs a high-level comparison result signal S2 when "V2 > V1" holds (i.e., when the voltage V2 is higher than the voltage V1), and outputs a low-level comparison result signal S2 when "V2 < V1" holds (i.e., when the voltage V1 is higher than the voltage V2). When "V2 = V1" holds, the comparison result signal S2 becomes high level or low level.

[0021] In the semiconductor integrated circuit device 100, the error voltage V ERR functions as the voltage V1. That is, the inverting input terminal of the comparator 14 is connected to the wiring WR11 to receive the error voltage V ERR as the voltage V1. In the semiconductor integrated circuit device 100, the slope voltage V SLP functions as the voltage V2. That is, the non-inverting input terminal of the comparator 14 receives the slope voltage V SLP as the voltage V2.

[0022] The clock signal generation circuit 15 generates and outputs a clock signal S1 having a predetermined frequency f PWM .

[0023] The logic circuit 16 generates and outputs a control signal S3 based on the clock signal S1 and the comparison result signal S2. The control signal S3 is a binary signal that takes a high or low signal level.

[0024] The drive circuit 17 supplies gate signals G1 and G2 to the gates of the transistors M1 and M2, respectively, in response to a control signal S3, thereby turning on or off the transistors M1 and M2 individually.

[0025] The logic circuit 16 and the drive circuit 17 constitute a drive control circuit CD that controls the output stage circuit MM based on the clock signal S1 and the comparison result signal S2.

[0026] The slope voltage generating circuit 13, the comparator 14, the clock signal generating circuit 15, and the drive control circuit CD generate an error voltage V ERR A first control unit is configured to control the switching of the transistors M1 and M2 based on the above.

[0027] The semiconductor integrated circuit device 100 includes an output transistor Q7 provided between a terminal IN and a terminal OUT, and a feedback voltage V FB and the reference voltage V REF and a driver that drives an output transistor Q7 based on the difference between

[0028] The output transistor Q7 is a P-channel MOSFET. The source of the output transistor Q7 is connected to the terminal IN. The drain of the output transistor Q7 is connected to the terminal OUT.

[0029] The driver comprises an error amplifier 21, a converter, a current amplifier and a transistor Q6 configured as a P-channel MOSFET.

[0030] The error amplifier 21 outputs the feedback voltage V FB and the reference voltage V REF It outputs an error voltage according to the difference between the feedback voltage V FBis supplied to the inverting input terminal of the error amplifier 21, and the reference voltage V REF is supplied to a non-inverting input terminal of the error amplifier 21. The power supply terminal of the error amplifier 21 is connected to the terminal IN.

[0031] The converter has a transistor Q1 configured as a P-channel MOSFET, and converts a voltage based on the output of the error amplifier 21 into a current. The gate of the transistor Q1 is connected to the output terminal of the error amplifier 21. The source of the transistor Q1 is connected to the terminal IN.

[0032] The current amplifier amplifies the output of the transistor Q1 and includes a constant current source 2, transistors Q2 and Q3 configured as P-channel MOSFETs, and transistors Q4 and Q5 configured as N-channel MOSFETs.

[0033] A first terminal of the constant current source 2 is connected to the drain of the transistor Q1. A second terminal of the constant current source 2 is connected to the terminal GND.

[0034] The transistors Q2 and Q3 form a current source type current mirror circuit. The sources of the transistors Q2 and Q3 are connected to the terminal IN. The gates of the transistors Q2 and Q3 and the drain of the transistor Q2 are connected to a first end of the constant current source 2. The mirror ratio (the size of the output side transistor relative to the size of the input side transistor) of the current mirror circuit formed by the transistors Q2 and Q3 is M. In order to prevent the pole of the current mirror circuit formed by the transistors Q2 and Q3 from being shifted to the low band as much as possible, M is preferably 5 or less, and more preferably 3 or less.

[0035] The transistors Q4 and Q5 form a current-sink type current mirror circuit. The drain of the transistor Q4 and the gates of the transistors Q4 and Q5 are connected to the drain of the transistor Q3. The sources of the transistors Q4 and Q5 are connected to the terminal GND. The mirror ratio (the size of the output transistor relative to the size of the input transistor) of the current mirror circuit formed by the transistors Q4 and Q5 is N. In order to prevent the pole of the current mirror circuit formed by the transistors Q4 and Q5 from being shifted to the low band as much as possible, N is preferably 5 or less, and more preferably 3 or less.

[0036] The output current I5 of the above current amplifier (the drain current of transistor Q5) is expressed by the following equation using the drain current I1 of transistor Q1, the constant current Ic output from the constant current source, and mirror ratios M and N. I5 = M × N × (Ic-I1)

[0037] A transistor Q6 configured as a P-channel MOSFET is provided between the current amplifier and an output transistor Q7. The transistor Q6 is paired with the output transistor Q7 to configure a current source type current mirror circuit. The mirror ratio (the size of the output transistor relative to the size of the input transistor) of the current mirror circuit configured by the transistor Q6 and the output transistor Q7 is 1.

[0038] The gates of the transistor Q6 and the output transistor Q7 and the drain of the transistor Q6 are connected to the drain of the transistor Q5. The source of the transistor Q6 is connected to the terminal IN.

[0039] The converter, the current amplifier, and transistor Q6 constitute a second control section that is configured to linearly control the output transistor Q7 based on the error voltage output from the error amplifier 21.

[0040] Fig. 2 is a diagram showing a schematic configuration of a switching power supply device according to a reference example. The switching power supply device shown in Fig. 2 includes a substrate 201, a semiconductor integrated circuit device 100 mounted on the substrate 201, an inductor L1 mounted on the substrate 201, and an output capacitor C1 mounted on the substrate 201.

[0041] In the switching power supply device shown in FIG. 2, the first control section is in an enabled state, and the second control section is in a disabled state.

[0042] The substrate 201 has wiring patterns P1 to P4. The wiring patterns P1 to P4 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P1 is a wiring pattern for electrically connecting the terminal SW and the first end of the inductor L1. The wiring pattern P2 is a wiring pattern for electrically connecting the second end of the inductor L1 and the first end of the output capacitor C1. The wiring pattern P3 is a wiring pattern for electrically connecting the second end of the output capacitor C1 and the terminal GND. The wiring pattern P4 is a wiring pattern for electrically connecting the wiring pattern P2 and the terminal OUT.

[0043] The wiring patterns P1 and P2 are wide wiring patterns that allow a large current to flow, while the wiring pattern P4 is a narrow wiring pattern that only needs to transmit voltage information.

[0044] 3 is a diagram showing a schematic configuration of a linear power supply device according to a reference example. The linear power supply device shown in Fig. 3 includes a substrate 202, a semiconductor integrated circuit device 100 mounted on the substrate 202, and an output capacitor C1 mounted on the substrate 202.

[0045] In the linear power supply device shown in FIG. 3, the first control section is in a disabled state, and the second control section is in an enabled state.

[0046] The substrate 202 has wiring patterns P5 and P6. The wiring patterns P5 and P6 are made of a conductive material such as copper foil or aluminum foil. The wiring pattern P5 is a wiring pattern for electrically connecting the terminal OUT and a first end of the output capacitor C1. The wiring pattern P6 is a wiring pattern for electrically connecting the second end of the output capacitor C1 and the terminal GND.

[0047] The wiring pattern P5 is a wide wiring pattern that allows a large current to flow.

[0048] As described above, the wiring pattern of the substrate 201 used when the semiconductor integrated circuit device 100 is used as part of a switching power supply device is different from the wiring pattern of the substrate 201 used when the semiconductor integrated circuit device 100 is used as part of a linear power supply device. In other words, when the semiconductor integrated circuit device 100 is used as part of a power supply device, the substrate for the switching power supply device and the substrate for the linear power supply device cannot be made common. Therefore, when the semiconductor integrated circuit device 100 is used as part of a power supply device, it is time-consuming to prepare the substrate for the switching power supply device and the substrate for the linear power supply device.

[0049] First Embodiment Fig. 4 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 101 shown in Fig. 4 differs from the semiconductor integrated circuit device 100 shown in Fig. 1 in that it does not include an error amplifier 21, the output terminal of the error amplifier 11 is connected to the gate of the transistor Q1, and the drain of the output transistor Q7 is connected to the terminal SW, but in other respects it has a basically similar configuration to the semiconductor integrated circuit device 100 shown in Fig. 1.

[0050] Fig. 5 is an external perspective view of semiconductor integrated circuit device 101. Semiconductor integrated circuit device 101 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of semiconductor integrated circuit device 101. Semiconductor integrated circuit device 101 is formed by sealing the semiconductor chip in a case (package) made of resin. Note that the number of external terminals of semiconductor integrated circuit device 101 and the type of case for semiconductor integrated circuit device 101 shown in Fig. 5 are merely examples, and can be designed arbitrarily.

[0051] In FIG. 4, only terminal IN, terminal SW, terminal OUT, and terminal GND are shown as some of the multiple external terminals provided on semiconductor integrated circuit device 101, but other external terminals (e.g., enable terminals, communication terminals, etc.) are also provided on semiconductor integrated circuit device 101.

[0052] In the semiconductor integrated circuit device 101, both the first control section configured to perform switching control and the second control section configured to perform linear control control the error voltage V ERR Since the control is based on the error amplifier, the number of error amplifiers can be reduced. As a result, the area efficiency of the semiconductor integrated circuit device 101 can be improved compared to that of the semiconductor integrated circuit device 100.

[0053] Since the semiconductor integrated circuit device 101 is configured to include a terminal SW configured to connect the connection node of transistors M1 and M2 and the drain of the output transistor Q7, it is possible to use a common substrate for both the switching power supply device and the linear power supply device.

[0054] Fig. 6 is a diagram showing a schematic configuration of a switching power supply device according to the first embodiment. The switching power supply device shown in Fig. 6 includes a substrate 201, a semiconductor integrated circuit device 100 mounted on the substrate 201, an inductor L1 mounted on the substrate 201, and an output capacitor C1 mounted on the substrate 201.

[0055] In the switching power supply device shown in FIG. 6, the first control section is enabled, and the second control section is disabled.

[0056] The substrate 201 has wiring patterns P1 to P4. The wiring patterns P1 to P4 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P1 electrically connects the terminal SW and a first end of the inductor L1. The wiring pattern P2 electrically connects the second end of the inductor L1 and a first end of the output capacitor C1. The wiring pattern P3 electrically connects the second end of the output capacitor C1 and the terminal GND. The wiring pattern P4 electrically connects the wiring pattern P2 and the terminal OUT.

[0057] The wiring patterns P1 and P2 are wide wiring patterns that allow a large current to flow, while the wiring pattern P4 is a narrow wiring pattern that only needs to transmit voltage information.

[0058] Fig. 7 is a diagram showing a schematic configuration of a linear power supply device according to the first embodiment. The linear power supply device shown in Fig. 7 includes a substrate 201, a semiconductor integrated circuit device 100 mounted on the substrate 201, a conductor D1 mounted on the substrate 201, and an output capacitor C1 mounted on the substrate 201. The conductor D1 is a discrete component with a resistance value of approximately 0 Ω.

[0059] In the linear power supply device shown in FIG. 3, the first control section is in a disabled state, and the second control section is in an enabled state.

[0060] The substrate 201 has wiring patterns P1 to P4. The wiring patterns P1 to P4 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P1 electrically connects the terminal SW and a first end of the conductor D1. The wiring pattern P2 electrically connects the second end of the conductor D and a first end of the output capacitor C1. The wiring pattern P3 electrically connects the second end of the output capacitor C1 and the terminal GND. The wiring pattern P4 electrically connects the wiring pattern P2 and the terminal OUT.

[0061] The wiring patterns P1 and P2 are wide wiring patterns that allow a large current to flow, while the wiring pattern P4 is a narrow wiring pattern that only needs to transmit voltage information.

[0062] As described above, when semiconductor integrated circuit device 101 is used as part of a power supply device, a common substrate can be used for both the switching power supply device and the linear power supply device. Therefore, when semiconductor integrated circuit device 101 is used as part of a power supply device, it takes time and effort to prepare a substrate for the switching power supply device and a substrate for the linear power supply device.

[0063] Incidentally, at the stage of evaluating whether to use semiconductor integrated circuit device 101 as part of a switching power supply device or as part of a linear power supply device, as described above, it is desirable to be able to use a common substrate for both the switching power supply device and the linear power supply device.

[0064] However, after the above evaluation is completed and it is determined whether semiconductor integrated circuit device 101 will be used as part of a switching power supply device or a linear power supply device, a substrate dedicated to a switching power supply device or a substrate dedicated to a linear power supply device may be fabricated.

[0065] The substrate dedicated to the switching power supply may have a configuration in which, for example, a wiring pattern having an inductor component whose first end is electrically connected to the terminal SW via the wiring pattern P1 and whose second end is electrically connected to the wiring pattern P2 is added to the substrate 201. This makes the inductor L1, which is a discrete component, unnecessary.

[0066] The substrate dedicated to the linear power supply device may have a configuration in which, for example, a wiring pattern not having an inductor component is added to the substrate 201, the first end of which is electrically connected to the terminal SW via the wiring pattern P1, and the second end of which is electrically connected to the wiring pattern P2. This makes the conductor D1, which is a discrete component, unnecessary. Note that not having an inductor component also includes the case where the inductor component is so small that it can be considered to be zero.

[0067] 8 is a diagram showing an example of the configuration of the phase compensation circuit 12. The phase compensation circuit 12 of the example configuration shown in FIG. 8 includes a plurality of capacitors and a plurality of switches corresponding to the capacitor 12a shown in FIG. 4, and includes a plurality of resistors and a plurality of switches corresponding to the resistor 12b shown in FIG. 4. The semiconductor integrated circuit device 101 includes a register 18 and a switch control unit 19. The register 18 stores the settings of the phase compensation circuit 12, specifically, the on / off settings of each switch in the phase compensation circuit 12. The switch control unit 19 controls the on / off of each switch in the phase compensation circuit 12 based on the settings of the phase compensation circuit 12 stored in the register 18.

[0068] Since the number of error amplifiers is reduced, it is not necessary to provide the register 18 and the switch control section 19 for each of the plurality of error amplifiers, and therefore the area efficiency of the circuit portion related to the phase compensation circuit 12 can be improved.

[0069] <Second embodiment> Fig. 9 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to the second embodiment. A semiconductor integrated circuit device 102 shown in Fig. 9 differs from the semiconductor integrated circuit device 101 shown in Fig. 4 in that it includes a switch SW1 and a switch control unit (not shown in Fig. 9) that controls the switch SW1, but otherwise has a basically similar configuration to the semiconductor integrated circuit device 101 shown in Fig. 4.

[0070] The switch SW1 switches the gate-source short circuit of the output transistor Q7 on and off. The switch SW1 is, for example, a P-channel MOSFET.

[0071] When the semiconductor integrated circuit device 102 is used as part of a switching power supply device, the first control section is enabled, the second control section is disabled, and the switch SW1 is turned on. As a result, the gate and source of the output transistor Q7 are short-circuited by the switch SW1, so that it is possible to prevent the output transistor Q7 from being turned on due to charging of the parasitic capacitance between the gate and source of the output transistor Q7.

[0072] When the semiconductor integrated circuit device 102 is used as part of a linear power supply device, the first control unit is disabled, the second control unit is enabled, and the switch SW1 is turned off.

[0073] <Third embodiment> Fig. 10 is a diagram showing a schematic configuration of a semiconductor integrated circuit device according to the third embodiment. The semiconductor integrated circuit device 103 shown in Fig. 10 differs from the semiconductor integrated circuit device 101 shown in Fig. 4 in that it includes switches SW2 and SW3 and a switch control unit (not shown in Fig. 9) that controls the switches SW2 and SW3, but otherwise has a basically similar configuration to the semiconductor integrated circuit device 101 shown in Fig. 4.

[0074] The switch SW2 is provided between the source of the transistor Q6 and the source of the output transistor Q7. The switch SW2 is, for example, a P-channel MOSFET.

[0075] The switch SW3 is provided between the gate of the transistor Q6 and the terminal GND. The switch SW3 is, for example, an N-channel MOSFET.

[0076] When the semiconductor integrated circuit device 102 is used as part of a switching power supply device, the first control unit is enabled, the second control unit is disabled, the switch SW2 is turned on, and the switch SW3 is turned off.

[0077] When the semiconductor integrated circuit device 102 is used as part of a linear power supply device, the first control unit is disabled, the second control unit is enabled, the switch SW2 is turned on, and the switch SW3 is turned off.

[0078] When the output transistor Q7 of the semiconductor integrated circuit device 102 is used as a load switch, the first control section is in a disabled state, the second control section is in an enabled state, the switch SW2 is turned off, and the switch SW3 is turned on. Since the switch SW2 is off, the gate of the output transistor Q7 is prevented from being clamped by the threshold voltage of the transistor Q6. Furthermore, since the switch SW3 is on, the ground voltage is supplied to the gate of the output transistor Q7. As a result, the output transistor Q7 is fully on. Therefore, the output transistor Q7 can be used as a load switch.

[0079] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0080] For example, a diode having an anode connected to the terminal GND and a cathode connected to the drain of the transistor M1 may be used instead of the transistor M2. When a diode is used instead of the transistor M2, the first control unit controls the on / off switching of the diode by controlling the voltage of the terminal SW through switching control of the transistor M1.

[0081] For example, the transistor M1 may be an N-channel MOSFET. When the transistor M1 is an N-channel MOSFET, a bootstrap circuit may be provided in the power supply device.

[0082] For example, in the above embodiment, the semiconductor integrated circuit device has built-in resistors R1 and R2, but the resistors R1 and R2 may be externally connected to the semiconductor integrated circuit device. FB is the output voltage of the power supply, V OUT The output voltage of the power supply V OUT It may be the same thing.

[0083] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0084] A semiconductor integrated circuit device (101, 102, 103) of the present disclosure is a semiconductor integrated circuit device configured to be part of a power supply device, and includes an error amplifier (11) configured to output an error voltage corresponding to an error between a feedback voltage based on an output voltage of the power supply device and a reference voltage, a first switching element (M1) and a second switching element (M2) connected in series, a first control unit (13, 14, 15, CD) configured to control the switching of the first switching element and the second switching element based on the error voltage, an output transistor (Q7), a second control unit (Q1 to Q6, 22) configured to linearly control the output transistor based on the error voltage, and a first terminal (SW) configured to connect a connection node of the first switching element and the second switching element to an output end of the output transistor (first configuration).

[0085] In the semiconductor integrated circuit device of the first configuration, since both the first control section configured for switching control and the second control section configured for linear control perform control based on the same error voltage, the number of error amplifiers can be reduced, thereby improving the area efficiency of the semiconductor integrated circuit device.

[0086] Furthermore, the semiconductor integrated circuit device of the first configuration described above is configured to include a first terminal configured to connect the connection node of the first switching element and the second switching element to the output end of the output transistor, so that the substrate for the switching power supply and the substrate for the linear power supply can be made common.

[0087] The semiconductor integrated circuit device of the first configuration may have a configuration (second configuration) including a phase compensation circuit (12) configured to perform phase compensation for the error amplifier.

[0088] The semiconductor integrated circuit device of the first or second configuration may be configured (third configuration) to include a first switch (SW1) configured to switch on and off a short circuit between the gate and source of the output transistor.

[0089] In the semiconductor integrated circuit device of any of the first to third configurations, a fourth configuration may be provided, which includes a field effect transistor (Q6) that is paired with the output transistor to form a current mirror circuit, and a second switch (SW2) that is provided between the source of the field effect transistor and the source of the output transistor.

[0090] The semiconductor integrated circuit device of the fourth configuration may be configured (fifth configuration) to include a third switch (SW3) provided between the gate of the field effect transistor and a second terminal (GND) configured to receive a ground voltage.

[0091] In the semiconductor integrated circuit device of the above-mentioned fifth configuration, a configuration (sixth configuration) may be provided having a first operation mode in which the second switch is turned on and the third switch is turned off, and a second operation mode in which the second switch is turned off and the third switch is turned on.

[0092] The power supply device of the present disclosure has a configuration (seventh configuration) including a substrate (201) and a semiconductor integrated circuit device of any one of the first to sixth configurations mounted on the substrate.

[0093] The power supply device of the seventh configuration may be configured (eighth configuration) to include an inductor (L1) mounted on the substrate and electrically connected to the terminal, or a wiring pattern having an inductor component formed on the substrate and electrically connected to the terminal.

[0094] In the power supply device of the seventh configuration described above, the power supply device may be configured (ninth configuration) to include a conductor (D1) provided on the substrate and electrically connected to the terminal, or a wiring pattern formed on the substrate and electrically connected to the terminal, the wiring pattern having no inductor component. [Explanation of symbols]

[0095] 11, 21 Error amplifier 12 Phase compensation circuit 12a capacitor 12b resistor 13 Slope voltage generation circuit 14 Comparator 15 Clock signal generation circuit 16 Logic Circuits 17 Drive circuit 18 Registers 19 Switch control section 22 Constant current source 100~103 Semiconductor integrated circuit device 201, 202 Board C1 Output capacitor CD control drive circuit D1 Conductor L1 Inductor M1, M2, Q1~Q6 transistors Q7 Output transistor R1, R2 resistance IN, SW, OUT, GND terminals P1~P6 Wiring pattern SW1~SW3 1st~3rd switches

Claims

1. A semiconductor integrated circuit device configured to be a part of a power supply device, an error amplifier configured to output an error voltage corresponding to an error between a feedback voltage based on an output voltage of the power supply device and a reference voltage; a first switching element and a second switching element connected in series; A first control unit configured to control switching of the first switching element and the second switching element based on the error voltage; An output transistor; A second control unit configured to linearly control the output transistor based on the error voltage; a first terminal configured to connect a connection node between the first switching element and the second switching element and an output end of the output transistor; A semiconductor integrated circuit device comprising:

2. 2. The semiconductor integrated circuit device according to claim 1, further comprising a phase compensation circuit configured to perform phase compensation for said error amplifier.

3. 2. The semiconductor integrated circuit device according to claim 1, further comprising a first switch configured to switch on and off a short circuit between the gate and source of said output transistor.

4. a field effect transistor which is paired with the output transistor to form a current mirror circuit; a second switch provided between the source of the field effect transistor and the source of the output transistor; 2. The semiconductor integrated circuit device according to claim 1, comprising:

5. 5. The semiconductor integrated circuit device according to claim 4, further comprising a third switch provided between the gate of said field effect transistor and a second terminal configured to receive a ground voltage.

6. a first operation mode in which the second switch is turned on and the third switch is turned off; 6. The semiconductor integrated circuit device according to claim 5, further comprising: a second operation mode in which said second switch is turned off and said third switch is turned on.

7. A substrate; A semiconductor integrated circuit device according to any one of claims 1 to 6, which is mounted on the substrate; A power supply device comprising:

8. 8. The power supply device according to claim 7, further comprising an inductor mounted on said substrate and electrically connected to said terminal, or a wiring pattern having an inductor component formed on said substrate and electrically connected to said terminal.

9. 8. The power supply device according to claim 7, further comprising a conductor provided on said substrate and electrically connected to said terminal, or a wiring pattern having no inductor component formed on said substrate and electrically connected to said terminal.

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