Semiconductor device and positional deviation measuring method of semiconductor device

Abstract

To provide a semiconductor device capable of easily measuring a positional deviation of a chip that is connected in flip-chip.SOLUTION: In a semiconductor device 100, a first substrate 10 comprises: a plurality of first pads 11; a plurality of conductive second pads 12 that are separated from each other in a D2 direction that is parallel to a surface of the substrate, and are arranged on the surface of the substrate; and a conductive member 13 that is provided to the surface of the substrate, and electrically connects the plurality of first pads and second pads. A second substrate 20 comprises: a plurality of third pads 21; and a plurality of conductive fourth pads 22 that are arranged so as to be separated from each other in the D2 direction, and are arranged on an opposite surface. The first substrate further comprises: a first measurement pad 23 that measures whether or not each third pad is conducted to each fourth pad via each first pad, the conductive member, and each second pad; and a second measurement pad 24 for confirming whether or not each third pad is conducted to each fourth pad in the plurality of fourth pads via each first pad, the conductive member, and each second pad.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for measuring misalignment of the semiconductor device. [Background technology]

[0002] The D2W (Die-to-Wafer) process, in which two types of chips are stacked together, has been known for some time. Patent Document 1 discloses multiple substrates that are flip-chip connected. The multiple substrates have two or more cross-shaped alignment marks in order to improve the yield of flip-chip connections (see FIG. 5 of Patent Document 1).

[0003] When metal wiring is formed on each of a plurality of substrates, alignment marks are formed on each substrate as a TEG (Test Elementary Group) pattern at the same time as the metal wiring. Therefore, the alignment marks formed on each substrate have a specific relative positional relationship with the metal wiring. A laser microscope is generally used to measure the relative positional deviation (hereinafter referred to as "positional deviation") between the alignment marks on one substrate and the alignment marks on the other substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 09-321086 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional technology, a laser microscope is used to measure the misalignment of the alignment marks, and therefore, due to the need to set up the laser microscope and perform maintenance on the laser microscope, it may not be possible to meet the need to further shorten the manufacturing time of semiconductor devices. Thus, there is room for improvement in measuring the misalignment of two types of chips (substrates) that are flip-chip connected.

[0006] In consideration of the above circumstances, an object of the present disclosure is to provide a semiconductor device and a method for measuring misalignment of a semiconductor device that can easily measure misalignment between two types of flip-chip connected chips. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems, a semiconductor device according to the present disclosure is a semiconductor device including a first substrate and a second substrate mounted on top of each other, the first substrate including a plurality of conductive first pads arranged on a substrate surface at intervals in a first direction parallel to a substrate surface of the first substrate when the first substrate is viewed in a plan view from a specific direction, a plurality of conductive second pads arranged on the substrate surface at intervals in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed in a plan view from the specific direction, and a conductive member provided on the substrate surface and electrically connecting the plurality of first pads and the second pads. The second substrate comprises a plurality of conductive third pads arranged on the opposing surface of the second substrate facing the first substrate, and a plurality of conductive fourth pads arranged on the opposing surface in the second direction, spaced apart from each other, when the second substrate is viewed in a plan view from the specific direction, wherein the first substrate further comprises a first measurement pad connected to at least one of the plurality of third pads and measuring whether or not the third pad is conductive with the fourth pad via the first pad, the conductive member, and the second pad, and a second measurement pad connected to at least one of the plurality of fourth pads and checking whether or not the third pad is conductive with the fourth pad via the first pad, the conductive member, and the second pad.

[0008] A method for measuring misalignment of a semiconductor device according to the present disclosure is a method for measuring misalignment of a semiconductor device, the semiconductor device comprising a first substrate and a second substrate mounted on top of each other, the first substrate comprising a plurality of conductive first pads arranged on a substrate surface at a distance from each other in a first direction parallel to a substrate surface of the first substrate when the first substrate is viewed in a plan view from a specific direction, a plurality of conductive second pads arranged on the substrate surface at a distance from each other in a second direction parallel to the substrate surface different from the first direction when the first substrate is viewed in a plan view from the specific direction, and a conductive member provided on the substrate surface and electrically connecting the plurality of first pads and the second pads, the second substrate comprising a plurality of conductive third pads arranged on a surface of the second substrate facing the first substrate at a distance from each other in the first direction when the second substrate is viewed in a plan view from the specific direction, and a plurality of conductive fourth pads arranged on the facing surface at a distance from each other in the second direction when the second substrate is viewed in a plan view from the specific direction, and a first measurement pad connected to at least one of the plurality of fourth pads and configured to measure whether the third pad is in electrical continuity with the fourth pad via the first pad, the conductive member, and the second pad; and a second measurement pad connected to at least one of the plurality of fourth pads and configured to confirm whether the third pad is in electrical continuity with the fourth pad via the first pad, the conductive member, and the second pad, wherein the measurement method includes the steps of: determining whether any of the plurality of third pads is in electrical continuity with any of the plurality of fourth pads using a measuring device connected to the first measurement pad and the second measurement pad; and determining that an amount of misalignment between a first chip formed on the first substrate and a second chip formed on the second substrate is within a specific range when any of the plurality of third pads is not in electrical continuity with any of the plurality of fourth pads, and determining that an amount of misalignment between the first chip and the second chip is outside the specific range when any of the plurality of third pads is in electrical continuity with any of the plurality of fourth pads. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a semiconductor device and a method for measuring misalignment of a semiconductor device that can easily measure misalignment between two types of flip-chip connected chips. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is an enlarged view of the vicinity of the bump shown in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the alignment mark. [Diagram 5] FIG. 5 is a diagram showing a configuration example of a measurement structure. [Figure 6] FIG. 6 is a flowchart for explaining the method for measuring misalignment of a semiconductor device according to the present disclosure. [Figure 7] FIG. 7 is a diagram for explaining the method for measuring misalignment of a semiconductor device according to the present disclosure. [Figure 8] FIG. 8 is a diagram for explaining the method for measuring misalignment of a semiconductor device according to the present disclosure. [Figure 9] FIG. 9 is a diagram for explaining the method for measuring misalignment of a semiconductor device according to the present disclosure. [Figure 10] FIG. 10 is a block diagram showing the hardware configuration of the position deviation measuring device. [Figure 11] FIG. 11 is a diagram showing the functional blocks of the position deviation measuring device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0012] (Embodiment) 1 and 2 are diagrams showing a configuration example of a semiconductor device according to an embodiment of the present disclosure, in which Fig. 1 shows a cross-sectional view of a semiconductor device 100, and Fig. 2 shows an external view of the semiconductor device 100.

[0013] 1, a semiconductor device 100 may include a first substrate 10 and a second substrate 20 that are mounted one above the other in a D2W process. The first substrate 10 may be interpreted as a substrate for a first chip. The second substrate 20 may be interpreted as a substrate for a second chip. Up and down may be interpreted as a relative positional relationship in a specific direction D.

[0014] In the D2W process, the first substrate 10 is adhered to the second substrate 20 by the bumps 30 arranged in an array. Specifically, the first substrate 10 on which a specific integrated circuit (e.g., a SEED chip) that is a first chip is mounted is flipped 180 degrees and then placed on the second substrate 20 on which another integrated circuit (e.g., a POT chip) that is a second chip is mounted, and the first substrate 10 is adhered to the second substrate 20 by the bumps 30 arranged in an array. This allows the two types of chips to be electrically connected.

[0015] The bumps 30 may be interpreted as protruding electrodes. The plurality of bumps 30 may be arranged in a direction D1. The direction D1 may be interpreted as a direction perpendicular to the direction D. Furthermore, the plurality of bumps 30 may be arranged in a direction D2. The direction D2 may be interpreted as a direction perpendicular to both the direction D and the direction D1.

[0016] The semiconductor device 100 may include a measurement structure 40 and an alignment mark 50. The measurement structure 40 and the alignment mark 50 may be provided between the first substrate 10 and the second substrate 20.

[0017] The alignment mark 50 may include a first alignment mark and a second alignment mark.

[0018] The first alignment mark may be provided on the substrate surface of the first substrate 10. The substrate surface of the first substrate 10 may be interpreted as the surface 10a of the first substrate 10 facing the second substrate 20 (see FIG. 2).

[0019] The second alignment mark may be provided on the substrate surface of the second substrate 20. The substrate surface of the second substrate 20 may be interpreted as the surface 20a (see FIG. 2) of the second substrate 20 facing the first substrate 10. Specific examples of the first alignment mark and the second alignment mark will be described later.

[0020] Fig. 3 is an enlarged view of the vicinity of the bumps shown in Fig. 1. It is assumed that by overlapping the first substrate 10 with the second substrate 20, the first substrate 10 is slightly displaced from a specific position on the second substrate 20 in one or both of the directions D1 and D2. Fig. 3 shows a state in which a plurality of electrodes provided on each of the first substrate 10 and the second substrate 20 are slightly displaced. The electrodes may include conductors mounted on each of the first substrate 10 and the second substrate 20, and the bumps 30 described above.

[0021] Even when the electrodes are misaligned in this way, so long as the amount of misalignment of the electrodes is within a specific range, electrical continuity between the chip on the first substrate 10 and the chip on the second substrate 20 can be ensured. On the other hand, if the amount of misalignment of the electrodes is outside the specific range, electrical continuity between the chip on the first substrate 10 and the chip on the second substrate 20 is highly likely not to be ensured. This can result in a decrease in yield of flip chip connection. In the prior art, in order to suppress a decrease in yield of flip chip connection, the amount of misalignment of the first alignment mark with respect to the second alignment mark described above is measured by a laser microscope.

[0022] Fig. 4 is a diagram showing an example of an alignment mark. The upper part of Fig. 4 shows a measurement structure 40 and an alignment mark 50. The measurement structure 40 and the alignment mark 50 are provided between the first substrate 10 and the second substrate 20 when these substrates are viewed in a plan view from the first substrate 10 towards the second substrate 20 in the direction D. The alignment mark 50 may be provided in the vicinity of the measurement structure 40. The lower part of Fig. 4 shows an enlarged view of the alignment mark 50 shown in the upper part of Fig. 4.

[0023] The alignment mark 50 may include a cross-shaped first alignment mark 51 and a second alignment mark 52. When forming metal wiring on a substrate, these marks are formed as a TEG pattern at the same time as the metal wiring, so that the relative positional relationship with the metal wiring can be specified. In the prior art, a laser microscope has generally been used to measure the amount of misalignment of the first alignment mark 51 with respect to the second alignment mark 52.

[0024] The semiconductor device 100 of the present disclosure includes a measurement structure 40, and it is possible to measure the presence or absence of misalignment between electrodes or two substrates, the amount of misalignment, etc., based on a change in the conduction state of a plurality of conductive members constituting this measurement structure 40, i.e., a change in the electrical connection state of the members. In other words, it is possible to measure the presence or absence of misalignment between electrodes or substrates, the amount of misalignment, etc., without using a laser microscope.

[0025] The configuration of the measurement structure 40 will be specifically described below with reference to FIG. 5. FIG. 5 is a diagram showing an example of the configuration of the measurement structure. FIG. 5 shows the measurement structure 40 in a plan view of the first substrate 10. Specifically, the measurement structure 40 is shown in a plan view of the first substrate 10 from the first substrate 10 toward the second substrate 20 in the direction D. The measurement structure 40 may be provided between the first substrate 10 and the second substrate 20. The measurement structure 40 may be composed of a plurality of conductive members provided on each of the first substrate 10 and the second substrate 20.

[0026] (First substrate 10) The first substrate 10 may include a plurality of first pads 11, a plurality of second pads 12, a conductive member 13 having a specific shape, and a first alignment mark 51. The specific shape may be interpreted as an L-shape.

[0027] (1st pad 11) Each of the multiple first pads 11 may be interpreted as a conductive terminal, wiring, or electrode. The multiple first pads 11 may be provided on the first extension portion 13a of the conductive member 13. Specifically, the multiple first pads 11 may be provided on the surface of the first extension portion 13a of the conductive member 13, the surface opposite to the first substrate 10 side. The surface opposite to the first substrate 10 side may be interpreted as the surface of the first extension portion 13a facing the second substrate 20. The first pads 11 may be electrically connected to the first extension portion 13a. The configuration of the conductive member 13 will be described in detail later.

[0028] The multiple first pads 11 may be arranged spaced apart from one another on the substrate surface of the first substrate 10 (the surface of the first extension portion 13a facing the second substrate 20) in the direction D1. The direction D1 may be interpreted as a first direction in a virtual plane parallel to the substrate surface of the first substrate 10 when the first substrate 10 is viewed in a plan view. The substrate surface of the first substrate 10 may be interpreted as the surface 10a of the first substrate 10 facing the second substrate 20 (see FIG. 2).

[0029] The first pads 11 may be arranged on a first virtual line extending in the direction D1. The first virtual line may be interpreted as a virtual line passing through the vicinity of the center of each of the first pads 11 in the direction D2 and parallel to the arrangement direction of these pads. The first virtual line may be interpreted as a line passing through the center 51a (see FIG. 4) of the first alignment mark 51 or the vicinity of the center 51a.

[0030] The distance between two adjacent specific first pads 11 may be set to become wider in order from the first pad 11 located closest to a virtual reference point P to the first pad 11 located farthest from the reference point P.

[0031] The reference point P may be interpreted as a portion overlapping with the central portion 51a (see FIG. 4) of the first alignment mark 51. The central portion 51a of the first alignment mark 51 may be interpreted as a portion where the center of the first alignment mark 51 in the direction D1 and the center of the first alignment mark 51 in the direction D2 overlap.

[0032] The center portion 51a of the first alignment mark 51 may be interpreted as the position where the first virtual line described above and a second virtual line described below intersect.

[0033] In order to ensure that the amount of misalignment between the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 falls within a specific range, the separation distance between the first pad 11 and the third pad 21 in the direction D1 may be set to a value as follows: In other words, the respective arrangement positions of the first pad 11 and the third pad 21 in the direction D1 may be set so as to ensure this distance. Distance Y1=2μm Distance Y2=4μm Distance Y3=6μm Distance Y4=8μm

[0034] (2nd pad 12) Each of the multiple second pads 12 may be interpreted as a conductive terminal, wiring, or electrode. The multiple second pads 12 may be provided on the second extension portion 13b of the conductive member 13. Specifically, the multiple second pads 12 may be provided on the surface of the second extension portion 13b of the conductive member 13, the surface opposite to the first substrate 10 side. The surface opposite to the first substrate 10 side may be interpreted as the surface of the second extension portion 13b facing the second substrate 20. The multiple second pads 12 may be electrically connected to the second extension portion 13b of the conductive member 13.

[0035] The second pads 12 may be arranged in direction D2 and spaced apart from one another on the substrate surface of the first substrate 10 (the surface of the second extension portion 13b facing the second substrate 20). The direction D2 may be interpreted as a second direction different from the first direction in a virtual plane parallel to the substrate surface of the first substrate 10 when the first substrate 10 is viewed in a plan view. Specifically, the second direction may be interpreted as a direction perpendicular to the first direction in the virtual plane, or may be interpreted as a direction other than a direction perpendicular to the first direction.

[0036] The second pads 12 may be arranged on a second imaginary line extending in the direction D2. The second imaginary line may be interpreted as a virtual line passing through the vicinity of the center of each of the second pads 12 in the direction D1 and parallel to the arrangement direction of these pads. The second imaginary line may be interpreted as a line passing through the center 51a (see FIG. 4) of the first alignment mark 51 or the vicinity of the center 51a.

[0037] The distance between any two adjacent second pads 12 may be set to become wider in order from the second pad 12 located closest to the virtual reference point P (or the center 51a) to the second pad 12 located farthest from the reference point P (or the center 51a).

[0038] In order to ensure that the amount of misalignment between the first chip and the second chip falls within a specific range, the separation distance between the second pad 12 and the fourth pad 22 in the direction D2 may be set to a value such as the following: In other words, the respective arrangement positions of the second pad 12 and the fourth pad 22 in the direction D2 may be set so as to ensure these distances. Distance X1=2μm Distance X2=4μm Distance X3=6μm Distance X4=8μm

[0039] (Conductive member 13) The conductive member 13 may be interpreted as a conductive terminal, wiring, or electrode that electrically connects the multiple first pads 11 and the second pads 12. The conductive member 13 may be interpreted as a member for electrically connecting the first measurement pad 23 and the second measurement pad 24. The conductive member 13 may be provided on the substrate surface of the first substrate 10. Specifically, the conductive member 13 may be provided on an opposing surface 10a (see FIG. 2) of the first substrate 10 that faces the second substrate 20.

[0040] The conductive member 13 may include a first extension portion 13a extending in a first direction (direction D1) and a second extension portion 13b extending in a second direction (direction D2) from an end portion of the first extension portion 13a.

[0041] (First extension part 13a) The first extending portion 13a may have a shape that extends to a position a certain distance away in the first direction from the reference point P. A plurality of first pads 11 may be provided on the first extending portion 13a.

[0042] (Second extension part 13b) The second extending portion 13b may have a shape that extends to a position a certain distance away in the second direction from the reference point P. A plurality of second pads 12 may be provided on the second extending portion 13b.

[0043] (Second substrate 20) The second substrate 20 may include a plurality of third pads 21, a plurality of fourth pads 22, a first measurement pad 23, a second measurement pad 24, and a second alignment mark 52.

[0044] (3rd pad 21) Each of the multiple third pads 21 may be interpreted as a conductive terminal, wiring, or electrode. The multiple third pads 21 may be provided on the substrate surface of the second substrate 20. The multiple third pads 21 may be arranged on the substrate surface of the second substrate 10 at a distance from each other in the direction D1. The multiple third pads 21 may be arranged so as to overlap with the first extension portion 13a of the conductive member 13 up to a position at a certain distance from the reference point P in the first direction. The substrate surface of the second substrate 10 may be interpreted as a surface 20a (see FIG. 2) of the second substrate 20 facing the first substrate 10.

[0045] Each of the multiple third pads 21 may be formed so as to be in electrical non-contact with the first extension portion 13a of the conductive member 13. Specifically, the thickness of each of the multiple third pads 21 in the direction D may be greater than the thickness of each of the multiple first pads 11 in the direction D. Also, an insulating film may be provided in a partial region (for example, between adjacent first pads 11) of the surface of the first extension portion 13a of the conductive member 13. This can prevent the third pad 21 from being in electrical contact with the first extension portion 13a of the conductive member 13 when the first substrate 10 is overlapped with the second substrate 20.

[0046] The third pads 21 may be arranged on a third imaginary line extending in the direction D1. The third imaginary line may be interpreted as an imaginary line passing through the vicinity of the center of each of the third pads 21 in the direction D2 and parallel to the arrangement direction of these pads. The third imaginary line may be interpreted as a line passing through the center 52a (see FIG. 4) of the second alignment mark 52 or near the center 52a.

[0047] The center portion 52a of the second alignment mark 52 may be interpreted as the position where the third virtual line described above and a fourth virtual line described below intersect.

[0048] The distance between any two adjacent third pads 21 may be set to become wider in order from the third pad 21 located closest to the center 52a of the second alignment mark 52 to the third pad 21 located farthest from the center 52a of the second alignment mark 52.

[0049] (4th pad 22) Each of the multiple fourth pads 22 may be interpreted as a conductive terminal, wiring, or electrode. The multiple fourth pads 22 may be provided on the substrate surface of the second substrate 20. The multiple fourth pads 22 may be arranged on the substrate surface of the second substrate 20 at a distance from each other in the direction D2. The multiple fourth pads 22 may be arranged to overlap with the second extension portion 13b of the conductive member 13 up to a position at a certain distance from the reference point P in the second direction.

[0050] Each of the multiple fourth pads 22 may be formed so as to be electrically non-contact with the second extension portion 13b of the conductive member 13. Specifically, the thickness of each of the multiple fourth pads 22 in the direction D may be greater than the thickness of each of the multiple second pads 12 in the direction D. Also, an insulating film may be provided in a partial region (for example, between adjacent second pads 12) of the surface of the second extension portion 13b of the conductive member 13. This can prevent the fourth pad 22 from being electrically contacted with the second extension portion 13b of the conductive member 13 when the first substrate 10 is overlapped with the second substrate 20.

[0051] The multiple fourth pads 22 may be arranged on a fourth imaginary line extending in the direction D2. The fourth imaginary line may be interpreted as an imaginary line passing through the vicinity of the center of each of the multiple fourth pads 22 in the direction D1 and parallel to the arrangement direction of these pads. The fourth imaginary line may be interpreted as a line passing through the center 52a (see FIG. 4) of the second alignment mark 52 or near the center 52a.

[0052] The distance between any two adjacent fourth pads 22 may be set to become wider in order from the fourth pad 22 located closest to the center 52a of the second alignment mark 52 to the fourth pad 22 located farthest from the center 52a of the second alignment mark 52.

[0053] (First measuring pad 23) Each of the multiple first measurement pads 23 may be interpreted as a pad for measuring whether or not the third pad 21 is electrically connected to the fourth pad 22 via the first pad 11, the conductive member 13, and the second pad 12. Each of the multiple first measurement pads 23 may be interpreted as a conductive terminal, wiring, or electrode.

[0054] The multiple first measurement pads 23 may be provided on a surface 20a (see FIG. 2) of the second substrate 20 facing the first substrate 10. The multiple first measurement pads 23 may be arranged on the substrate surface (facing surface 20a) of the second substrate 20 spaced apart from each other in the direction D1. Each of the multiple first measurement pads 23 may be electrically connected to at least one of the multiple third pads 21. The positions of the multiple first measurement pads 23 are not particularly limited, and may be any position that allows easy connection of wiring, connectors, etc. extending from the measuring device 200.

[0055] (Second measuring pad 24) Each of the multiple second measurement pads 24 may be interpreted as a pad for measuring whether or not the third pad 21 is electrically connected to the fourth pad 22 via the first pad 11, the conductive member 13, and the second pad 12. Each of the multiple second measurement pads 24 may be interpreted as a conductive terminal, wiring, or electrode.

[0056] The multiple second measurement pads 24 may be provided on a surface 20a (see FIG. 2) of the second substrate 20 facing the first substrate 10. The multiple second measurement pads 24 may be arranged on the substrate surface (facing surface 20a) of the second substrate 20 spaced apart from one another in the direction D2. Each of the multiple second measurement pads 24 may be electrically connected to at least one of the multiple fourth pads 22. The positions of the multiple second measurement pads 24 are not particularly limited as long as they are positions at which wiring, connectors, etc. extending from the measuring device 200 can be easily connected.

[0057] A measuring device 200 may be connected to the first measurement pad 23 and the second measurement pad 24. The configuration of the measuring device 200 will be described in detail later.

[0058] It is preferable that the first measurement pad 23 is provided for each of the third pads 21. It is also preferable that the second measurement pad 24 is provided for each of the fourth pads 22. This allows a plurality of current paths to be provided. That is, a plurality of paths can be provided for electrically connecting the first measurement pad 23 and the second measurement pad 24. By providing a plurality of current paths, the flow rate of the current changes compared to the case where there is only one current path, so that the measurement device 200 can estimate the amount of positional deviation of the electrodes, etc. based on the current. Specifically, the measurement device 200 can calculate the amount of positional deviation corresponding to the value of the current flowing from the first measurement pad 23 to the second measurement pad 24 by using table information that associates the value of the current with the amount of positional deviation of the electrodes, etc.

[0059] Next, a method for measuring misalignment of the semiconductor device 100 will be described with reference to Fig. 6 to Fig. 9. Fig. 6 is a flowchart for explaining the method for measuring misalignment of the semiconductor device according to the present disclosure. Figs. 7, 8, and 9 are diagrams for explaining the method for measuring misalignment of the semiconductor device according to the present disclosure.

[0060] Fig. 7 shows a first substrate 10 and a second substrate 20 that are mounted on top of each other so that the amount of misalignment falls within a specific range. The state of the first substrate 10 and the second substrate 20 shown in Fig. 7 is equivalent to the state of the first substrate 10 and the second substrate 20 shown in Fig. 5. In contrast, Figs. 8 and 9 show a first substrate 10 and a second substrate 20 that are mounted on top of each other so that the amount of misalignment falls outside the specific range.

[0061] The misalignment measuring method for the semiconductor device 100 may include a continuity determination process for determining continuity, and a misalignment amount determination process for determining the presence or absence of misalignment, the amount of misalignment, and the like.

[0062] In step S1 shown in FIG. 6, the continuity determination process may measure the current flowing through the first measurement pad 23 and the second measurement pad 24, the voltage applied to the first measurement pad 23 and the second measurement pad 24, etc. (step S1).

[0063] Next, in step S2, the continuity determination process may determine, based on the measured current or the like, whether any of the multiple third pads 21 is in a non-conductive state or a conductive state with any of the multiple fourth pads 22. In other words, it may determine whether any of the multiple first measurement pads 23 is in a non-conductive state or a conductive state with any of the multiple second measurement pads 24.

[0064] The non-conductive state may be interpreted as a state in which none of the multiple third pads 21 is in contact with any of the multiple first pads 11, or a state in which none of the multiple fourth pads 22 is in contact with any of the multiple second pads 12, as shown in FIG.

[0065] The conductive state may be interpreted as a state in which any of the multiple third pads 21 is in contact with any of the multiple first pads 11, and any of the multiple fourth pads 22 is in contact with any of the multiple second pads 12, as shown in Figures 8 and 9. For example, as shown in Figure 8, when two third pads 21 are in contact with two first pads 11, and two second pads 12 are in contact with two fourth pads 22, two current paths A are formed.

[0066] As shown in FIG. 7, in the case of a non-conductive state (step S2, YES), in step S3, the misalignment amount determination process may determine that the amount of misalignment between the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 is within a specific range.

[0067] As shown in FIGS. 8 and 9, in the case of the conductive state (step S2, NO), in the positional deviation amount determination process in step S4, it may be determined that the amount of positional deviation is outside a specific range.

[0068] In the misalignment amount determination process, if one or two current paths A are formed, it may be determined that the amount of misalignment between the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 is within a specific range. In the misalignment amount determination process, if three or more current paths A are formed, it may be determined that the amount of misalignment is outside the specific range.

[0069] In the misalignment amount determination process, when two current paths A are formed, the amount of misalignment may be determined to be a specific value X (μm), when three current paths A are formed, the amount of misalignment may be determined to be a specific value Y (μm) greater than X, and when four current paths A are formed, the amount of misalignment may be determined to be a specific value Z (μm) greater than Y. In the misalignment amount determination process, when one current path A is formed, the amount of misalignment may be determined to be a specific value M (μm) less than X.

[0070] 10 is a block diagram showing the hardware configuration of the position deviation measuring device. The position deviation measuring device 200 includes a CPU (Central Processing Unit) 11, a storage unit 13A which is a non-volatile memory, a display 14 such as a liquid crystal display, an input device 15, a memory 16 which is a temporary storage area, and a network I / F (Interface) 17. The CPU 11, the storage unit 13A, the display 14, the input device 15, the memory 16, and the network I / F 17 are connected to a bus 18.

[0071] The CPU 11 may be interpreted as a processor. The input device 15 may include a pointing device such as a keyboard or a mouse. The storage unit 13A may be realized by a hard disk drive (HDD), a solid state drive (SSD), a flash memory, or the like. A positional deviation measuring program 12A is stored in the storage unit 13A. The CPU 11 may read out the positional deviation measuring program 12A from the storage unit 13A, expand the positional deviation measuring program 12A in the memory 16, and execute the expanded positional deviation measuring program 12A.

[0072] Next, functions of the position deviation measuring device 200 will be described with reference to Fig. 11. Fig. 11 is a diagram showing functional blocks of the position deviation measuring device. The position deviation measuring device 200 may include an input unit 201, a conductivity determination unit 202, and a position deviation amount determination unit 203. The input unit 201, the conductivity determination unit 202, and the position deviation amount determination unit 203 may be realized by the CPU 11 shown in Fig. 10 executing the position deviation measurement program 12A.

[0073] (Input unit 201) The input section 201 may input information indicating the current flowing through the first measurement pad 23 and the second measurement pad 24, the voltage applied to these pads, and the like.

[0074] (Continuity determination section 202) The conductivity determination unit 202 may determine whether any of the multiple third pads 21 is conductive with any of the multiple fourth pads 22 based on the value of the current, the value of the voltage, etc. flowing through the first measurement pad 23 and the second measurement pad 24.

[0075] (positional deviation amount determination unit 203) The misalignment amount determination unit 203 may determine whether the amount of misalignment between the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 is within a specific range or outside the specific range, and may transmit information indicating the determination result to the display 14. The display 14 may have a display control unit, which may display the presence or absence of misalignment, the amount of misalignment, etc. based on the information.

[0076] (Action and effect) In the semiconductor device 100 of the present disclosure, the first substrate 10 includes a plurality of first pads 11, a plurality of second pads 12, and a conductive member 13, and the second substrate 20 includes a plurality of third pads 21, a plurality of fourth pads 22, a first measurement pad 23, and a second measurement pad 24. This makes it possible to measure the presence or absence of misalignment of the chips on the first substrate 10 and the second substrate 20 that are mounted one on top of the other, and the amount of misalignment, etc., by detecting changes in the electrical connection state of these conductive members. Therefore, the amount of misalignment, etc., can be easily measured without using a laser microscope.

[0077] Moreover, since the laser microscope is no longer necessary, it is possible to reduce the time required for setting up the laser microscope, maintaining the laser microscope, and the like, and thus further shorten the manufacturing time of the semiconductor device 100. The manufacturing cost of the semiconductor device 100 can also be reduced.

[0078] In addition, the following supplementary notes are provided in relation to the above description.

[0079] (Appendix 1) A semiconductor device including a first substrate and a second substrate mounted on top of each other, The first substrate is a plurality of conductive first pads arranged on a substrate surface, spaced apart from one another, in a first direction parallel to a substrate surface of the first substrate when the first substrate is viewed in a plan view from a specific direction; a plurality of conductive second pads arranged on the substrate surface at intervals in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed in a plan view from the specific direction; a conductive member provided on the substrate surface and electrically connecting the first pads and the second pads; The second substrate is a plurality of conductive third pads arranged in the first direction, spaced apart from one another, on a surface of the second substrate facing the first substrate when the second substrate is viewed in a plan view from the specific direction; a plurality of conductive fourth pads arranged on the opposing surface in the second direction and spaced apart from each other when the second substrate is viewed in a plan view from the specific direction; a first measurement pad connected to at least one of the plurality of third pads and configured to measure whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; a second measurement pad connected to at least one of the plurality of fourth pads, for checking whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; A semiconductor device comprising:

[0080] (Appendix 2) the conductive member includes a first extension portion extending in the first direction and a second extension portion extending in the second direction from an end of the first extension portion, The first pads are provided on the first extension portion, The second pads are provided on the second extension portion, The first measurement pad is provided on each of the plurality of third pads, 2. The semiconductor device according to claim 1, wherein the second measurement pad is provided for each of the plurality of fourth pads.

[0081] (Appendix 3) A method for measuring a positional deviation of a semiconductor device, comprising the steps of: The semiconductor device includes a first substrate and a second substrate mounted on top of each other, The first substrate is a plurality of conductive first pads arranged on a substrate surface, spaced apart from one another, in a first direction parallel to a substrate surface of the first substrate when the first substrate is viewed in a plan view from a specific direction; a plurality of conductive second pads arranged on the substrate surface at intervals in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed in a plan view from the specific direction; a conductive member provided on the substrate surface and electrically connecting the first pads and the second pads; The second substrate is a plurality of conductive third pads arranged in the first direction, spaced apart from one another, on a surface of the second substrate facing the first substrate when the second substrate is viewed in a plan view from the specific direction; a plurality of conductive fourth pads arranged on the opposing surface in the second direction and spaced apart from each other when the second substrate is viewed in a plan view from the specific direction; a first measurement pad connected to at least one of the plurality of third pads and configured to measure whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; a second measurement pad connected to at least one of the plurality of fourth pads, for checking whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; Equipped with determining whether any of the third pads is electrically connected to any of the fourth pads by using a measuring device connected to the first measurement pad and the second measurement pad; determining that an amount of misalignment between a first chip formed on the first substrate and a second chip formed on the second substrate is within a specific range when any of the third pads is not electrically connected to any of the fourth pads, and that an amount of misalignment between the first chip and the second chip is outside the specific range when any of the third pads is electrically connected to any of the fourth pads; A method for measuring a positional deviation of a semiconductor device, comprising: [Explanation of symbols]

[0082] 10 First board 10a Opposite surface 11 First Pad 12A Measurement Program 12 2nd Pad 13 Conductive materials 13A Storage section 13a 1st extension section 13b 2nd extension section 14 Display 15 Input Devices 16 Memory 18 Bus 20 Second board 20a Opposite surface 21 3rd Pad 22 4th Pad 23 First measuring pad 24 Second measuring pad 30 Bump 40 Measurement structure 50 Alignment Mark 51 First alignment mark 51a center 52 Second alignment mark 52a center 100 Semiconductor device 200 Measuring Equipment 201 Input section 202 Continuity determination section 203 Deviation amount judgment unit

Claims

1. A semiconductor device including a first substrate and a second substrate mounted on top of each other, The first substrate is a plurality of conductive first pads arranged on a substrate surface, spaced apart from one another, in a first direction parallel to a substrate surface of the first substrate when the first substrate is viewed in a plan view from a specific direction; a plurality of conductive second pads arranged on the substrate surface at intervals in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed in a plan view from the specific direction; a conductive member provided on the substrate surface and electrically connecting the first pads and the second pads; The second substrate is a plurality of conductive third pads arranged in the first direction on a surface of the second substrate facing the first substrate and spaced apart from each other in a plan view of the second substrate from the specific direction; a plurality of conductive fourth pads arranged on the opposing surface in the second direction and spaced apart from each other when the second substrate is viewed in a plan view from the specific direction; a first measurement pad connected to at least one of the plurality of third pads and configured to measure whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; a second measurement pad connected to at least one of the plurality of fourth pads, for checking whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; A semiconductor device comprising:

2. the conductive member includes a first extension portion extending in the first direction and a second extension portion extending in the second direction from an end of the first extension portion, The first pads are provided on the first extension portion, The second pads are provided on the second extension portion, The first measurement pad is provided on each of the plurality of third pads, The semiconductor device according to claim 1 , wherein the second measurement pad is provided for each of the plurality of fourth pads.

3. A method for measuring a positional deviation of a semiconductor device, comprising the steps of: The semiconductor device includes a first substrate and a second substrate mounted on top of each other, The first substrate is a plurality of conductive first pads arranged on a substrate surface, spaced apart from one another, in a first direction parallel to a substrate surface of the first substrate when the first substrate is viewed in a plan view from a specific direction; a plurality of conductive second pads arranged on the substrate surface at intervals in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed in a plan view from the specific direction; a conductive member provided on the substrate surface and electrically connecting the first pads and the second pads; The second substrate is a plurality of conductive third pads arranged in the first direction on a surface of the second substrate facing the first substrate and spaced apart from each other in a plan view of the second substrate from the specific direction; a plurality of conductive fourth pads arranged on the opposing surface in the second direction and spaced apart from each other when the second substrate is viewed in a plan view from the specific direction; a first measurement pad connected to at least one of the plurality of third pads and configured to measure whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; a second measurement pad connected to at least one of the plurality of fourth pads, for checking whether the third pad is electrically connected to the fourth pad via the first pad, the conductive member, and the second pad; Equipped with determining whether any of the third pads is electrically connected to any of the fourth pads by using a measuring device connected to the first measurement pad and the second measurement pad; determining that an amount of misalignment between a first chip formed on the first substrate and a second chip formed on the second substrate is within a specific range when any of the third pads is not electrically connected to any of the fourth pads, and that an amount of misalignment between the first chip and the second chip is outside the specific range when any of the third pads is electrically connected to any of the fourth pads; A method for measuring a positional deviation of a semiconductor device, comprising:

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