Method for manufacturing packaging substrate and packaging substrate using the same

Abstract

To provide a packaging substrate that uses a glass substrate and transmits and receives signals between photoelectric elements by using the characteristics of the glass substrate that allows signals in the form of optical energy to pass therethrough.SOLUTION: A packaging substrate includes a core layer including a glass substrate 21 having a first surface and a second surface facing each other and a cavity portion 28, an insulating layer 253 formed on the first surface, and a light-emitting portion 81 formed on the upper surface of the insulating layer, and a light-receiving portion 82 is disposed in the cavity portion. The insulating layer may include a via VI penetrating in a thickness direction, and a part of the bottom surface of a light-emitting portion may contact the via. With this configuration, a space required for the configuration for electrically connecting the conventional photoelectric element is reduced, and the packaging substrate is manufactured compactly, resulting in the effect of improving the spatial contrast sensing efficiency and performance of the photoelectric sensor.SELECTED DRAWING: Figure 8A

Description

[Technical field]

[0001] This document relates to a packaging substrate, a semiconductor package, a method for manufacturing a packaging substrate, and a method for manufacturing a semiconductor package. [Background technology]

[0002] In the manufacture of electronic components, the process of forming circuits on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE). This back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, over 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections, rather than the performance of the semiconductor technology itself.

[0004] The packaging substrate is made of ceramic or resin. Ceramic substrates such as silicon substrates have high resistance or high dielectric constant, so it is not easy to mount high-performance, high-frequency semiconductor elements on them. Resin substrates can mount relatively high-performance, high-frequency semiconductor elements, but there is a limit to how much the wiring pitch can be reduced.

[0005] Recently, silicon or glass can be applied to high-end packaging substrates. By forming through holes in the silicon or glass substrate and applying a conductive material to the through holes, the wiring length between the device and the motherboard can be shortened, resulting in excellent electrical characteristics.

[0006] Related prior art includes Japanese Patent Publication No. 2022-108493 and Korean Patent Publication No. 10-2020-0100887. Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the embodiment is to provide a packaging substrate using a glass substrate, in which signals are transmitted and received between photoelectric elements using the characteristics of the glass substrate that allows signals in the form of optical energy to pass through, and a packaging substrate using the same.

[0008] In addition, an object of the embodiment is to provide a method for manufacturing a packaging substrate in which signals in the form of optical energy are transmitted and received between photoelectric elements via a glass substrate, thereby reducing the space required for constructing an electrical connection structure and making the packaging substrate compact, and a packaging substrate using the same. [Means for solving the problem]

[0009] In order to achieve the above object, a packaging substrate according to one embodiment includes a glass substrate having a first surface and a second surface facing each other, a core layer including a cavity portion, an insulating layer formed on the first surface, and a light-transmitting portion formed on an upper surface of the insulating layer, a light-receiving portion is disposed in the cavity portion, the insulating layer includes a via penetrating in a thickness direction, and a portion of a bottom surface of the light-transmitting portion is in contact with the via.

[0010] A photo-energy signal output from the light-emitting unit may be transmitted to the light-receiving unit through the glass substrate.

[0011] The light energy signal may include visible light or infrared light.

[0012] The via width may be between 10 μm and 500 μm.

[0013] The vias may contain a vacuum or an inert gas.

[0014] The vias may contain air or a light-transmissive material.

[0015] The optically transparent material may have a thermal expansion coefficient of 10 to 24 ppm / °C.

[0016] The cavity may be formed in the form of a recessed surface that opens toward the second surface of the glass substrate and has a space in which a light receiving unit is disposed.

[0017] Meanwhile, in order to achieve the above object, a manufacturing method of a packaging substrate according to one embodiment includes the steps of: creating a cavity portion in a glass substrate having a first surface and a second surface facing each other; arranging a light receiving portion in the cavity portion; forming an insulating layer on the first surface; creating a via in the insulating layer; and stacking a light projecting portion on the insulating layer, and a portion of a bottom surface of the light projecting portion is in contact with the via.

[0018] A photo-energy signal output from the light-emitting unit may be transmitted to the light-receiving unit through the glass substrate.

[0019] The light energy signal may include visible light or infrared light.

[0020] The via width may be between 10 μm and 500 μm.

[0021] The vias may contain a vacuum or an inert gas.

[0022] The vias may contain air or a light-transmissive material.

[0023] The optically transparent material may have a thermal expansion coefficient of 10 to 24 ppm / °C.

[0024] The cavity may be formed in the form of a recessed surface that opens toward the second surface of the glass substrate and has a space in which a light receiving unit is disposed. Effect of the Invention

[0025] The packaging substrate manufacturing method and packaging substrate using the same of the embodiment utilize the characteristics of the glass substrate that transmits signals in the form of optical energy, thereby reducing the space required for an electrical connection structure between photoelectric elements, thereby enabling a packaging substrate including a photoelectric sensor to be manufactured in a compact manner.

[0026] Furthermore, by increasing the signal transmission amount of the photoelectric element in the same space compared to the conventional photoelectric sensor, the sensing efficiency and performance of the photoelectric sensor can be greatly improved in a small space. [Brief description of the drawings]

[0027] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 10(a) to 10(e) are flow charts illustrating a process of forming a core distribution layer in a cross section during a manufacturing process of a packaging substrate according to an embodiment. [Diagram 5] 10(a) to 10(e) are flow charts illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] 1A and 1B are diagrams illustrating an example of a packaging substrate including a conventional photoelectric sensor and a device including the same; [Figure 7] 1 is a conceptual diagram illustrating an example of a cross-sectional structure of a packaging substrate including a conventional photoelectric sensor. [Figure 8A] 1 illustrates an example of a cross-sectional structure of a packaging substrate produced according to an embodiment. [Figure 8B] 1 illustrates an example of a cross-sectional structure of a packaging substrate produced according to an embodiment. [Figure 8C] 1 illustrates an example of a cross-sectional structure of a packaging substrate produced according to an embodiment. [Figure 8D] 1 illustrates an example of a cross-sectional structure of a packaging substrate produced according to an embodiment. [Figure 9A] 13 is an example of a cross-sectional structure of a packaging substrate produced according to another embodiment. [Figure 9B] 13 is an example of a cross-sectional structure of a packaging substrate produced according to another embodiment. [Figure 9C] 13 is an example of a cross-sectional structure of a packaging substrate produced according to another embodiment. [Figure 9D] 13 is an example of a cross-sectional structure of a packaging substrate produced according to another embodiment. BEST MODE FOR CARRYING OUT THEINVENTION

[0028] The following detailed description is provided to facilitate a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalents of the method, device and / or system described herein will become apparent after the contents presented in this application are understood. For example, the order of operations described herein is merely exemplary and is not limited to the operations described herein. Except for steps that necessarily proceed in a certain order, the order of operations may be changed depending on the understanding of the contents presented in this application. In addition, the description of known features may be omitted to improve clarity and conciseness after the disclosure of this application is understood. However, the omission of such features and their descriptions is not intended to be an admission of common knowledge.

[0029] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein, but rather the embodiments described herein are provided to illustrate some of the many possible ways of implementing the methods, apparatus and / or systems described herein that will become apparent after reading the present disclosure.

[0030] As used herein, terms such as "first," "second," and "third" may be used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections to these words. Instead, such terms are used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in any embodiment described herein could also be a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0031] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "bonded" to another element, it may be described as being directly "on," "connected," or "bonded" to the other element, or there may be one or more intervening elements between them. In contrast, when an element is described as being "directly on," "directly connected," or "directly bonded," there may not be any other intervening elements between them. Similarly, expressions such as "between" and "directly between," and "adjacent" and "directly adjacent" may be interpreted as previously described.

[0032] The terms used herein are merely for describing particular examples and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any one or more combinations of the associated listed items. As used herein, the terms "comprises," "comprises," and "has" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the use of the term "can" in connection with an example or embodiment (e.g., what the example or embodiment can include or embody) means that there is at least one example or embodiment in which such feature is included or embodied, but not all examples are limited thereto.

[0033] In this application, "B is located on A" means that B is in direct contact with A or that B is disposed on A with another layer or structure therebetween, and therefore should not be construed as B being in direct contact with A.

[0034] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0035] In one or more of the above examples, the term "A and / or B" means "A, B, or A and B."

[0036] In one or more of the above examples, terms such as "first," "second," "A," or "B" are used to distinguish identical terms from one another.

[0037] In one or more of the above instances, the singular forms are to be construed as including the plural forms as well as the singular forms unless specifically stated otherwise.

[0038] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0039] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0040] The packaging substrate 20 according to one embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be disposed.

[0041] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0042] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0043] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0044] The core layer 22 may include a glass substrate 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness, a plurality of core vias 23 penetrating the glass substrate 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting a first surface 213 of the glass substrate 21 to a second surface 214 opposite the first surface via the core vias 23.

[0045] The second region 222 of the core layer 22 may serve as a cavity structure.

[0046] In the same area, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are generally parallel to each other, so that the glass substrate 21 has a constant thickness throughout.

[0047] An internal space 281 formed by the difference in thickness between the first section 221 and the second section 222 serves to accommodate a part or the whole of the cavity element 40 .

[0048] The glass substrate 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222, and may be formed at a desired pitch and pattern.

[0049] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0050] In the embodiment, to solve this problem, the glass substrate 21 is used as a support for the core layer 22. In addition, by using the glass substrate 21 and the core via 23 formed penetrating the glass substrate 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0051] The glass substrate 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0052] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0053] Specifically, the formation of the core via 23 may be achieved by forming a defect (scratch) on the surface of the glass substrate using a method such as a laser, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0054] The core vias 23 may be positioned in a number of 100 to 3000, 100 to 2500, or 225 to 1024 per unit area (1 cm×1 cm) of the glass substrate 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0055] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 that surrounds the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, and connects the upper and lower parts of the glass substrate over a relatively short distance, thereby allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0056] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0057] The cavity element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0058] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that surrounds the cavity distribution pattern.

[0059] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by the same process as the process of forming the core via 23, and the area and shape penetrating the glass substrate 21 may be different from those of the core via 23.

[0060] In this embodiment, an insulating layer may be formed in the cavity portion after the cavity element 40 is arranged in the cavity portion. That is, an insulating layer may be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0061] The core distribution pattern 241 may be patterned so as to be electrically connectable with the cavity element 40 .

[0062] The cavity element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0063] When an element such as a transistor that converts electrical signals between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, a transistor or the like is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0064] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0065] Meanwhile, the cavity element 40 may be applied by inserting passive elements such as capacitors individually, or an element group including a number of passive elements embedded between insulating layers (cavity element insulating layers) may be formed with electrodes exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex elements.

[0066] The glass substrate 21 acts as an intermediate or mediating role connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting these electrical signals, thereby ensuring smooth signal transmission. The core vias arranged in the first area 221 are referred to as first area core vias to distinguish them from the core vias in the second area 222 described below.

[0067] A top layer 26 is positioned on the first surface 213 .

[0068] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0069] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251, which is an electrically conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, embedded in the upper insulating layer 253. The upper distribution layers 25 arranged one above the other can be connected to each other through blind vias.

[0070] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0071] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0072] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0073] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer is formed, unnecessary parts of the insulating layer are removed, an electrically conductive layer is formed by a method such as copper plating, and an unnecessary part of the electrically conductive layer is selectively removed, an insulating layer is formed again on the electrically conductive layer, the unnecessary parts are removed again, and an electrically conductive layer is formed by a method such as plating, and the like. By repeating these methods, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern can be formed.

[0074] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval each of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0075] The upper connection layer 27 includes an upper connection pattern 272, at least a portion of which is electrically connected to the upper distribution pattern 251 and located on the upper insulating layer 253, and an upper connection electrode 271 that electrically connects the semiconductor device unit 30 and the upper connection pattern 272. The upper connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and when the upper connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer or the like may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by surface polishing, surface etching, or the like.

[0076] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0077] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0078] The cavity portion 28 is located above and / or below the second region 222 and includes a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the cavity element 40 is located. The cavity distribution layer 282 may be formed through a second region core via.

[0079] Specifically, the thickness of the glass substrate 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass substrate 21 serve as an electrical connection structure that connects the cavity element 40 to an external element.

[0080] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass substrate 21, rather than the second area 222, and a cavity element 40 may be arranged in the cavity portion.

[0081] The packaging substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 may be directly connected to a core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, or may be electrically connected to the motherboard 10 via a board connection part 52 such as a solder ball. The core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22. The element connection part 51 and the board connection part 52 are collectively referred to as a connection part 50.

[0082] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass substrate 21 .

[0083] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. This is understood to be applied in such a multi-layer form for at least two reasons. One is that there is a scale problem when directly bonding the fine pattern of the device to the motherboard, and the other is that there is a risk of damage to the wiring due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device. In the embodiment, this problem is solved by applying a glass substrate with a thermal expansion coefficient similar to that of the semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting the device on the first surface and the upper layer of the glass substrate.

[0084] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0085] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0086] First, as shown in (a) of FIG. 4, a glass substrate 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass substrate may be a glass substrate used for substrates of electronic devices, for example, but is not limited to, an alkali-free glass substrate. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or other methods.

[0087] 4(b), the glass substrate 21a having the defect (groove) 21b is subjected to an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass substrate forms a via in the defective portion, and the surface of the glass substrate 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied, but in consideration of the troublesome process of applying and removing the masking film, the glass substrate having the defect may itself be etched, and in this case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0088] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0089] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0090] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. In forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc., and in this case, the adhesion between the glass and the metal may be improved due to an anchor effect in which the surface morphology of the glass and the metal particles interact with each other.

[0091] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0092] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0093] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0094] FIG. 5 illustrates the manufacturing steps for forming an insulating layer and an upper distribution pattern according to one embodiment.

[0095] As shown in (a) of Fig. 5, the core via may undergo an insulating layer formation step in which an insulating layer is used to fill empty spaces after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be in the form of a film, and may be, for example, a method of vacuum laminating an insulating layer in the form of a film. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the empty spaces inside the core via, thereby forming a core insulating layer without the formation of voids.

[0096] 5(b)-(e) illustrate the top layer fabrication steps.

[0097] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film, and if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts the glass substrate at least in part, and therefore has sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic of satisfying an adhesion test value of 4B or more according to ASTM D3359.

[0098] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer, and in the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0099] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0100] The upper connection pattern and the upper connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon again, and then forming an etching layer of the electrically conductive layer, or by selectively forming only the electrically conductive layer without applying an etching method. The cover layer may be formed by forming openings (not shown) at positions corresponding to the upper connection electrodes to expose the upper connection electrodes and to allow direct connection to the element connection parts or terminals of the elements.

[0101] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0102] Meanwhile, as a specific example of the packaging substrate, a packaging substrate including a photo-electric sensor or an opto-electric sensor may be proposed.

[0103] The photoelectric sensor may be called a photo sensor or an image sensor. A photo sensor is an element that stores the amount of charge according to the intensity of light as information and outputs the stored information in response to an external control signal, and is widely used in X-ray detectors, scanners, digital copiers, fingerprint recognition systems, facsimiles, digital cameras, camcorders, PCS (Personal Communication Systems), game devices, security cameras, medical micro cameras, etc.

[0104] A conventional photosensor will be described below with reference to FIGS.

[0105] FIG. 6 is a diagram illustrating an example of a packaging substrate including a conventional photoelectric sensor and a device 900 including the same.

[0106] The device 900 may include a sensing unit 930 disposed on a support unit 910, and an optical fiber unit 950 connected to the sensing unit 930 and transmitting an optical signal. A packaging substrate including a light projecting unit and a light receiving unit, which will be described later, may be disposed in the sensing unit.

[0107] FIG. 7 is a conceptual diagram illustrating an example of a cross-sectional structure of a packaging substrate including a conventional photoelectric sensor.

[0108] 7, photo-electric components may be formed in a substrate 200. The substrate 200 has a first surface 200a and a second surface 200b, and a circuit element CX may be formed on the first surface 200a of the substrate 200. The circuit element CX may include a plurality of transistors (e.g., transfer transistors, reset transistors, drive transistors, and / or selection transistors) that transmit and amplify an electrical signal (e.g., photocharge) corresponding to incident light.

[0109] 7, first to fourth upper insulating films 210, 220, 230, and 240 may be formed on the circuit element CX. Vias VI and wiring IL may be formed in the first to fourth upper insulating films 210, 220, 230, and 240. A second insulating film 350b may be formed on the fourth upper insulating film 240.

[0110] The packaging substrate including the conventional photoelectric sensor as shown in FIG. 7 includes an electrically connected structure for transmitting and receiving signals between photoelectric elements. The electrically connected structure may refer to a plug, a through electrode, a through contact, or the like. The structure may include a circuit element CX of FIG. 7, an insulating film formed on the circuit element CX, and a via VI and a wiring IL formed in the insulating film. That is, the conventional photoelectric sensor requires space for forming an electrically connected structure for transmitting and receiving signals of the photoelectric elements, and therefore there is a limit to compactly manufacturing the photoelectric sensor and improving the spatial contrast sensing efficiency.

[0111] Therefore, the present specification proposes a packaging substrate including a photoelectric sensor using a glass substrate and a method for manufacturing the same. Specifically, an embodiment of the packaging substrate is proposed in which a signal of a photoelectric element can be transmitted and received in the form of optical energy through a glass substrate by using the characteristic that the glass substrate can transmit light. The packaging substrate manufacturing method and the packaging substrate using the same of the embodiment enable a packaging substrate including a photoelectric sensor to be manufactured in a compact manner. As a result, compared to a conventional photoelectric sensor, the signal transmission amount of the photoelectric element can be increased for the same space, and a photoelectric sensor having improved sensing efficiency and performance can be manufactured in a small space.

[0112] 8A to 8D are cross-sectional views of an example of a packaging substrate produced according to an embodiment. FIGs. 8A to 8D are conceptually simplified views for explaining a packaging substrate produced according to an embodiment, and the contents described with reference to FIGs. 1 to 5 may be applied.

[0113] For example, referring to FIG. 8A, a core layer of a packaging substrate produced according to an embodiment includes a glass substrate 21 having first and second surfaces facing each other.

[0114] The glass substrate 21 may include a cavity portion 28, which may be formed in the form of a recessed surface that is open to only one of the first and second surfaces. Alternatively, the cavity portion 28 may be recessed to open toward the first or second surface of the glass substrate 21, or may have a space penetrating the first and second surfaces in which an element is disposed.

[0115] The cavity portion 28 may be formed simultaneously through the same forming step as the core via, or may be formed independently after or before the core via is formed. Also, referring to Fig. 8A, a photo interface component 82 may be disposed in the cavity portion 28. An electrode 63 may be formed on the surface of the glass substrate 21.

[0116] Also, referring to FIG. 8A, the packaging substrate may include an insulating layer formed on a first surface of the glass substrate 21.

[0117] The insulating layer may be the upper insulating layer 253 described above. The insulating layer may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, and may be, for example, but is not limited to, an epoxy resin containing a filler. The insulating layer may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin.

[0118] For example, the insulating layer may include Ajinomoto Build-up Film (ABF). The insulating layer may be formed by forming a coating layer and curing it, or by laminating an insulating film that is in an uncured or semi-cured state onto the core layer and curing it.

[0119] 8A, at least one via VI may be formed in the insulating layer, and the width of the via VI formed in the insulating layer may be 10 μm to 500 μm.

[0120] For example, the via VI can be manufactured by ablating the insulating layer to a specific width using a laser or the like, and then removing the insulating layer using a laser or the like.

[0121] For example, the via VI formed in the insulating layer may be an empty space. For example, the via VI formed in the insulating layer may contain an inert gas or may be vacuum treated.

[0122] Alternatively, for example, the vias VI formed in the insulating layer may be filled with a light-transmitting material. The light-transmitting material may be transparent or may transmit a certain level or more of light of a specific wavelength applied as a signal. The light-transmitting material may be a light-transmitting organic material, a light-transmitting inorganic material, a light-transmitting composite material, etc., and may be, for example, polysilicon (poly-SiO2) and / or a transparent polymer.

[0123] For example, the optically transparent material may have a thermal expansion coefficient of 10 to 24 ppm / ° C. The optically transparent material may have a thermal expansion coefficient of 10 ppm / ° C. or more, 12 ppm / ° C. or more, or 15 ppm / ° C. or more. The optically transparent material may have a thermal expansion coefficient of 24 ppm / ° C. or less, 20 ppm / ° C. or less, or 18 ppm / ° C. or less.

[0124] Also, referring to FIG. 8A, a photo-electronic component may be laminated on the insulating layer.

[0125] The photoelectric element may refer to a light-projecting unit 81. For example, the light-projecting unit 81 may be formed on an upper surface of an insulating layer formed on the first surface. A portion of a bottom surface of the light-projecting unit 81 may contact the via VI formed in the insulating layer. The light-projecting unit 81 may be connected to the insulating layer via an element connecting unit 51 such as a solder ball. The light-projecting unit 81 may be connected to a connection electrode located on the insulating layer via an element connecting unit 51 such as a solder ball.

[0126] 8A, a signal in the form of light energy (photo-energy) output from the light-projecting unit 81 may be transmitted to the light-receiving unit 82 through the glass substrate 21. That is, a signal in the form of light energy output from the light-projecting unit 81 may be transmitted to the light-receiving unit 82 through the glass substrate 21. Also, for example, a signal in the form of light energy output from the light-projecting unit 81 may be transmitted to the light-receiving unit 82 by avoiding an electrode. Also, referring to FIG. 8A, a device connection unit 51 such as a solder ball may be formed on a bottom surface of the light-receiving unit 82. The light-receiving unit 82 may be connected to a connection electrode via the device connection unit 51.

[0127] 8B, for example, an element connection part 51 such as a solder ball may be formed on an upper surface of the light receiving part 82 in a core layer of a packaging substrate generated according to an embodiment. The light receiving part 82 may be connected to a connection electrode of a core via formed on a closed surface of the cavity part 28 of the glass substrate via the element connection part 51. For example, a signal in the form of optical energy output from the light emitting part 81 may be transmitted to the light receiving part 82 by avoiding an electrode.

[0128] 8C, the cavity portion 28 of the packaging substrate produced according to the embodiment may have a space in which a device is disposed, penetrating the first surface and the second surface of the glass substrate 21. Also, referring to FIG. 8C, device connection portions 51 such as solder balls may be formed on the top and bottom surfaces of the light receiving portion 82. The light receiving portion 82 may be connected to a connection electrode via the device connection portion 51. For example, a signal in the form of optical energy output from the light emitting portion 81 may be transmitted to the light receiving portion 82, bypassing an electrode.

[0129] The optical energy signal may include visible light or infrared light, and thus, by reducing the space required for electrically connecting the conventional photoelectric element, the packaging substrate may be manufactured compactly, and the spatial contrast sensing efficiency and performance of the photoelectric sensor may be improved.

[0130] Also, for example, referring to FIG. 8D, a core layer of a packaging substrate produced according to an embodiment may include a glass substrate 21 having first and second surfaces facing each other.

[0131] The glass substrate 21 may include a cavity portion 28, which may be formed in the form of a recessed surface that is open to only one of the first and second surfaces. Alternatively, the cavity portion 28 may be recessed to open toward the first or second surface of the glass substrate 21, or may have a space penetrating the first and second surfaces in which an element is disposed.

[0132] The cavity portion 28 may be formed simultaneously with the core via through the same forming step, or may be formed independently after or before the core via is formed. Also, referring to Fig. 8D, a photo interface component 82 may be disposed in the cavity portion 28. An electrode 63 may be formed on the surface of the glass substrate 21.

[0133] 8D, the packaging substrate may include an upper insulating layer 253 formed on a first surface of the glass substrate 21 and a lower insulating layer 254 formed on a second surface of the glass substrate 21. The insulating layer may include the upper insulating layer 253 and the lower insulating layer 254.

[0134] The insulating layer may be applied as an insulator layer for a semiconductor device or a packaging substrate, and may be, for example, but is not limited to, an epoxy resin containing a filler. The insulating layer may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin. For example, the insulating layer may include Ajinomoto Build-up Film (ABF). The insulating layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulating film that is made into a film in an uncured or semi-cured state on the core layer and curing it.

[0135] 8D, at least one via VI may be formed in the upper insulating layer 253 and / or the lower insulating layer 254. The width of the via VI formed in the upper insulating layer 253 and / or the lower insulating layer 254 may be 10 μm to 500 μm. For example, the via VI may be formed by ablating the upper insulating layer 253 and / or the lower insulating layer 254 to a specific width using a laser, etc., and then removing a portion of the upper insulating layer and / or the lower insulating layer using a laser. Alternatively, the via VI may be formed by removing a portion of the surface of the glass substrate 21 together with the insulating layer.

[0136] A specific description of the inside of the via VI formed in the insulating layer overlaps with the above description, so a detailed description will be omitted.

[0137] 8D, a photo-electronic component may be stacked on the upper insulating layer 253. The photo-electronic component may refer to a light-projecting unit 81. For example, the light-projecting unit 81 may be formed on an upper surface of the upper insulating layer 253. A portion of a bottom surface of the light-projecting unit 81 may contact the via formed in the upper insulating layer 253. The light-projecting unit 81 may be connected to the upper insulating layer 253 via an element connection unit 51 such as a solder ball.

[0138] Referring to FIG. 8D, a signal in the form of photo-energy output from the light-emitting unit 81 may be transmitted to the light-receiving unit 82 through the glass substrate 21 .

[0139] That is, a photo-energy signal output from the light-projecting unit 81 can be transmitted to the light-receiving unit 82 through the glass substrate 21. The description of the photo-energy signal overlaps with the above description, so a detailed description will be omitted.

[0140] Meanwhile, an embodiment in which the light-projecting unit 81 and the light-receiving unit 82 are arranged opposite to those shown in Fig. 8A may also be proposed. An embodiment in which the light-projecting unit 81 and the light-receiving unit 82 are arranged opposite to those shown in Fig. 8A will be described in detail with reference to Figs. 9A to 9D below.

[0141] 9A to 9D are examples of cross-sectional structures of a packaging substrate produced according to another embodiment. FIGs. 9A to 9D are conceptually simplified views for explaining a packaging substrate produced according to an embodiment, and the contents described with reference to FIGs. 1 to 5 may be applied.

[0142] For example, referring to FIGS. 9A to 9D, a core layer of a packaging substrate produced according to an embodiment may include a glass substrate 21 having first and second surfaces facing each other.

[0143] The glass substrate 21 may include a cavity portion 28, which may be formed in the form of a recessed surface that is open to only one of the first and second surfaces. Alternatively, the cavity portion 28 may be recessed to open toward the first or second surface of the glass substrate 21, or may have a space penetrating the first and second surfaces in which an element is disposed.

[0144] The cavity portion 28 may be formed simultaneously through the same forming step as the core via, or may be formed independently after or before the core via is formed. Referring to Figs. 9A to 9D, a light-emitting portion 81 may be disposed in the cavity portion 28. An electrode 63 may be formed on the surface of the glass substrate 21. Referring to Figs. 9A to 9D, a light-receiving portion 82 may be laminated on an insulating layer. For example, the light-receiving portion 82 may be formed on the upper surface of an insulating layer formed on the first surface. A part of the bottom surface of the light-receiving portion 82 may contact the via VI formed in the insulating layer. The light-receiving portion 82 may be connected to the insulating layer via an element connecting portion 51 such as a solder ball. The light-receiving portion 82 may be connected to a connection electrode located on the insulating layer via an element connecting portion 51 such as a solder ball.

[0145] 9A to 9D, a signal in the form of optical energy (photo-energy) output from the light-projecting unit 81 may be transmitted to the light-receiving unit 82 through the glass substrate 21. That is, a signal in the form of optical energy (photo-energy) output from the light-projecting unit 81 may be transmitted to the light-receiving unit 82 through the glass substrate 21. Also, for example, a signal in the form of optical energy output from the light-projecting unit 81 may be transmitted to the light-receiving unit 82 by avoiding an electrode.

[0146] 9A, an element connection part 51 such as a solder ball may be formed on a bottom surface of the light-projecting part 81. The light-projecting part 81 may be connected to a connection electrode via the element connection part 51.

[0147] 9B, for example, a device connection part 51 such as a solder ball may be formed on an upper surface of the light-projecting part 81 in a core layer of a packaging substrate generated according to an embodiment. The light-projecting part 81 may be connected to a connection electrode of a core via formed on a closed surface of the cavity part 28 of a glass substrate via the device connection part 51. For example, a signal in the form of optical energy output from the light-projecting part 81 may be transmitted to the light-receiving part 82, bypassing an electrode.

[0148] 9C, for example, the cavity portion 28 of the packaging substrate produced according to the embodiment may have a space in which a device is disposed, penetrating the first surface and the second surface of the glass substrate 21. Also, referring to FIG. 9C, device connection portions 51 such as solder balls may be formed on the upper and bottom surfaces of the light-projecting portion 81. The light-projecting portion 81 may be connected to a connection electrode via the device connection portion 51. For example, a signal in the form of optical energy output from the light-projecting portion 81 may be transmitted to the light-receiving portion 82, bypassing an electrode.

[0149] 9D, the packaging substrate may include an upper insulating layer 253 formed on a first surface of the glass substrate 21 and a lower insulating layer 254 formed on a second surface of the glass substrate 21. The insulating layer may include the upper insulating layer 253 and the lower insulating layer 254.

[0150] The insulating layer may be applied as an insulator layer for a semiconductor device or a packaging substrate, and may be, for example, but is not limited to, an epoxy resin containing a filler. The insulating layer may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin. For example, the insulating layer may include Ajinomoto Build-up Film (ABF). The insulating layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulating film that is made into a film in an uncured or semi-cured state on the core layer and curing it.

[0151] A specific description of the optical energy signal overlaps with the above description, so a detailed description will be omitted.

[0152] The present specification also proposes a manufacturing method for producing the packaging substrate according to the embodiment disclosed in Figures 8A to 8D and 9A to 9D. For example, the manufacturing method for producing the packaging substrate according to the embodiment of the present specification is as follows.

[0153] For example, a cavity portion 28 may be formed in a glass substrate 21 having a first surface and a second surface facing each other. The cavity portion 28 may be formed in the form of a recessed surface in which only one of the first surface and the second surface is open. The cavity portion 28 may be formed in the form of a recessed surface in which only one of the first surface and the second surface is open, and may have a space in which an element is disposed. Alternatively, the cavity portion 28 may be recessed to open toward the first surface or the second surface of the glass substrate 21, or may penetrate the first surface and the second surface to have a space in which an element is disposed.

[0154] Then, a photo interface component 82 or a photo projection component 81 can be disposed in the cavity portion 28 .

[0155] Next, an insulating layer may be formed on the first surface. For example, a glass substrate 21 having an insulating layer formed on the first surface may be provided. For example, a process of laminating an insulating layer on the first surface (lamination on top) may be performed. Alternatively, an insulating layer may be formed on the first surface and the second surface. For example, a glass substrate 21 having an upper insulating layer formed on the first surface and a lower insulating layer formed on the second surface may be provided. For example, a process of laminating an insulating layer on the first surface and the second surface may be performed. Here, for example, the light receiving unit 82 or the light projecting unit 81 may be connected to the lower insulating layer via an element connecting unit 51 such as a solder ball. For example, the insulating layer may include an insulating mixture, and the insulating mixture may include inorganic particles and a polymer resin. For example, the insulating layer may include the above-mentioned ABF (Ajinomoto Build-up Film).

[0156] Next, vias VI may be generated in the insulating layer. For example, the insulating layer formed on the first surface may be ablated to a specific width using a laser or the like, and the glass substrate 21 may be cut using a laser or a dicing saw to generate vias VI in the insulating layer. The width of the vias VI generated in the insulating layer may be 10 μm to 500 μm. Alternatively, for example, the upper insulating layer may be ablated to a specific width using a laser or the like, and the glass substrate 21 may be cut using a laser to generate vias VI in the upper insulating layer, and the lower insulating layer may be ablated to a specific width using a laser or the like, and the glass substrate 21 may be cut using a laser to generate vias VI in the lower insulating layer. The width of the vias VI generated in the upper insulating layer 253 and the lower insulating layer 254 may be 10 μm to 500 μm.

[0157] A specific description of the inside of the via VI formed in the insulating layer overlaps with the above description, so a detailed description will be omitted.

[0158] Next, the light-transmitting section 81 or the light-receiving section 82 may be laminated on the insulating layer. For example, the light-transmitting section 81 or the light-receiving section 82 may be laminated on the insulating layer formed on the first surface. For example, the light-transmitting section 81 or the light-receiving section 82 may be laminated on the upper insulating layer formed on the first surface. That is, for example, the light-transmitting section 81 or the light-receiving section 82 may be formed on the upper surface of the insulating layer formed on the first surface. The light-transmitting section 81 may include a photo-electric component. A part of the bottom surface of the light-transmitting section 81 or the light-receiving section 82 may be in contact with the via VI formed in the insulating layer (or, for example, the upper insulating layer). The light-transmitting section 81 or the light-receiving section 82 may be connected to the insulating layer via an element connection section 51 such as a solder ball.

[0159] For example, a signal in the form of light energy (photo-energy) output from the light-projecting unit 81 may pass through the glass substrate 21 and be transmitted to the light-receiving unit 82. That is, a light energy (photo-energy) signal output from the light-projecting unit 81 may pass through the glass substrate 21 and be transmitted to the light-receiving unit 82. The light energy signal may include visible light or infrared light.

[0160] The packaging substrate manufacturing method according to the above-described embodiments and the packaging substrate using the same may reduce the space required for a conventional structure for electrically connecting a photoelectric element, thereby enabling the packaging substrate to be manufactured compactly and providing the effect of improving the spatial contrast sensing efficiency and performance of the photoelectric sensor.

[0161] The above description of the present specification has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and a person having ordinary skill in the art will understand that various modifications and variations of the embodiments are possible. In other words, the scope of the present specification is not limited to the above-mentioned embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the accompanying claims also belong to the scope of the embodiments. Therefore, the true technical scope of protection of the present specification must be determined by the technical ideas of the accompanying claims. [Explanation of symbols]

[0162] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21, 21a Glass substrate 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 254 Lower Insulation Layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 281 Interior Space 282 Cavity Distribution Layer 40 Cavity element 50 Connection 51 Element connection part 52 Board connection 81 Light projector 82 Light receiving part

Claims

1. a core layer including a glass substrate having a first surface and a second surface opposed to each other, and a cavity portion; An insulating layer formed on the first surface; a light projecting portion formed on an upper surface of the insulating layer, A light receiving portion is disposed in the cavity portion, the insulating layer includes a via penetrating in a thickness direction; A packaging substrate, wherein a portion of a bottom surface of the light projecting portion is in contact with the via.

2. 2. The packaging substrate of claim 1, wherein a photo-energy signal output from the light-emitting portion is transmitted to the light-receiving portion through the glass substrate.

3. The packaging substrate of claim 2 , wherein the light energy signal comprises visible light or infrared light.

4. The packaging substrate of claim 1 , wherein the via has a width of 10 μm to 500 μm.

5. The packaging substrate of claim 1 , wherein the vias contain a vacuum or an inert gas.

6. the via comprises an optically transparent material; 2. The packaging substrate according to claim 1, wherein the optically transparent material has a thermal expansion coefficient of 10 to 24 ppm / .degree.

7. The packaging substrate of claim 1 , wherein the cavity portion is formed in the form of a recessed surface that opens toward the second surface of the glass substrate and has a space in which a light receiving portion is disposed.

8. A method for manufacturing a packaging substrate, comprising: Producing a cavity portion in a glass substrate having a first surface and a second surface opposed to each other; disposing a light receiving portion in the cavity portion; forming an insulating layer on the first surface; creating a via in the insulating layer; and laminating a light projecting portion on the insulating layer, A part of a bottom surface of the light projecting portion is in contact with the via.

9. 9. The method of claim 8, wherein a photo-energy signal output from the light-emitting part is transmitted to the light-receiving part through the glass substrate.

10. The method for manufacturing a packaging substrate according to claim 9 , wherein the light energy signal comprises visible light or infrared light.

Images