Voltage regulator

Abstract

To provide a voltage regulator that can suppress an excessive voltage from occurring at an output terminal when a voltage adjusting terminal is earthed.SOLUTION: A voltage regulator (100) comprises: an output transistor (14) that outputs an output voltage VOUT to an output terminal (3); dividing resistors (12, 13) that divide an adjusting voltage VADJ input to a voltage adjusting terminal (4), and output a feedback voltage Vfb; a first reference voltage circuit (11) that outputs a first reference voltage Vref; an error amplifier circuit (10) that controls a gate voltage of the output transistor (14) based on the first reference voltage Vref and the feedback voltage Vfb; and an earth protection circuit (20) that raises the feedback voltage Vfb to the first reference voltage Vref when the earth protection circuit monitors the adjusting voltage VADJ to detect that the voltage adjusting terminal (4) is earthed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a voltage regulator. [Background technology]

[0002] In general, a voltage regulator generates a constant voltage from a power supply voltage input to an input terminal, outputs a constant voltage to an output terminal, and maintains the output voltage at a constant value even if the power supply voltage or load current fluctuates.The voltage regulator is equipped with an overcurrent protection circuit that controls an output transistor to turn off when an excessive current flows through the output terminal, such as when the output terminal has a ground fault (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-169503 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a voltage adjustment terminal for adjusting the output voltage is provided in addition to the output terminal, in the overcurrent protection circuit of a conventional voltage regulator, it is difficult to prevent an excessive voltage from occurring at the output terminal when a dividing resistor connected to the voltage adjustment terminal has a ground fault.

[0005] In consideration of the above-mentioned circumstances, an object of the present invention is to provide a voltage regulator capable of suppressing an excessive voltage from occurring at an output terminal when a voltage adjustment terminal has a ground fault. [Means for solving the problem]

[0006] A voltage regulator according to an embodiment of the present invention is characterized by comprising an output transistor that outputs an output voltage to an output terminal, a dividing resistor that divides an regulated voltage input to a voltage adjustment terminal and outputs a feedback voltage, a first reference voltage circuit that outputs a first reference voltage, an error amplifier circuit that controls the gate voltage of the output transistor based on the first reference voltage and the feedback voltage, and a ground fault protection circuit that monitors the regulated voltage and increases the feedback voltage to the first reference voltage when it detects a ground fault at the voltage adjustment terminal. Effect of the Invention

[0007] According to the present invention, a voltage regulator is provided that is equipped with a ground fault protection circuit that monitors the regulated voltage and raises the feedback voltage to a first reference voltage when it detects that the voltage adjustment terminal has a ground fault. This makes it possible to provide a voltage regulator that can prevent excessive voltage from being generated at the output terminal when the voltage adjustment terminal has a ground fault. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating an example of a voltage regulator according to an embodiment of the present invention. [Diagram 2] 1 is a circuit diagram showing an example of a ground fault protection circuit according to an embodiment of the present invention; [Diagram 3] FIG. 4 is a circuit diagram showing another example of the ground fault protection circuit of the present embodiment. [Figure 4] FIG. 4 is a circuit diagram showing another example of the ground fault protection circuit of the present embodiment. [Diagram 5] FIG. 4 is a circuit diagram showing another example of the ground fault protection circuit of the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A voltage regulator according to an embodiment of the present invention will now be described with reference to the drawings.

[0010] FIG. 1 is a circuit diagram of a voltage regulator 100, which is an example of a voltage regulator according to an embodiment of the present invention.

[0011] The voltage regulator 100 includes an input terminal 1, a ground terminal 2, an output terminal 3, a voltage adjustment terminal 4, an error amplifier circuit 10, a reference voltage circuit 11, resistors 12 and 13 which are dividing resistors, an output transistor 14, and a ground fault protection circuit 20.

[0012] The ground fault protection circuit 20 includes a comparison circuit 21, a PMOS transistor 22, and a reference voltage circuit .

[0013] The output transistor 14 has a source connected to the input terminal 1, a drain connected to the output terminal 3, and a gate connected to the output terminal of the error amplifier circuit 10. The error amplifier circuit 10 has an inverting input terminal (-) connected to the output terminal of the reference voltage circuit 11, and a non-inverting input terminal (+) connected to the connection point of resistors 12 and 13. Resistors 12 and 13 are connected in series between the voltage adjustment terminal 4 and the ground terminal 2.

[0014] The ground fault protection circuit 20 is connected as follows.

[0015] The comparator circuit 21 has a power supply terminal connected to the output terminal 3, a non-inverting input terminal + connected to the voltage adjustment terminal 4, an inverting input terminal − connected to the output terminal of the reference voltage circuit 23, and an output terminal connected to the gate of the PMOS transistor 22. The PMOS transistor 22 has a source connected to the output terminal 3 and a drain connected to the non-inverting input terminal + of the error amplifier circuit 10.

[0016] The connection point of resistors Ra and Rb, which are dividing resistors, is connected to the voltage adjustment terminal 4. That is, the voltage regulator 100 can arbitrarily adjust the output voltage Vout by the external resistors Ra and Rb. A load LD is connected to the output terminal 3.

[0017] The operation of the voltage regulator 100 will now be described.

[0018] The voltage regulator 100 generates a constant voltage from a voltage VIN input to an input terminal 1, and outputs it as an output voltage VOUT from an output terminal 3. Resistors 12 and 13 generate a feedback voltage Vfb from an adjustment voltage VADJ input from a voltage adjustment terminal 4. The error amplifier circuit 10 controls the gate voltage of the output transistor 14 based on a reference voltage Vref output by a reference voltage circuit 11 and the feedback voltage Vfb. That is, the output voltage VOUT of the voltage regulator 100 is controlled to a voltage at which the feedback voltage Vfb is equal to the reference voltage Vref.

[0019] If the voltage adjustment terminal 4 is grounded for some reason, the adjustment voltage VADJ, i.e., the feedback voltage Vfb, drops to the voltage of the ground terminal 2. When the feedback voltage Vfb drops and becomes lower than the reference voltage Vref, the error amplifier circuit 10 lowers the output voltage. Therefore, the gate voltage of the output transistor 14 drops, and the output voltage VOUT of the voltage regulator 100 becomes higher than the desired voltage. At this time, since the resistor Ra is connected to the output terminal 3, no overcurrent flows to the output terminal 3. In other words, even if an overcurrent protection circuit is provided, the rise in the output voltage VOUT cannot be suppressed.

[0020] Next, the operation of the ground fault protection circuit 20 when a ground fault occurs at the voltage adjustment terminal 4 will be described.

[0021] When the voltage adjustment terminal 4 is shorted to ground, the adjustment voltage VADJ and the feedback voltage Vfb drop to the voltage of the ground terminal 2. The error amplifier circuit 10 controls the gate voltage of the output transistor 14 to decrease, thereby increasing the output voltage VOUT.

[0022] When the adjustment voltage VADJ input to the non-inverting input terminal + of the comparison circuit 21 falls below the reference voltage V1 of the reference voltage circuit 23 input to the inverting input terminal -, the voltage at the output terminal of the comparison circuit 21 drops. The PMOS transistor 22 turns on because its gate voltage drops. Since the source of the PMOS transistor 22 is connected to the output terminal 3, the feedback voltage Vfb rises.

[0023] Therefore, when the feedback voltage Vfb input to the non-inverting input terminal + rises and becomes higher than the reference voltage Vref input to the inverting input terminal -, the error amplifier circuit 10 controls the gate voltage of the output transistor 14 to rise so that the output voltage VOUT decreases.

[0024] At this time, the feedback voltage Vfb is generated by the current of the PMOS transistor 22 flowing through the parallel-connected resistors 12 and 13. Therefore, the output voltage VOUT stabilizes at a voltage lower than the desired voltage at which the feedback voltage Vfb becomes equal to the reference voltage Vref. In this way, the ground fault protection circuit 20 prevents the output voltage VOUT from becoming higher than the desired voltage when the voltage adjustment terminal 4 is grounded.

[0025] Furthermore, the ground fault protection circuit 20 does not interfere with the operation of the voltage regulator 100 during normal operation.

[0026] First, both the output voltage VOUT and the adjustment voltage VADJ are low before the start-up of the voltage regulator 100. The PMOS transistor 22 does not turn on because its source is the output voltage VOUT.

[0027] Next, when the voltage regulator 100 starts up, the adjustment voltage VADJ also rises together with the rise in the output voltage VOUT, so that the PMOS transistor 22 does not turn on.

[0028] FIG. 2 is a circuit diagram showing an example of the ground fault protection circuit 20 of the present embodiment.

[0029] 2 uses a comparator having two PMOS transistors, two NMOS transistors, and a current source as comparison circuit 21. Because reference voltage V1 for detecting a ground fault at voltage adjustment terminal 4 is set to a low voltage, it is desirable to configure the two NMOS transistors as depletion type. In this ground fault protection circuit 20, PMOS transistor 22 is on / off controlled by the comparator, i.e., it operates as a switch.

[0030] FIG. 3 is a circuit diagram showing another example of the ground fault protection circuit 20 of the present embodiment.

[0031] 3, the comparison circuit 21a is composed of a PMOS transistor and two NMOS transistors, and the reference voltage circuit 23a is composed of a constant current source and a resistor. In the reference voltage circuit 23a, a reference voltage V1 is generated across a resistor. The PMOS transistor of this comparison circuit 21a forms a current mirror circuit together with the PMOS transistor 22. Therefore, when the PMOS transistor 22 is turned on, a current corresponding to the current of the PMOS transistor flows, thereby increasing the feedback voltage Vfb.

[0032] FIG. 4 is a circuit diagram showing another example of the ground fault protection circuit 20 of the present embodiment.

[0033] The ground fault protection circuit 20 in Fig. 4 is provided with a diode 24, which is a reverse current prevention element, at the drain of the PMOS transistor 22 in the ground fault protection circuit 20 in Fig. 3. The diode 24 has an anode connected to the drain of the PMOS transistor 22 and a cathode connected to the non-inverting input terminal + of the error amplifier circuit 10.

[0034] The diode 24 is effective in preventing current from flowing from the junction of the resistors 12 and 13 to the output terminal 3 through the parasitic diode of the PMOS transistor 22 .

[0035] FIG. 5 is a circuit diagram showing another example of the ground fault protection circuit 20 of the present embodiment.

[0036] The ground fault protection circuit 20 of FIG. 5 is different from the ground fault protection circuit 20 of FIG. 3 in that a current source 25, which is a pull-up element, is provided between the output terminal 3 and the gate of the PMOS transistor 22.

[0037] The current source 25 is effective in preventing leakage current of the PMOS transistor 22 from flowing to the connection point between the resistors 12 and 13 during normal operation.

[0038] As described above, according to the voltage regulator 100 of this embodiment, the voltage adjustment terminal 4 is provided with the ground fault protection circuit 20, so that even if a ground fault occurs at the voltage adjustment terminal 4, the generation of an excessive voltage at the output terminal 3 of the voltage regulator 100 can be suppressed.

[0039] The present invention is not limited to the above-described embodiment, but can be embodied in various forms. Various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. These embodiments and modifications are included within the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0040] 1 Input terminal 2 Ground terminal 3 Output terminal 4 Voltage adjustment terminal 10 Error amplifier circuit 11, 23 Reference voltage circuit 12, 13 resistance (divided resistance) 14 Output transistor 20 Earth fault protection circuit 21 Comparison circuit 22 PMOS transistor 24 Diode (reverse current prevention element) 25 Constant current source (pull-up element) 100 Voltage Regulator

Claims

1. an output transistor that outputs an output voltage to an output terminal; A dividing resistor that divides an adjusted voltage input to a voltage adjustment terminal and outputs a feedback voltage; a first reference voltage circuit that outputs a first reference voltage; an error amplifier circuit for controlling a gate voltage of the output transistor based on the first reference voltage and the feedback voltage; a ground fault protection circuit that monitors the regulated voltage and increases the feedback voltage to the first reference voltage when it detects that the voltage regulation terminal has a ground fault; A voltage regulator comprising:

2. The ground fault protection circuit includes: a comparison circuit for comparing the regulated voltage with a second reference voltage; a first MOS transistor having a source connected to an output terminal, a drain connected to the output terminal of the dividing resistor, and a gate connected to the output terminal of the comparison circuit; 2. The voltage regulator according to claim 1, comprising:

3. The comparison circuit includes: Comparator 3. The voltage regulator according to claim 2, wherein the voltage regulator comprises:

4. The ground fault protection circuit includes: a second reference voltage circuit including a current source and a resistor connected in series between the input terminal and a ground terminal; a comparison circuit including a second MOS transistor provided between the current source and the resistor, the drain and gate of which are connected, a third MOS transistor, the gate of which is connected to the gate of the second MOS transistor, and a fourth MOS transistor, the drain of which is connected to the gate and drain of the third MOS transistor, the comparison circuit comparing the adjustment voltage with the second reference voltage; a first MOS transistor having a source connected to an output terminal, a drain connected to the output terminal of the dividing resistor, and a gate connected to a gate of the fourth MOS transistor of the comparison circuit; 2. The voltage regulator according to claim 1, comprising:

5. The ground fault protection circuit includes: A backflow prevention element is provided at the drain of the first MOS transistor.

5. The voltage regulator according to claim 4,

6. The ground fault protection circuit includes: A pull-up element is provided on the gate of the first MOS transistor.

6. The voltage regulator according to claim 4, wherein:

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