Switching power supply control device, switching power device, and electrical device

Abstract

To provide a switching power supply control device, a switching power device, and an electrical device to reduce overshoot of an output voltage and to shorten the time it takes for the output voltage to return to a target value when an overshoot occurs.SOLUTION: A switching power supply control device (2) is configured to control a first switching element (M1) and a second switching element (M2) connected in series with the first switching element and provided on a lower potential side than the first switching element. The switching power supply control device includes a control unit (CD) configured to inhibit turn-on of the first switching element if a feedback voltage based on an output voltage is larger than a threshold value at a first timing coming at a constant cycle, to turn off the second switching element, then, to turn on the second switching element if the feedback voltage is larger than the threshold value at the first timing coming after a predetermined number of cycles, and to release the inhibition of turning on the first switching element if the feedback voltage is smaller than the threshold value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a switching power supply control device, a switching power supply device, and an electric device. [Background technology]

[0002] The switching power supply device disclosed in Patent Document 1 detects by a light load detection comparator that the output voltage is higher than a set value (target value) by a predetermined value or more. The light load detection comparator has a hysteresis setting.

[0003] In the switching power supply device disclosed in Patent Document 1, after the light load detection comparator detects that the output voltage is higher than the set value (target value) by a predetermined value or more, switching operation is stopped until the level of the signal output from the light load detection comparator is switched. By such control, the switching power supply device disclosed in Patent Document 1 can reduce overshoot of the output voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-221099 A

[0005] [overview] However, the switching power supply device disclosed in Patent Document 1 has a problem in that the circuit area increases due to the provision of the light load detection comparator.

[0006] Furthermore, the switching power supply device disclosed in Patent Document 1 has a problem in that the amount of overshoot of the output voltage varies depending on the accuracy of the light load detection comparator.

[0007] Furthermore, in the switching power supply device disclosed in Patent Document 1, after the light load detection comparator detects that the output voltage is higher than the set value (target value) by a predetermined value or more, the connection node between the high-side switching element and the low-side switching element maintains a high impedance state until the level of the signal output from the light load detection comparator is switched. Therefore, in the switching power supply device disclosed in Patent Document 1, the time it takes for the output voltage to fall to the set value (target value) after an output voltage overshoot occurs depends on the load current. In other words, the switching power supply device disclosed in Patent Document 1 has a problem that when the load current is small, it takes a long time for the output voltage to fall to the set value (target value) after an output voltage overshoot occurs.

[0008] The switching power supply control device disclosed in this specification is a switching power supply control device configured to control a first switching element and a second switching element connected in series to the first switching element and arranged on a lower potential side than the first switching element, and includes a control unit configured to prohibit turn-on of the first switching element and turn-off the second switching element if a feedback voltage based on an output voltage is greater than a threshold value at a first timing that arrives at a constant cycle, to prohibit turn-on of the first switching element at the first timing, to turn on the second switching element if the feedback voltage is greater than the threshold value at the first timing that arrives a predetermined number of times after turning off the second switching element, and to lift the prohibition of turn-on of the first switching element if the feedback voltage is smaller than the threshold value.

[0009] The switching power supply device disclosed in this specification includes a switching power supply control device having the above configuration, the first switching element, and the second switching element.

[0010] The electrical device disclosed in this specification includes a switching power supply device having the above-described configuration. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a switching power supply device according to an embodiment. [Diagram 2] FIG. 2 is an external perspective view of the power supply IC according to the embodiment. [Diagram 3] FIG. 3 is a waveform diagram of a clock signal. [Figure 4] FIG. 4 is a waveform diagram of the clock signal, the comparison result signal, and the control signal. [Diagram 5] FIG. 5 is a state machine diagram showing the transition of the operating states of the switching power supply device. [Figure 6] FIG. 6 is a waveform diagram of the switch voltage, the output current, and the output voltage. [Figure 7] FIG. 7 is a state machine diagram showing the transition of operating states including the overshoot reduction control of the switching power supply device. [Figure 8] FIG. 8 is a diagram showing a modified example of the power supply IC. [Figure 9] FIG. 9 is a schematic block diagram of a car navigation device.

[0012] [Detailed Description] In this specification, MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) refers to a field effect transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0013] Fig. 1 is an overall configuration diagram of a switching power supply device 1 according to an embodiment. The switching power supply device 1 in Fig. 1 includes a power supply IC (Integrated Circuit) 2, which is a switching power supply control device, and a plurality of discrete components externally connected to the power supply IC 2. The plurality of discrete components provided in the switching power supply device 1 include an output inductor L0, an output capacitor C0, and feedback resistors R1 and R2. The switching power supply device 1 is configured to receive an externally supplied input voltage V IN More desired output voltage V OUT The output terminal OUT has an output voltage V OUT That is, the output terminal OUT is the output voltage V OUT The application terminal (output voltage V OUT The output voltage V OUT is supplied to a load LD connected to the output terminal OUT.

[0014] Input voltage V IN and the output voltage V OUT is a positive DC voltage, and the output voltage V OUT is the input voltage V IN For example, the input voltage V IN is 12V, the output voltage V can be set to a desired positive voltage value less than 12V (e.g., 3.3V or 5V) by adjusting the resistance of the feedback resistors R1 and R2. OUT The current supplied to the load LD via the output terminal OUT can be stabilized as the output current I OUT The output current I OUT can also be referred to as the load current.

[0015] Figure 2 shows an external perspective view of power supply IC2. Power supply IC2 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) that houses the semiconductor chip, and a number of external terminals that are exposed from the case to the outside of power supply IC2. Power supply IC2 is formed by sealing the semiconductor chip in a case (package) made of resin. Note that the number of external terminals of power supply IC2 and the type of case for power supply IC2 shown in Figure 2 are merely examples, and can be designed as desired.

[0016] In FIG. 1, only the input terminal IN, the switch terminal SW, the ground terminal GND, and the feedback terminal FB are shown as some of the multiple external terminals provided in the power supply IC2, but other external terminals (e.g., an enable terminal, a power good terminal, and a boot terminal) are also provided in the power supply IC2.

[0017] The external configuration of the power supply IC2 is explained. The input voltage V IN is supplied to the input terminal IN. An output inductor L0 is connected in series between the switch terminal SW and the output terminal OUT. That is, one end of the output inductor L0 is connected to the switch terminal SW, and the other end of the output inductor L0 is connected to the output terminal OUT. The output terminal OUT is connected to ground via an output capacitor C0. Furthermore, the output terminal OUT is connected to one end of a feedback resistor R1, and the other end of the feedback resistor R1 is connected to ground via a feedback resistor R2. The connection node between the feedback resistors R1 and R2 is connected to a feedback terminal FB. The ground terminal GND is connected to ground. The current flowing through the output inductor L0 is referred to as the inductor current I L The inductor current I flows from the switch terminal SW to the output terminal OUT. L has positive polarity, and the inductor current I L has negative polarity.

[0018] The following describes the internal configuration of the power supply IC 2. The power supply IC 2 includes an output stage circuit MM, an error amplifier 11, a phase compensation circuit 12, a slope voltage generation circuit 13, a comparator 14, a clock signal generation circuit 15, a logic circuit 16, a drive circuit 17, and a backflow detection circuit 18.

[0019] The output stage circuit MM includes transistors M1 and M2 configured as N-channel MOSFETs. The transistors M1 and M2 are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, ground). The transistors M1 and M2 are switched to generate an input voltage V IN is switched, and a square-wave switch voltage V SW The transistor M1 is provided on the higher potential side than the transistor M2. In other words, the transistor M2 is provided on the lower potential side than the transistor M1. Specifically, the drain of the transistor M1 is connected to the input voltage V IN It is connected to the input terminal IN, which is the application terminal of the input voltage V IN The source of the transistor M1 and the drain of the transistor M2 are commonly connected to a switch terminal SW. The source of the transistor M2 is connected to ground. However, a resistor for current detection may be inserted between the source of the transistor M2 and ground in some cases.

[0020] The transistor M1 functions as an output transistor, and the transistor M2 functions as a synchronous rectifier transistor. Hereinafter, the transistor M1 will be referred to as the output transistor, and the transistor M2 will be referred to as the synchronous rectifier transistor M2, as appropriate. The output inductor L0 and the output capacitor C0 are connected to a switch terminal SW and a square-wave-shaped switch voltage V SW is rectified and smoothed to produce the output voltage V OUT The feedback resistors R1 and R2 form a rectifying and smoothing circuit 3 that generates an output voltage V OUT By dividing the output voltage V OUT Feedback voltage V according to FBThe connection node between the feedback resistors R1 and R2 is connected to the feedback terminal FB to form a feedback voltage V FB is input to the feedback terminal FB.

[0021] Gate signals G1 and G2 are supplied to the gates of the transistors M1 and M2 as drive signals, respectively, and the transistors M1 and M2 are turned on and off according to the gate signals G1 and G2. When the gate signal G1 is at a high level, the transistor M1 is turned on, and when the gate signal G1 is at a low level, the transistor M1 is turned off. Similarly, when the gate signal G2 is at a high level, the transistor M2 is turned on, and when the gate signal G2 is at a low level, the transistor M2 is turned off. Basically, the transistors M1 and M2 are turned on and off alternately, but both the transistors M1 and M2 may be maintained in an off state. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a Hi-Z state (high impedance state). The Hi-Z state may also be referred to as an output off state. In the output high state, the transistors M1 and M2 are in an on state and an off state, respectively. In the output low state, the transistors M1 and M2 are in the off state and the on state, respectively. In the Hi-Z state, the transistors M1 and M2 are both in the off state. The transistors M1 and M2 are never both in the on state.

[0022] The power supply IC2 has a feedback voltage V FB Based on this, the on / off states of the transistors M1 and M2 are controlled by controlling the levels of the gate signals G1 and G2, respectively, so that a feedback voltage V FB Output voltage V according to OUT Causes the following to occur.

[0023] Although not shown in the figure, the power supply IC2 has an input voltage V INAn internal power supply circuit is provided that generates an internal power supply voltage based on the internal power supply voltage Vcc, and each circuit in the power supply IC2 is driven based on the internal power supply voltage. The gate signal G2 is a signal based on the ground potential, while the gate signal G1 is a signal based on the potential of the switch terminal SW. A low-level gate signal G1 has the potential of the switch terminal SW, and a high-level gate signal G1 is a predetermined voltage higher than the potential of the switch terminal SW. The predetermined voltage here is higher than the gate threshold voltage of the transistor M1. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal G1.

[0024] The error amplifier 11 is a current output type transconductance amplifier. The error amplifier 11 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 11 is connected to a feedback terminal FB and outputs a feedback voltage V FB The non-inverting input terminal of the error amplifier 11 receives a predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the power supply IC 2. The output terminal of the error amplifier 11 is connected to a wiring WR11.

[0025] The error amplifier 11 outputs the feedback voltage V FB and the reference voltage V REF The feedback voltage V FB and the reference voltage V REF Error voltage V according to the difference between ERR The charge generated by the current signal I11 is input to and output from the wire WR11. Specifically, the error amplifier 11 generates a feedback voltage V FB is the reference voltage V REF When the voltage of the feedback voltage V FB is the reference voltage V REFWhen the feedback voltage V is higher than 1 V, a current is drawn from the wire WR11 to the error amplifier 11 by the current signal I11 so that the potential of the wire WR11 decreases. FB and the reference voltage V REF As the absolute value of the difference between increases, the magnitude of the current due to current signal I11 also increases.

[0026] In addition, when the power supply IC2 starts up, the reference voltage V REF A soft-start voltage may be generated in the power supply IC2, which gradually rises to a voltage above the reference voltage V. In this case, the error amplifier 11 REF The lower voltage between the feedback voltage V FB In this embodiment, the soft start voltage is compared with the reference voltage V REF In the following, the existence of the soft-start voltage is ignored.

[0027] The phase compensation circuit 12 is provided between the wiring WR11 and the ground, and receives the current signal I11 to generate an error voltage V ERR The phase compensation circuit 12 has a series circuit of a resistor 12a and a capacitor 12b. Specifically, one end of the resistor 12a is connected to a wiring WR11, the other end of the resistor 12a is connected to one end of the capacitor 12b, and the other end of the capacitor 12b is connected to ground. By appropriately setting the resistance value of the resistor 12a and the capacitance value of the capacitor 12b, the error voltage V ERR The phase of the output feedback loop can be compensated to prevent oscillation.

[0028] The slope voltage generating circuit 13 generates a slope voltage V SLP Generates and outputs the slope voltage V SLP is a sawtooth waveform voltage synchronized with the clock signal S1.

[0029] Comparator 14 includes an inverting input terminal that receives voltage V1, a non-inverting input terminal that receives voltage V2, and an output terminal. Voltage V1 is the first comparison voltage, and voltage V2 is the second comparison voltage. Comparator 14 compares voltages V1 and V2 and outputs a signal S2 (hereinafter referred to as the comparison result signal S2) indicating the comparison result from its output terminal. The comparison result signal S2 is a binary signal having a high-level or low-level signal level. Comparator 14 outputs a high-level comparison result signal S2 when "V2 > V1" holds (i.e., when voltage V2 is higher than voltage V1), and outputs a low-level comparison result signal S2 when "V2 < V1" holds (i.e., when voltage V1 is higher than voltage V2). When "V2 = V1" holds, the comparison result signal S2 becomes high-level or low-level.

[0030] In power supply IC2, error voltage V ERR functions as voltage V1. That is, the inverting input terminal of comparator 14 is connected to wiring WR11 to receive error voltage V ERR as voltage V1. In power supply IC2, slope voltage V SLP functions as voltage V2. That is, the non-inverting input terminal of comparator 14 receives slope voltage V SLP as voltage V2. However, the sum voltage of slope voltage V SLP and the voltage corresponding to inductor current I L may be used as voltage V2. Hereinafter, unless otherwise specified, it is considered that slope voltage V SLP itself is voltage V2. Note that the comparison result signal S2 is input to the slope voltage generation circuit 13.

[0031] The clock signal generation circuit 15 generates and outputs a clock signal S1 having a predetermined frequency f PWM . The waveform of the clock signal S1 is shown in Figure 3. The clock signal S1 is a signal in which pulses occur at frequency f PWM . That is, a pulse that becomes high-level for a very short time occurs in the clock signal S1 for each period of the clock signal S1. The length of one period of the clock signal S1 is the reciprocal of the frequency f PWM . Frequency fPWM The level of the clock signal S1 transitions from low to high at intervals equal to the inverse of PWM The level of the clock signal S1 transitions from high to low at intervals equal to the reciprocal of the frequency f PWM The reciprocal of this is called the PWM period.

[0032] The logic circuit 16 generates and outputs a control signal S3 based on the clock signal S1 and the comparison result signal S2. The control signal S3 is a binary signal that takes a high or low signal level. The relationship between the signals S1 to S3 will be described with reference to FIG. 4. When the comparison result signal S2 and the control signal S3 are at a low level and an up edge of the clock signal S1 occurs, the logic circuit 16 switches the level of the control signal S3 from a low level to a high level in synchronization with the up edge of the clock signal S1. After that, when an up edge occurs in the comparison result signal S2, the logic circuit 16 switches the level of the control signal S3 from a high level to a low level in synchronization with the up edge of the comparison result signal S2.

[0033] The drive circuit 17 supplies gate signals G1 and G2 corresponding to the control signal S3 to the gates of the transistors M1 and M2, respectively, to turn on or off the transistors M1 and M2 individually. Under the assumption that the backflow detection signal ZX is at a low level, the drive circuit 17 sets the gate signal G1 to a high level and the gate signal G2 to a low level during a high level period of the control signal S3 to set the output stage circuit MM in an output high state, and sets the gate signal G1 to a low level and the gate signal G2 to a high level during a low level period of the control signal S3 to set the output stage circuit MM in an output low state. When the drive circuit 17 controls the output stage circuit MM to be in an output low state, if the backflow detection signal ZX is switched from a low level to a high level, the drive circuit 17 switches the state of the output stage circuit MM from an output low state to a Hi-Z state (output off state), and keeps the output stage circuit MM in the Hi-Z state until the control signal S3 is switched to a high level next time.

[0034] The logic circuit 16 and the drive circuit 17 constitute a drive control circuit CD that controls the output stage circuit MM based on the clock signal S1 and the comparison result signal S2.

[0035] The reverse current detection circuit 18 is connected to the switch terminal SW and detects the switch voltage V SW Based on the inductor current I L The reverse current detection signal ZX is a binary signal that can take a high or low signal level. L The reverse flow of the inductor current I is the inductor current I flowing from the output inductor L0 to the ground through the switch terminal SW and the transistor M2 when the output stage circuit MM is in the output low state. L In principle, the reverse current detection circuit 18 sets the reverse current detection signal ZX to a low level and the inductor current I L When a reverse current is detected, the reverse current detection circuit 18 switches the level of the reverse current detection signal ZX to a high level and latches it at the high level. After that, the reverse current detection circuit 18 releases the latch at the rising edge of the control signal S3 or the rising edge of the gate signal G1, and returns the level of the reverse current detection signal ZX to a low level. For example, during the period when the output stage circuit MM is in the output low state, the reverse current detection circuit 18 SW When the polarity of the inductor current I L It can be determined that a reverse current of the inductor current I L The operation of cutting off the backflow by switching the output stage circuit MM from the output low state to the Hi-Z state when a backflow is detected is hereinafter referred to as a backflow cutting operation.

[0036] When the output stage circuit MM is in the high output state, the inductor current I L is supplied to the output inductor L0. After that, by switching the state of the output stage circuit MM to the output low state, the inductor current IL is supplied to the output inductor L0. By switching the output stage circuit MM between alternate output high and output low states, the input voltage V IN to output voltage V OUT can be generated.

[0037] FIG. 5 is a state machine diagram showing the operational state transitions of the switching power supply device 1 described above.

[0038] When a rising edge occurs in the comparison result signal S2 during a period in which the output stage circuit MM is in the output high state, the period in which the output stage circuit MM is in the output high state transitions to a period in which the output stage circuit MM is in the output low state.

[0039] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a low level during a period in which the output stage circuit MM is in an output low state, the period in which the output stage circuit MM is in an output high state transitions.

[0040] When the backflow detection signal ZX goes high during a period in which the output stage circuit MM is in the low output state, the period in which the output stage circuit MM is in the low output state transitions to a period in which the output stage circuit MM is in the Hi-Z state.

[0041] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a low level during the period in which the output stage circuit MM is in the Hi-Z state, the period in which the output stage circuit MM is in the Hi-Z state transitions to a period in which the output stage circuit MM is in the output high state.

[0042] In addition to the above-mentioned control, the switching power supply device 1 also controls the output voltage V OUT In addition, overshoot reduction control is performed to reduce the overshoot of the output.

[0043] The overshoot reduction control will be described with reference to FIG. 6. The logic circuit 16 reduces the feedback voltage V FBIf the threshold voltage V is greater than the threshold voltage V, the output transistor M1 is inhibited from turning on and the synchronous rectifier transistor M2 is turned off. In this embodiment, the threshold voltage V REF to slope voltage V SLP . Therefore, if the comparison result signal S2 is at a high level at the first timing TM1 that arrives at a constant cycle (PWM cycle), the logic circuit 16 prohibits the output transistor M1 from being turned on and turns off the synchronous rectification transistor M2. In this embodiment, the first timing TM1 is a timing based on the clock signal S1. More specifically, in this embodiment, the first timing TM1 is a timing at which a rising edge occurs in the clock signal S1.

[0044] In FIG. 6, just before the first timing TM1A, which is one of the first timings TM1, the load becomes light and the output current I OUT Assume that the output voltage V suddenly decreases, and the comparison result signal S2 becomes high level at the first timing TM1A. Therefore, the logic circuit 16 prohibits the output transistor M1 from being turned on, and turns off the synchronous rectifier transistor M2, at the first timing TM1A. With this control, at the first timing TM1A, both the output transistor M1 and the synchronous rectifier transistor M2 are turned off, and the output stage circuit MM is in the Hi-Z state. At this time, a current flows from the synchronous rectifier transistor M2 to the output inductor L0 via the body diode of the synchronous rectifier transistor M2, so that the switch voltage V SW becomes lower than the ground potential by the forward voltage of the body diode of the synchronous rectifier transistor M2.

[0045] The logic circuit 16 inhibits the output transistor M1 from being turned on at the first timing TM1A, and maintains the output transistor M1 and the synchronous rectifier transistor M2 off until the first timing TM1B that arrives for the first time after the synchronous rectifier transistor M2 is turned off, thereby maintaining the Hi-Z state of the output stage circuit MM. Since the Hi-Z state of the output stage circuit MM is maintained from the first timing TM1A to the first timing TM1B, the switching power supply device 1 maintains the output voltage VOUT In addition, since the switching power supply device 1 does not require the light load detection comparator provided in the switching power supply device disclosed in Patent Document 1, it is possible to reduce the overshoot of the output voltage V OUT Moreover, since the switching power supply device 1 does not require the light load detection comparator provided in the switching power supply device disclosed in Patent Document 1, the problem of the amount of overshoot of the output voltage varying depending on the accuracy of the light load detection comparator does not occur.

[0046] In this embodiment, as described above, the output transistor M1 is prohibited from being turned on at the first timing TM1A, and the output transistor M1 and the synchronous rectification transistor M2 are kept off until the first timing TM1B that arrives for the first time after the synchronous rectification transistor M2 is turned off. However, unlike this embodiment, the output transistor M1 may be prohibited from being turned on at the first timing TM1A, and the output transistor M1 and the synchronous rectification transistor M2 may be kept off until the first timing TM1B that arrives for the second time after the synchronous rectification transistor M2 is turned off. Also, instead of the first or second time, it may be the Nth time (N is an integer of 3 or more). However, the larger N is, the greater the output voltage V OUT When an overshoot of the output voltage V occurs, OUT It tends to be difficult to shorten the time it takes for the temperature to return to the set value (target value).

[0047] Then, at the first timing TM1B, if the comparison result signal S2 is at a high level, the logic circuit 16 determines whether the output voltage V OUT Since the overshoot of the output voltage V continues, the synchronous rectification transistor M2 is turned on. By this control, if the comparison result signal S2 is at a high level at the first timing TM1B, the output transistor M1 is turned off and the synchronous rectification transistor M2 is turned on, and the output stage circuit MM is in an output low state. As a result, the switching power supply device 1 quickly reduces the output voltage V OUTIn other words, the switching power supply device 1 can reduce the output voltage V OUT When an overshoot of the output voltage V occurs, OUT In FIG. 6, the output voltage V OUT The output voltage V OUT The waveform of is depicted by a dotted line.

[0048] In FIG. 6, the switch voltage V SW The waveform diagram is depicted.

[0049] The logic circuit 16 maintains the on state of the synchronous rectification transistor M2 until the comparison result signal S2 becomes low level at the first timing TM1, which arrives after the synchronous rectification transistor M2 is turned on at the first timing TM1B. OUT The output voltage V OUT It is possible to maintain a state in which the value can be reduced to the set value (target value).

[0050] In FIG. 6, the switch voltage V SW The waveform diagram is depicted.

[0051] On the other hand, if the comparison result signal S2 is at a low level at the first timing TM1B, the logic circuit 16 OUTSince the overshoot of the output transistor M1 has ended, the inhibition of turning on the output transistor M1 is lifted. With this control, if the comparison result signal S2 is at a low level at the first timing TM1B, the output transistor M1 is turned on and the synchronous rectifier transistor M2 is turned off, and the output stage circuit MM is in an output high state. In other words, if the comparison result signal S2 is at a low level at the first timing TM1B, the logic circuit 16 returns to normal switching control operation.

[0052] FIG. 7 is a state machine diagram showing the transition of operating states including the overshoot reduction control of the switching power supply device 1. As shown in FIG.

[0053] When a rising edge occurs in the comparison result signal S2 during a period in which the output stage circuit MM is in the output high state, the period in which the output stage circuit MM is in the output high state transitions to a period in which the output stage circuit MM is in the output low state.

[0054] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a low level during a period in which the output stage circuit MM is in an output low state, the period in which the output stage circuit MM is in an output high state transitions.

[0055] When the backflow detection signal ZX goes high during a period in which the output stage circuit MM is in the low output state, the period in which the output stage circuit MM is in the low output state transitions to a period in which the output stage circuit MM is in the Hi-Z state.

[0056] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a low level during the period in which the output stage circuit MM is in the Hi-Z state, the period in which the output stage circuit MM is in the Hi-Z state transitions to a period in which the output stage circuit MM is in the output high state.

[0057] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a high level during a period in which the output stage circuit MM is in an output low state, the period in which the output stage circuit MM is in an output low state transitions to a period in which the output stage circuit MM is in a Hi-Z state (a period added by implementing overshoot reduction control).

[0058] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a low level during the period in which the output stage circuit MM is in the Hi-Z state (the period added by implementing overshoot reduction control), the period in which the output stage circuit MM is in the Hi-Z state (the period added by implementing overshoot reduction control) transitions to a period in which the output stage circuit MM is in the output high state.

[0059] If an up edge occurs in the clock signal S1 and the comparison result signal S2 is at a high level during the period in which the output stage circuit MM is in the Hi-Z state (the period added by implementing overshoot reduction control), the period transitions from the period in which the output stage circuit MM is in the Hi-Z state (the period added by implementing overshoot reduction control) to the period in which the output stage circuit MM is in the output low state (the period added by implementing overshoot reduction control).

[0060] If a rising edge occurs in the clock signal S1 and the comparison result signal S2 is at a low level during the period in which the output stage circuit MM is in the output low state (the period added by implementing overshoot reduction control), a transition occurs from the period in which the output stage circuit MM is in the output low state (the period added by implementing overshoot reduction control) to a period in which the output stage circuit MM is in the output high state.

[0061] When the backflow detection signal ZX becomes high level during the period in which the output stage circuit MM is in the output low state (the period added by implementing overshoot reduction control), the period in which the output stage circuit MM is in the output low state transitions to a period in which the output stage circuit MM is in the Hi-Z state.

[0062] The power supply IC2 in FIG. 1 can be modified, for example, into a power supply IC20 shown in FIG. 8. The power supply IC20 is a three-phase power supply IC and includes three sets of components of the power supply IC2. The power supply IC20 controls three pairs of output transistors M1 and synchronous rectification transistors M2. In the power supply IC20, a plurality of first timings corresponding to the three pairs are shifted from one another. That is, in the power supply IC20, the rising edges of the three clock signals S1 output from the three clock signal generating circuits 15 are shifted from one another. This allows the switching noise of the power supply IC20 to be dispersed over time.

[0063] The number of multi-phases in power supply IC 20 is 3, but may be other than 3. Also, in power supply IC 20, an input terminal IN is provided for each phase, but the input terminal IN may be shared among the multiple phases. Similarly, in power supply IC 20, a ground terminal GND is provided for each phase, but the ground terminal GND may be shared among the multiple phases.

[0064] 9 is a schematic block diagram of a car navigation device 100. The car navigation device 100 includes a switching power supply device 101, a DC / DC converter 102, and a functional block 103. The switching power supply device 1 described above is used as the switching power supply device 101. The input voltage V IN may be supplied from a battery installed in the vehicle in which the car navigation device 100 is mounted. The DC / DC converter 102 converts the output voltage V OUT The switching power supply device 101 converts the output voltage V of the switching power supply device 101 into a DC voltage of 1 or more having a desired voltage value, and supplies the obtained DC voltage to a functional block 103. The functional block 103 operates based on the DC voltage supplied from the DC / DC converter 102. The functional block 103 includes a plurality of components that realize the respective functions of the car navigation device 100, including a display device, a speaker, a microprocessor, etc. OUTmay be directly fed to function block 103.

[0065] In the car navigation device 100, the DC / DC converter 102 and the functional block 103 can be considered as a load LD of the switching power supply device 101. Of course, the switching power supply device 101 may be mounted not only in a car navigation device but also in any electric device including any load LD.

[0066] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0067] For example, in the above embodiment, the power supply IC2 has a configuration in which the output transistor M1 and the synchronous rectification transistor M2 are built in, but the output transistor M1 and the synchronous rectification transistor M2 may be externally connected to the power supply IC2.

[0068] For example, in the above embodiment, the feedback resistors R1 and R2 are externally connected to the power supply IC2, but the power supply IC2 may have the feedback resistors R1 and R2 built in. Also, the switching power supply device 1 may be configured without the feedback resistors R1 and R2, and the feedback voltage V FB is the output voltage V of switching power supply unit 1. OUT The output voltage V of switching power supply unit 1 is OUT It may be the same thing.

[0069] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0070] A switching power supply control device (2) disclosed herein is a switching power supply control device configured to control a first switching element (M1) and a second switching element (M2) connected in series to the first switching element and provided on a lower potential side than the first switching element, and is configured to include a control unit (CD) configured to prohibit turn-on of the first switching element and turn-off the second switching element if a feedback voltage based on an output voltage is greater than a threshold value at a first timing that arrives at a constant period, to prohibit turn-on of the first switching element at the first timing, to turn on the second switching element if the feedback voltage is greater than the threshold value at the first timing that arrives a predetermined number of times after turning off the second switching element, and to cancel the prohibition of turn-on of the first switching element if the feedback voltage is smaller than the threshold value (first configuration).

[0071] In the switching power supply control device of the first configuration described above, the control unit may be configured (second configuration) to maintain the on state of the second switching element at the first timing that arrives after turning on the second switching element at the first timing, until the feedback voltage becomes smaller than the threshold value.

[0072] In the switching power supply control device of the first or second configuration, the predetermined number of times may be a first or second time (third configuration).

[0073] In the switching power supply control device of any of the above first to third configurations, the first timing may be a timing based on a clock signal (fourth configuration).

[0074] In the switching power supply control device of any of the first to fourth configurations, a configuration (fifth configuration) may be adopted in which a plurality of pairs of the first switching elements and the second switching elements are controlled, and a plurality of the first timings corresponding to the respective pairs are shifted from one another.

[0075] The switching power supply device (1) of the present disclosure may have a configuration (sixth configuration) including a switching power supply control device having any of the first to fifth configurations, the first switching element, and the second switching element.

[0076] An electric device (100) of the present disclosure has a configuration (seventh configuration) including the switching power supply device of the sixth configuration. [Explanation of symbols]

[0077] 1 Switching power supply 2 Power IC 3 Rectifier smoothing circuit 4 Feedback voltage generation circuit 11 Error Amplifier 12 Phase compensation circuit 13 Slope voltage generation circuit 14 Comparator 15 Clock signal generation circuit 16 Logic Circuits 17 Drive circuit 18 Reverse current detection circuit 20 Power IC 100 Car navigation device 101 Switching power supply 102 DC / DC converter 103 Function Blocks CD control drive circuit MM output stage circuit M1 Output transistor M2 Synchronous rectifier transistor L0 Output inductor C0 Output Capacitor R1, R2 Feedback resistors LD load IN Input terminal OUT Output terminal SW Switch terminal GND Ground terminal FB Feedback pin

Claims

1. 1. A switching power supply control device configured to control a first switching element and a second switching element connected in series to the first switching element and provided on a lower potential side than the first switching element, If a feedback voltage based on an output voltage is greater than a threshold value at a first timing that arrives at a constant period, the first switching element is inhibited from being turned on and the second switching element is turned off; a control unit configured to prohibit turn-on of the first switching element at the first timing, to turn on the second switching element if the feedback voltage is higher than the threshold value at the first timing that arrives a predetermined number of times after turning off the second switching element, and to cancel the prohibition of turn-on of the first switching element if the feedback voltage is lower than the threshold value.

2. 2. The switching power supply control device according to claim 1, wherein the control unit is configured to maintain the second switching element in an on state until the feedback voltage becomes smaller than the threshold voltage at the first timing that arrives after turning on the second switching element at the first timing.

3. 2. The switching power supply control device according to claim 1, wherein the predetermined number of times is a first or second time.

4. 2. The switching power supply control device according to claim 1, wherein the first timing is based on a clock signal.

5. configured to control a plurality of pairs of the first switching elements and the second switching elements; The switching power supply control device according to claim 1 , wherein the first timings corresponding to the respective pairs are shifted from one another.

6. A switching power supply control device according to any one of claims 1 to 5, The first switching element; the second switching element.

7. An electric device comprising the switching power supply device according to claim 6.

Images