Semiconductor device

Abstract

To provide a semiconductor device with high productivity, by which excellent characteristics can be obtained regarding the respective transistors with different characteristics.SOLUTION: A semiconductor device includes a first semiconductor layer, a first gate electrode facing the first semiconductor layer, a first gate insulating layer between the first semiconductor layer and the first gate electrode, a first insulating layer provided over the first gate electrode, a first electrode provided in a region overlapping with the first semiconductor layer in a plan view and electrically connected to the first semiconductor layer, a second semiconductor layer formed of a material different from the first semiconductor layer, a second gate electrode facing the second semiconductor layer, a second gate insulating layer between the second semiconductor layer and the second gate electrode, a second electrode provided in a region overlapping with the second semiconductor layer in the plan view and electrically connected to the second semiconductor layer, and a first metal nitride layer between the second semiconductor layer and the second electrode.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In recent years, development of semiconductor devices has been underway in which transistors using different semiconductor materials as semiconductor layers are formed on the same substrate. For example, by using a transistor using silicon for a transistor that is required to operate at high speed and a transistor using an oxide semiconductor for a transistor that is required to perform switching operations, transistors having different characteristics according to required functions can be formed on the same substrate.

[0003] Patent Document 1 discloses a display device in which a transistor using silicon is formed in a driver circuit and a transistor using an oxide semiconductor is formed in a display region, both over the same substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 2018-128693 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment of the present invention is to provide a highly productive semiconductor device capable of obtaining good characteristics for each of transistors having different characteristics. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a first semiconductor layer, a first gate electrode facing the first semiconductor layer, a first gate insulating layer between the first semiconductor layer and the first gate electrode, a first insulating layer provided above the first gate electrode, a first electrode provided in a region overlapping with the first semiconductor layer in a planar view and electrically connected to the first semiconductor layer, a second semiconductor layer made of a material different from the first semiconductor layer, a second gate electrode facing the second semiconductor layer, a second gate insulating layer between the second semiconductor layer and the second gate electrode, a second electrode provided in a region overlapping with the second semiconductor layer in a planar view and electrically connected to the second semiconductor layer, and a first metal nitride layer between the second semiconductor layer and the second electrode. [Brief description of the drawings]

[0007] [Figure 1] 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 16] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 20] 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, the same symbols are used for configurations similar to those described above with respect to the previous figures, and detailed explanations may be omitted as appropriate.

[0009] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". Thus, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a direction different from that illustrated. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the stacking order in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0010] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] [1. First embodiment] An example of the structure of a semiconductor device 100 according to one embodiment of the present invention will be described with reference to FIGS.

[0015] [1-1. Configuration of semiconductor device] Fig. 1 is a plan view of a semiconductor device 100 according to one embodiment of the present invention. Fig. 2 is a cross-sectional view of the semiconductor device 100 shown in Fig. 1 taken along line A1-A2. As shown in Figs. 1 and 2, the semiconductor device 100 according to one embodiment of the present invention has a transistor 110 provided on a substrate 101 and a transistor 120 provided above the transistor 110.

[0016] The transistor 110 includes a semiconductor layer 111 , a gate insulating layer 112 , and a gate electrode 113 .

[0017] Either an N-type transistor or a P-type transistor may be used as the transistor 110. In this embodiment, an example in which a top-gate N-type transistor using polysilicon for a semiconductor layer is used as the transistor 110 will be described.

[0018] The semiconductor layer 111 in the N-type transistor has a channel region 111a, a source region 111d, a drain region 111e, and low-concentration impurity regions 111b and 111c. The low-concentration impurity region 111b is provided between the channel region 111a and the source region 111d. The low-concentration impurity region 111c is provided between the channel region 111a and the drain region 111e. The source and drain may be interchanged depending on the operation of the transistor 110. That is, the region 111d may function as the drain region, and the region 111e may function as the source region.

[0019] The semiconductor layer 111 in the channel region 111a has semiconductor properties. That is, the semiconductor layer 111 in the channel region 111a is switched between a state in which it functions as a current path and a state in which it does not function as a current path, depending on the voltage applied to the gate electrode 113. The carrier concentration in the semiconductor layer 111 in the source region 111d and the drain region 111e is higher than the carrier concentration in the semiconductor layer 111 in the channel region 111a.

[0020] Interlayer insulating layers 114 and 116 are provided on the transistor 110. A source electrode 117a and a drain electrode 117b are provided on the interlayer insulating layers 114 and 116. The source electrode 117a and the drain electrode 117b are connected to a source region 111d and a drain region 111e through openings 115a and 115b provided in the interlayer insulating layers 114 and 116.

[0021] The transistor 120 is provided in a region different from the region in which the transistor 110 is provided. The transistor 120 includes an oxide semiconductor layer 121, a gate insulating layer 122, a gate electrode 123, a gate electrode 128, and a gate insulating layer 129. An interlayer insulating layer 126 is provided over the gate electrode 123. The oxide semiconductor layer 121 is polycrystalline, the details of which will be described later.

[0022] The gate electrode 128 is provided between the gate insulating layer 112 and the interlayer insulating layer 114. The gate electrode 128 is provided in a region overlapping the oxide semiconductor layer 121 (particularly, the channel region 121a) in a plan view. A wiring 119 is provided on the interlayer insulating layers 114 and 116. The wiring 119 is connected to the gate electrode 128 through an opening 115c provided in each of the interlayer insulating layers 114 and 116. The wiring 119 is in the same layer as the source electrode 117a and the drain electrode 117b. In other words, the wiring 119 is in contact with the interlayer insulating layer 116 in the same manner as the source electrode 117a and the drain electrode 117b.

[0023] A channel region 121a, and a source region 121d and a drain region 121e adjacent to the channel region 121a are provided in the oxide semiconductor layer 121. The channel region 121a overlaps with the gate electrode 123 in a plan view.

[0024] The oxide semiconductor layer 121 in the channel region 121a has semiconductor properties. That is, the oxide semiconductor layer 121 in the channel region 121a is switched between a state where it functions as a current path and a state where it does not function as a current path depending on the voltage applied to the gate electrodes 123 and 128. The carrier concentration in the oxide semiconductor layer 121 in the source region 121d and the drain region 121e is higher than the carrier concentration in the oxide semiconductor layer 121 in the channel region 121a.

[0025] For example, the sheet resistance of the oxide semiconductor layer 121 in the source region 121d and the drain region 121e is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. In other words, the oxide semiconductor layer 121 in the channel region 121a has a higher electrical resistivity (or a lower electrical conductivity) than each of the oxide semiconductor layers 121 in the source region 121d and the drain region 121e.

[0026] A voltage for controlling the channel region 121a is supplied to the gate electrodes 123 and 128. That is, in this embodiment, a dual-gate transistor using an N-type oxide semiconductor is exemplified as the transistor 120. However, the transistor 120 may be a bottom-gate transistor provided with only the gate electrode 128, or a top-gate transistor provided with only the gate electrode 123.

[0027] The gate insulating layer 122 and the interlayer insulating layer 126 are provided with openings 127d and 127e that reach the source region 121d and the drain region 121e of the oxide semiconductor layer 121. Metal nitride layers 124c and 124d are provided inside the openings 127d and 127e and on the source region 121d and the drain region 121e. The metal nitride layers 124c and 124d are in contact with the upper surface of the oxide semiconductor layer 121 and the upper surface of the interlayer insulating layer 126. A source electrode 125c and a drain electrode 125d are provided inside the openings 127d and 127e and on the metal nitride layers 124c and 124d.

[0028] In the above configuration, the semiconductor layer 111 may be referred to as the "first semiconductor layer", the gate electrode 113 as the "first gate electrode", the gate insulating layer 112 as the "first gate insulating layer", the interlayer insulating layer 114 as the "first insulating layer", and the source electrode 117a and the drain electrode 117b as the "first electrode". Similarly, the oxide semiconductor layer 121 may be referred to as the "second semiconductor layer", the gate electrode 123 as the "second gate electrode", the gate insulating layer 122 as the "second gate insulating layer", the gate electrode 128 as the "third gate electrode", the gate insulating layer 129 as the "third gate insulating layer", the metal nitride layers 124c and 124d as the "first metal nitride layer", and the source electrode 125c and the drain electrode 125d as the "second electrode". Similarly, the interlayer insulating layer 116 may be referred to as the "second insulating layer". On the other hand, different from the above, the gate electrode 123 may be referred to as the "third gate electrode", the gate insulating layer 122 may be referred to as the "third gate insulating layer", the gate electrode 128 may be referred to as the "second gate electrode", and the gate insulating layer 129 may be referred to as the "second gate insulating layer".

[0029] When expressed as above, the configuration of the semiconductor device 100 can be rephrased as follows. The first gate electrode (gate electrode 113) faces the first semiconductor layer (semiconductor layer 111). The first gate insulating layer (gate insulating layer 112) exists between the first semiconductor layer (semiconductor layer 111) and the first gate electrode (gate electrode 113). The first insulating layer (interlayer insulating layer 114) is provided above the first gate electrode (gate electrode 113). The first electrodes (source electrode 117a and drain electrode 117b) are provided in a region overlapping with the first semiconductor layer (semiconductor layer 111) in a plan view, and are electrically connected to the first semiconductor layer (semiconductor layer 111). The second semiconductor layer (oxide semiconductor layer 121) is made of a material different from the first semiconductor layer (semiconductor layer 111). The second semiconductor layer (oxide semiconductor layer 121) is provided above the first insulating layer (interlayer insulating layer 114). The second gate electrode (gate electrode 123) faces the second semiconductor layer (oxide semiconductor layer 121) below the second semiconductor layer (oxide semiconductor layer 121). The second gate insulating layer (gate insulating layer 122) exists between the second semiconductor layer (oxide semiconductor layer 121) and the second gate electrode (gate electrode 123). The second electrodes (source electrode 125c and drain electrode 125d) are provided in a region overlapping with the second semiconductor layer (oxide semiconductor layer 121) in a plan view, and are electrically connected to the second semiconductor layer (oxide semiconductor layer 121). The first metal nitride layer (metal nitride layers 124c, 124d) exists between the second semiconductor layer (oxide semiconductor layer 121) and the second electrodes (source electrode 125c and drain electrode 125d).

[0030] Similarly, the configuration of the semiconductor device 100 can be restated as follows. The first metal nitride layer (metal nitride layers 124c, 124d) is in contact with the second semiconductor layer (oxide semiconductor layer 121). The second insulating layer (interlayer insulating layer 116) is provided above the first insulating layer (interlayer insulating layer 114). The third gate electrode (gate electrode 128) faces the second semiconductor layer (oxide semiconductor layer 121) below the first insulating layer (interlayer insulating layer 114). The third gate insulating layer (gate insulating layer 129) exists between the second semiconductor layer (oxide semiconductor layer 121) and the third gate electrode (gate electrode 128). The second gate electrode (gate electrode 123) is provided above the second insulating layer (interlayer insulating layer 116). The first insulating layer (interlayer insulating layer 114) and the second insulating layer (interlayer insulating layer 116) are each provided with openings 115a, 115b. The first electrodes (source electrode 117a and drain electrode 117b) are provided above the second insulating layer (interlayer insulating layer 116) and inside the openings 115a and 115b. The first electrodes (source electrode 117a and drain electrode 117b) are in the same layer as the second gate electrode (gate electrode 123).

[0031] Conventionally, when a transistor using polysilicon and a transistor using an oxide semiconductor are formed on the same substrate, the following problems have arisen. When the oxide semiconductor is processed into a desired shape and when a conductive layer in contact with the oxide semiconductor is processed, damage may occur on the surface of the oxide semiconductor. The oxide semiconductor in the damaged region contains many oxygen vacancies. When oxygen vacancies occur in the oxide semiconductor, the off-leak current of the transistor increases. In order to solve this problem, it is necessary to sufficiently introduce oxygen into the oxide semiconductor by heat treatment. However, the heat treatment causes a problem that the source electrode and the drain electrode react with the oxide semiconductor, thereby decreasing the on-current of the transistor. Therefore, in one embodiment of the present invention, a metal nitride layer is provided between the oxide semiconductor layer and the source electrode and between the oxide semiconductor layer and the drain electrode. The metal nitride layer suppresses the reaction between the oxide semiconductor and the electrodes caused by the heat treatment.

[0032] On the other hand, when a metal nitride layer is provided between the polysilicon and the source electrode and between the polysilicon and the drain electrode, nitrogen is implanted into the polysilicon when the metal nitride layer is formed. This increases the contact resistance between the source electrode and the drain electrode and the polysilicon via the metal nitride layer. In one embodiment of the present invention, a structure in which a metal nitride layer is provided only in a transistor using an oxide semiconductor is exemplified. That is, the polysilicon is in direct contact with the source electrode and the drain electrode without the metal nitride layer. On the other hand, the oxide semiconductor is connected to the source electrode and the drain electrode via the metal nitride layer. This allows each transistor to have good characteristics.

[0033] [1-2. Materials of each component of the semiconductor device 100] As the substrate 101, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 101 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used. When a substrate containing a resin is used as the substrate 101, impurities may be introduced into the resin in order to improve the heat resistance of the substrate 101. In particular, when the semiconductor device 100 is a top-emission display, the substrate 101 does not need to be transparent, and therefore impurities that deteriorate the transparency of the substrate 101 may be used. When the semiconductor device 100 is used in an integrated circuit that is not a display device, a substrate not having light-transmitting properties, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, is used as the substrate 101.

[0034] The semiconductor layer 111 may be made of, for example, low-temperature polysilicon, amorphous silicon, or single crystal silicon.

[0035] A typical metal material is used as the conductive layer including the gate electrode 113, the source electrode 117a, the drain electrode 117b, the wiring 119, the gate electrodes 123 and 128, the source electrode 125c, and the drain electrode 125d. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as these members. The above materials may be used as a single layer or a laminated layer as the conductive layer.

[0036] A general insulating material is used for the insulating layers including the gate insulating layer 112, the interlayer insulating layers 114, 116, and 126, and the gate insulating layers 122 and 129. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x ), aluminum oxide nitride (AlN x O y ) or other inorganic insulating layers are used.

[0037] An insulating layer having a function of releasing oxygen by heat treatment is used as the interlayer insulating layer 126. That is, an oxide insulating layer containing excess oxygen is used as the interlayer insulating layer 126. The temperature of the heat treatment at which the interlayer insulating layer 126 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the interlayer insulating layer 126 releases oxygen at a heat treatment temperature performed in the manufacturing process of the semiconductor device 100 when a glass substrate is used as the substrate 101, for example.

[0038] An insulating layer with few defects is used as the gate insulating layers 112, 122, 129. For example, when the oxygen composition ratio in the gate insulating layers 112, 122, 129 is compared with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layers 112, 122, 129 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the gate insulating layers 112, 122, 129 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, silicon oxide (SiO x ), the composition ratio of oxygen in the silicon oxide used as the gate insulating layers 112, 122, and 129 is closer to the stoichiometric ratio of silicon oxide than the composition ratio of oxygen in the silicon oxide used as the interlayer insulating layer 126. For example, the gate insulating layers 112, 122, and 129 may be layers in which no defects are observed when evaluated by electron spin resonance (ESR).

[0039] The above SiO x N y and AlO x N y is a silicon and aluminum compound that contains a smaller ratio (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds that contain a smaller proportion of oxygen than nitrogen (x>y).

[0040] A metal oxide having semiconductor properties may be used as the oxide semiconductor layer 121. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used as the oxide semiconductor layer 121. For example, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 may be used as the oxide semiconductor layer 121. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition. An oxide semiconductor having a composition different from the above may be used as the oxide semiconductor. For example, an oxide semiconductor layer having a ratio of In larger than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer having a ratio of Ga larger than the above may be used to increase the band gap and reduce the influence of light irradiation.

[0041] The oxide semiconductor layer 121 may be made of an oxide semiconductor containing two or more metals including indium (In). In this case, the ratio of indium elements to all metal elements in the oxide semiconductor layer 121 may be 50% or more in atomic ratio. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanoid may be used for the oxide semiconductor layer 121. Elements other than the above may also be used for the oxide semiconductor layer 121.

[0042] As the oxide semiconductor layer 121, other elements may be added to an oxide semiconductor containing In, Ga, Zn, and O, and for example, a metal element such as Al or Sn may be added. In addition to the above oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), an oxide semiconductor containing In and W, or the like may be used as the oxide semiconductor layer 121.

[0043] When the ratio of the indium element is high, the oxide semiconductor layer 121 is likely to crystallize. As described above, by using a material in which the ratio of the indium element to all metal elements in the oxide semiconductor layer 121 is 50% or more, the oxide semiconductor layer 121 having a polycrystalline structure can be obtained. The oxide semiconductor layer 121 preferably contains gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 121 is not impaired by gallium, and the oxide semiconductor layer 121 has a polycrystalline structure.

[0044] Although a detailed manufacturing method of the oxide semiconductor layer 121 will be described later, the oxide semiconductor layer 121 can be formed by a sputtering method. The composition of the oxide semiconductor layer 121 formed by a sputtering method depends on the composition of a sputtering target. Even when the oxide semiconductor layer 121 has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer 121 are approximately the same. In this case, the composition of the metal elements of the oxide semiconductor layer 121 can be specified based on the composition of the metal elements of the sputtering target.

[0045] When the oxide semiconductor layer 121 has a polycrystalline structure, the composition of the oxide semiconductor layer may be identified by X-ray diffraction (XRD). Specifically, the composition of metal elements in the oxide semiconductor layer can be identified based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by XRD. Furthermore, the composition of metal elements in the oxide semiconductor layer 121 can also be identified by X-ray fluorescence analysis, Electron Probe Micro Analyzer (EPMA) analysis, or the like. However, the oxygen element contained in the oxide semiconductor layer 121 may change depending on the process conditions of sputtering, and therefore may not be identified by these methods.

[0046] As described above, the oxide semiconductor layer 121 may include an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be manufactured using a Poly-OS (Polycrystalline Oxide Semiconductor) technique described later. In the following description, an oxide semiconductor having a polycrystalline structure may be referred to as Poly-OS to distinguish it from an oxide semiconductor having an amorphous structure.

[0047] Note that a semiconductor other than an oxide semiconductor may be used instead of the oxide semiconductor layer 121. In that case, the semiconductor used instead of the oxide semiconductor is made of a different material or has a different composition from the semiconductor used for the semiconductor layer 111. In other words, the transistor 110 has characteristics different from those of the transistor 120.

[0048] A metal oxide layer may be provided between the gate insulating layer 129 and the oxide semiconductor layer 121. In this case, the metal oxide layer may be in contact with the oxide semiconductor layer 121. A metal oxide containing aluminum as a main component is used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ) is used. "Aluminum-based metal oxide layer" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0049] The metal nitride layers 124c and 124d are made of nitrides of common metal materials. For example, titanium nitride, molybdenum nitride, tungsten nitride, and tantalum nitride are used for the metal nitride layers 124c and 124d. The metal nitride layers 124c and 124d contain the same metal element as the source electrode 125c and the drain electrode 125d. For example, when the source electrode 125c and the drain electrode 125d have a structure of Al / Ti (upper layer / lower layer), the metal nitride layers 124c and 124d may be titanium nitride.

[0050] In this case, the lower layer (Ti) included in the source electrode 125c and the drain electrode 125d (second electrode) may be referred to as the "first conductive layer", and the upper layer (Al) may be referred to as the "second conductive layer". When expressed as above, the configuration of the semiconductor device 100 described above can be rephrased as follows. The second electrode (the source electrode 125c and the drain electrode 125d) includes the first conductive layer (Ti) and the second conductive layer (Al) on the first conductive layer (Ti). The first conductive layer (Ti) is in contact with the first metal nitride layer (metal nitride layers 124c, 124d). The first metal nitride layer (metal nitride layers 124c, 124d) (for example, TiN) includes the same metal element as the metal element included in the first conductive layer (Ti).

[0051] [1-3.Poly-OS technology] The Poly-OS included in the oxide semiconductor layer can be formed by sputtering and heat treatment. Here, a method for forming the oxide semiconductor layer will be described.

[0052] First, an oxide semiconductor layer is formed by sputtering. The formed oxide semiconductor layer has an amorphous structure. Here, the amorphous structure refers to a structure in which a long-range ordered structure does not exist and a periodic crystal lattice arrangement is not observed. For example, when an oxide semiconductor layer having an amorphous structure is observed using an XRD method, a specific peak based on the crystal structure is not obtained in the diffraction pattern. Note that an oxide semiconductor layer having an amorphous structure may have a short-range ordered structure in a micro-domain. However, such an oxide semiconductor layer does not exhibit the characteristics of Poly-OS, and therefore can be classified as an oxide semiconductor layer having an amorphous structure.

[0053] In the Poly-OS technique, the oxide semiconductor layer is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor layer is formed is 150° C. or lower, preferably 100° C. or lower, and more preferably 50° C. or lower. If the temperature of the substrate is high during the formation of the oxide semiconductor layer, microcrystals are likely to be generated in the oxide semiconductor to be formed. The oxygen partial pressure in the chamber during the film formation is 1% to 10%, preferably 1% to 5%, and more preferably 2% to 4%. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to excess oxygen contained in the oxide semiconductor. On the other hand, under the condition of an oxygen partial pressure of less than 1%, the oxygen composition in the oxide semiconductor layer becomes nonuniform, and an oxide semiconductor layer containing many microcrystals or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0054] Next, the oxide semiconductor layer formed by sputtering is subjected to heat treatment. The heat treatment is performed in air, but the atmosphere is not limited thereto. The heat treatment temperature is 300° C. to 500° C., and preferably 350° C. to 450° C. The heat treatment time is 15 minutes to 120 minutes, and preferably 30 minutes to 60 minutes. By performing the heat treatment, the oxide semiconductor layer having an amorphous structure is crystallized, and an oxide semiconductor layer containing Poly-OS is formed.

[0055] [1-4. Characteristics of the oxide semiconductor layer 121] Next, characteristics of the oxide semiconductor layer containing Poly-OS used as the oxide semiconductor layer 121 will be described below.

[0056] The oxide semiconductor layer has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer is very small when the oxide semiconductor layer is etched using an etching solution for wet etching. This means that the oxide semiconductor layer is hardly etched by the etching solution. When the oxide semiconductor layer is etched using an etching solution containing phosphoric acid as a main component at a temperature of about 40° C., the etching rate is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the etching solution is 50% or more, 60% or more, or 70% or more. The etching solution may contain nitric acid and acetic acid in addition to phosphoric acid. Note that the temperature of about 40° C. is the set temperature of an apparatus that holds the etching solution, and the actual temperature of the etching solution is 35° C. or more and 45° C. or less.

[0057] On the other hand, when an oxide semiconductor layer not containing Poly-OS, for example an oxide semiconductor layer having an amorphous structure before heat treatment, is etched at a temperature of about 40° C. using an etching solution containing phosphoric acid as a main component, the etching rate is 100 nm / min or more.

[0058] When an oxide semiconductor layer including Poly-OS is etched using a 0.5% hydrofluoric acid solution at room temperature (for example, about 22° C.), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Here, room temperature is 25° C.±5° C. The actual temperature of the etching solution is 20° C. or higher and 30° C. or lower.

[0059] On the other hand, when an oxide semiconductor layer not containing Poly-OS is etched with a 0.5% hydrofluoric acid solution at room temperature, the etching rate is 15 nm / min or more.

[0060] Here, an example of the oxide semiconductor layer is shown in Table 1. Table 1 shows the etching rates of the prepared samples with respect to the mixed acid etching solution and 0.5% hydrofluoric acid solution. As the mixed acid etching solution, "Mixed Acid AT-2F (product name)" from Rasa Kogyo Co., Ltd. was used. The ratio of phosphoric acid in the mixed acid etching solution was about 65%. When etching each sample, the temperature of the mixed acid etching solution was about 40°C, and the temperature of the 0.5% hydrofluoric acid solution was room temperature. In Table 1, Sample 1 is an oxide semiconductor layer containing Poly-OS, Sample 2 is an oxide semiconductor layer having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor layer containing indium gallium zinc oxide (IGZO) with an indium ratio of less than 50%.

[0061] [Table 1]

[0062] As shown in Table 1, Sample 1 (oxide semiconductor layer containing Poly-OS) is hardly etched using a mixed acid etching solution, and is etched at only 2 nm / min even when using a 0.5% hydrofluoric acid solution. Sample 1 has an etching rate of 1 / 100 or less with a mixed acid etching solution and approximately 1 / 10 or less with a 0.5% hydrofluoric acid solution than Sample 2 (oxide semiconductor layer having an amorphous structure before heat treatment). Sample 1 also has an etching rate of 1 / 100 or less with a mixed acid etching solution than Sample 3 (oxide semiconductor layer containing IGZO with an indium ratio of less than 50%). That is, Sample 1 is significantly more etch-resistant than Samples 2 and 3.

[0063] Such excellent etching resistance of the oxide semiconductor layer containing Poly-OS is a property that cannot be obtained with conventional oxide semiconductors having a polycrystalline structure that are fabricated by a process at or below 500° C. Although the detailed mechanism behind the excellent etching resistance of the oxide semiconductor layer containing Poly-OS is unclear, it is thought that Poly-OS has a polycrystalline structure that is different from the conventional ones.

[0064] As described above, the etching rate of the oxide semiconductor layer containing Poly-OS with respect to the etching solution is very small. Therefore, it is very difficult to pattern the oxide semiconductor layer. Therefore, when forming an island-shaped oxide semiconductor layer, an oxide semiconductor layer having an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize the oxide semiconductor layer. In this way, an island-shaped oxide semiconductor layer containing Poly-OS can be formed.

[0065] [1-5. Manufacturing method of semiconductor device 100] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 3 to 6. Figures 3 to 6 are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0066] 3, first, a semiconductor layer made of polysilicon is formed on a substrate 101, and the semiconductor layer is processed by a photolithography process to form a semiconductor layer 111. Next, a gate insulating layer 112 is formed on the substrate 101 and the semiconductor layer 111. Next, a conductive layer is formed on the gate insulating layer 112, and the conductive layer is processed by a photolithography process to form a gate electrode 113 overlapping with the semiconductor layer 111 and a gate electrode 128 included in the transistor 120.

[0067] Next, impurities are injected into the semiconductor layer 111 through the gate insulating layer 112 using the gate electrode 113 as a mask. The channel region 111a and other impurity regions are formed by the injection of the impurities. Thereafter, a mask is formed using a resist or the like to cover the regions corresponding to the channel region 111a and the low-concentration impurity regions 111b and 111c, and additional impurities are injected. The source region 111d and the drain region 111e are formed in the regions adjacent to the low-concentration impurity regions 111b and 111c by the injection of the additional impurities. The low-concentration impurity regions 111b and 111c may be omitted. In that case, the channel region 111a is adjacent to the source region 111d and the drain region 111e.

[0068] Next, an interlayer insulating layer 114 is formed over the gate insulating layer 112 and the gate electrodes 113 and 128. Next, an oxide semiconductor layer is formed over the interlayer insulating layer 114 and processed by a photolithography process to form the oxide semiconductor layer 121. Next, an insulating layer is formed over the interlayer insulating layer 114 and the oxide semiconductor layer 121. The insulating layer functions as the interlayer insulating layer 116 in the transistor 110 and functions as the gate insulating layer 122 in the transistor 120.

[0069] 4, the gate insulating layer 112 and the interlayer insulating layers 114 and 116 are processed by a photolithography process to form openings 115a and 115b that reach the source region 111d and the drain region 111e of the semiconductor layer 111, and an opening 115c that reaches the gate electrode 128. Next, a conductive layer is formed on the interlayer insulating layer 116 and inside the openings 115a, 115b, and 115c. The formed conductive layer is processed by a photolithography process to form a source electrode 117a, a drain electrode 117b, a wiring 119, and a gate electrode 123.

[0070] Next, using the gate electrode 123 as a mask, impurities are injected into the oxide semiconductor layer 121 through the gate insulating layer 122. By the injection of the impurities, a channel region 121a, a source region 121d, and a drain region 121e are formed. A method for forming the source region 121d and the drain region 121e will be described in detail later.

[0071] 5, an interlayer insulating layer 126 that covers the source electrode 117a, the drain electrode 117b, the wiring 119, and the gate electrode 123 is formed on the interlayer insulating layer 116. The interlayer insulating layers 116 and 126 are processed by a photolithography process to form openings 127d and 127e that reach the source region 121d and the drain region 121e of the oxide semiconductor layer 121.

[0072] 6, the metal nitride layer 124 and the conductive layer 125 are formed on the interlayer insulating layer 126 and inside the openings 127d and 127e. The formed metal nitride layer 124 and the conductive layer 125 are processed by a photolithography process to form the metal nitride layers 124c and 124d, the source electrode 125c, and the drain electrode 125d shown in FIG.

[0073] As described above, since the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, an increase in contact resistance can be suppressed. Furthermore, since the semiconductor layer 111 contacts the source electrode 117a and the drain electrode 117b without a metal nitride layer therebetween, an increase in contact resistance can be suppressed.

[0074] [1-6. Method for forming source region 121d and drain region 121e] A method for forming the source region 121d and the drain region 121e will be described with reference to Fig. 4. As shown in Fig. 4, in a state in which a gate insulating layer 122 and a gate electrode 123 are formed on the oxide semiconductor layer 121, ion implantation is performed on the oxide semiconductor layer 121. For example, boron (B) is implanted as an impurity element into the oxide semiconductor layer 121 by ion implantation. However, instead of boron, other impurity elements such as phosphorus (P) may be implanted into the oxide semiconductor layer 121.

[0075] In a region where the gate electrode 123 is not provided (the source region 121d and the drain region 121e), the impurity element passes through the gate insulating layer 122 and reaches the oxide semiconductor layer 121. However, in a region where the gate electrode 123 is provided (the channel region 121a), the impurity element is blocked by the gate electrode 123 and does not reach the oxide semiconductor layer 121.

[0076] The above ion implantation forms a source region 121d and a drain region 121e in which the impurity element is implanted in the oxide semiconductor layer 121. Since oxygen defects are formed in the source region 121d and the drain region 121e of the oxide semiconductor layer 121 by the implantation of the impurity element, the resistance of the oxide semiconductor layer 121 in the source region 121d and the drain region 121e is reduced. Note that in the oxide semiconductor layer 121 including Poly-OS, the source region 121d and the drain region 121e in which the impurity element is implanted may have crystallinity. This is also one of the characteristics of Poly-OS. In this case, the crystal structure of each of the source region 121d and the drain region 121e is the same as the crystal structure of the channel region 121a.

[0077] [2. Second embodiment] An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIGS.

[0078] [2-1. Configuration of semiconductor device] Fig. 7 is a cross-sectional view of the semiconductor device 100 taken along line A1-A2, similar to Fig. 1. As shown in Fig. 1 and Fig. 7, the semiconductor device 100 according to one embodiment of the present invention has a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110.

[0079] The configurations of the transistors 110 and 120 in FIG. 7 are the same as those of the transistors 110 and 120 in FIG. 2, and therefore the description thereof will be omitted. As shown in FIG. 7, metal nitride layers 124a and 124b are provided on an interlayer insulating layer 126. A source electrode 125a and a drain electrode 125b are provided on the metal nitride layers 124a and 124b. The source electrode 125a and the drain electrode 125b are connected to the source region 111d and the drain region 111e through openings 115a and 115b provided in the interlayer insulating layers 114, 116, and 126. The metal nitride layers 124a and 124b are formed only on the upper surface of the interlayer insulating layer 126, and are not formed on the sidewalls of the openings 115a and 115b, the upper surface of the source region 111d, and the upper surface of the drain region 111e.

[0080] The metal nitride layers 124a and 124b may be formed using the same material as the metal nitride layers 124c and 124d. The source electrode 125a and the drain electrode 125b may be formed using the same material as the source electrode 125c and the drain electrode 125d.

[0081] In the above configuration, the metal nitride layers 124a and 124b may be referred to as "second metal nitride layers," and the source electrode 125a and the drain electrode 125b may be referred to as "first electrodes." When expressed in this way, the configuration of the semiconductor device 100 described above can be rephrased as follows. The second insulating layer (interlayer insulating layer 116) is provided above the first insulating layer (interlayer insulating layer 114). The first insulating layer (interlayer insulating layer 114) and the second insulating layer (interlayer insulating layer 116) are each provided with openings 115a and 115b. The first electrodes (source electrode 125a and drain electrode 125b) are provided above the second insulating layer (interlayer insulating layer 116) and inside the openings 115a and 115b, and are in contact with the first semiconductor layer (semiconductor layer 111). The second metal nitride layer (metal nitride layers 124a, 124b) is provided above the second insulating layer (interlayer insulating layer 116) and between the second insulating layer (interlayer insulating layer 116) and the first electrodes (source electrode 125a and drain electrode 125b).

[0082] [2-2. Manufacturing method of semiconductor device 100] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 8 to 11. Figures 8 to 11 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0083] 8, first, a semiconductor layer made of polysilicon is formed on a substrate 101, and the semiconductor layer is processed by a photolithography process to form a semiconductor layer 111. Next, a gate insulating layer 112 is formed on the substrate 101 and the semiconductor layer 111. Next, a conductive layer is formed on the gate insulating layer 112, and the conductive layer is processed by a photolithography process to form a gate electrode 113 overlapping with the semiconductor layer 111 and a gate electrode 128 included in the transistor 120.

[0084] Next, impurities are injected into the semiconductor layer 111 through the gate insulating layer 112 using the gate electrode 113 as a mask. The channel region 111a and other impurity regions are formed by the injection of the impurities. Thereafter, a mask is formed using a resist or the like to cover the regions corresponding to the channel region 111a and the low-concentration impurity regions 111b and 111c, and additional impurities are injected. The source region 111d and the drain region 111e are formed in the regions adjacent to the low-concentration impurity regions 111b and 111c by the injection of the additional impurities. The low-concentration impurity regions 111b and 111c may be omitted. In that case, the channel region 111a is adjacent to the source region 111d and the drain region 111e.

[0085] Next, an interlayer insulating layer 114 is formed over the gate insulating layer 112 and the gate electrodes 113 and 128. Next, a semiconductor layer is formed over the interlayer insulating layer 114 and processed by a photolithography process to form an oxide semiconductor layer 121. Next, an insulating layer is formed over the interlayer insulating layer 114 and the oxide semiconductor layer 121. The insulating layer functions as the interlayer insulating layer 116 in the transistor 110 and functions as the gate insulating layer 122 in the transistor 120.

[0086] Next, the interlayer insulating layers 114 and 116 are processed by a photolithography process to form an opening 115c that reaches the gate electrode 128. Next, a conductive layer is deposited on the interlayer insulating layer 116 and inside the opening 115c. The deposited conductive layer is processed by a photolithography process to form a wiring 119 and a gate electrode 123.

[0087] 9, an interlayer insulating layer 126 is formed on the interlayer insulating layer 116, on the wiring 119, and on the gate electrode 123. The interlayer insulating layers 116 and 126 are processed by a photolithography process to form openings 127d and 127e reaching the source region 121d and the drain region 121e of the oxide semiconductor layer 121.

[0088] 10, first, a metal nitride layer 124 is formed on the interlayer insulating layer 126 and inside the openings 127d and 127e. The formed metal nitride layer 124, the gate insulating layer 112, and the interlayer insulating layers 114, 116, and 126 are processed by a photolithography process to form openings 115a and 115b reaching the source region 111d and the drain region 111e of the semiconductor layer 111.

[0089] 11, a conductive layer 125 is formed on the metal nitride layer 124 and inside the openings 115a and 115b. The formed conductive layer 125 is processed by a photolithography process to form the source electrode 125a and the drain electrode 125b shown in FIG.

[0090] As described above, since the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, an increase in contact resistance can be suppressed. Furthermore, since the semiconductor layer 111 contacts the source electrode 125a and the drain electrode 125b without a metal nitride layer therebetween, an increase in contact resistance can be suppressed.

[0091] [3. Third embodiment] An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIGS.

[0092] [3-1. Configuration of semiconductor device] Fig. 12 is a cross-sectional view of the semiconductor device 100 taken along line A1-A2, similar to Fig. 1. As shown in Fig. 1 and Fig. 12, the semiconductor device 100 according to one embodiment of the present invention has a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110.

[0093] The configuration of the transistor 110 shown in Fig. 12 is almost the same as the configuration of the transistor 110 shown in Fig. 7. However, while the insulating layers provided between the semiconductor layer 111 and the source electrode 125a (and the drain electrode 125b) are the gate insulating layer 112 and the interlayer insulating layers 114, 116, and 126 in Fig. 7, the insulating layers are the gate insulating layer 112 and the interlayer insulating layer 114 in Fig. 12. That is, the metal nitride layers 124a and 124b are in contact with the upper surface of the interlayer insulating layer 114 in Fig. 12.

[0094] 12, a metal nitride layer 118 is provided on the interlayer insulating layer 114. A wiring 119 is provided on the metal nitride layer 118. The wiring 119 is connected to the gate electrode 128 through an opening 115c provided in the interlayer insulating layer 114. The metal nitride layer 118 is formed only on the upper surface of the interlayer insulating layer 114, and is not formed on the sidewall of the opening 115c or the upper surface of the gate electrode 128.

[0095] 12, an oxide semiconductor layer 121 is provided on a gate insulating layer 129. Metal nitride layers 124c and 124d are provided on the upper surface and side surfaces of the oxide semiconductor layer 121. A source electrode 125c and a drain electrode 125d are provided on the upper surfaces of the metal nitride layers 124c and 124d.

[0096] The source electrode 125c and the metal nitride layer 124c are provided in a region including the source region 121d. The drain electrode 125d and the metal nitride layer 124d are provided in a region including the drain region 121e. The metal nitride layers 124c and 124d, the source electrode 125c, and the drain electrode 125d are not provided in the channel region 121a. In other words, the oxide semiconductor layer 121 in the channel region 121a is exposed from the metal nitride layer and the conductive layer formed thereon.

[0097] 12, a voltage for controlling the channel region 121a is supplied to the gate electrode 128. That is, the transistor 120 is a bottom-gate transistor.

[0098] The above configuration can be restated as follows. The first insulating layer (interlayer insulating layer 114) is the same layer as the third gate insulating layer (gate insulating layer 129). The first gate electrode (gate electrode 113) is the same layer as the third gate electrode (gate electrode 128). The first metal nitride layer (metal nitride layers 124c, 124d) contacts the upper surface and side surface of the second semiconductor layer (oxide semiconductor layer 121). The first insulating layer (interlayer insulating layer 114) has openings 115a, 115b. The first electrodes (source electrode 125a and drain electrode 125b) are provided above the first insulating layer (interlayer insulating layer 114) and inside the openings 115a, 115b, and contact the first semiconductor layer (semiconductor layer 111). The second metal nitride layer (metal nitride layers 124a, 124b) is provided above the first insulating layer (interlayer insulating layer 114) and between the first insulating layer (interlayer insulating layer 114) and the first electrodes (source electrode 125a and drain electrode 125b).

[0099] [3-2. Manufacturing method of semiconductor device 100] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 13 to 15. Figures 13 to 15 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0100] 13 is the same as the manufacturing method shown in Fig. 3 up to the step of forming the oxide semiconductor layer 121, and therefore a description thereof will be omitted. As shown in Fig. 13, after the oxide semiconductor layer 121 is formed, a metal nitride layer 124 is formed on the interlayer insulating layer 114 and on the oxide semiconductor layer 121.

[0101] As shown in FIG. 14, the deposited metal nitride layer 124, gate insulating layer 112, and interlayer insulating layer 114 are processed by a photolithography process to form openings 115a, 115b reaching the source region 111d and drain region 111e of the semiconductor layer 111, as well as an opening 115c reaching the gate electrode 128.

[0102] 15, a conductive layer 125 is formed on the metal nitride layer 124 and inside the openings 115a, 115b, and 115c. The formed conductive layer 125 is processed by a photolithography process to form the metal nitride layers 124a, 124b, 124c, 124d, and 118, the source electrodes 125a and 125c, the drain electrodes 125b and 125d, and the wiring 119 shown in FIG.

[0103] As described above, since the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, an increase in contact resistance can be suppressed. Furthermore, since the semiconductor layer 111 contacts the source electrode 125a and the drain electrode 125b without a metal nitride layer therebetween, an increase in contact resistance can be suppressed.

[0104] [4. Fourth embodiment] An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIGS.

[0105] [4-1. Configuration of semiconductor device] Fig. 16 is a cross-sectional view of the semiconductor device 100 taken along line A1-A2, similar to Fig. 1. As shown in Fig. 1 and Fig. 16, the semiconductor device 100 according to one embodiment of the present invention has a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110.

[0106] The configuration of each of the transistors 110, 120 shown in FIG. 16 is similar to the configuration of each of the transistors 110, 120 shown in FIG. 12, but differs in the region where the metal nitride layer is provided.

[0107] 12, metal nitride layers 124a, 124b are provided between the source electrode 125a and the interlayer insulating layer 114 and between the drain electrode 125b and the interlayer insulating layer 114, but in the transistor 120 shown in Fig. 16, no metal nitride layers are provided in the same positions as above. That is, the source electrode 125a and the drain electrode 125b are in contact with the upper surface of the interlayer insulating layer 114.

[0108] 12, the metal nitride layer 118 is provided between the wiring 119 and the interlayer insulating layer 114, but the metal nitride layer is not provided in the same position as above in the transistor 120 shown in FIG 16. That is, the source electrode 125a and the drain electrode 125b are in contact with the upper surface of the interlayer insulating layer 114.

[0109] 12, the metal nitride layers 124c and 124d are formed from the top surface of the oxide semiconductor layer 121, over the side surfaces of the oxide semiconductor layer 121, to the top surface of the interlayer insulating layer 114, whereas in the transistor 120 shown in Fig. 16, the metal nitride layers 124c and 124d are formed only on the top surface of the oxide semiconductor layer 121. In other words, the metal nitride layers 124c and 124d are not formed on the side surfaces of the oxide semiconductor layer 121, and are in contact with the source electrode 125c and the drain electrode 125d provided above the metal nitride layers 124c and 124d.

[0110] [4-2. Manufacturing method of semiconductor device 100] A method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to Figures 17 to 19. Figures 17 to 19 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0111] 17 is the same as the manufacturing method shown in Fig. 3 up to the step of forming the interlayer insulating layer 114, and therefore a description thereof will be omitted. After the interlayer insulating layer 114 is formed, an oxide semiconductor layer 121 and a metal nitride layer 124 are formed on the interlayer insulating layer 114.

[0112] 18, the formed oxide semiconductor layer 121 and metal nitride layer 124 are processed by a photolithography process. Next, the gate insulating layer 112 and the interlayer insulating layer 114 are processed by a photolithography process to form openings 115a and 115b reaching the source region 111d and the drain region 111e of the semiconductor layer 111, and an opening 115c reaching the gate electrode 128.

[0113] 19, a conductive layer 125 is formed on the metal nitride layer 124 and inside the openings 115a, 115b, and 115c. The formed conductive layer 125 is processed by a photolithography process to form metal nitride layers 124c and 124d, source electrodes 125a and 125c, drain electrodes 125b and 125d, and a wiring 119 shown in FIG.

[0114] As described above, since the metal nitride layer 124c is provided between the oxide semiconductor layer 121 and the source electrode 125c, and the metal nitride layer 124d is provided between the oxide semiconductor layer 121 and the drain electrode 125d, an increase in contact resistance can be suppressed. Furthermore, since the semiconductor layer 111 contacts the source electrode 125a and the drain electrode 125b without a metal nitride layer therebetween, an increase in contact resistance can be suppressed.

[0115] [5. Fifth Embodiment] An example of the structure of a semiconductor device 100 according to an embodiment of the present invention will be described with reference to FIG.

[0116] [5-1. Configuration of semiconductor device] Fig. 20 is a cross-sectional view of the semiconductor device 100 taken along line A1-A2, similar to Fig. 1. As shown in Fig. 1 and Fig. 20, the semiconductor device 100 according to one embodiment of the present invention has a transistor 110 provided on a substrate 101 and a transistor 120 provided on the transistor 110.

[0117] The configuration of the transistor 120 shown in FIG. 20 is similar to the configuration of each of the transistors 120 shown in FIG. 12, but differs from the transistor 120 shown in FIG. 12 in that a gate electrode 123 is provided above the oxide semiconductor layer 121. In the transistor 120 shown in FIG. 20, a voltage for controlling the channel region 121a is supplied to the gate electrodes 123 and 128. That is, the transistor 120 is a dual-gate type transistor. In the transistor 120, the voltage for controlling the channel region 121a may not be supplied to the gate electrode 128, and a predetermined fixed voltage may be supplied thereto. The gate electrode 128 may be floating. The transistor 120 may be a top-gate type transistor in which the gate electrode 128 is omitted and a voltage for controlling the channel region 121a is supplied only to the gate electrode 123.

[0118] 12, an interlayer insulating layer 126 is formed, a conductive layer is formed over the interlayer insulating layer 126, and the conductive layer is processed into the shape of the gate electrode 123 by a photolithography process. The interlayer insulating layer 126 functions as a gate insulating layer.

[0119] The semiconductor device 100 according to this embodiment can also provide the same effects as the other embodiments described above.

[0120] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0121] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0122] 100: semiconductor device, 101: substrate, 110: transistor, 111: semiconductor layer, 111a: channel region, 111b, 111c: low concentration impurity regions, 111d: source region, 111e: drain region, 112: gate insulating layer, 113: gate electrode, 114: interlayer insulating layer, 115a, 115b, 115c: opening, 116: interlayer insulating layer, 117a: source electrode, 117b: drain electrode, 118: metal nitride layer, 119: wiring, 120: transistor, 121: oxide semiconductor layer, 121a: channel region, 121d: source region, 121e: drain region, 122: gate insulating layer, 123: gate electrode, 124: metal nitride layer, 125: conductive layer, 125a, 125c: source electrodes; 125b, 125d: drain electrodes; 126: interlayer insulating layer; 127d, 127e: openings; 128: gate electrode; 129: gate insulating layer

Claims

1. A first semiconductor layer; a first gate electrode facing the first semiconductor layer; a first gate insulating layer between the first semiconductor layer and the first gate electrode; a first insulating layer provided above the first gate electrode; a first electrode provided in a region overlapping with the first semiconductor layer in a plan view and electrically connected to the first semiconductor layer; a second semiconductor layer provided above the first insulating layer and made of a material different from that of the first semiconductor layer; a second gate electrode facing the second semiconductor layer; a second gate insulating layer between the second semiconductor layer and the second gate electrode; a second electrode provided in a region overlapping with the second semiconductor layer in a plan view and electrically connected to the second semiconductor layer; a first metal nitride layer between the second semiconductor layer and the second electrode; the second semiconductor layer is polycrystalline; A semiconductor device, wherein the etching rate of the second semiconductor layer in an etching solution containing phosphoric acid as a main component at a temperature of 40° C. is less than 3 nm / min.

2. The semiconductor device according to claim 1 , wherein the first metal nitride layer contains the same metal element as the metal element contained in the second electrode.

3. the second electrode includes a first conductive layer and a second conductive layer on the first conductive layer; the first conductive layer is in contact with the first metal nitride layer; The semiconductor device according to claim 1 , wherein the first metal nitride layer contains the same metal element as the metal element contained in the first conductive layer.

4. The semiconductor device according to claim 1 , wherein the first metal nitride layer is in contact with the second semiconductor layer.

5. a second insulating layer above the first insulating layer; a third gate electrode facing the second semiconductor layer below the first insulating layer; a third gate insulating layer between the second semiconductor layer and the third gate electrode, the second gate electrode is provided above the second insulating layer, An opening is provided in each of the first insulating layer and the second insulating layer, the first electrode is provided above the second insulating layer and within the opening, 4. The semiconductor device according to claim 1, wherein the first electrode and the second gate electrode are in the same layer.

6. a second metal nitride layer; a second insulating layer above the first insulating layer, An opening is provided in each of the first insulating layer and the second insulating layer, 4 . The semiconductor device according to claim 1 , wherein the first electrode is provided above the second insulating layer and inside the opening, and is in contact with the first semiconductor layer.

7. The semiconductor device according to claim 6 , wherein the second metal nitride layer is provided above the second insulating layer and between the second insulating layer and the first electrode.

8. the first insulating layer is the same layer as the third gate insulating layer, 6. The semiconductor device according to claim 5, wherein said first gate electrode and said third gate electrode are in the same layer.

9. The semiconductor device according to claim 8 , wherein the first metal nitride layer contacts an upper surface and a side surface of the second semiconductor layer.

10. Further comprising a second metal nitride layer; The first insulating layer has an opening, The semiconductor device according to claim 8 , wherein the first electrode is provided above the first insulating layer and inside the opening, and is in contact with the first semiconductor layer.

11. The semiconductor device according to claim 10 , wherein the second metal nitride layer is provided above the first insulating layer and between the first insulating layer and the first electrode.

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