Display device and mother board for display device

Abstract

To provide a display device capable of improving yield.SOLUTION: In an embodiment, a display device includes a lower electrode, a rib layer, a first partition wall, an organic layer, an upper electrode, and a second partition wall. The lower electrode is disposed in a display region to display images. The rib layer is disposed in the display region and a peripheral region around the display region, and has a pixel opening overlapping with the lower electrode. The first partition wall is disposed over the rib layer in the display region. The organic layer is in contact with the lower electrode through the pixel opening and emits light in accordance with voltage application. The upper electrode covers the organic layer and is in contact with the first partition wall. The second partition wall is disposed over the rib layer in the peripheral region. Each of the first partition wall and the second partition wall includes a lower part disposed over the rib layer and an upper part having an end part projecting from a side surface of the lower part. In addition, the second partition wall includes a plurality of segments that are apart from each other and each segment includes a plurality of openings.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present invention relates to a display device and a mother substrate for the display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that enables improvement of yields in this type of display device is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2000-195677 A [Patent Document 2] JP 2004-207217 A [Patent Document 3] JP 2008-135325 A [Patent Document 4] JP 2009-32673 A [Patent Document 5] JP 2010-118191 A [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a mother substrate for the display device that can improve the yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes a lower electrode, a rib layer, a first partition, an organic layer, an upper electrode, and a second partition. The lower electrode is disposed in a display region that displays an image. The rib layer is disposed in the display region and a peripheral region around the display region, and has a pixel opening overlapping the lower electrode. The first partition is disposed above the rib layer in the display region. The organic layer contacts the lower electrode through the pixel opening and emits light in response to application of a voltage. The upper electrode covers the organic layer and contacts the first partition. The second partition is disposed above the rib layer in the peripheral region. Each of the first partition and the second partition includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. Furthermore, the second partition includes a plurality of segments spaced apart from each other, and each of the plurality of segments has a plurality of openings.

[0006] According to an embodiment, a mother substrate for a display device includes a plurality of panel sections, a marginal region around the plurality of panel sections, a lower electrode, a rib layer, a first partition wall, an organic layer, an upper electrode, and a second partition wall. The plurality of panel sections each include a display region and a peripheral region around the display region. The lower electrode is disposed in the display region. The rib layer has a pixel opening overlapping with the lower electrode. The first partition wall is disposed above the rib layer in the display region. The organic layer contacts the lower electrode through the pixel opening and emits light in response to application of a voltage. The upper electrode covers the organic layer and contacts the first partition wall. The second partition wall is disposed above the rib layer in at least one of the peripheral region and the marginal region. Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion. Furthermore, the second partition includes a plurality of segments spaced apart from one another, and each of the plurality of segments has a plurality of openings. [Brief description of the drawings]

[0007] [Figure 1]FIG. 1 is a diagram showing an example of the configuration of a display device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Diagram 3] FIG. 3 is a schematic cross-sectional view of the display panel taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of the motherboard according to the first embodiment. [Diagram 5] FIG. 5 is a schematic plan view of a portion of the motherboard according to the first embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an example of the partition wall (second partition wall) according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view of the motherboard taken along line VII-VII in FIG. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a step of forming a panel portion on a mother substrate. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a schematic cross-sectional view showing a step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a schematic cross-sectional view showing a step subsequent to FIG. 8F. [Figure 9] FIG. 9 is a schematic plan view of a plurality of segments according to the second embodiment. [Figure 10] FIG. 10 is a schematic plan view of a plurality of segments according to the third embodiment. [Figure 11] FIG. 11 is a schematic plan view of a plurality of segments according to the fourth embodiment. [Figure 12]FIG. 12 is a schematic plan view of a plurality of segments according to the fifth embodiment. [Figure 13] FIG. 13 is a schematic plan view of a plurality of segments according to the sixth embodiment. [Figure 14] FIG. 14 is a schematic plan view of a plurality of segments according to the seventh embodiment. [Figure 15] FIG. 15 is a schematic plan view of a plurality of segments according to the eighth embodiment. [Figure 16] FIG. 16 is a schematic plan view showing another example of an arrangement of a plurality of segments according to the eighth embodiment. [Figure 17] FIG. 17 is a schematic plan view showing yet another example of an arrangement of a plurality of segments according to the eighth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and those who are skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. In addition, the drawings may be schematic in width, thickness, shape, etc. of each part compared to the actual embodiment in order to make the explanation clearer, but they are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each figure, components that perform the same or similar functions as those described above with respect to the previous figures are given the same reference numerals, and duplicate detailed explanations may be omitted as appropriate.

[0009] In addition, in the drawings, an X-axis, a Y-axis, and a Z-axis that are perpendicular to each other are shown as necessary to facilitate understanding. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of a plane that includes the X-direction and the Y-direction. Moreover, viewing various elements parallel to the Z-direction is called planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing a configuration example of a display device DSP according to a first embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The display panel PNL has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in a plan view is rectangular. However, the shape of the substrate 10 in a plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. The pixels PX include a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. However, the pixel PX may include subpixels SP of other colors, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements constituted by, for example, thin film transistors.

[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power lines PL. In the example of Fig. 1, the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0017] It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and a column in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG.

[0020] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 2, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio, and the subpixel SP3 has the smallest aperture ratio.

[0021] The subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap the pixel aperture AP3.

[0022] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 overlapping with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 overlapping with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 overlapping with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] A conductive partition wall 6A (first partition wall) is disposed above the rib layer 5. The partition wall 6A entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. That is, the partition wall 6A has openings in each of the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition wall 6A are lattice-shaped in a planar view and surround each of the display elements DE1, DE2, and DE3. The partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0024] Fig. 3 is a schematic cross-sectional view of the display panel PNL taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power lines PL shown in Fig. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes unevenness caused by the circuit layer 11.

[0025] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. Ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0026] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6A is called an overhanging shape.

[0027] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In addition, in the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0028] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6A.

[0029] The display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. The display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. The display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0030] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0031] A part of the laminated film FL1 is located on the upper part 62. This part is separated from a part of the laminated film FL1 located around the partition wall 6A (a part that constitutes the display element DE1). Similarly, a part of the laminated film FL2 is located on the upper part 62, and this part is separated from a part of the laminated film FL2 located around the partition wall 6A (a part that constitutes the display element DE2). Furthermore, a part of the laminated film FL3 is located on the upper part 62, and this part is separated from a part of the laminated film FL3 located around the partition wall 6A (a part that constitutes the display element DE3).

[0032] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6A around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6A around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6A around the subpixel SP3.

[0033] 3, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6A. Also, the laminated film FL1 and the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6A.

[0034] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least throughout the entire display area DA, and a part of them extends into the peripheral area SA.

[0035] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0036] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0037] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0038] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg), etc. For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0039] The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are laminated in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called tandem structure including a plurality of light-emitting layers.

[0040] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, a plurality of transparent layers are stacked. These transparent layers may include layers formed of inorganic materials and layers formed of organic materials. In addition, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0041] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0042] For example, the upper portion 62 of the partition wall 6A has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. The metal material forming the lower layer may be, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. The conductive oxide forming the upper layer may be, for example, ITO or IZO. The upper portion 62 may have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0043] A common voltage is supplied to the partition 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal of the signal line SL is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0044] The organic layers OR1, OR2, and OR3 emit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength region. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength region. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength region.

[0045] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0046] When manufacturing the display device DSP, a large-sized mother substrate on which a plurality of regions (panel portions) each corresponding to the display panel PNL are formed is prepared. A configuration applicable to this mother substrate will be described below.

[0047] 4 is a schematic plan view of a mother substrate MB (mother substrate for display devices) according to this embodiment. The mother substrate MB is rectangular as shown in the figure, but may be other shapes such as circular. The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA around the panel portions PP.

[0048] 5 is a schematic plan view of a portion of the mother substrate MB. The outer shape of each panel portion PP corresponds to a cut line CL1 for cutting out the panel portion PP from the mother substrate MB.

[0049] Each panel unit PP has the display area DA and the peripheral area SA described above. Furthermore, each panel unit PP has an inspection area TA. In the inspection area TA, inspection pads for inspecting the operation of the display panel PNL are arranged.

[0050] A cut line CL2 is formed between the peripheral area SA and the inspection area TA. When manufacturing the display device DSP, first, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Furthermore, the above-mentioned inspection is performed on the cut-out panel portion PP. After this inspection, the inspection area TA is cut off from the panel portion PP along the cut line CL2.

[0051] In this embodiment, partitions 6B (second partitions) are arranged in the blank area BA, the peripheral area SA, and the inspection area TA. In Fig. 5, a lattice pattern is applied to the area where the partitions 6B are arranged. Note that this lattice pattern does not represent the shape of the partitions 6B itself.

[0052] From the viewpoint of efficiently cutting out the panel portion PP, it is preferable that the partition walls 6B are not provided at the cut line CL1, and similarly, it is preferable that the partition walls 6B are not provided at the cut line CL2.

[0053] Fig. 6 is a schematic plan view showing an example of a partition 6B. The partition 6B has a plurality of segments SG spaced apart from each other. In the example of Fig. 6, these segments SG have the same shape and are aligned in the X direction and the Y direction. Each segment SG is a quadrangle (rectangle or square) having two sides extending in the X direction and two sides extending in the Y direction.

[0054] The segment SG has three apertures APa, APb, and APc. The apertures APa, APb, and APc are arranged in a layout similar to that of the pixel apertures AP1, AP2, and AP3, for example. That is, in the example of FIG. 6, the apertures APb and APc are aligned with the aperture APa in the X direction. Furthermore, the apertures APb and APc are aligned with the aperture APa in the Y direction. Moreover, the apertures APb and APc are smaller than the aperture APa. The sizes of the apertures APb and APc are, for example, the same, but may be different from each other.

[0055] Between adjacent segments SG, there is formed a gap G. In the example of Fig. 6, the gap G has a lattice shape including a portion extending in the X direction and a portion extending in the Y direction.

[0056] The segment SG has a width Wx in the X direction and a width Wy in the Y direction. The gap G has a uniform width Wg overall, although the gap G may vary partially.

[0057] The widths Wx and Wy are, for example, each equal to or greater than the width in the X direction and the width in the Y direction of the pixel PX, but are not limited to this example. The widths Wx and Wy may be the same or different from each other. The width Wg is, for example, smaller than the widths Wx and Wy (Wg < Wx, Wy). Preferably, the width Wg is 40 μm or less (Wg ≦ 40 μm). Thereby, as will be described later, the effect of suppressing the peeling of the laminated films FL1, FL2, and FL3 is enhanced.

[0058] Note that the segment SG having the shape shown in FIG. 6 does not necessarily have to be arranged over the entire blank area BA, peripheral area SA, and inspection area TA. Other-shaped segments (partition walls 6B) may be arranged in at least a part of the blank area BA, peripheral area SA, and inspection area TA.

[0059] Also, the shape of the segment SG is not limited to the quadrilateral as shown in FIG. 6, and may be other polygonal shapes or a shape including a curved contour. The number and shape of the openings that the segment SG has are not limited to the example of FIG. 6.

[0060] FIG. 7 is a schematic cross-sectional view of the mother substrate MB along line VII-VII in FIG. 6. The partition wall 6B is arranged on the rib layer 5, similarly to the partition wall 6A. In the example of FIG. 7, a circuit layer 11 and an organic insulating layer 12 are arranged between the rib layer 5 and the substrate 10. In at least a part of the blank area BA, peripheral area SA, and inspection area TA, the circuit layer 11 and the organic insulating layer 12 may not be arranged.

[0061] The partition wall 6B includes a lower part 61 and an upper part 62, similarly to the partition wall 6A. Further, the lower part 61 of the partition wall 6B includes a bottom layer 63 and a shaft layer 64. Also in the partition wall 6B, the end of the upper part 62 protrudes from the side surface of the lower part 61 (shaft layer 64).

[0062] In the openings APa, APb, APc and the gap G, the rib layer 5 is exposed from the partition wall 6B. The width Wg of the above-described gap G corresponds to the distance between the upper parts 62 of the adjacent segments SG via the gap G.

[0063] Next, an example of a manufacturing method of the display device DSP will be described. Figures 8A to 8G are schematic cross-sectional views showing the process of forming a panel part PP on a mother substrate MB. In Figures 8A to 8G, attention is mainly focused on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0064] In forming the panel portion PP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10 of a motherboard MB. Next, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12, as shown in FIG. 8A.

[0065] Subsequently, as shown in Fig. 8B, the rib layer 5 and the partition wall 6A are formed. The pixel openings AP1, AP2, and AP3 of the rib layer 5 may be provided after or before the formation of the partition wall 6A. The partition wall 6B shown in Fig. 7 is formed in the same process as the partition wall 6A.

[0066] After the rib layer 5 and the partition walls 6A and 6B are formed, a process for forming the display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order of forming the display elements DE1, DE2, and DE3 is not limited to this example.

[0067] In forming the display element DE1, first, as shown in Fig. 8C, a laminated film FL1 and a sealing layer SE11 are formed. As shown in Fig. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1.

[0068] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by deposition, and the sealing layer SE11 is formed by CVD (Chemical Vapor Deposition).

[0069] The laminated film FL1 and the sealing layer SE11 are formed on the entire mother substrate MB including not only the display area DA of each panel unit PP but also the peripheral area SA, the inspection area TA, and the blank area BA. The laminated film FL1 is divided into a plurality of parts by overhanging partition walls 6A and 6B. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6A and 6B.

[0070] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R is disposed on the sealing layer SE11 as shown in Fig. 8D. The resist R covers the subpixel SP1 and a part of the partition wall 6A around it.

[0071] Thereafter, by etching using the resist R as a mask, the laminated film FL1 and the sealing layer SE11 are removed in portions exposed from the resist R as shown in FIG. 8E. In other words, the laminated film FL1 and the sealing layer SE11 are left in portions overlapping with the lower electrode LE1, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, in the peripheral area SA, the inspection area TA, and the blank area BA, the laminated film FL1 and the sealing layer SE11 are removed by this etching. This etching may include wet etching or dry etching that is performed in order on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R is removed.

[0072] The display element DE2 is formed in the same manner as the display element DE1. That is, in forming the display element DE2, a laminated film FL2 and a sealing layer SE12 are formed on the entire mother substrate MB. As shown in FIG. 3, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0073] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by deposition. The sealing layer SE12 is formed by CVD. The laminated film FL2 is divided into a plurality of parts by overhanging partition walls 6A and 6B. The sealing layer SE12 continuously covers each divided part of the laminated film FL2 and the partition walls 6A and 6B. By patterning such laminated film FL2 and sealing layer SE2, a display element DE2 is formed in the subpixel SP2 as shown in FIG. 8F. For example, in the peripheral area SA, the inspection area TA, and the blank area BA, the laminated film FL2 and the sealing layer SE12 are removed by etching during the patterning.

[0074] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when the display element DE3 is formed, a laminated film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, the laminated film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0075] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by deposition. The sealing layer SE13 is formed by CVD. The laminated film FL3 is divided into a plurality of parts by overhanging partition walls 6A and 6B. The sealing layer SE13 continuously covers each divided part of the laminated film FL3 and the partition walls 6A and 6B. By patterning such laminated film FL3 and sealing layer SE13, a display element DE3 is formed in the subpixel SP3 as shown in FIG. 8G. For example, in the peripheral area SA, the inspection area TA, and the blank area BA, the laminated film FL3 and the sealing layer SE13 are removed by etching during the patterning.

[0076] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 are formed in this order as shown in Fig. 3. Furthermore, each panel portion PP is cut out from the mother substrate MB along the cut line CL1.

[0077] After that, each panel portion PP is inspected. This inspection includes an inspection of the lighting of each display element DE1, DE2, DE3 using inspection pads arranged in the inspection area TA. After the inspection, the inspection area TA is cut along the cut line CL2. This completes the display panel PNL.

[0078] At least one of the laminated films FL1, FL2, FL3 may be left without being removed in the peripheral area SA, the inspection area TA, and the blank area BA.

[0079] Here, some advantages of this embodiment will be described. When the display elements DE1, DE2, DE3 are formed, the laminated films FL1, FL2, FL3 are formed over the entire mother substrate MB. The laminated films FL1, FL2, FL3 formed by vapor deposition have poor adhesion to the base, so there is a possibility that they will peel off from the base during the manufacturing process of the display device DSP. If this peeling spreads, the laminated films FL1, FL2, FL3 and the sealing layers SE11, SE12, SE13 thereon will peel off and become undesirable particles.

[0080] In the display area DA, the stacked films FL1, FL2, and FL3 are finely divided by the lattice-shaped partitions 6A. Therefore, the stacked films FL1, FL2, and FL3 are unlikely to peel off from the base. In addition, in this embodiment, partitions 6B are arranged in the peripheral area SA, the inspection area TA, and the margin area BA. This prevents the stacked films FL1, FL2, and FL3 from peeling off in the peripheral area SA, the inspection area TA, and the margin area BA.

[0081] 6, the partition 6B includes a plurality of segments SG, and each segment SG has a plurality of openings APa, APb, APc. With this configuration, the stacked films FL1, FL2, FL3 are finely divided in the peripheral area SA, the inspection area TA, and the blank area BA, which enhances the effect of suppressing peeling of the stacked films FL1, FL2, FL3.

[0082] If the partitions 6B are not divided into multiple segments SG and are arranged over a wide area without gaps, the partitions 6B form a relatively large single conductor. In this case, electrostatic discharge (ESD) is likely to occur due to the partitions 6B. If electrostatic discharge occurs, the partitions 6B and the surrounding elements may be damaged.

[0083] Furthermore, if the partition wall 6B is not divided into a plurality of segments SG, there is a possibility that the resist (for example, the resist for patterning the rib layer 5) disposed behind the partition wall 6B may be poorly formed. That is, the partition wall 6B may suppress the spread of the resist, and there may be a portion under the upper portion 62 of the partition wall 6B where the resist is not sufficiently filled. In this case, when the resist is dried in a reduced pressure environment, the space where the resist is not disposed may expand and burst.

[0084] In the present embodiment, when the partition 6B is composed of a plurality of segments SG spaced apart by gaps G, the partition 6B, which is a conductor, is segmented, making it difficult for the electrostatic discharge to occur. In addition, the resist spreads easily through the gaps G, which can prevent the resist from being deformed.

[0085] If the width Wg is too large, the effect of suppressing peeling of the laminated films FL1, FL2, and FL3 may decrease. In relation to this point, the inventors' verification confirmed that, as described above, if the width Wg is 40 μm or less, peeling of the laminated films FL1, FL2, and FL3 can be suppressed satisfactorily.

[0086] In this way, the configuration according to this embodiment can suppress peeling of the laminated films FL1, FL2, FL3, electrostatic discharge, or defective resist shapes, and can improve the yield during the manufacture of the display devices DSP and mother substrates MB.

[0087] The shape and arrangement of the segments SG that form the partition wall 6B are not limited to those shown in Fig. 6. In the following second to eighth embodiments, other examples that can be applied to the segments SG will be disclosed.

[0088] [Second embodiment] Fig. 9 is a schematic plan view of a plurality of segments SG according to the second embodiment. In this embodiment, the segments SG adjacent in the Y direction are shifted in the X direction. Specifically, in the example of Fig. 9, a first row RW1 including a plurality of segments SG1 (first segments) aligned in the X direction (first direction) and a second row RW2 including a plurality of segments SG2 (second segments) aligned in the X direction are formed. In the Y direction (second direction), the first row RW1 and the second row RW2 are alternately arranged.

[0089] The segments SG1 and SG2 are shifted in the X direction, so that a T-shaped gap G between the segments SG1 and SG2 is formed, for example, as in the portion surrounded by the dashed circle C1.

[0090] When peeling of the above-mentioned stacked films FL1, FL2, and FL3 occurs in the gap G, the peeling tends to progress over a wide area if the gap G is linear. In contrast, when the gap G is T-shaped and the peeling progresses in the direction indicated by the arrow A in FIG. 9, the segment SG2 located in the direction of the progress of the peeling suppresses the peeling from spreading further.

[0091] 9 shows an example in which the segments SG adjacent in the Y direction are shifted in the X direction. As another example, the segments SG adjacent in the X direction may be shifted in the Y direction.

[0092] [Third embodiment] 10 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG3) according to the third embodiment. The segments SG3 have a stepped (zigzag) planar shape.

[0093] The segment SG3 has a number of openings APa, APb, and APc. The segment SG3 has a polygonal shape with an interior angle θ larger than 180°. In the example of FIG. 10, the interior angle θ is 270°.

[0094] Between adjacent segments SG3, a stepped gap G is formed. That is, as shown in the portion surrounded by the dashed circle C2, the gap G is bent in an L-shape. Even with this configuration, it is possible to suppress the spread of peeling of the stacked films FL1, FL2, and FL3 along the gap G.

[0095] The gap G has, for example, a uniform width Wg over the entire gap G. The width Wg is preferably 40 μm or less, as in the first embodiment. The width Wg may vary partially.

[0096] [Fourth embodiment] 11 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG4) according to the fourth embodiment. The segment SG4 has a V-shaped planar shape. Specifically, the segment SG4 has a first portion P4a, a second portion P4b, and a third portion P4c that connects the first portion P4a and the second portion P4b. The first portion P4a and the second portion P4b extend in different directions. The directions in which the first portion P4a and the second portion P4b extend intersect with, for example, the X direction and the Y direction.

[0097] The first portion P4a and the second portion P4b are stepped like the segment SG3 shown in Fig. 10. The first portion P4a, the second portion P4b and the third portion P4c have a large number of openings APa, APb, APc.

[0098] The multiple segments SG4 are arranged such that the first portions P4a are aligned in the X direction, the second portions P4b are aligned in the X direction, and the third portions P4c are aligned in the X direction. Between the first portions P4a of adjacent segments SG4 and between the second portions P4b of adjacent segments SG4, the gaps G are stepped.

[0099] 11, the gap G is wider in a region Ga located between the third portions P4c of adjacent segments SG4. In one example, the width Wg of the gap G is 40 μm or less except for the region Ga. However, the shape of each segment SG4 may be determined so that the width Wg is uniform throughout the gap G.

[0100] [Fifth embodiment] Fig. 12 is a schematic plan view of a plurality of segments SG according to the fifth embodiment. In the example of Fig. 12, a plurality of types of segments SG51 to SG57 having different shapes are arranged. Each of the segments SG51 to SG57 has a number of openings APa, APb, and APc.

[0101] Segment SG51 has a complex planar shape with many arms protruding from a rectangular center. Segment SG52 is a rectangular shape elongated in the Y direction. Segment SG53 is a rectangular shape elongated in the X direction. Segment SG54 is L-shaped with a portion extending in the X direction and a portion extending in the Y direction. Segment SG55 is L-shaped by rotating segment SG54 90° clockwise. Segment SG56 is L-shaped by rotating segment SG55 90° clockwise. Segment SG57 is L-shaped by rotating segment SG56 90° clockwise. Segments SG51, SG54 to SG57 are polygonal shapes with at least one interior angle greater than 180°, specifically, an interior angle of 270°, like segment SG3 and the like.

[0102] As an example of the arms of the segment SG51, attention is focused on the first arm P51a and the second arm P51b extending in the Y direction. In Fig. 12, the segment SG52 is disposed between the first arm P51a and the second arm P51b. This forms a U-shaped gap G as shown in the area surrounded by the dashed circle C3.

[0103] In addition to the location of interest here, many such U-shaped gaps G are formed around the segment SG51. In the example of Fig. 12, L-shaped gaps G are also formed in various places, such as the area surrounded by the dashed circle C2. In the U-shaped gaps G, the progression of peeling of the stacked films FL1, FL2, and FL3 is suppressed, just like in the L-shaped and T-shaped gaps G.

[0104] In this embodiment as well, it is preferable that the width Wg of the gap G formed between any two adjacent ones of the segments SG51 to SG57 is 40 μm or less. The width Wg may be uniform throughout the gap G, or may vary partially.

[0105] [Sixth embodiment] 13 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG6) according to the sixth embodiment. The segments SG6 have a stepped planar shape that is shorter than the segments SG3 shown in FIG.

[0106] The segment SG6 has a number of openings APa, APb, and APc. Similarly to the segment SG3, the segment SG6 has a polygonal shape with multiple interior angles greater than 180°, specifically multiple interior angles of 270°.

[0107] In the example of Fig. 13, a T-shaped gap G is formed where three segments SG3 are adjacent to each other, as in the area surrounded by a dashed circle C1. Also, an L-shaped gap G is formed between two adjacent segments SG6, as in the area surrounded by a dashed circle C2. In this embodiment, too, it is preferable that the width Wg of the gap G is 40 µm or less. The width Wg may be uniform throughout the gap G, or may vary partially.

[0108] [Seventh embodiment] 14 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG7) according to the seventh embodiment. The segments SG7 have a cross-shaped planar shape. Adjacent segments SG7 are shifted in both the X and Y directions.

[0109] The segment SG7 has a number of openings APa, APb, and APc. Similarly to the segment SG3, the segment SG7 has a polygonal shape having multiple interior angles greater than 180°, specifically, multiple interior angles of 270°.

[0110] 14, an L-shaped gap G is formed between adjacent segments SG7 as shown in the portion surrounded by a dashed circle C2. In this embodiment, the width Wg of the gap G is preferably 40 μm or less. The width Wg may be uniform throughout the gap G or may vary partially.

[0111] [Eighth embodiment] 15 is a schematic plan view of a plurality of segments SG (hereinafter referred to as segments SG8) according to the eighth embodiment. The segment SG8 has a so-called "Manji" shape in plan view. Specifically, the segment SG8 has four arms P81 to P84 extending in different directions.

[0112] The arm P81 is L-shaped having a straight portion L1 extending in the X direction and a straight portion L2 extending in the Y direction. In the example of FIG. 15, the straight portions L1 and L2 are equal in length. The arm P82 is L-shaped by rotating the arm P81 90° clockwise. The arm P83 is L-shaped by rotating the arm P82 90° clockwise. The arm P84 is L-shaped by rotating the arm P83 90° clockwise. Adjacent segments SG8 are offset in both the X direction and the Y direction.

[0113] Segment SG8 has a number of openings APa, APb, and APc. Similarly to segment SG3, segment SG8 has a polygonal shape with multiple interior angles greater than 180°, specifically multiple interior angles of 270°.

[0114] Between the arms P81 and P82 of each segment SG8, ​​a part of the arm P84 of the other segment SG8 is located. Also, between the arms P83 and P84 of each segment SG8, ​​a part of the arm P82 of the other segment SG8 is located. This forms a U-shaped gap G as shown in the area surrounded by the dashed circle C3.

[0115] 15, no other segment SG8 is located between the arms P81 and P84 of each segment SG8, ​​and no other segment SG8 is located between the arms P82 and P83 of each segment SG8.

[0116] 15, the gap G is made up of a plurality of portions having different widths. That is, the gap G is wider in the region Gb between the arms P81, P84 of each segment SG8, ​​the region Gc between the arms P82, P83 of each segment SG8, ​​and the region Gd surrounded by the arms P81-P84 of each different segment SG8 than in the portion surrounded by the dashed circle C3.

[0117] It is preferable that the width Wg of the gap G is 40 μm or less in most parts. In one example, the width Wg of the gap G may be 40 μm or less except for the regions Gb, Gc, and Gd.

[0118] Fig. 16 is a schematic plan view showing another example of the arrangement of the segments SG8. The shape of the segments SG8 shown in this figure is similar to that shown in Fig. 15. However, in the example of Fig. 16, the segments SG8 are arranged so that the areas Gb and Gc shown in Fig. 15 disappear and the area Gd shrinks.

[0119] 16, a part of an arm P83 of each segment SG8 is located between the arm P81 and arm P84 of the other segment SG8, ​​and a part of an arm P81 of each segment SG8 is located between the arm P82 and arm P83 of the other segment SG8.

[0120] In this way, by eliminating the regions Gb and Gc, it is possible to increase the U-shaped portion in the gap G. As a result, even if peeling occurs in the stacked films FL1, FL2, and FL3 in the gap G, the progression of peeling is easily suppressed.

[0121] Fig. 17 is a schematic plan view showing yet another example of the arrangement of the segment SG8. The shape of the segment SG8 shown in this figure differs from that shown in Figs. 15 and 16 in that the straight line portion L2 is shorter than the straight line portion L1 in each of the arms P81 to P84.

[0122] In the example of Fig. 17, the segments SG8 are arranged so that all of the regions Gb, Gc, and Gd shown in Fig. 15 disappear. This makes it possible to make the width Wg of the gap G uniform overall.

[0123] In addition to the first to eighth embodiments, various shapes and arrangements of the segments SG may be applied. Two or more of the segments SG disclosed in each embodiment may be arranged in at least a part of the surrounding area SA, the inspection area TA, and the blank area BA.

[0124] In each embodiment, it is assumed that the partitions 6B (segments SG) are arranged in each of the peripheral area SA, the inspection area TA, and the blank area BA. As another example, the partitions 6B may not be arranged in any of the peripheral area SA, the inspection area TA, and the blank area BA. When the partitions 6B are not arranged in the peripheral area SA, a display panel PNL and a display device DSP that do not include the partitions 6B are manufactured.

[0125] All display devices, motherboards, and manufacturing methods that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices, motherboards, and manufacturing methods disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0126] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, those in which a person skilled in the art appropriately adds or removes components or modifies the design of the above-mentioned embodiment, or adds or omits steps or modifies conditions, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0127] Furthermore, with regard to other effects and advantages brought about by the aspects described in the above-mentioned embodiments, those which are obvious from the description in this specification or which can be appropriately thought up by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0128] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, SG...segment, APa, APb, APc...opening, G...gap.

Claims

1. a lower electrode disposed in a display area for displaying an image; a rib layer disposed in the display region and in a peripheral region around the display region, the rib layer having pixel openings overlapping the lower electrodes; a first partition disposed above the rib layer in the display area; an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and in contact with the first partition wall; a second partition wall disposed above the rib layer in the peripheral region; Equipped with Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion, the second partition wall includes a plurality of segments spaced apart from one another; Each of the plurality of segments has a plurality of openings. Display device.

2. At least a portion of the gaps formed between the plurality of segments has a width of 40 μm or less. The display device according to claim 1 .

3. At least one of the plurality of segments has a plurality of openings of different sizes. The display device according to claim 1 .

4. The plurality of segments include a first row including a plurality of first segments aligned in a first direction; a second row adjacent to the first row in a second direction intersecting the first direction and including a plurality of second segments aligned in the first direction; Including, the first segments and the second segments are offset in the first direction; The display device according to claim 1 .

5. At least one of the plurality of segments is a polygon having an interior angle greater than 180°. The display device according to claim 1 .

6. At least one of the plurality of segments is stepped. The display device according to claim 1 .

7. At least one of the plurality of segments is cross-shaped. The display device according to claim 1 .

8. At least one of the plurality of segments includes a first arm and a second arm; A part of the other segment is disposed between the first arm and the second arm. The display device according to claim 1 .

9. At least one of the plurality of segments has a plurality of arms extending in different directions. The display device according to claim 1 .

10. The gaps formed between the plurality of segments include T-shaped, L-shaped, or U-shaped portions. The display device according to claim 1 .

11. A plurality of panel units each including a display area and a peripheral area around the display area; a margin area around the plurality of panel portions; A lower electrode disposed in the display area; a rib layer having a pixel opening overlapping the lower electrode; a first partition disposed above the rib layer in the display area; an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and in contact with the first partition wall; a second partition wall disposed above the rib layer in at least one of the peripheral region and the marginal region; Equipped with Each of the first partition wall and the second partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion, the second partition wall includes a plurality of segments spaced apart from one another; Each of the plurality of segments has a plurality of openings. Mother board for display devices.

12. At least a portion of the gaps formed between the plurality of segments has a width of 40 μm or less. The mother substrate for a display device according to claim 11.

13. At least one of the plurality of segments has a plurality of openings of different sizes. The mother substrate for a display device according to claim 11.

14. The plurality of segments include a first row including a plurality of first segments aligned in a first direction; a second row adjacent to the first row in a second direction intersecting the first direction and including a plurality of second segments aligned in the first direction; Including, the first segments and the second segments are offset in the first direction; The mother substrate for a display device according to claim 11.

15. At least one of the plurality of segments is a polygon having an interior angle greater than 180°. The mother substrate for a display device according to claim 11.

16. At least one of the plurality of segments is stepped. The mother substrate for a display device according to claim 11.

17. At least one of the plurality of segments is cross-shaped. The mother substrate for a display device according to claim 11.

18. At least one of the plurality of segments includes a first arm and a second arm; A part of the other segment is disposed between the first arm and the second arm. The mother substrate for a display device according to claim 11.

19. At least one of the plurality of segments has a plurality of arms extending in different directions. The mother substrate for a display device according to claim 11.

20. The gaps formed between the plurality of segments include T-shaped, L-shaped, or U-shaped portions. The mother substrate for a display device according to claim 11.

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