Class d amplifier circuit

Abstract

To provide a class D amplifier circuit capable of accurately detecting abnormality even if delay process is performed.SOLUTION: A class D amplifier circuit includes a PWM modulation processing part for performing a PWM modulation process for an inputted signal, a signal amplification part for amplifying the PWM modulated signal with a switching element, and an abnormality detection part for detecting, as an abnormality, the occurrence of a continuous voltage drop for a set time or more in a signal after passing through the signal amplification part.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a class D amplifier circuit. [Background technology]

[0002] In a class D amplifier circuit, which amplifies a PWM (Pulse Width Modulation) modulated signal using a signal amplifier section with switching elements, a transistor with a very large output is used, so if an abnormality such as a ground fault at the output terminal or a short circuit between the output terminals occurs, a large current may be generated and cause the circuit to break down. Therefore, a protection circuit is required to be installed in the class D amplifier circuit to protect the circuit when an abnormality is detected.

[0003] Patent Document 1 discloses a class D amplifier circuit equipped with such a protection circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-017268 A Summary of the Invention [Problem to be solved by the invention]

[0005] In the class D amplifier circuit described in Patent Document 1, a sampling circuit compares the level of a PWM modulated signal with the level of a signal output from a signal amplifier section to detect an abnormality.

[0006] In general, in a class D amplifier circuit, a delay processing section that performs delay processing to prevent a shoot-through current from flowing through a switching element is provided in a pre-driver in the stage preceding the signal amplifier.

[0007] Therefore, a timing discrepancy occurs between the PWM-modulated signal and the timing of the signal output from the signal amplifier, and if the delay and timing discrepancy are large, it may not be possible to accurately detect an abnormality.

[0008] In consideration of the above circumstances, an object of the present disclosure is to provide a class D amplifier circuit that is capable of accurately detecting an abnormality even when delay processing is performed. [Means for solving the problem]

[0009] The class D amplifier circuit disclosed herein comprises a PWM modulation processing unit that performs PWM modulation processing on an input signal, a signal amplification unit that amplifies the PWM modulated signal using a switching element, and an anomaly detection unit that detects an anomaly when a voltage drop occurs continuously for a set period of time or more in the signal after passing through the signal amplification unit. Effect of the Invention

[0010] According to the class D amplifier circuit of the present disclosure, even when delay processing is performed, abnormality can be accurately detected. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating a configuration of a class D amplifier including a class D amplifier circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating a configuration of a pre-driver in the above-mentioned class D amplifier. [Diagram 3] 4 is a graph showing a signal waveform in the above-mentioned class D amplifier. [Figure 4] FIG. 1 is a diagram illustrating a configuration of a class-D amplifier of a comparative example. [Diagram 5] 11 is a graph showing a signal waveform in a class D amplifier of a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Next, an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a diagram showing a circuit configuration of a class D amplifier 1 including a class D amplifier circuit according to an embodiment of the present disclosure. Fig. 2 is a diagram showing a configuration of a pre-driver 20P in the class D amplifier 1.

[0013] 1, a class D amplifier 1 of this embodiment includes an LSI (Large Scale Integration) 10 as a class D amplifier circuit, an external power supply 50 that supplies power to the LSI 10, and a digital signal output unit 51 that outputs a digital audio signal DS to the LSI 10. A speaker RSP is connected to the class D amplifier 1 as a load.

[0014] LSI10 comprises a PWM modulation processing unit 11 that performs PWM modulation processing on the input digital signal DS, a positive side signal circuit unit 12 that processes the positive side signal of the speaker output, a negative side signal circuit unit 13 that processes the negative side signal of the speaker output, and a control unit 14 that controls the overall operation of LSI10.

[0015] The positive side signal circuit unit 12 includes a pre-driver 20P having a delay processing unit 21P (shown in FIG. 2) that performs delay processing on the positive output signal PWMP of the PWM modulated signal, a signal amplification unit 30P that amplifies the signal after passing through the pre-driver 20P using a switching element 31P, and an abnormality detection unit 40P that detects abnormalities in the signal after passing through the signal amplification unit 30P.

[0016] The signal amplifier 30P is the final output stage of the class D amplifier circuit, and includes a switching element 31P including a P-channel transistor P1 and an N-channel transistor N1. Each of the transistors P1 and N1 is, for example, a field effect transistor.

[0017] The source terminal of the P-channel transistor P1 is connected to the external power supply 50 via wiring resistors R1 and ROUT. The source terminal of the N-channel transistor N1 is connected to ground via wiring resistor R2. The drain terminals of the P-channel transistor P1 and the N-channel transistor N1 are connected to each other, and this connection point is connected to the positive output terminal SPOUTP of the speaker.

[0018] The pre-driver 20P distributes the positive output signal PWMP, which is a PWM modulated signal, into two systems and outputs them to the gate terminal of a P-channel transistor P1 and the gate terminal of an N-channel transistor N1.

[0019] In addition, in order to prevent a through current from flowing through the switching element 31P, the pre-driver 20P performs a delay process when outputting a positive output signal PWMP to the P-channel transistor P1 and the N-channel transistor N1 so that the two transistors P1 and N1 are not turned on simultaneously.

[0020] Here, the delay process is a process that prevents the two transistors P1 and N1 from being turned on at the same time, and may be any process, such as providing a dead time during which both transistors P1 and N1 are turned off when switching is turned on and off.

[0021] 2, the pre-driver 20P includes a delay processing unit 21P. The delay processing unit 21P includes a common delay processing unit 22P that performs common delay processing on signals output to the gate terminal of the P-channel transistor P1 and the gate terminal of the N-channel transistor N1, and an individual delay processing unit 23P that performs individual delay processing on signals output to the gate terminal of the P-channel transistor P1 and the gate terminal of the N-channel transistor N1.

[0022] The common delay processing unit 22P is composed of a plurality of buffer circuits, a plurality of buffer resistors, a plurality of buffer capacitors, etc. In the configuration of this embodiment, the logic of the signal after passing through the switching element 31P is inverted with respect to the signal before passing through. Therefore, the common delay processing unit 22P includes a NOT circuit that inverts the logic of the positive output signal PWMP of the PWM modulated signal, and is configured so that the positive output signal PWMP of the PWM modulated signal and the signal after passing through the signal amplifier 30P are in phase. The individual delay processing unit 23P is composed of a buffer circuit.

[0023] The configuration of the delay processing unit 21P is not limited to the above configuration, and may be any circuit that performs processing so that the two transistors P1 and N1 are not turned on at the same time.

[0024] The abnormality detection unit 40P detects an abnormality when a voltage drop occurs continuously for a set period of time or more in the signal that has passed through the signal amplification unit 30P.

[0025] In detail, the abnormality detection unit 40P includes a P-channel transistor 41P, a NOT circuit 42P connected to the gate terminal which is the input terminal of the P-channel transistor 41P and inverts the logic of the signal after passing through the signal amplification unit 30P, an RC parallel circuit 43P connected to the drain terminal which is the output terminal of the P-channel transistor 41P and consisting of a resistor R5 and a capacitance C1 connected in parallel, a NOT circuit 44P connected to the drain terminal of the P-channel transistor 41P and inverts the logic of the output signal of the P-channel transistor 41P, and an AND circuit 45P that performs a logical AND operation on the output signal of the NOT circuit 44P and a signal ENP input from outside indicating that abnormality detection is valid.

[0026] The NOT circuit 42P is an example of a first inversion circuit in the technology of the present disclosure. The NOT circuit 44P is an example of a second inversion circuit in the technology of the present disclosure. The AND circuit 45P is an example of a logical AND circuit in the technology of the present disclosure.

[0027] The P-channel transistor 41P is configured by a field effect transistor. The source terminal, which is the ground terminal, of the P-channel transistor 41P is connected to the external power supply 50 via a wiring resistor ROUT.

[0028] When the output signal of the NOT circuit 44P and the signal ENP are both in a high level state, the AND circuit 45P outputs a signal indicating that an abnormality has been detected, that is, a high level signal, from the output signal terminal ERRP. The output signal terminal ERRP of the AND circuit 45P is connected to the control unit 14.

[0029] The control unit 14 determines whether or not an abnormality has occurred in the class D amplifier 1 based on the output signal terminal ERRP of the AND circuit 45P, and if an abnormality has occurred, stops the supply of power to the switching element 31P to protect the switching element 31P.

[0030] The negative side signal circuit unit 13 includes a pre-driver 20M equipped with a delay processing unit that performs delay processing on the inverted output signal PWMN of the PWM modulated signal, a signal amplification unit 30M that amplifies the signal after passing through the pre-driver 20M using a switching element 31M, and an abnormality detection unit 40M that detects abnormalities in the signal after passing through the signal amplification unit 30M.

[0031] The negative side signal circuit section 13 has the same configuration as the positive side signal circuit section 12 described above, except that an inverted output signal PWMN of a signal that has been PWM modulated is input to the pre-driver 20M, and that the connection point between the drain terminals of the P-channel transistor P2 and the N-channel transistor N2 of the switching element 31M is connected to the negative side output terminal SPOUTM of the speaker. Therefore, a description thereof will be omitted.

[0032] In the class D amplifier 1, by connecting a speaker RSP, which is a load, between the positive output terminal SPOUTP and the negative output terminal SPOUTM, it is possible to reproduce sound corresponding to the input digital signal DS.

[0033] Next, the abnormality detection processing in the abnormality detection unit 40P of the plus side signal circuit unit 12 and the abnormality detection unit 40M of the minus side signal circuit unit 13 will be described in detail. Since the processing in the abnormality detection unit 40P and the processing in the abnormality detection unit 40M are basically the same, the abnormality detection unit 40P will be described here as an example. Figure 3 is a graph showing a signal waveform in the above-mentioned class D amplifier 1.

[0034] As shown in the "normal" region of Figure 3, when there is no abnormality such as a ground fault at the output terminal or a short circuit between the output terminals, i.e., when the class D amplifier 1 is operating normally, the high-level signal in the signal SPOUTP after passing through the signal amplification unit 30P will be at a level that exceeds the threshold voltage VTh.

[0035] Here, the threshold voltage VTh can be set to the following value, for example. For example, in typical speaker output power specifications, when the power supply voltage is 5V, the output is 1W, and the load resistance is 8Ω, the maximum output current is about 800mA. The threshold voltage VTh may be determined based on the voltage level of the signal SPOUTP when a current of 800mA or more flows through the switching element 31P due to a ground fault at the output terminal or a short circuit between the output terminals.

[0036] Node A is a node that indicates a voltage drop detection signal that detects a voltage drop in the signal amplifier 30P, and is the output terminal of a NOT circuit 42P that inverts the logic of a signal that has passed through the signal amplifier 30P. When a voltage drop occurs in the signal amplifier 30P, the signal at node A becomes a high level state.

[0037] The NOT circuit 42P inverts only the high-level signal portion exceeding the threshold voltage VTh in the signal SPOUTP after passing through the signal amplifier 30P to a low level and outputs the inverted signal. Also, the NOT circuit 42P regards the signal SPOUTP having a voltage equal to or lower than the threshold voltage VTh as a low level in the signal SPOUTP after passing through the signal amplifier 30P, and inverts the low-level portion to a high level and outputs the inverted signal.

[0038] Node B is the output terminal of the P-channel transistor 41P, that is, the drain terminal of the P-channel transistor 41P, and an inverted signal of node A is output therefrom.

[0039] However, an RC parallel circuit 43P in which a resistor R5 and a capacitance C1 are connected in parallel is connected to node B. Therefore, when the high-level signal at node B changes to a low-level signal, that is, when the high-level signal changes to a signal equal to or lower than the threshold voltage VTh, a time equivalent to the time constant of the resistor R5 and the capacitance C1 is required.

[0040] Node C is a node that indicates an abnormality detection signal that detects an abnormality in the signal amplifier 30P, and is the output terminal of a NOT circuit 44P that inverts the logic of the output signal of the P-channel transistor 41P. When an abnormality occurs in the signal amplifier 30P, the signal at node C becomes a high level state.

[0041] The NOT circuit 44P inverts only the high-level signal portion exceeding the threshold voltage VTh in the output signal of the P-channel transistor 41P to a low level and outputs the inverted signal. Also, the NOT circuit 44P regards the signal equal to or lower than the threshold voltage VTh in the output signal of the P-channel transistor 41P as a low level, and inverts the low-level portion to a high level and outputs the inverted signal.

[0042] First, when audio playback starts, the signal SPOUTP is in a low level state, so the voltage drop detection signal at node A is always in a high level state. At that time, node B is in a low level state, and in response, node C is in a high level state.

[0043] In order not to detect the high level state of node C in this state as an abnormality, the signal ENP is set to a low level when audio playback starts, and an abnormality detection signal is not output from the AND circuit 45P. After audio playback starts, the signal ENP is set to a high level, and if node C subsequently goes to a high level, an abnormality is detected.

[0044] Under normal circumstances when there is no abnormality such as a ground fault at the output terminal or a short circuit between the output terminals, node A repeatedly switches between high and low levels. However, node B, which is the inverted signal of node A, goes to a high level once and then goes to a low level, requiring a time constant determined by resistance R5 and capacitance C1.

[0045] For signal PWMP, the maximum continuous time for which the low level state continues for the longest period of time under normal circumstances is determined by the specifications. Therefore, by using resistor R5 and capacitance C1 to ensure a time constant for the non-detection time, which is a time period with a margin longer than the maximum continuous time, node B is prevented from going to a low level state under normal circumstances.

[0046] As a result, node C will not be in a high level state during normal operation, and therefore an abnormality will not be detected during normal operation.

[0047] As an example, if the non-detection time, which is the maximum continuous time when a low-level state continues for the longest time under normal circumstances with some leeway, is set to 100 μS, and an abnormality is detected when node B is in a low-level state for 100 μS or more, then resistance R5 can be set to 1 MΩ and capacitance C1 can be set to 100 pF.

[0048] When an abnormality such as a ground fault at the output terminal or a short circuit between the output terminals occurs, node A continues to maintain a high level state, so node B gradually goes to a low level state. When the signal falls below the threshold voltage VTh, node C goes to a high level state and the abnormality is detected.

[0049] Here, in order to clearly explain the effect of the class-D amplifier 1 of this embodiment, a comparative class-D amplifier 100 will be described. Fig. 4 is a diagram showing the configuration of the comparative class-D amplifier. Fig. 5 is a graph showing a signal waveform in the comparative class-D amplifier.

[0050] 4, the class D amplifier 100 of the comparative example is different from the class D amplifier 1 of the present embodiment in the configurations of the abnormality detection unit 140P of the positive side signal circuit unit 12 and the abnormality detection unit 140M of the negative side signal circuit unit 13. Since the configuration and processing of the abnormality detection unit 140P and the abnormality detection unit 140M are basically the same, the abnormality detection unit 140P will be described here as an example.

[0051] The abnormality detection unit 140P includes an AND circuit 141P that performs a logical AND operation on two input signals, and a NOT circuit 142P that inverts the logic of the input signal.

[0052] The AND circuit 141P receives a signal INVP that is output from the connection point of the two transistors P1 and N1 and inverted by a NOT circuit 142P, and a reference signal INP that is a PWM-modulated signal PWMP.

[0053] When both the signal INVP and the reference signal INP are in a high level state, the abnormality detection unit 140P outputs a signal indicating that an abnormality has been detected, that is, a high level signal, from the output signal terminal ERRP by the AND circuit 141P.

[0054] In other words, the abnormality detection unit 140P samples the signal INVP based on the reference signal INP, and compares the two signals, the signal INVP and the reference signal INP, to detect an abnormality.

[0055] In this case, if there is a timing discrepancy between the two signals, there is a risk that abnormalities cannot be detected accurately.

[0056] A maximum delay of about 300 ns occurs in the delay processing unit 21P in the class-D amplifier 1 of this embodiment and the comparative class-D amplifier 100. Also, a delay of about several ns occurs in the signal amplifying unit 30P, although this is smaller than that of the delay processing unit 21P.

[0057] In the comparative class D amplifier 100, the PWM modulated signal PWMN is used as a reference signal INP, and two signals are compared: this reference signal INP and a signal INVP inverted by a NOT circuit 42P after passing through a signal amplification section 30P.

[0058] In this case, as shown in FIG. 5, the signal SPOUTP after passing through the signal amplifier 30P is significantly delayed in the delay processing unit 21P and the signal amplifier 30P, causing a difference in timing between the two signals (delay time TD). As a result, the two signals cannot be compared at the same timing, and therefore abnormalities cannot be detected accurately.

[0059] As a result, for example, as shown in the "normal" region of FIG. 5, false detection of an abnormality occurs even in a region where no abnormality occurs.

[0060] In contrast, in the class D amplifier 1 of this embodiment, sampling is not performed using the signal PWMP, which is the signal before passing through the pre-driver 20P and the signal amplifier 30P, as a reference signal, thereby eliminating the influence of the above-mentioned delay processing.

[0061] Furthermore, in the abnormality detection unit 40P of this embodiment, an RC parallel circuit 43P in which a resistor R5 and a capacitance C1 are connected in parallel is provided in the abnormality detection unit 40P. This means that an abnormality is not detected in a state in which high level states and low level states occur periodically at node A for a time equal to or less than the non-detection time determined by the RC parallel circuit 43P, and therefore an abnormality is not erroneously detected under normal circumstances.

[0062] Furthermore, in the abnormality detection unit 40P of this embodiment, when an abnormality such as a ground fault at an output terminal or a short circuit between output terminals occurs and node A is continuously in a low level state for a period of time that exceeds the non-detection time, this can be detected as an abnormality.

[0063] Therefore, according to the class D amplifier 1 of this embodiment, even if delay processing is performed, it is possible to accurately detect an abnormality.

[0064] [Variations] Although the preferred embodiments of the class D amplifier circuit of the present disclosure have been described above, the class D amplifier circuit of the present disclosure is not limited to the above-described embodiments and may be modified in various ways.

[0065] For example, in the above embodiment, P-channel transistors are used as the transistors of the abnormality detection units 40P and 40M, but this is not limiting, and N-channel transistors may also be used.

[0066] When N-channel transistors are used as the transistors of the abnormality detection units 40P and 40M, the peripheral circuits of the N-channel transistors may be appropriately modified.

[0067] In the above embodiment, a digital class D amplifier circuit is used in which a digital signal is input to the PWM modulation processing unit 11. However, an analog class D amplifier circuit may be used in which an analog signal is input to the PWM modulation processing unit 11. [Explanation of symbols]

[0068] 1, 100 D class amplifier 11 Modulation processing section 12 Positive signal circuit section 13 Negative signal circuit section 14 Control section 20M, 20P pre-driver 21P Delay processing section 22P Common delay processing section 23P Individual delay processing unit 30M, 30P signal amplifier 31M, 31P switching elements 40M, 40P Abnormality Detection Unit 41M, 41P P-channel transistors 42M, 42P NOT circuit 43M, 43P RC parallel circuit 44M, 44P NOT parallel circuit 45M, 45P AND circuit 50 External power supply 51 Digital signal output section 140M, 140P Abnormality Detection Unit 141M, 141P AND circuit 142M, 142P NOT circuit

Claims

1. A PWM modulation processing unit that performs PWM modulation processing on an input signal; a signal amplifier that amplifies the PWM modulated signal by a switching element; an abnormality detection unit that detects an abnormality when a voltage drop occurs continuously for a set period of time or more in the signal that has passed through the signal amplification unit. Class D amplifier circuit.

2. The abnormality detection unit includes a field effect transistor, a first inversion circuit connected to an input terminal of the field effect transistor and inverting a logic of a signal that has passed through the signal amplification unit, and a parallel circuit connected to an output terminal of the field effect transistor and including a resistor and a capacitor connected in parallel.

2. The class D amplifier circuit according to claim 1.

3. The abnormality detection unit further includes a second inversion circuit connected to an output terminal of the field effect transistor and inverting a logic of an output signal of the field effect transistor, and a logical AND circuit performing a logical AND operation between the output signal of the second inversion circuit and a signal indicating validity of the abnormality detection input from outside.

3. The class D amplifier circuit according to claim 2.

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