Reference voltage generating circuit and semiconductor device

Abstract

To provide a reference voltage generating circuit and a semiconductor device, which enable a value of an internal reference voltage to be adjusted each time a power source is started.SOLUTION: A reference voltage generating circuit 21 comprises: an internal reference voltage generating circuit 31 that includes a voltage dividing circuit 43 including an output 45b, a plurality of resistive elements 47 connected in series between a low voltage power source line 19 and the output 45b, and a current source 41, and that generates an internal reference voltage VREF in the output 45b; a target voltage generating circuit 33 having an output 45c for providing a target voltage VTRG; an adjusting circuit 37 including switches SW connected to the resistive elements 47 so that a certain element 47 of the resistive elements 47 can be individually short-circuited; and a comparison circuit 37 configured to specify the conduction / non-conduction of a switch SW and including a storage circuit 51 having respective volatile storage devices, and a determination circuit 53 configured to determine a value stored in the storage circuit 51 based on a magnitude relationship between the internal reference voltage VREF and the target voltage VTRG.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a reference voltage generating circuit and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a voltage detection circuit that uses a fuse element, which is connected in series with a MOS transistor as a trimming element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-141041 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device, the initial value of the internal reference voltage varies due to variations in manufacturing process conditions. The shift in the initial value due to the process variations can be adjusted by laser trimming a fuse element in the semiconductor device.

[0005] Specifically, the internal reference voltage is adjusted by changing the resistance value by laser trimming of the fuse element during a wafer test in manufacturing the semiconductor device.

[0006] While this method can provide a semiconductor device with an internal reference voltage of a desired value, it requires both an element area for the fuse element and time required for trimming.

[0007] The internal reference voltage can be adjusted by reading the fuse element and setting the value of the internal reference voltage each time the power supply of the semiconductor device is turned on.

[0008] An object of the present disclosure is to provide a reference voltage generating circuit and a semiconductor device that make it possible to adjust the value of an internal reference voltage each time the power supply is turned on. [Means for solving the problem]

[0009] A reference voltage generation circuit according to a first aspect of the present invention is an internal reference voltage generation circuit including a current source and a voltage divider circuit connected in series from one side of a high voltage power line and a low voltage power line to the other side, and an output, and configured to generate an internal reference voltage at the output, the voltage divider circuit comprising: an internal reference voltage generation circuit including a plurality of resistors connected in series between the output and the high voltage power line or the low voltage power line; a target voltage generation circuit connected between the high voltage power line and the low voltage power line and having an output for providing a target voltage; adjustment circuits including respective switches connected to at least some of the resistors so as to be able to individually short out at least some of the resistors; storage circuits having respective volatile storages configured to determine the conduction / non-conduction of the switches of the adjustment circuit; and a comparison circuit including a determination circuit configured to determine the stored value of the storage circuit based on the magnitude relationship between the internal reference voltage and the target voltage, and the current source of the internal reference voltage generation circuit is configured to receive a voltage from an intermediate node of the voltage divider circuit.

[0010] A semiconductor device according to a second aspect of the present invention comprises the reference voltage generating circuit according to the first aspect, and an internal circuit including a circuit for receiving the internal reference voltage of the reference voltage generating circuit. Effect of the Invention

[0011] According to the above aspects, it is possible to provide a reference voltage generating circuit and a semiconductor device that enable adjustment of the value of the internal reference voltage each time the power supply is turned on. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating a schematic configuration of a semiconductor device according to the present embodiment. [Diagram 2] FIG. 2 is a diagram illustrating a schematic configuration of a reference voltage generating circuit of the semiconductor device according to the present embodiment. [Diagram 3] FIG. 3 is a diagram illustrating a schematic diagram of a determination circuit of the reference voltage generating circuit according to the present embodiment. [Figure 4] FIG. 4 is a diagram illustrating an exemplary reference voltage generating circuit. [Diagram 5] FIG. 5 is a diagram showing operational waveforms of main nodes of the reference voltage generating circuit shown in FIG. [Figure 6] FIG. 6 is a diagram showing the main steps in a method of operating the reference voltage generating circuit according to the present embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same parts are designated by the same reference numerals and duplicated description will be omitted.

[0014] FIG. 1 is a diagram that shows a schematic diagram of a semiconductor device according to the present embodiment. FIG. 2 is a diagram that shows a schematic diagram of a reference voltage generating circuit of the semiconductor device according to the present embodiment. FIG. 3 is a diagram that shows a schematic diagram of a determination circuit of the reference voltage generating circuit according to the present embodiment. In the following description, a symbol of a field effect transistor is drawn in the diagram as an exemplary transistor. This field effect transistor has a source electrode, a drain electrode, and a gate electrode, and the source electrode, the drain electrode, and the gate electrode are referred to as "S", "D", and "G", respectively.

[0015] Referring to Fig. 1, a semiconductor system 11 is shown. The semiconductor system 11 can include a semiconductor device 13 and a power supply device 15. The power supply device 15 supplies power to the semiconductor device 13 via a high-voltage power line 17 and a low-voltage power line 19. The semiconductor device 13 includes a reference voltage generating circuit 21, an internal circuit 23, and a control circuit 25. Although the semiconductor device 13 is depicted in Fig. 1 as including the reference voltage generating circuit 21, the internal circuit 23, and the control circuit 25, the semiconductor device 13 can include additional circuits.

[0016] The internal circuit 23 may include a circuit that receives the internal reference voltage VREF of the reference voltage generating circuit 21. An exemplary internal circuit 23 may include a voltage regulator that operates by receiving the internal reference voltage VREF.

[0017] The semiconductor device 13 may include a plurality of electrodes 20 (20a, 20b, 20c, 20d, 20e, 20f) that enable electrical connection to the outside of the semiconductor device 13, and each of the exemplary electrodes 20 (20a, 20b, 20c, 20d, 20e, 20f) may include one or more pad electrodes. Specifically, the electrode 20 (20a) is configured to receive one or more control signals (CTL) that control the operation of the semiconductor device 13. These control signals are provided to a control circuit 25. The electrode 20 (20b) may be connected to a high-voltage power supply line 17 from the power supply device 15. Also, the electrode 20 (20c) may be connected to a low-voltage power supply line 19 from the power supply device 15. In the following description, the high-voltage power supply line 17 is referred to as one power supply line in the semiconductor device 13, and the low-voltage power supply line 19 is referred to as the other power supply line in the semiconductor device 13. The electrode 20 (20d) can be connected to the output of an exemplary internal circuit 23 such as a voltage regulator. For example, the load circuit 10 is connected to the electrode 20 (20d). The electrode 20 (20e) can be used to provide the internal reference voltage VREF of the reference voltage generating circuit 21 to the outside. The electrode 20 (20f) can be used to provide the target voltage VTRG of the reference voltage generating circuit 21 to the outside.

[0018] The control circuit 25 is configured to receive one or more control signals and a clock signal for synchronous operation from the electrode 20 (20a), provide control signals (CTL1, CTL3, CTL4) to the reference voltage generation circuit 21, and provide a control signal (CTL2) to the internal circuit 23.

[0019] Referring to FIG. 2, the reference voltage generating circuit 21 may include an internal reference voltage generating circuit 31, a target voltage generating circuit 33, an adjusting circuit 35, and a comparing circuit 37.

[0020] The internal reference voltage generating circuit 31 includes a current source 41 and a voltage dividing circuit 43, which are connected in series from one side to the high voltage power supply line 17 and the low voltage power supply line 19. The internal reference voltage generating circuit 31 includes an output 45b, which can be connected to a shared node NCOM1 of the current source 41 and the voltage dividing circuit 43.

[0021] The internal reference voltage generating circuit 31 is configured to generate an internal reference voltage VREF at the output 45b. The current source 41 can provide a constant current to the voltage divider circuit 43. The voltage divider circuit 43 includes a plurality of resistors 47 connected in series between one of the high voltage power supply line 17 or the low voltage power supply line 19 (the low voltage power supply line 19 in the exemplary voltage divider circuit 43) and the output 45b. The exemplary resistors 47 can include at least one of a polysilicon resistor, a resistor of a highly doped semiconductor region, and a resistor formed by a dedicated ion implantation into a semiconductor. The series connection of the exemplary resistors 47 can be configured by a series connection of resistors of the same type.

[0022] While FIG. 1 depicts resistors 47 with the same reference numerals, the same reference numerals do not indicate that the resistors of resistors 47 have the same resistance value. For example, a plurality of unit resistors may be formed on a semiconductor substrate, and each of resistors 47 may be configured to include at least one unit resistor. Specifically, first resistor 47 may include a single unit resistor, and second resistor 47 may include two (2 1 ) unit resistors, and the third resistor 47 includes 4 (22 ) unit resistors.

[0023] Moreover, the intermediate node NDM of the exemplary voltage divider circuit 43 is shared by two resistors 47. Each of these resistors 47 is not connected to the switch SW. The resistance ratio of these resistors 47 can be designed so that the internal reference voltage generating circuit 31 generates a value close to the target voltage VTRG as the internal reference voltage VREF when the remaining resistors 47 are all shorted by the switch SW. One of the two resistors 47 can be connected between the shared node NCOM1 and the intermediate node NDM, and the other of the two resistors 47 can be connected between one of the high-voltage power supply line 17 or the low-voltage power supply line 19 and the intermediate node NDM.

[0024] In the exemplary internal reference voltage generating circuit 31, the current source 41 may include a reference voltage source 57, such as a bandgap reference circuit, a differential amplifier circuit 59, and a current source transistor 61. The reference voltage source 57, such as a bandgap reference circuit, is connected between the high voltage power supply line 17 and the low voltage power supply line 19. The differential amplifier circuit 59 has a first input 59b connected to the output of the bandgap reference circuit, a second input 59c connected to an intermediate node NDM, and an output 59d. The current source transistor 61 is connected to the output 59d of the differential amplifier circuit 59. The current source transistor 61 provides a current to the voltage divider circuit 43, which generates an intermediate voltage at the intermediate node NDM. The current source 41 of the internal reference voltage generating circuit 31 is configured to receive a voltage from the intermediate node NDM of the voltage divider circuit 43.

[0025] The target voltage generating circuit 33 has an output 45c connected between the high voltage power rail 17 and the low voltage power rail 19 and providing the target voltage VTRG.

[0026] An exemplary target voltage generating circuit 33 may include one or more first resistors 67b and one or more second resistors 67c. The first resistor 67b and the second resistor 67c are connected in series between the high voltage power supply line 17 and the low voltage power supply line 19. Specifically, the first resistor 67b is connected in series between the output 45c of the target voltage generating circuit 33 and the high voltage power supply line 17, and the second resistor 67c is connected in series between the output 45c of the target voltage generating circuit 33 and the low voltage power supply line 19. As a result, a shared node of the first resistor 67b and the second resistor 67c connected in series is connected to the output 45c.

[0027] This target voltage generating circuit 33 can provide to the output 45c a divided voltage value (target voltage VTRG) obtained by dividing the potential difference between the high voltage power line 17 and the low voltage power line 19 by the first resistor 67b and the second resistor 67c.

[0028] The target voltage generation circuit 33 may include a switch, for example, a transistor 67d, that blocks current flowing through the first resistor 67b and the second resistor 67c. The transistor 67d as an exemplary switch may be connected to either the high-voltage power supply line 17 or the low-voltage power supply line 19, in this embodiment, the low-voltage power supply line 19. The exemplary target voltage generation circuit 33 does not include any other transistors except for the transistor 67d.

[0029] The exemplary first resistor 67b and the exemplary second resistor 67c may include at least one of a polysilicon resistor, a resistor of a highly doped semiconductor region, and a resistor formed by dedicated ion implantation into a semiconductor. The exemplary series connection of the first resistor 67b and the exemplary second resistor 67c may be configured by a series connection of resistors of the same type. Thereby, the target voltage VTRG is not sensitive to the characteristic variations of the first resistor 67b and the second resistor 67c and is determined by the potential difference between the high voltage power line 17 and the low voltage power line 19.

[0030] In the reference voltage generating circuit 21, the adjustment circuit 35 may include a plurality of switches SW, and the switches SW are connected to at least some of the resistors 47 connected in series in the voltage dividing circuit 43. Each switch SW is connected in parallel to one or more resistors 47. The switches SW have respective control inputs CNT that individually set the conduction / non-conduction of the switches SW. Each of the switches SW is connected to one end and the other end of a single resistor 47, and can individually short-circuit the resistor 47. Each of the exemplary switches SW may include a field effect transistor, and the gate of the field effect transistor may be connected to the control input CNT.

[0031] In the exemplary regulator circuit 35, the switch SW is connected to a portion of the series-connected resistors 47. When the switch SW is connected to each of all the resistors 47, the conduction of all the switches SW connects the current source 41 directly to one of the high-voltage power supply line 17 or the low-voltage power supply line 19, in this exemplary voltage divider circuit 43, to the low-voltage power supply line 19.

[0032] The exemplary adjustment circuit 35 may include a select circuit 63, which is configured to control the conduction / non-conduction of the switch in response to an output value from each of the storage circuits 51. The select circuit 63 may include a plurality of storages 65 provided for each switch SW. Each of the exemplary storages 65 includes a static circuit, such as a logic gate, capable of holding a logical value specifying the conduction / non-conduction of the switch SW, and a circuit that does not pass through current in a static operation. When the power supply is lost, the stored value of the storage 55 is also lost. The storage 65 may be disposed closer to the switch SW than the storage 55 of the storage circuit 51, thereby reducing the effect of electrical disturbance on the conduction / non-conduction of the switch SW. Each of the exemplary storages 65 may include at least one latch circuit.

[0033] In the reference voltage generating circuit 21 , the comparison circuit 37 may include a storage circuit 51 and a determination circuit 53 .

[0034] The storage circuit 51 is configured to identify the conductive / non-conductive state of the switch SW of the adjustment circuit 35. The storage circuit 51 can be a volatile holding circuit. The storage circuit 51 can include a plurality of storages 55 provided for each switch SW, and the storages 55 can include a circuit capable of statically maintaining its output value. Each of the exemplary storages 55 can include at least one latch circuit. Each of the storages 55 holds a value defining the conductive / non-conductive state of any one of the switches SW.

[0035] The storage device 55 of the storage circuit 51 stores a stored value that specifies the conductive / non-conductive state of each switch SW, and the stored value of the storage device 55 is also lost when the power supply is lost.

[0036] The conduction / non-conduction of each switch SW is specified by the stored value in the storage device 55. The conduction / non-conduction of the switch SW changes the intermediate voltage of the intermediate node NDM. This intermediate voltage is fed back to the input 59c of the differential amplifier circuit 59, and the internal reference voltage generation circuit 31 changes the internal reference voltage VREF.

[0037] 3 is a diagram illustrating a schematic diagram of a determination circuit of the reference voltage generating circuit according to the present embodiment. The reference voltage generating circuit 21 (and the semiconductor system 11) can have a normal operation mode and an adjustment operation mode.

[0038] The adjustment operation mode is set for a period from when the semiconductor system 11 is powered on until the internal circuit 23 starts operating thereafter. During this period, the reference voltage generation circuit 21 adjusts the internal reference voltage VREF to a desired value in the adjustment operation mode. Specifically, the reference voltage generation circuit 21 uses the determination circuit 53 to determine the value of the storage unit 55 of the storage circuit 51 so that the internal reference voltage VREF of the internal reference voltage generation circuit 31 is equal to or closest to the desired value. Prior to the adjustment operation, the exemplary storage circuit 51 can set the value of the storage unit 55 so that all of the switches SW are non-conductive.

[0039] In contrast, in the normal operating mode, the internal reference voltage generating circuit 31 operates using the specified value in the storage 55 of the storage circuit 51 to generate an internal reference voltage VREF regulated to a desired value.

[0040] The determination circuit 53 may include a detection circuit 69 and an adjustment control circuit 71 .

[0041] The adjustment operation of the adjustment control circuit 71 can be started after start-up of the power supply that supplies the voltage between the high voltage power line 17 and the low voltage power line 19. In the adjustment operation mode, the decision circuit 53 of the comparison circuit 37 is used.

[0042] The determination circuit 53 can be configured to perform the following operations. Specifically, the determination circuit 53 prepares a series of set values ​​to be used as candidate values ​​for specifying the value of the storage unit 55 of the storage circuit 51 in the adjustment operation mode. The determination circuit 53 also causes the internal reference voltage generation circuit 31 to generate candidate values ​​for the internal reference voltage VREF by sequentially using the series of set values. Furthermore, the determination circuit 53 is configured to specify the stored value of the storage circuit 51 based on the magnitude relationship between the candidate values ​​for the internal reference voltage VREF and the target voltage VTRG.

[0043] The exemplary detection circuit 69 includes a comparator 77, which can be configured to determine a stored value in the storage circuit 51 based on the magnitude relationship between the internal reference voltage VREF and the target voltage VTRG in the adjustment operation. The comparator 77 is configured to compare the internal reference voltage VREF and the target voltage VTRG in the adjustment operation and output a comparison result. The comparison result is stored in a first storage circuit 79. The first storage circuit 79 can include, for example, a latch circuit.

[0044] The detection circuit 69 may further include a holding circuit 81. The holding circuit 81 is configured to receive a previous result (held value), which is a previous comparison result, from the first storage circuit 79 and update the previous result every time the comparator 77 performs a comparison. The holding circuit 81 may include, for example, a latch circuit.

[0045] The detection circuit 69 may further include a mismatch detection circuit 49. The mismatch detection circuit 49 is configured to determine whether the value of the first storage circuit 79, i.e., the latest comparison result, matches / mismatches the value of the holding circuit 81, i.e., the previous result, and generate a mismatch signal when a mismatch is detected. The mismatch detection circuit 49 may include an exclusive OR gate.

[0046] The occurrence of a mismatch signal indicates that either the value stored in storage circuit 51 immediately before the mismatch signal was generated or the value stored in storage circuit 51 at the time the mismatch signal was generated is capable of generating an internal reference voltage VREF that is closest to the desired value.

[0047] The most recent comparison result is stored in a first storage circuit 79 , while the previous result is stored in a holding circuit 81 .

[0048] In response to the mismatch detection circuit 49 detecting a mismatch between the latest comparison result and the previous result, the determination circuit 53 can perform at least one of the following operations: Hold the setting value when the mismatch was detected, or hold the setting value immediately before the mismatch was detected.

[0049] In the adjustment operation mode, the adjustment control circuit 71 operates to sequentially provide a series of setting values ​​to the storage unit 55 of the storage circuit 51, the setting values ​​specifying the stored values ​​in the storage unit 55 of the storage circuit 51. Illustratively, the adjustment control circuit 71 may include a setting control circuit 73. The adjustment control circuit 71 may operate upon receiving a clock signal CLK for synchronous operation.

[0050] The setting control circuit 73 is configured to sequentially transfer a series of setting values ​​(the series of setting values ​​includes an initial value) for candidate values ​​of the storage device 55 to the storage circuit 51 in an adjustment operation for identifying a stored value of the storage circuit 51. The initial value of the series of setting values ​​is transferred first. The setting control circuit 73 is also configured to sequentially transfer the series of setting values ​​to the second storage circuit 75. The series of setting values ​​are held in the storage circuit 51 and the second storage circuit 75. The second storage circuit 75 may include the same number of storage devices as the storage circuit 51.

[0051] The second storage circuit 75 may include a main circuit 75b that stores the latest setting value transferred from the setting control circuit 73, and an auxiliary circuit 75c that stores the previous setting value. The auxiliary circuit 75c updates the previous setting value when the main circuit 75b receives the latest setting value.

[0052] In the adjustment operation, the setting control circuit 73 is configured to first set an initial value in the adjustment operation of the internal reference voltage VREF. The setting control circuit 73 sets a value specifying the conductive / non-conductive state of the switch SW of the adjustment circuit 35 as the initial value in the storage circuit 51 of the comparison circuit 37. In response to the stored value in the storage circuit 51, the internal reference voltage generation circuit 31 generates a certain voltage value.

[0053] The exemplary initial value can cause the internal reference voltage generating circuit 31 to generate a voltage value closer to one of the voltages of the high-voltage power line 17 or the low-voltage power line 19 than the other. The exemplary initial value can be a voltage value closest to one of the voltages of the high-voltage power line 17 or the low-voltage power line 19. Furthermore, when the initial value is set or prior to setting the initial value, the holding circuit 81 is initialized according to an initial value in a series of set values. The exemplary holding circuit 81 is reset or preset to correspond to the initial value. Accordingly, the holding circuit 81 stores a value assuming a comparison result between the voltage generated by the internal reference voltage generating circuit 31 according to the initial value and the target voltage VTRG in the adjustment operation of the internal reference voltage VREF.

[0054] Specifically, the setting control circuit 73 can be configured so that the output value (internal reference voltage VREF during the adjustment operation) generated by the internal reference voltage generation circuit 31 in response to the initial value is set to a voltage value closest to the high-voltage power supply line 17. Alternatively, the setting control circuit 73 can be configured so that the output value generated by the internal reference voltage generation circuit 31 in response to the initial value is set to a voltage value closest to the low-voltage power supply line 19. A series of exemplary setting values ​​can be prepared so that the internal reference voltage generation circuit 31 changes the output value in a direction from one of the maximum voltage value and the minimum voltage value of the internal reference voltage VREF during the adjustment operation to the other in response to the initial value.

[0055] An exemplary sequence of operations can proceed as follows.

[0056] The storage circuit 51 receives an initial setting value set as an initial value from the setting control circuit 73. The adjustment circuit 35 specifies the conductive / non-conductive state of each switch SW in response to the initial setting value. The conductive / non-conductive state of the switch SW specifies the resistance value of the voltage divider circuit 43, and the internal reference voltage generation circuit 31 generates a voltage value (the internal reference voltage VREF being adjusted) associated with the initial setting value at the output 45b.

[0057] The comparator 77 compares the voltage value from the output 45b of the internal reference voltage generating circuit 31 (the internal reference voltage VREF being adjusted) with the target voltage VTRG, and generates a comparison result.

[0058] The result of this comparison is stored in the first storage circuit 79, while the holding circuit 81 stores a value corresponding to an initial value in the series of set values. The mismatch detection circuit 49 compares the value of the first storage circuit 79 with the value of the holding circuit 81 with each other. At the initial value, the mismatch detection circuit 49 generates a signal indicating "match". This signal is sent to the second storage circuit 75, which is set to continue receiving the series of set values.

[0059] In an adjustment operation for specifying a stored value in the storage circuit 51, the setting control circuit 73 sequentially transfers a series of setting values ​​stored in the storage device 55 to the storage circuit 51 and the second storage circuit 75. In response to the transfer of the sequential setting values, the adjustment circuit 35 specifies the conductive / non-conductive state of each switch SW for each transfer. The conductive / non-conductive state of the switch SW specifies the resistance value of the voltage divider circuit 43, and the internal reference voltage generation circuit 31 generates a voltage value (internal reference voltage VREF being adjusted) associated with the current setting value at the output 45b. The comparator 77 compares the voltage value (internal reference voltage VREF being adjusted) from the output 45b of the internal reference voltage generation circuit 31 with the target voltage VTRG to generate a comparison result.

[0060] The mismatch detection circuit 49 generates a signal indicating a "match," which is sent to the second storage circuit 75 to configure the second storage circuit 75 to subsequently receive the sequence of set values.

[0061] In this manner, the adjustment operation for determining the stored value in the storage circuit 51 proceeds.

[0062] At a certain setting in the sequence of setting value transfers, the mismatch detection circuit 49 generates a mismatch signal indicating a "mismatch" between the comparison result and the previous result. This mismatch signal is sent to the second storage circuit 75, which can be set not to receive subsequent setting values. This setting can be maintained in the current adjustment operation.

[0063] Upon receiving the mismatch signal, the second storage circuit 75 can store the latest set value in the main circuit 75b and store the previous set value in the auxiliary circuit 75c. In the second storage circuit 75 that is configured not to receive subsequent set values, the stored values ​​in the main circuit 75b and the auxiliary circuit 75c are not updated upon and after receiving the mismatch signal.

[0064] In an exemplary adjustment operation, even after the mismatch signal is generated, the setting control circuit 73 can sequentially transfer a series of setting values ​​to the storage circuit 51 and the second storage circuit 75. In response to the transfer of the successive setting values, the adjustment circuit 35 specifies the conduction / non-conduction of each switch SW for each transfer. The conduction / non-conduction of the switch SW specifies the resistance value of the voltage divider circuit 43, and the internal reference voltage generation circuit 31 generates a voltage value (the internal reference voltage VREF being adjusted) associated with the current setting value at the output 45b.

[0065] After transferring all of the series of setting values ​​in the adjustment operation to the storage circuit 51 and the second storage circuit 75, or after the adjustment operation is completed, the setting control circuit 73 can load (reset) the setting value stored in either the main circuit 75b or the auxiliary circuit 75c of the second storage circuit 75 into the storage device 55 of the storage circuit 51. Completion of this loading completes the substantial adjustment operation of identifying the stored value in the storage circuit 51. In the resetting, it can be set in advance or individually as to whether the setting value stored in the main circuit 75b or the auxiliary circuit 75c is to be used.

[0066] A set of settings can be generated as follows.

[0067] The exemplary adjustment control circuit 71 may include a counter circuit 83 that operates in response to a clock signal CLK. The counter circuit 83 (n bits) is configured to generate a series of setting values ​​(n bits) that specify the conductive / non-conductive state of the switch SW for the adjustment operation. The setting control circuit 73 is configured to transfer the series of setting values ​​from the counter circuit 83 to the storage circuit 51 in synchronization with the clock signal CLK. The counter circuit 83 may be reset or preset prior to the adjustment operation. An overflow of the counter circuit 83 indicates the end of the adjustment operation.

[0068] Moreover, the exemplary adjustment control circuit 71 may further include a third storage circuit 85 configured to store a series of setting values ​​specifying the conductive / non-conductive state of the switch SW for the adjustment operation. The exemplary third storage circuit 85 may include a readable memory (ROM and / or RAM). The setting control circuit 73 is configured to transfer the series of setting values ​​from the third storage circuit 85 to the storage circuit 51 in synchronization with the clock signal CLK. The third storage circuit 85 may be connected to an address generation circuit 87, and the address generation circuit 87 generates a memory address of the readable memory in response to the clock signal CLK.

[0069] As already explained, the setting control circuit 73 sequentially transfers a series of setting values ​​to the storage circuit 51 and the second storage circuit 75. The stored value in the storage circuit 51 can be changed so that the internal reference voltage changes from an initial value closer to one of the high-voltage power line or the low-voltage power line voltage toward the other of the high-voltage power line or the low-voltage power line voltage.

[0070] The generation of the set of set points is not limited to the exemplary circuit above.

[0071] Fig. 4 is a diagram showing an exemplary reference voltage generating circuit. Fig. 5 is a diagram showing operation waveforms of main nodes of the reference voltage generating circuit shown in Fig. 4. In the following description, for ease of understanding, the reference symbols used in the above description will be used where possible.

[0072] The reference voltage generating circuit 21 (and the semiconductor system 11) shown in Fig. 4 can have a start-up period TIGN, an adjustment operation period TADJ, and a normal operation period TNML, as shown in Fig. 5. The voltage dividing circuit 43 includes six resistors 47 connected in series, and two resistors 47 are connected to the output 45b, and two resistors 47 are connected to the low-voltage power supply line 19, respectively. The select circuit 63 provides values ​​(N1, N2, N3, and N4) that specify the conduction / non-conduction of the four switches SW.

[0073] 5, at time t0, the reference voltage generation circuit 21 (and the semiconductor system 11) is powered on. During the startup period TIGN, the high voltage power line 17 and the low voltage power line 19 become stable. Specifically, at time t1, the target voltage generation circuit 33 begins to operate. At time t2, the high voltage power line 17, the low voltage power line 19, and the target voltage VTRG become stable. In addition, the internal reference voltage generation circuit 31 begins to operate at time t1 to generate the internal reference voltage VREF, while this internal reference voltage VREF is not adjusted.

[0074] An adjustment operation period TADJ starts at time t3, and a series of set values ​​are sequentially provided to the storage circuit 51. In response to the sequential changes in the series of set values, the internal reference voltage VREF changes monotonically. In response to each set value in the series of set values, the internal reference voltage generation circuit 31 generates an unadjusted internal reference voltage VREF, while the internal reference voltage VREF is compared with the target voltage VTRG in the decision circuit 53 to generate a comparison result. At time t4, the decision circuit 53 detects that the latest comparison result is different from the previous result. In response to this detection, at time t5, the decision circuit 53 generates a mismatch signal, which is held in the mismatch detection circuit 49. The second storage circuit 75 holds the latest set value in the main circuit 75b and the previous set value in the auxiliary circuit 75c for each set value in the series. In response to the mismatch signal, the second storage circuit 75 can stop updating the set values ​​at time t6. The second storage circuit 75 holds the setting value that generated the mismatch signal and a backup value of the setting value immediately before that. The transfer of the series of setting values ​​ends at time t7. At time t8, the storage circuit 51 is reset using the backup value.

[0075] At time t9, the adjustment operation period TADJ ends and the normal operation period TNML begins. During the normal operation period TNML, various circuits operate, so the noise environment of the high voltage power line 17 and the low voltage power line 19 becomes worse than during the adjustment operation period TADJ.

[0076] 6 is a diagram showing the main steps of a method for operating the reference voltage generating circuit according to the present embodiment. In the following description, the reference symbols used in the above description will be used where possible for ease of understanding.

[0077] 6, there is shown a method 100. The steps in the method 100 enable the reference voltage generating circuit 21 to adjust the internal reference voltage VREF during a period following power-on and prior to the start of operation of the internal circuit 23.

[0078] In step S101, the semiconductor device 13 or the reference voltage generating circuit 21 is prepared.

[0079] In step S102, the high voltage power supply line 17 and the low voltage power supply line 19 of the reference voltage generating circuit 21 and the target voltage generating circuit 33 are activated to generate the internal reference voltage VREF and the target voltage VTRG.

[0080] In step S103, after starting up the high voltage power line 17 and the low voltage power line 19, the switches SW of the adjustment circuit 35 are sequentially switched between conductive and non-conductive states to change the internal reference voltage VREF.

[0081] In step S104, each time the switch SW is switched, a determination is made as to which of the internal reference voltage VREF and the target voltage VTRG is larger.

[0082] In step S105, the value stored in the volatile storage circuit 51 that defines the conductive / non-conductive state of the switch SW of the adjustment circuit 35 is identified as a result of the determination.

[0083] In step S106, the stored value in the storage circuit 51 is identified, and then the identified stored value is reset in the storage circuit 51.

[0084] In step S107, after the stored value is reset in the storage circuit 51, the internal circuit 23 is operated.

[0085] As described above, a reference voltage generating circuit and a semiconductor device are provided that enable adjustment of the value of the internal reference voltage each time the power supply is turned on.

[0086] As can be understood from the above description, the present embodiment has various aspects.

[0087] A reference voltage generation circuit of a first aspect according to this embodiment is an internal reference voltage generation circuit including a current source and a voltage divider circuit connected in series from one side of a high voltage power line and a low voltage power line to the other, and an output, and configured to generate an internal reference voltage at the output, wherein the voltage divider circuit is provided with: an internal reference voltage generation circuit including a plurality of resistors connected in series between the output and the high voltage power line or the low voltage power line; a target voltage generation circuit connected between the high voltage power line and the low voltage power line and having an output for providing a target voltage; an adjustment circuit including respective switches connected to at least some of the resistors so as to be able to individually short out at least some of the resistors; storage circuits having respective volatile storages configured to determine the conduction / non-conduction of the switches of the adjustment circuit; and a comparison circuit including a determination circuit configured to determine the stored value of the storage circuit based on the magnitude relationship between the internal reference voltage and the target voltage.

[0088] In the reference voltage generating circuit of the second aspect according to the first aspect of the present embodiment, the current source of the internal reference voltage generating circuit can be configured to receive a voltage from an intermediate node of the voltage divider circuit.

[0089] In a third aspect of the reference voltage generating circuit according to the second aspect of this embodiment, the current source of the internal reference voltage generating circuit may include a bandgap reference circuit connected between the high voltage power supply line and the low voltage power supply line, a differential amplifier circuit having a first input connected to an output of the bandgap reference circuit and a second input connected to the intermediate node, and a current source transistor connected to the output of the differential amplifier circuit.

[0090] In a reference voltage generating circuit according to the first, second or third aspect of this embodiment, the adjustment circuit may include a select circuit configured to control the conduction / non-conduction of the switch in response to an output value from each of the storage circuits.

[0091] In a reference voltage generation circuit of a fifth aspect according to the first aspect, the second aspect, the third aspect or the fourth aspect of this embodiment, the target voltage generation circuit may include a plurality of first resistors connected in series between the output of the target voltage generation circuit and the high voltage power supply line, and a plurality of second resistors connected in series between the output of the target voltage generation circuit and the low voltage power supply line.

[0092] In the reference voltage generating circuit of the sixth aspect according to the first aspect, the second aspect, the third aspect, the fourth aspect, or the fifth aspect of this embodiment, the judgment circuit further includes a detection circuit, and the detection circuit can include a comparator configured to compare the internal reference voltage with the target voltage in an adjustment operation of the internal reference voltage to generate a comparison result, a holding circuit configured to receive a previous result, which is a previous comparison result, each time the comparison result is generated and hold the previous result, and a mismatch detection circuit configured to detect a mismatch between the comparison result and the previous result and generate a mismatch signal.

[0093] In the reference voltage generating circuit of the seventh aspect according to the sixth aspect of this embodiment, the judgment circuit can be configured to perform at least one of the following in response to the mismatch detection circuit detecting the mismatch: retaining a set value at the time of detecting the mismatch; and retaining a set value immediately before detecting the mismatch.

[0094] In the reference voltage generating circuit of the eighth aspect according to the sixth or seventh aspect of this embodiment, the determination circuit further comprises an adjustment control circuit, the adjustment control circuit includes a setting control circuit, and the setting control circuit is configured to set, in the storage circuit of the comparison circuit, a value specifying the conduction / non-conduction of the switch of the adjustment circuit so that the internal reference voltage generating circuit generates, as an initial value in the adjustment operation of the internal reference voltage, a voltage value in which the internal reference voltage is closer to one of the voltages of the high voltage power line or the low voltage power line than the other of the voltages of the high voltage power line or the low voltage power line, and the setting control circuit can be configured to transfer a series of setting values ​​including the initial value to the storage circuit for the adjustment operation.

[0095] In the reference voltage generating circuit of a ninth aspect according to the eighth aspect of this embodiment, the adjustment control circuit may further include a second storage circuit configured to hold a setting value in the setting control circuit in response to the mismatch signal.

[0096] In the reference voltage generating circuit of the tenth aspect according to the ninth aspect of this embodiment, the adjustment control circuit can be configured to reset the storage circuit of the comparison circuit according to the stored value of the second storage circuit after the adjustment operation is completed.

[0097] The semiconductor device of an eleventh aspect of this embodiment may include a reference voltage generation circuit described in any one of the first to tenth aspects, and an internal circuit including a circuit that receives the internal reference voltage of the reference voltage generation circuit.

[0098] In a semiconductor device according to a twelfth aspect of the eleventh aspect of the present embodiment, the internal circuit may include a voltage regulator that receives the internal reference voltage and operates accordingly.

[0099] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0100] 10...Load circuit, 11. Semiconductor systems, 13 Semiconductor device, 15...Power supply device, 17 High voltage power lines, 19. Low voltage power line, 20...electrode, 21... Reference voltage generating circuit, 23...internal circuit, 25... Control circuit, 31: Internal reference voltage generating circuit; 33...Target voltage generation circuit, 35...adjustment circuit, 37...comparison circuit, 41...current source, 43... Voltage divider circuit, 45b, 45c... Output, 47 Resistor, 49....Mismatch detection circuit, 51... Storage circuit, 53...judgment circuit, 55...container, 57 Reference voltage source, 59 Differential amplifier circuit, 59b, 59c... Input, 59d...output, 61 - current source transistor; 63...Select circuit, 65...container, 67b... First resistor, 67c...Second resistor, 67d Transistor, 69... Detection circuit, 71... Regulating control circuit, 73... Setting control circuit, 75... second storage circuit, 75b Main circuit, 75c...Auxiliary circuit, 77 Comparator, 79... First storage circuit; 81...Holding circuit, 83 Counter circuit, 85... third storage circuit, 87 Address generation circuit, CLK: Clock signal, NCOM1: Shared node, NDM: intermediate node, SW... Switch, TADJ...Adjustment operation period, TIGN: Start-up period, TNML...Normal operating period, VREF: Internal reference voltage, VTRG Target voltage.

Claims

1. an internal reference voltage generating circuit including a current source and a voltage dividing circuit connected in series from one side of a high voltage power line and a low voltage power line to the other side, and an output, and configured to generate an internal reference voltage at the output, the voltage dividing circuit including a plurality of resistors connected in series between the output and the high voltage power line or the low voltage power line; a target voltage generating circuit connected between the high voltage power line and the low voltage power line, the target voltage generating circuit having an output for providing a target voltage; an adjustment circuit including switches connected to at least some of the resistors so as to individually short out at least some of the resistors; a comparison circuit including a storage circuit having a volatile storage unit configured to determine whether the switch of the adjustment circuit is conductive or non-conductive, and a determination circuit configured to determine a stored value of the storage circuit based on a magnitude relationship between the internal reference voltage and the target voltage; Equipped with Reference voltage generation circuit.

2. The current source of the internal reference voltage generating circuit is configured to receive a voltage from an intermediate node of the voltage dividing circuit.

2. The reference voltage generating circuit according to claim 1.

3. the current source of the internal reference voltage generating circuit includes: a bandgap reference circuit connected between the high voltage power supply line and the low voltage power supply line; a differential amplifier circuit having a first input connected to an output of the bandgap reference circuit and a second input connected to the intermediate node; and a current source transistor connected to an output of the differential amplifier circuit.

3. The reference voltage generating circuit according to claim 2.

4. the adjustment circuit includes a select circuit configured to control the conduction / non-conduction of the switch in response to an output value from each of the storage circuits; 2. The reference voltage generating circuit according to claim 1.

5. the target voltage generation circuit includes a plurality of first resistors connected in series between the output of the target voltage generation circuit and the high voltage power supply line, and a plurality of second resistors connected in series between the output of the target voltage generation circuit and the low voltage power supply line; 2. The reference voltage generating circuit according to claim 1.

6. The determination circuit further includes a detection circuit, The detection circuit includes: a comparator configured to compare the internal reference voltage with the target voltage in an adjustment operation of the internal reference voltage to generate a comparison result; a holding circuit configured to receive a previous result, which is a previous comparison result, for each generation of the comparison result and hold the previous result; a mismatch detection circuit configured to detect a mismatch between the comparison result and the previous result and generate a mismatch signal; Including, 2. The reference voltage generating circuit according to claim 1.

7. The determination circuit, in response to the mismatch detection circuit detecting the mismatch, retaining the set value upon detection of said mismatch; and maintaining a setting value immediately prior to detection of said mismatch; configured to perform at least one of 7. The reference voltage generating circuit according to claim 6.

8. The determination circuit further includes an adjustment control circuit, The adjustment control circuit includes a setting control circuit, the setting control circuit is configured to set, as an initial value in an adjustment operation of the internal reference voltage, in the storage circuit of the comparison circuit, a value specifying the conduction / non-conduction of the switch of the adjustment circuit so that the internal reference voltage generation circuit generates a voltage value in which the internal reference voltage is closer to one of the voltages of the high-voltage power line or the low-voltage power line than to the other of the voltages of the high-voltage power line or the low-voltage power line; the setting control circuit is configured to transfer a set of setting values ​​including the initial value to the storage circuit for the adjustment operation; 7. The reference voltage generating circuit according to claim 6.

9. the adjustment control circuit further comprises a second storage circuit configured to hold a setting value within the setting control circuit in response to the mismatch signal; 9. The reference voltage generating circuit according to claim 8.

10. the adjustment control circuit is configured to reset the storage circuit of the comparison circuit according to the stored value of the second storage circuit after the adjustment operation is completed; 10. The reference voltage generating circuit according to claim 9.

11. A reference voltage generating circuit according to any one of claims 1 to 10; an internal circuit including a circuit for receiving the internal reference voltage of the reference voltage generating circuit; A semiconductor device comprising:

12. the internal circuit includes a voltage regulator that operates in response to the internal reference voltage; The semiconductor device according to claim 11.

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