Display device

Abstract

To provide a novel display device.SOLUTION: A display device with a 2T-1C circuit structure includes a switch between a current supply line and a transistor. The switch is controlled to be turned off in a data voltage writing period. By turning off the switch, one of a source and a drain of the transistor can be made an electrically floating state. Thus, the increase in potential on an anode side of a light-emitting element can be suppressed and unintended light emission in the data voltage writing period can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter Therefore, one embodiment of the present invention disclosed in the present specification more specifically relates to The technical fields include semiconductor devices, display devices, light-emitting devices, power storage devices, imaging devices, memory devices, The driving method thereof or the manufacturing method thereof can be given as an example. [Background technology]

[0003] Electroluminescence (EL) element (hereafter referred to as Display devices equipped with light-emitting elements, typically EL elements, are being actively developed.

[0004] For example, Patent Documents 1 to 4 disclose a pixel having two transistors and at least one A circuit configuration of a 2T-1C structure with a capacitor is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2007 / 0268210 [Patent Document 2] US Patent Application Publication No. 2009 / 0219234 [Patent Document 3] US Patent Application Publication No. 2008 / 0030436 [Patent Document 4] International Publication No. 2006 / 060902 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, there are many different circuit configurations that a display device has. Each configuration has its advantages and disadvantages, and the appropriate configuration is selected depending on the situation. If display devices and the like could be proposed, it would lead to greater freedom of choice.

[0007] An object of one embodiment of the present invention is to provide a novel display device, a driving method for the novel display device, and the like. It shall be one of the following.

[0008] In the 2T-1C pixel of Patent Documents 1 to 4, a gate is generated by passing a current through a transistor. -The voltage held between the source and drain is adjusted to achieve mobility compensation. The current is passed by increasing the potential of the wiring (current supply line) for passing the current to the light-emitting element. However, if the potential of the current supply line is increased during the correction period, There is a risk of unintended emission of light from the light-emitting element.

[0009] In view of the above, one embodiment of the present invention is a method for suppressing unintended light emission from a light-emitting element during a period in which correction is performed. It is an object of the present invention to provide a semiconductor device or the like having a novel structure.

[0010] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. This does not preclude the existence of other issues. Other issues may be discussed in the following sections. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by reading the specification or can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. It should be noted that one aspect of the present invention is to achieve at least one of the above-listed and / or other objects. Both of these methods solve a single problem. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a first switch, a transistor, a capacitor, and a light-emitting element. and a wiring electrically connected to one terminal of the second switch. an apparatus, comprising: a first electrode of the capacitor electrically connected to a gate of a transistor; The second electrode of the capacitor is connected to one of the source and drain of the transistor and the light-emitting element. The other of the source and drain of the transistor is electrically connected to the first electrode. The wiring is electrically connected to the other terminal of the switch 2 and serves to supply current to the light-emitting element. The first switch is turned on to apply a data voltage to the gate of the transistor. The second switch has a function of supplying a data voltage to the gate of the transistor. By turning off the transistor between the source and drain, the other of the transistors is left in an electrically floating state. It is a display device having the function of

[0012] In one embodiment of the present invention, a transistor includes an oxide semiconductor in a channel formation region. A display device which is a transistor is preferred.

[0013] One embodiment of the present invention is a semiconductor device including a first switch, a transistor, a capacitor, and a light-emitting element. and a wiring electrically connected to one terminal of the second switch, The first electrode of the capacitor is electrically connected to the gate of the transistor, and the second electrode of the capacitor is electrically connected to the gate of the transistor. The electrode is connected to one of the source and drain of the transistor and the first electrode of the light-emitting element. The other of the source or drain of the transistor is electrically connected to the other of the second switch. a terminal of the display device, and the wiring has a function of supplying a current to the light-emitting element; The driving method includes first to third periods, and the first period is a period during which a threshold voltage of a transistor is increased. The first period is a period during which a voltage corresponding to the data voltage is held in the capacitor, and the second period is a period during which a voltage corresponding to the data voltage is held in the capacitor. The third period is a period during which the applied voltage is held in the capacitor, and the third period is a period during which the light emitting element is turned on. In the second period, the second switch is turned off to turn on the transistor. This is a method for driving a display device in which the other of the source or drain of a transistor is placed in an electrically floating state.

[0014] One embodiment of the present invention is a semiconductor device including a first switch, a transistor, a capacitor, and a light-emitting element. and a wiring electrically connected to one terminal of the second switch, The first electrode of the capacitor is electrically connected to the gate of the transistor, and the second electrode of the capacitor is electrically connected to the gate of the transistor. The electrode is connected to one of the source and drain of the transistor and the first electrode of the light-emitting element. The other of the source or drain of the transistor is electrically connected to the other of the second switch. a terminal of the display device, and the wiring has a function of supplying a current to the light-emitting element; The driving method includes first to third periods, and the first period is a period during which a threshold voltage of a transistor is increased. The first period is a period during which the capacitor is held at a voltage corresponding to the data voltage in the threshold voltage. The third period is a period during which the applied voltage is held in the capacitor, and the third period is a period during which the light-emitting element In the first period, the second switch is turned on to emit light. The potential of the other of the source or drain of the light emitting element is set to a potential higher than the potential applied to the second electrode of the light emitting element. In the second period, the second switch is turned off to turn on the transistor. This is a method for driving a display device in which the potential of the other of the source or drain is kept in an electrically floating state.

[0015] In one embodiment of the present invention, in the third period, the second switch is turned on to The potential of the other of the source or drain of the light emitting element is set to a potential higher than the potential applied to the second electrode of the light emitting element. A method of driving a display device that provides a large potential is preferred.

[0016] Other aspects of the present invention will be described in the following embodiments and As shown in the drawings. Effect of the Invention

[0017] One embodiment of the present invention can provide a novel display device or the like.

[0018] Alternatively, according to one embodiment of the present invention, unintended light emission from a light-emitting element can be suppressed during a period in which correction is performed. It is possible to provide a display device or the like having a novel configuration.

[0019] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects are described below. The effects not mentioned in this section are obvious to those skilled in the art in the art from the description or the description. can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. In addition, one embodiment of the present invention has at least one of the above-listed effects and / or other effects. Therefore, one aspect of the present invention is, in some cases, In some cases, it may not have the effects described above. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 2] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 5] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 7] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 8] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 9] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 10] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 11] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 12] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 13] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 14] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 15] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 16] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 17] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 18] FIG. 1 is a block diagram illustrating one embodiment of the present invention. [Figure 19] 1 is a timing chart illustrating one embodiment of the present invention. [Figure 20]1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 22] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 23] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 24] FIG. 1 is a top view illustrating one embodiment of the present invention. [Diagram 25] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 26] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 27] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 28] FIG. 1 is a top view illustrating one embodiment of the present invention. [Figure 29] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 30] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 31] FIG. 1 is a layout diagram illustrating one embodiment of the present invention. [Diagram 32] FIG. 1 is a schematic cross-sectional view illustrating one embodiment of the present invention. [Diagram 33] FIG. 1 is a layout diagram illustrating one embodiment of the present invention. [Diagram 34] FIG. 1 is a layout diagram illustrating one embodiment of the present invention. [Diagram 35] FIG. 1 is a schematic cross-sectional view illustrating one embodiment of the present invention. [Diagram 36] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 38] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Figure 39] FIG. 1 is a perspective view illustrating one embodiment of the present invention. [Diagram 40] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 41] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 42] FIG. 1 is a cross-sectional view illustrating one embodiment of the present invention. [Diagram 43] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Diagram 44] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 45] FIG. 1 is a schematic diagram illustrating one embodiment of the present invention. [Figure 46] FIG. 1 is a schematic diagram illustrating one embodiment of the present invention. [Figure 47] FIG. 1 is a schematic diagram illustrating one embodiment of the present invention. [Figure 48] FIG. 1 is a schematic diagram illustrating one embodiment of the present invention. [Figure 49] FIG. 1 is a perspective view illustrating one embodiment of the present invention. [Figure 50] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 51] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 52] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. [Figure 53] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, an embodiment will be described with reference to the drawings. However, the embodiment may be different from the embodiment. The present invention can be implemented in any manner without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to refer to the mixture of elements. Therefore, it does not limit the number of components. In addition, the order of the components is not limited. The components referred to as "first" in the above may be included in other embodiments or in the claims. In addition, for example, the second component may be referred to as a "second" component in the present specification. A component referred to as "first" in one embodiment may be used in other embodiments or in particular It may be omitted within the scope of the claims.

[0023] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In the following description, the same reference numerals may be used to denote elements or components formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0024] (Embodiment 1) The structure of a display device according to one embodiment of the present invention will be described with reference to FIGS.

[0025] <About pixels> First, the pixels of the display device will be described.

[0026] The pixel described in this embodiment is, as an example, a trans-pixel that adversely affects a displayed image. It has the function of correcting the variation in threshold voltage of the transistor.

[0027] A simple example of a mechanism for correcting the variation in threshold voltage is as follows. The data voltage written between the pixels and corresponding to the gradation level to be displayed is initialized. Set the transistor to be in the on state (conducting state). Then, set the threshold voltage or A voltage having a magnitude corresponding to the threshold voltage is held in the capacitor. A voltage according to a data voltage corresponding to the gray scale to be displayed is added to the held threshold voltage. After that, a current is passed through the light emitting element according to a voltage obtained by adding the data voltage to the threshold voltage. By doing so, it is possible to reduce the influence of the threshold voltage of the transistor on the current flowing through the light emitting element. can.

[0028] The above-mentioned operations are, in other words, for example, an initialization period, a threshold voltage correction period, a data voltage write period, and a In either period, a pixel can be selected and By switching the voltage of each wiring, such as the gate line, data line, and current supply line, a predetermined voltage is applied to the pixel. This is often the case.

[0029] In one aspect of this embodiment, as an example, in a data voltage writing period, The current supply line and the current supply line are electrically floating. A state of non-continuity is established between the current supply line and a circuit having a function of supplying voltage or the like to the current supply line. In this state, the data voltage is applied. A current supply line provided for passing a current through an element is made to be floating for a predetermined period of time. For this purpose, for example, a switch is provided between a current supply line and a transistor included in the pixel. During the data voltage writing period, the switch is turned off (non-conducting). This structure realizes an electrically floating state between the transistors. Regardless of the state, the potential of the anode of the light-emitting element can be prevented from increasing. Therefore, unintended light emission from the light emitting element can be suppressed.

[0030] Next, an example of a circuit configuration of a pixel will be described.

[0031] FIG. 1A illustrates a pixel 100 of a display device according to one embodiment of the present invention. , PIX) includes a switch 101, a transistor 102, a capacitor 103, and The pixel 100 includes a light emitting element 104. Also, in FIG. That is, as an example, the switch 106 is set outside the pixel 100. In addition, a plurality of pixels are provided in the display device. corresponds to one pixel selected from among a plurality of pixels.

[0032] In FIG. 1A, the gate of the transistor 102 is connected to a node N G Also, Fig. 1 In (A), the node between the transistor 102 and the light emitting element 104 is called a node N S Shown as In FIG. 1A, the node between the transistor 102 and the switch 106 is Node N D The transistor 102 is a driving transistor. There are cases.

[0033] One terminal of the switch 101 is connected to the data line DL, for example. The other terminal of 01 is, for example, a node N G The switch 101 is connected to The switch 101 may be called a first switch. Alternatively, the switch 101 may be called a selection switch. There are also cases where this is the case.

[0034] For example, the data line DL is supplied with an initialization voltage during the initialization period and the threshold voltage correction period. The data line DL is an example of a wiring that has the function of applying (or transmitting) pressure. In the data voltage writing period, a data voltage (or a video signal voltage, a video signal voltage) is applied to the pixel 100. It is a wiring that has the function of giving (or transmitting) a digital signal. The data line DL, for example, provides (or transmits) a precharge voltage to the pixel 100. However, the functions of the data line DL are not limited to these. Therefore, the data line DL may be simply called a wiring or a first wiring.

[0035] The data voltage applied to the data line DL is a voltage for causing the light emitting element 104 to emit light with a desired gradation value. The data voltage is V DATA It may be expressed as:

[0036] The initialization voltage applied to the data line DL is used to initialize the voltage across the capacitor 103. Alternatively, the initialization voltage is a voltage that has a function of turning on the transistor 102. The initialization voltage is V G-INI It may be expressed as:

[0037] The gate of transistor 102 is connected to node N G The source of transistor 102 is connected to Or one of the drains is connected to node N S The source of transistor 102 or The other drain is connected to node N D The source and drain of the transistor are connected to Therefore, for example, during the light emission period, the current supply line PL Since the potential of the cathode line CL is higher than the potential of the cathode line CL, in this case, the source of the transistor 102 The node N S In the following explanation, The transistor 102 will be described as an n-channel type. , and the threshold voltage of the transistor 102 is V TH It is expressed as:

[0038] The other terminal of the switch 106 is connected to the current supply line PL, for example. Switch 106 may be referred to as a first switch or a second switch.

[0039] The current supply line PL initializes the voltage across the capacitor 103 during the initialization period, for example. The current supply line PL is a wiring having a function of applying an initialization voltage for initializing the current. During the initialization period, node N S It has a function to provide an initialization voltage to initialize the voltage of The current supply line PL is a wiring that supplies the transistor 1 02 gate-source voltage (V GS The voltage required to pass a current according to The current supply line PL is a wiring that has the function of applying (or transmitting) pressure. During the light emission period, the V GS A current is passed through the light emitting element 104 according to the However, the function of the current supply line PL is to Therefore, the current supply line PL is not limited to a wiring or a first wiring. There are cases where this is said.

[0040] The initialization voltage applied to the current supply line PL is used to initialize the voltage across the capacitor 103. Alternatively, the initialization voltage is a voltage that is set so that the transistor 102 is turned on. The initialization voltage is V P-INI In addition, V P-I NI and V G-INI For example, different voltages. In some cases, the voltage may be the same.

[0041] The V of the transistor 102 is applied to the current supply line PL. GS The voltage required to pass the current according to For example, the light emitting element 104 is turned on to emit light, and the voltage across the capacitor 103 is turned on to This voltage is used to make the voltage held at the pole the threshold voltage of transistor 102. Zista 102 V GS The voltage required to pass the current according to P-EMI It may be expressed as .

[0042] In addition, when the light emitting element 104 emits light and when the threshold voltage of the transistor 102 is obtained, The magnitude of the voltage of the current supply line PL may be different in the above cases. When the transistor 104 emits light and when the threshold voltage of the transistor 102 is obtained, If the voltage of the current supply line PL is the same, the configuration of the circuit that supplies the voltage can be simplified as follows: This is more preferable because it allows

[0043] The voltage applied to the cathode line CL is V CS However, the function of the cathode ray CL is Therefore, the cathode line CL is simply a wiring, a first wiring, etc. There are cases where this is said.

[0044] One electrode of the capacitor 103 is connected to a node N G The other terminal of the capacitor 103 is connected to The electrode is node N S is connected to.

[0045] One electrode of the light emitting element 104 is connected to a node N S The other electrode of the light emitting element 104 is connected to is connected to the cathode line CL. The cathode line CL has V CS Note that the capacitor 103 can be omitted by utilizing the gate capacitance (parasitic capacitance) of the transistor 102. An example of a circuit diagram of the pixel 100I in this case is shown in FIG.

[0046] <Pixel operation> Next, an example of the operation of the pixel 100 in FIG.

[0047] FIG. 1B shows an example of a timing chart for explaining the operation of the pixel 100. 3 to 5 show the voltages of the wiring and the operation of the switches during each period shown in FIG. 1(B). , a circuit diagram showing the voltages at nodes is shown.

[0048] The timing chart of FIG. 1B includes a light emission period P11, an initialization period P12, and an initialization completion period P13. The period is divided into a threshold voltage correction period P13, a threshold voltage correction period P14, and a data voltage writing period P15. The initialization period P12 and the initialization completion period P13 correspond to the initialization period described above. do.

[0049] The light emission period P11, the initialization period P12, the initialization completion period P13, and the threshold voltage correction period P 14 and a data voltage writing period P15 are provided. An embodiment of the present invention is not limited thereto. For example, an embodiment of the present invention may be used in a period other than these periods. Alternatively, for example, one aspect of the present invention may include At least one period may not be provided. For example, when the transistor 102 is on, If this state is the case, the initialization period P12 does not necessarily have to be provided.

[0050] The timing chart of FIG. 1B shows the state of the node N D , cathode ray CL, node N G, node N S In addition, in Fig. 1(B), the voltage change of each wiring and and the V that the node can take P-EMI , V DATA , V CS , V G-INI , V P-INI of An example of the magnitude relationship is shown with the vertical axis representing voltage. The threshold voltage of 102 is V TH , the voltage V held at both ends of the capacitor 103 CP , a voltage V applied to the electrodes at both ends of the light emitting element 104 EL Also, Fig. 1(B) shows As an example, the on / off states of the switches 101 and 106 are shown. In the description of FIG. 1B, the transistor 102 is normally on, that is, has a threshold voltage of Voltage V TH In this case, the transistor 102 is in the negative state. It can be operated normally whether in normal on or normally off mode.

[0051] In FIG. 1(B), even if the timing is the same or the potential is the same, However, in order to ensure visibility of the voltage changes of the wiring and nodes, the positions are shifted slightly. Therefore, the magnitude relationship of each voltage and the timing are not necessarily as shown in the figure. There are cases where this is the case.

[0052] First, in the initialization period P12, the potential held at the gate of the transistor 102 in the previous light emission period P11 is Alternatively, the voltage applied to the transistor 102 is turned on. Or, node N S Therefore, the voltage of When the transistor 102 is in an on state, the initialization period P12 is not necessarily provided. First, for example, node N G The voltage at is V G-INI and switch 101 is on This is the state of node N. G As the voltage at node N S of The voltage also drops. After the initialization period P12, the voltage of the cathode line CL drops to V CS does not change. However, the voltage of the cathode lines CL may be changed depending on the situation. By this, node N G The voltage at is V G-INI Each wiring and each The voltages of the nodes are as shown in FIG. 3(A). In the initialization period P12, The switch 106 may be in the off state.

[0053] Although the operation in the initialization period P12 has been described, one embodiment of the present invention is not limited to this. For example, in one embodiment of the present invention, various operations are performed in the initialization period P12. Therefore, the initialization period P12 may be simply called a period or a first period. There is a match.

[0054] Next, in the initialization completion period P13, the node N S The voltage held in the First, for example, the voltage of the current supply line PL is V P-INI and the switch 106 is in the on state. Node N D As the voltage on the transistor 102 drops, a current flows through the transistor 102. Node N S The voltage at node N S of Voltage is V P-INIThe voltages of each wiring and each node during the initialization completion period P13 are as shown in FIG. The result is as shown in Figure 3(B).

[0055] Furthermore, the voltage V P-INI For example, V CS Keep it smaller than this. This makes it possible to prevent current from flowing through the light emitting element 104. G-IN I V P-INI In this way, the transistor 102 However, the threshold voltage of the transistor 102 is large. Depending on the node N S The voltage at node N G Even if the voltage is higher than the In such a case, a current may flow through the transistor 102. S The voltage at node N G The voltage may be higher than the voltage during the initialization completion period P1. In 3, the switch 101 may be in the off state.

[0056] Although the operation during the initialization completion period P13 has been described, one aspect of the present invention is to For example, in one embodiment of the present invention, various operations are performed during the initialization completion period P13. Therefore, the initialization completion period P13 may be simply a period or a first period. There are cases where:

[0057] Next, in the threshold voltage correction period P14, V TH Or, V TH In order to maintain a voltage according to S Electricity In addition, when the variation in the characteristics of the transistor 102 is small, Or, when a moving image is being displayed, the influence of variations in the characteristics of the transistor 102 may occur. If the influence is small, it is not necessary to obtain the threshold voltage of the transistor 102. Therefore, depending on the situation, the threshold voltage correction period P13 may not be provided. The voltage of the supply line PL is V P-EMI and the switches 101 and 106 are in the on state. Node N D The voltage at node N rises, causing a current to flow through transistor 102. S The voltage at the switch 103 rises, and the charge stored in the capacitor 103 is discharged. 101 is in the on state, so node N G The voltage at node N does not change. S The voltage rise of V of transistor 102 GS V TH As a result, the current flowing through the transistor 102 becomes small. The current stops because the node N S The voltage of is the voltage (V G-INI -V TH ) and the capacitor 103 has a voltage (V TH ) accumulates. Therefore, the V of transistor 102 TH At this time, the transistor 10 If 2 is normally on, then node N S The voltage at node N G The voltage is higher than Node N S The voltage of is the voltage (V G-INI -V TH ) but , V TH Since is a negative value, the actual node N S The voltage at node N GThe voltage is higher than In other words, by performing such an operation, transistor 1 Even if the transistor 02 is normally on, the threshold voltage can be appropriately acquired. The voltages of the wirings and nodes during the positive period P14 are as shown in FIG. During this period, the voltage of the current supply line PL is V P-EMI For example, The voltage of the current supply line PL is the voltage of the node N S The voltage is higher than the That would be good.

[0058] Here, the V of the transistor 102 GS V TH However, V G S V TH The charge stored in the capacitor 103 does not need to be discharged until For example, the V of transistor 102 GS V TH When the magnitude of the In that case, the voltage acquisition operation may be terminated. TH Large according to This means that the voltage magnitude has been obtained.

[0059] Note that the operation during the threshold voltage correction period P14 has been described. For example, in one embodiment of the present invention, various Therefore, the threshold voltage correction period P14 may simply be a period or a first period. It may also be referred to as a period of time.

[0060] Next, in the data voltage write period P15, V DATA And, Switch 101 is in the on state. Node N G The voltage at is V G-INI From V DATA To Also, the switch 101 is in the OFF state. Therefore, the node N D is electrically Node N is in a floating state. S The voltage at node N G The voltage change of Therefore, it changes according to the capacitive coupling of the capacitor 103 .

[0061] Here, the voltage of the capacitor 103 is V CP In addition, the capacitance of the capacitor 103 is C 103 The capacitance of the light emitting element 104 is C EL In Fig. 6, The voltage and capacitance of the element are shown. The voltage held on the electrodes of the capacitor is V CP is capacitively coupled to V TH +ΔV. ΔV is the voltage at node N G The change in voltage ( V DATA -V G-INI ) and the capacitance of the capacitor 103 and the light-emitting element 104 Ratio(C EL / (C 103 +C EL )) can be expressed as

[0062] That is, in the data voltage input period P15, the node N S The voltage at (V DATA -V CP ) However, the capacitance C of the light emitting element 104 EL By increasing In addition, the node N S Even if the voltage rises, the data voltage writing period Between P15 and node N DTherefore, the current supply line PL is Since no current flows through the transistor 102 toward the light emitting element 104, the light emitting element 10 Unintended light emission of 4 can be suppressed. Each wiring by the data voltage input period P15, The voltage at each node becomes as shown in FIG.

[0063] Although the operation during the data voltage writing period P15 has been described, one aspect of the present invention is However, the present invention is not limited to this. For example, in one aspect of the present invention, Therefore, the data voltage writing period P15 is simply It may be referred to as the period, the first period, etc.

[0064] In the configuration of this embodiment, the switch 106 is turned on during the data voltage writing period P15. In the off state, node N D Therefore, during the data voltage write period, Node N between S The change in the voltage of the light emitting element 104 can be suppressed. If the length of the data voltage writing period P15 is long, Even if you do, node N D is electrically floating, so node N S Suppress the voltage change of It is possible.

[0065] If the switch 106 is in the on state during the data voltage writing period P15, is connected from the current supply line PL through the transistor 102 to the node N S Current flows towards the As a result, node N S The potential of the data voltage writing period P1 If the length of 5 is longer, then the node NS The potential of the capacitor increases further, and finally The voltage of the 103 resistor is V TH Then, the transistor 102 is turned off. As a result, the supplied V DATA As a result, the data is lost. During the data voltage writing period P15, it is desirable that the switch 106 be in the off state. However, one embodiment of the present invention is not limited thereto.

[0066] Next, during the light emission period P11, the voltage of the current supply line PL is V P-EMI and switch 106 is in the on state, and switch 101 is in the off state. D Voltage is supplied to the Node N G Since the node N S The voltage at node N G Since is floating, node N S of As the voltage rises, node N G The voltage of the transistor V GS Data voltage list V set during the write period CP Hold the V CP is V TH V DATA A term containing Therefore, the light emitting element 104 is supplied with a voltage of V TH It does not depend on the size of V DAT A In other words, a current according to V TH The effect of variation in Note that node N S V CS From V EL A voltage higher than the EL +V CS ) Also, node N G is (V CS +V EL ) to V CP A voltage higher than the CP +V CS +V EL The voltages of the wiring and nodes during the light emission period P11 are as shown in FIG. become.

[0067] Although the operation in the light emission period P11 has been described, one embodiment of the present invention is not limited to this. For example, in one embodiment of the present invention, various operations may be performed in the light emission period P11. Therefore, the light emission period P11 may be simply called the period or the first period. do.

[0068] In the above-described structure according to one embodiment of the present invention, the source or drain of the transistor 102 A switch is provided on the side of the gate where the current supply line PL is located. By turning off the switch during this period, the pixel 100 is electrically disconnected from the current supply line PL. The wiring that supplies current to the pixel 100 is electrically floating. The node N on the anode side of the light-emitting element S This suppresses the rise in the voltage of the data write However, in one embodiment of the present invention, this can be achieved by suppressing unintended light emission during the light-receiving period. Not limited.

[0069] <Modification of pixel>

[0070] Next, a modification of the circuit configuration of the pixel shown in FIG. 1(A) will be described.

[0071] The switch 101 and the switch 106 of the pixel 100 in FIG. A circuit diagram of this case is shown in FIG. 7. The transistor 101A is used instead of the switch 101 in FIG. The on / off state of the transistor 101A is controlled by the potential applied to the gate line GL. Therefore, the transistor 101A may be called a selection transistor. .

[0072] In addition, in FIG. 7, a transistor 106A is illustrated in place of the switch 106. The on / off state of the transistor 106A is controlled by the power supply control line P EN It is controlled by the potential applied to It is possible.

[0073] For example, the transistor 101A and the transistor 106A each have a channel formation region The transistor is preferably an oxide semiconductor transistor (OS transistor). The transistor can reduce the off-current. Therefore, the transistor functions as a switch. By turning off the transistor 101A, the node N G The fluctuation of the potential can be reduced. , the transistor 106A, which functions as a switch, is turned off, so that the node N D Electric potential of Alternatively, the transistor 101A and the transistor 106A can reduce the fluctuation of the transistor. It may be a transistor having silicon in the channel forming region (Si transistor). Note that the transistor 102 is also a transistor having an oxide semiconductor in a channel formation region. However, one embodiment of the present invention is not limited to this. For example, the transistor 102 is a transistor having silicon in a channel formation region. The channel formation in a Si transistor may be performed. The regions may be polycrystalline silicon, amorphous silicon, or monocrystalline silicon. It may be crystalline silicon.

[0074] The pixel 100 in FIG. 1A has, as an example, a capacitor in parallel with a light emitting element 104. It is preferable that the pixel 100B shown in FIG. 8A has a circuit diagram in this case. has a capacitor 105 in addition to the configuration of FIG.

[0075] In the above-mentioned embodiment of the present invention, the capacitance ratio of the capacitor 103 to the light-emitting element 104 is The capacitance of the capacitor 103 is connected to the capacitance of the light emitting element 104. If the data voltage input period P15 is larger than the node N S The potential of the There is a risk that the optical element will emit light. Therefore, it is preferable to provide a capacitor 105 separately. The configuration in Figure 8(A) is preferable because it allows the capacitor to be fabricated without increasing the number of wirings. be.

[0076] The capacitor 105 may be fabricated by providing a separate capacitance line. The circuit diagram in this case is shown in FIG. The pixel 100C shown in FIG. 8B has a capacitance line C The capacitor 105 has one electrode connected to the SL.

[0077] In the configuration of FIG. 8B, although the number of wirings increases, the cathode of the light emitting element 104 is connected to the transistor 10 Since it can be easily fabricated without going through complicated processes such as connecting to the electrode layer of 2, It is possible to make it.

[0078] FIG. 9A shows a pixel 100D which is a modified version of the pixel 100A shown in FIG. 0D is a transistor with a back gate that functions as a switch. The transistor 106A has the same configuration as the transistor 101B. It is possible to make the following:

[0079] FIG. 9B shows a pixel 100E which is a modified version of the pixel 100A in FIG. 0E is a transistor that functions as a switch and is connected in series. The transistor 106A is also the same as the transistor 101C. It is possible to have a similar configuration.

[0080] FIG. 10A shows a pixel 100F which is a modified version of the pixel 100A shown in FIG. 00F has a back gate as the transistor 102, and the same potential is applied to the upper and lower gates. The transistor 102D is a transistor that can be used as a transistor having a capacitance of 102A.

[0081] FIG. 10B shows a pixel 100G which is a modification of the pixel 100A shown in FIG. 00G has a back gate as the transistor 102, and the upper and lower gates have different potentials. The back gate of the transistor 102E is connected to the voltage V BG Give, Tran The threshold voltage of the resistor 102E can be controlled.

[0082] FIG. 10C shows a pixel 100H which is a modification of the pixel 100A in FIG. 00H has a back gate as the transistor 102, and the upper and lower gates have different potentials. The back gate of the transistor 102F is connected to the node N S Applying a voltage of There are.

[0083] Note that the transistor 102 in the pixel 100 in FIG. 1A is an n-channel transistor. However, one aspect of the present invention is not limited to this. 11 shows a different configuration from that of the transistor 102. The transistor 102p is a diode type transistor.

[0084] The transistor 102 is connected to the current supply line PL via a switch 106. However, one embodiment of the present invention is not limited thereto. For example, in the pixel 100K in FIG. 1A. In FIG. 12A, the transistor 102 and , a current supply line PL_A via a switch 106A, and a current supply line PL_B via a switch 106B. The current supply line PL_B is connected to the current supply line PL_C via the switch 106C. The current supply lines PL_A, PL_B, and PL_C are set to different voltages, V P-EMI , V CS , V P-INI and controls the on / off of the switches 106A, 106B, and 106C. By this, the magnitude of the voltage supplied to the transistor 102 can be controlled. By providing the switches in this way, the current supply lines PL_A, PL_B, and PL_C It is possible to realize a similar operation without changing the position.

[0085] In the pixel 100K in FIG. 12A, different current supply lines PL_A, PL_B, and PL_C are provided. The configuration is such that a constant voltage is applied, and the wiring that applies a voltage by switching is used. The pixel circuit diagram in this case is shown in FIG. In pixel 100L of FIG. 12(B), a current flows through transistor 102 and switch 106D. The supply line PL_D is connected to the current supply line PL_E via the switch 106E, and the current supply line PL_E is connected to the supply line PL_D via the switch 106E. The current supply line PL_D is connected to V P-EMI , V to the current supply line PL_E CS or V P-INI By controlling the on / off of the switches 106D and 106E, The magnitude of the voltage supplied to transistor 102 can be controlled.

[0086] Note that the pixel 100M in FIG. 13A has a different configuration from that in FIG. 1A. In 3(A), node N S The line IL is connected to the line IL via a switch 107. The line IL is the initialization voltage V P-INI This switch 107 is set to ON for at least the initialization period. By turning on the power supply line P12 during the period P13, the current can be increased without lowering the voltage of the current supply line PL. Node N S In addition, the voltage can be controlled to a low voltage during periods other than the initialization period P12. In this case, it is desirable that the switch 107 is in an off state. One aspect is not limited to this.

[0087] In addition, the switches 101 and 107 in the pixel 100M in FIG. The circuit diagram of the pixel in this case is shown in FIG. The pixel 100N includes a transistor 101A and a transistor 107A. Transistor 101A can be controlled by gate line GL_A. A can be controlled by gate line GL_B.

[0088] The pixel 100O in FIG. 14(A) has a different configuration from that in FIG. 1(A). ) at node N S A switch 108 may be provided between the light emitting element 104 and the For example, the switch 108 is turned on during at least one period other than the light emission period P11. Alternatively, the switch may be turned off during the light emission period P11 and turned on during at least the light emission period P12. The switch 108 may be turned on during the data voltage writing period P15. This makes it possible to prevent the light emitting element 104 from unintentionally emitting light. This switch may be in the on state also during the data voltage input period P15.

[0089] In addition, the switches 101 and 108 in the pixel 100O in FIG. The circuit diagram of the pixel in this case is shown in FIG. The pixel 100P includes a transistor 101A and a transistor 108A. Transistor 101A can be controlled by gate line GL_A. A can be controlled by the gate line GL_C.

[0090] The pixel 100Q in FIG. 14C has a different configuration from that in FIG. 14A. C) At node N S and the light emitting element 104, but between the transistor 102 and the switch A switch 108 is provided between the switch 106 and the The switch can be controlled in this way.

[0091] The pixel 100R in FIG. 15(A) has a different configuration from that in FIG. 1(A). ) a switch 106D and a circuit 1 The circuit 109A and the switch 106E are provided. The circuit 109A controls the voltage of the current supply line PL to Node N D This is a circuit that has the function of smoothing the waveform when it is applied to the The pixel 100R may be provided inside the pixel 100R or outside the pixel 100R. stomach.

[0092] The circuit 109A functions by changing the on state of the switches 106D and 106E. It is preferable to switch between a function and a non-function. If you want 09A to function, you need to use node N. D This is the case when you want to smooth out the waveform. An example of such a case is the light emission period P11. When the transition to 1 is made, as shown in FIG. 15(B), the switches 106D and 106E are turned on. Change the node state and D By smoothing the voltage waveform, the brightness changes smoothly. This reduces the amount of glare felt by the eyes when using the display device. It is expected that this will reduce eye strain and the perception of flicker. It is expected that this will be gentle on the eyes and reduce eye fatigue.

[0093] The circuit 109A may be, for example, a resistor element as shown in FIG. It may be configured as a diode as shown in FIG. 16(B). Alternatively, it may be configured as shown in FIG. 16(C). The transistor may be diode-connected as shown in FIG.

[0094] As shown in FIG. 16(D), when the circuit 109A is to be operated, the switch 106D is turned on. When the switch 106 is turned off, and when the switch 106 is not to be operated, the switch 106D may be turned on. Also, the circuit 109A combines a resistor element and a capacitor as shown in FIG. A circuit having the same configuration may also be used.

[0095] It is also possible to configure a circuit by combining the circuits shown in FIGS. 12 to 15. For example, a pixel 100S in the case of combining FIG. 12(A) and FIG. 13(A) is shown in FIG. 17(A). Similarly, pixel 10 in the case of combining FIG. 12(A) and FIG. 14(A) is 0T is shown in FIG. 17(B). Similarly, FIG. 12(A), FIG. 13(A), and FIG. 14(A) are combined. The pixel 100U in this case is shown in FIG. It is also possible to configure a path.

[0096] As described above, various modifications can be applied to one embodiment of the present invention.

[0097] <Block diagram of display device> Next, an example of a block diagram of a display device to which the pixel shown in FIG. 1A can be applied will be described. do.

[0098] FIG. 18 shows an example of a block diagram of a display device, which includes a gate line side driving circuit 110, a data line A pixel section 140 having a side driving circuit 120, a current supply line control circuit 130, and pixels 100 is illustrated.

[0099] In the pixel section 140, a plurality of pixels 100 are arranged in a matrix in the xy direction. In the pixel section 140, the gate lines GL The gate lines GL1 to GLm (m is a natural number) are provided. For example, the gate line GL in FIG. 10 in the pixel section 140. Also, in the Y direction, The data lines DL1 to DLn (n is a natural number) are provided. are connected to each pixel 100. For example, the data line DL in FIG. The data line side driver circuit 120 is connected to the data line side driver circuit 120 .

[0100] The current supply line PL is connected to the current supply line control circuit 130 in the X direction as shown in FIG. The current supply lines PL1 to PLm can be provided so as to be connected to each pixel 100. For example, node N in Fig. D are connected to the current supply line control circuit 130.

[0101] The current supply line control circuit 130 can scan the current supply lines PL1 to PLm one row at a time. The current supply line control circuit 130 can also control the power supply control line P1 EN ~Pm EN By each line The power supply control line P1 can be turned on or off. EN ~Pm EN In this case, the switches provided in the current supply lines PL1 to PLm are turned off for each row, and the current supply lines are electrically floating. The switches provided in the current supply lines PL1 to PLm can be in a free state. For example, this corresponds to switch 106 in FIG.

[0102] In addition, in FIG. 19, gate lines GL1 to GLm, current supply lines PL1 to PLm, and power Control line P1 EN ~Pm EN The state of the switches controlled by the The timing chart of the operation is shown below.

[0103] <Modifications of pixel operation> Next, a modified example of the operation of the pixel 100 shown in FIG. 1(A) will be described.

[0104] FIG. 20A shows a circuit diagram of the pixel 100 shown in FIG. 1A. FIG. 1B is a timing chart illustrating a modified example of the operation of the pixel 100. 21 to 23, the voltage of each wiring in each period shown in FIG. 20(B) is A circuit diagram showing the voltages at the inputs, switches, and nodes is shown.

[0105] In the explanation of FIG. 20B, unlike FIG. 1B, the transistor 102 is normally-off. f, i.e., the threshold voltage V TH In the following, we will assume that is positive. The above explanation may be used to refer to similar points, and the same points may be omitted. do.

[0106] The timing chart of FIG. 20B shows a light emission period P21, an initialization period P22, and an initialization completion period P23. The period is divided into a period P23, a threshold voltage correction period P24, and a data voltage writing period P25. The initialization period P22 and the initialization completion period P23 are different from the initialization period described above. Respond.

[0107] The timing chart of FIG. 20B shows the state of the node N D , Cathode ray CL, No DoN G , node N S In addition, in FIG. 20(B), the voltage change of each wiring and the possible V for the node P-EMI , V DATA , V CS , V P-INI The relationship between the magnitude The vertical axis represents voltage. In FIG. 20B, the threshold voltage of the transistor 102 is Pressure is V TH , the voltage V held at both ends of the capacitor 103 CP , light-emitting element 10 The voltage V applied to the electrodes at both ends of 4 EL In FIG. 20(B), 1 represents the on or off state of switch 101 and switch 106.

[0108] First, in the initialization period P22, the voltage held at the gate of the transistor 102 in the previous light emission period P21 is The difference from the initialization period P12 is that the data line DL is V CS In addition, node N G is V CS Each wiring and each node during the initialization period P22 The voltage of the node is as shown in FIG. 21(A).

[0109] Next, in the initialization completion period P23, the node N S The voltage held in the The difference from the initialization completion period P23 is that the voltage of the current supply line PL is V P-INI is Node N G V CS V P-INI Therefore, the transistor 102 The node N S The voltage at node N S V P-INI Initialization The voltages of each wiring and each node during the completion period P23 are as shown in FIG. 21(B).

[0110] Next, in the threshold voltage correction period P24, V TH Hold Therefore, a current flows through transistor 102, and node N SThis operates to increase the voltage. The difference in the operation during the threshold voltage correction period P24 is that the data line DL is set to V CS In addition, Node N G is V CS The voltage of the current supply line PL is V CS The current supply line PL is V CS Therefore, node N S The voltage at node N S The voltage rise of the transistor Sta 102 V GS V TH This reduces the current flowing through transistor 102. This means that the current stops at node N S The voltage of is the voltage (V CS -V TH ) Note that 20(B) at node N S The voltage rise of node N G Voltage V TH Stops at a lower voltage This is because the transistor 102 is normally off. The voltages of each wiring and each node in 24 are as shown in FIG.

[0111] Next, in the data voltage write period P25, the data line DL is V DATA and switch 1 01 is in the ON state. Also, the switch 106 is in the OFF state. At this time, the node N D teeth In the data voltage write period P25, the data voltage is written in an electrically floating state. This is the same as the data voltage write period P15. Note that in FIG. S Voltage of Rise is Node N S Since the voltage of is smaller than that in Figure 1(B), V CS Smaller voltage This is because the transistor 102 is normally off. , node N S The light emitting element 104 does not emit light due to the voltage of data voltage writing period P2 The voltages of each wiring and each node in accordance with 5 are as shown in FIG.

[0112] Next, in the light emission period P21, the voltage of the current supply line PL is V P-EMI Light emission period P21 The operation of each wiring and each node during the light emission period P21 is the same as that during the light emission period P11. will be as shown in FIG. 23.

[0113] In the above-described structure according to one embodiment of the present invention, the threshold voltage of the transistor 102 is positive or negative. Regardless of the above, the time required to obtain the threshold voltage can be increased. Node N on the side S This suppresses the voltage rise in the data voltage writing period. The light emission can be suppressed.

[0114] Note that one embodiment of the present invention has been described in this embodiment. An embodiment of the present invention will be described below. However, the embodiment of the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. In the above example, the variation in the threshold voltage of the transistor is corrected. The manner is not limited thereto. For example, depending on the circumstances or the situation, In one embodiment, compensation for variations in other characteristics may be performed. Alternatively, depending on the situation, in one embodiment of the present invention, the variation in the threshold voltage of the transistor is compensated for. It doesn't have to be right.

[0115] (Embodiment 2) In this embodiment, a channel transistor applicable to the pixel transistor described in the above embodiment will be described. a transistor in which a gate formation region is formed using an oxide semiconductor film (OS transistor); and and a transistor in which the channel formation region is formed of silicon (Si transistor). An example will be given.

[0116] <Transistor configuration example 1> First, a transistor in which a channel formation region is formed using an oxide semiconductor film (OS transistor) This section explains the

[0117] Figures 24(A), 24(B), and 24(C) show three transistors with different device structures. The top view (layout diagram) of the resistors (TA1, TA2, TB1) and their respective circuit symbols are shown below. FIG. 25 is a cross-sectional view of the transistors (TA1, TA2, and TB1). TA1 is a cross-sectional view taken along the lines a1-a2 and b1-b2. Cross-sectional views taken along lines a4 and b3-b4, and lines a5-a6 of transistor TB1; The cross-sectional views taken along the line b5-b6 are shown in FIG. 25(A) and FIG. 25(B). The cross-sectional structure in the channel length direction is shown in FIG. 25(A), and the cross-sectional structure in the channel width direction is shown in FIG. Shown in Figure 25(B).

[0118] As shown in FIG. 25(A) and FIG. 25(B), the transistors (TA1, TA2, TB1) are These transistors are integrated on the same insulating surface and are fabricated in the same manufacturing process. In order to clarify the device structure, the structure of each transistor is shown in Fig. Wiring for supplying potential and power to the gate (G), source (S), and drain (D) Electrical connections to the wires are omitted.

[0119] The transistor TA1 (FIG. 24(A)) and the transistor TA2 (FIG. 24(B)) have gates The transistor has a gate (G) and a back gate (BG). One of the gates (BG) corresponds to the first gate, and the other corresponds to the second gate. The transistors TA1 and TA2 have a structure in which the back gate is connected to the gate. The transistor TB1 (FIG. 24(C)) is a transistor that does not have a BG. As shown in FIG. 25, these transistors (TA1, TA2, TB1) are The configuration of these transistors will be described below with reference to FIGS. 24 and 25. Reveal.

[0120] [Transistor TA1] The transistor TA1 includes a gate electrode GE1, a source electrode SE1, a drain electrode DE1, and a The gate electrode BGE1 and the oxide semiconductor film OS1 are provided.

[0121] In the following description, the transistor TA1 is referred to as TA1, and the back gate is referred to as BG. The oxide semiconductor film OS1 is referred to as OS1 or film OS1, and the elements and components of the elements are omitted. Similarly, signals, potentials, circuits, and the like may also be abbreviated.

[0122] In this embodiment, the channel length of the OS transistor is determined by dividing the length of the source electrode and the drain electrode by the distance between the source electrode and the drain electrode. The channel width of the OS transistor is the distance between the oxide semiconductor film and the gate electrode. The width of the source electrode or drain electrode in the overlapping region is defined as the width of the The channel length is La1 and the channel width is Wa1.

[0123] The film OS1 overlaps with the electrode GE1 via the insulating film 34. A pair of electrodes (SE1, DE1) are formed in contact with the substrate. As shown in FIG. The membrane OS1 has a portion that does not overlap with the electrode GE1 and the pair of electrodes (SE1, DE1). The length of the film OS1 in the channel length direction is longer than the channel length La1, and The length in the width direction is longer than the channel width Wa1.

[0124] The insulating film 35 and the insulating film 36 cover the film OS1, the electrode GE1, the electrode SE1, and the electrode DE1. An electrode BGE1 is formed on the insulating film 36. The electrode BGE1 is The electrode G is provided so as to overlap with the electrode OS1 and the electrode GE1. The electrode BGE1 is provided so as to have the same shape and be located in the same position as E1. 1, the electrode GE is disposed in an opening CG1 penetrating the insulating film 34, the insulating film 35, and the insulating film 36. 1. This structure electrically connects the gate and backgate of transistor TA1. is connected to.

[0125] By connecting the back gate electrode BGE1 to the gate electrode GE1, By providing the back gate electrode BGE1, the on-current can be increased. The strength of the resistor TA1 can be improved. BGE1 acts as a reinforcing member to make transistor TA1 less likely to break.

[0126] The film OS1 including the channel formation region has a multi-layer structure. Here, as an example, three oxides are used. The semiconductor film OS1 has a three-layer structure consisting of oxide semiconductor films (31, 32, 33). The conductive film is preferably a metal oxide film containing at least one of the same metal elements, and In It is particularly preferable that the semiconductor film of the transistor contains In. Metal oxide films include In-Ga oxide film, In-M-Zn oxide film (where M is Al, Ga, The typical examples of the metal oxide film are Y, Zr, La, Ce, and Nd. Films containing added other elements or materials may also be used.

[0127] "32" is a film that constitutes the channel forming region of the transistor TA1. " constitutes the channel forming regions of the transistor TA2 and the transistor TB1 described later. Therefore, the required thickness of the transistor TA2 and the transistor TB1 is Depending on the electrical properties (e.g., field effect mobility, threshold voltage, etc.), oxides of appropriate composition are selected. For example, an oxide semiconductor film can be used so that a channel is formed at "32". It is preferable to adjust the composition of the metal elements that are the main components of the conductive films 31-33.

[0128] In the transistor TA1, a channel is formed at "32". This can prevent the panel formation region from contacting the insulating films 34 and 35. By making the body films 31-33 metal oxide films containing at least one of the same metal elements, At the interface between 『31』 and 『32』 and 『33』, interface scattering is unlikely to occur. This allows the field effect mobility of the transistor TA1 to be reduced. It can be made higher than TA2 and transistor TB1, and the drain voltage in the on state The current (on-current) can be increased.

[0129] [Transistor TA2] The transistor TA2 includes a gate electrode GE2, a source electrode SE2, a drain electrode DE2, and a The gate electrode BGE2 and the oxide semiconductor film OS2 are insulating The electrode GE2 is in contact with the opening CG2 penetrating the film 34 through the insulating film 36. The transistor TA2 is a modification of the transistor TA1, in which the film OS2 is not an oxide semiconductor film 33. The transistor TA1 is different from the transistor TA1 in that it has a single-layer structure. Then, the channel length La2 and the channel width Wa2 of the transistor TA2 are The channel length La1 and the channel width Wa1 of the first embodiment are set to be equal to those of the first embodiment.

[0130] [Transistor TB1] The transistor TB1 has a gate electrode GE3, a source electrode SE3, a drain electrode DE3 and a The transistor TB1 is a modified example of the transistor TA2. As in the transistor TA2, the film OS3 has a single-layer structure made of an oxide semiconductor film 33. The transistor TA1 differs from the transistor TA2 in that it does not have a back gate electrode. The layout of OS3 and electrodes (GE3, SE3, DE3) is different. As shown in the figure, the region of the membrane OS3 that does not overlap with the electrode GE3 is connected to the electrode SE3 or the electrode DE3. 3. Therefore, the channel width Wb1 of the transistor TB1 is The channel length Lb1 is determined by the width of the electrode SE, as in the transistor TA2. 3 and the electrode DE3, where the channel length La2 of the transistor TA2 is It's longer than that.

[0131] [Insulating film] The insulating films 34, 35 and 36 are formed on the transistors (TA1, TA2 , TB1) is formed on the entire region where the insulating film 34, the insulating film 35, and The insulating film 34 and the insulating film 36 are formed of a single layer or multiple layers of insulating film. The insulating film 35 and the insulating film 36 are films that constitute the gate insulating film of the transistors (TA1, TA2, TB1). and the insulating film 36 are the gates on the back channel side of the transistors (TA1, TA2, TB1). The insulating film 36 on the top surface is a film that constitutes a transistor insulating film. It is preferable that the insulating film 36 is made of a material that functions as a protective film for the transistor. In order to insulate the third layer electrode BGE1 from the second layer electrodes (SE1, DE1), Therefore, it is sufficient that at least one insulating film exists between them.

[0132] The insulating films 34 to 36 may be formed of a single layer insulating film or a multilayer insulating film having two or more layers. The insulating films 34 to 36 can be made of aluminum oxide. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, nitrogen silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, Examples of the film include films made of lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. These insulating films can be formed by sputtering, CVD, MBE, ALD, or It can be formed by using a PLD method.

[0133] [Oxide semiconductor film] Here, an oxide semiconductor film which forms a semiconductor film of an OS transistor will be described. When the semiconductor film has a multi-layer structure as in OS1, the oxide semiconductor film constituting the multi-layer structure is small. It is preferable that the metal oxide film contains at least one of the same metal elements, and that the metal oxide film contains In. preferable.

[0134] For example, if "31" is an In-Ga oxide film, the atomic ratio of In is set higher than the atomic ratio of Ga. In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or In the case of Nd), the atomic ratio of In is made smaller than the atomic ratio of M. In this case, the atomic ratio of Zn The numerical ratio can be maximized.

[0135] For example, if the number of atoms of In is 32, the number of atoms of Ga is 32. In the case of an In-M-Zn oxide film, the atomic ratio of In is made larger than the atomic ratio of M. In the In-M-Zn oxide film, the atomic ratio of In is higher than the atomic ratios of M and Zn. It is preferable to make it larger.

[0136] For example, if "33" is an In-Ga oxide film, the atomic ratio of In is set to the same as the atomic ratio of Ga. In the case of an In-M-Zn oxide film, the ratio of the number of In atoms to the number of M atoms is increased or decreased. In this case, the atomic ratio of Zn should be larger than that of In and M. Here, "33" is the transistor TA2 and transistor TB1, which will be described later. It is also a film that constitutes the channel forming region.

[0137] The atomic ratio of the oxide semiconductor films 31 to 33 is In the case of CVD, this is possible by adjusting the atomic ratio of the target's constituent materials. When forming a film by this method, it is possible to adjust the flow rate ratio of the raw material gases. The semiconductor film 31 to the oxide semiconductor film 33 are formed by sputtering an In-M-Zn oxide The targets used in film formation are described below using the case of forming a thin film as an example. To deposit the film, a target made of In-M-Zn oxide is used.

[0138] The atomic ratio of the metal elements in the target "31" is In:M:Zn=x1:y1:z1. and 、 It is preferable that x1 / y1 is 1 / 6 or more and less than 1. Also, z1 / y1 is 1 / It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less.

[0139] Representative examples of the atomic ratio of the target metal elements are In:M:Zn=1:3:2, In :M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4: 6, In:M:Zn=1:4:7, In:M:Zn=1:4:8, In:M:Zn=1: 5:5, In:M:Zn=1:5:6, In:M:Zn=1:5:7, In:M:Zn= 1:5:8, In:M:Zn=1:6:8, etc.

[0140] The atomic ratio of the metal elements in the target "32" is In:M:Zn=x2:y2:z2. and 、 It is preferable that x2 / y2 is greater than 1 and equal to or less than 6. Also, z2 / y2 is greater than 1 and equal to or less than 6. The atomic ratio of the metal elements in the target is preferably greater than 6. is In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Z n=2:1:3, In:M:Zn=3:1:2, In:M:Zn=3:1:3, In:M :Zn=3:1:4 etc.

[0141] The atomic ratio of the metal elements in the target "33" is In:M:Zn=x3:y3:z3. and 、 It is preferable that x3 / y3 is 1 / 6 or more and 1 or less. Also, z3 / y3 is 1 / It is preferably 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Representative examples of the molecular ratio are In:M:Zn=1:1:1 and In:M:Zn=1:1:1. 2, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1: 3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:4, In:M:Zn= 1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:4:7, In:M:Z n=1:4:8, In:M:Zn=1:5:5, In:M:Zn=1:5:6, In:M :Zn=1:5:7, In:M:Zn=1:5:8, In:M:Zn=1:6:8 etc. do.

[0142] In the deposition target for the In-M-Zn oxide film, the atomic ratio of metal elements is In:M: When Zn=x:y:z, by setting 1≦z / y≦6, the In-M-Zn oxide film can be obtained. This is preferable because it is easy to form a CAAC-OS film. More details will be given later.

[0143] The oxide semiconductor films 31 to 33 are each formed of an oxide semiconductor having a low carrier density. For example, the oxide semiconductor films 31 to 33 are formed using oxide semiconductor films having a carrier density is 1×10 17 pieces / cm 3 Less than or equal to 1×10 15 pieces / cm 3 The following is more preferable: 1×10 13 pieces / cm3 The following oxide semiconductor film is used. In particular, the oxide semiconductor film 31 The oxide semiconductor film 33 has a carrier density of 8×10 11 pieces / cm 3 Less than, better Preferably 1×10 11 pieces / cm 3 less than 1×10 10 pieces / cm 3 Less than Yes, and 1×10 -9 pieces / cm 3 It is preferable to use any of the above oxide semiconductor films.

[0144] The oxide semiconductor films 31 to 33 each have a low impurity concentration and a low density of defect states. By using a low-temperature oxide semiconductor film, a transistor with better electrical characteristics can be fabricated. Here, the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). High purity authentic or substantially high purity authentic means that the Intrinsic oxide semiconductors have a low carrier density because they have few carrier generation sources. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film can be formed. The transistor has electrical characteristics in which the threshold voltage is negative (also called normally on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film is Since the defect level density is low, the trap level density may also be low. The oxide semiconductor film that is substantially intrinsic or highly pure has an extremely small off-state current and a large channel width. is 1×10 6 Even if the device has a channel length L of 10 μm, the source and drain electrodes When the electrode voltage (drain voltage) is in the range of 1V to 10V, the off-state current is Below the measurement limit of the meter analyzer, i.e. 1×10-13 Obtaining a characteristic of A or lower Therefore, a transistor in which a channel region is formed in the oxide semiconductor film can be The fluctuation of electrical characteristics is small, resulting in a highly reliable transistor. The metals include elements such as elements of alkali metals, alkaline earth metals, and the like.

[0145] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water and an acid. Oxygen vacancies are formed in the lattice from which the atoms are desorbed (or in the part from which oxygen is desorbed). When hydrogen enters the electron carrier, it can generate electrons. When it bonds with oxygen, which bonds with a metal atom, it may generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. Easy to use.

[0146] As a result, hydrogen is generated in addition to oxygen vacancies in the oxide semiconductor films 31 to 33. Specifically, the oxide semiconductor films 31 to 32 are preferably In the film 33, secondary ion mass spectrometry (SIMS) was used. The hydrogen concentration obtained by ss Spectrometry was calculated as 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 at oms / cm 3 Less than 1 x 10 18 atoms / cm 3 More preferably, 5×10 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 The following applies.

[0147] The oxide semiconductor films 31 to 33 each contain silicon or carbon, which is one of Group 14 elements. If oxygen is contained in the film, oxygen vacancies in the film increase, and the film becomes n-type. The concentrations of silicon and carbon in the nitride semiconductor film 31 and the oxide semiconductor film 33 (secondary ion mass) The concentration obtained by quantitative analysis is 2 x 10 18 atoms / cm 3 Below, preferably 2 ×10 17 atoms / cm 3 The following applies.

[0148] In addition, the oxide semiconductor films 31 to 33 were analyzed by secondary ion mass spectrometry. The resulting concentration of alkali metal or alkaline earth metal is expressed as 1×10 18 atoms / c m 3 Less than or equal to 2×10 16 atoms / cm 3 The following are the alkali metals and When alkaline earth metals combine with oxide semiconductors, they can generate carriers. As a result, the off-state current of the oxide semiconductor film 31 to the oxide semiconductor film 32 may increase. It is preferable to reduce the concentration of alkali metal or alkaline earth metal in the compound semiconductor film 33. .

[0149] When nitrogen is contained in the oxide semiconductor films 31 to 33, the electrons acting as carriers can be easily This causes the formation of electrons, increases the carrier density, and makes it easier to convert to n-type. Since a transistor using a semiconductor tends to have normally-on characteristics, the oxide semiconductor film 31 The nitrogen content in the oxide semiconductor film 33 is preferably as low as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is 5 × 10 18 atoms / cm 3 Below Preferably, it is placed below.

[0150] Although the oxide semiconductor films 31 to 33 have been described above, the present invention is not limited to these. The semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistors An oxide semiconductor film having an appropriate composition may be used depending on the required transistor. In order to obtain semiconductor characteristics and electrical characteristics of the oxide semiconductor film 31, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, and interatomic distance of the film 33 It is preferable to make the material suitable in terms of the material properties, density, etc.

[0151] The transistor TA1 is a Ga or M (M is Al, Ga, Y, Zr, La, Ce, or A channel is formed in the oxide semiconductor film 32 in which the atomic ratio of In is larger than the atomic ratio of Nd. This allows the field effect mobility to be increased. Typically, the field effect mobility is , 10cm 2 / Vs > 60cm 2 / Vs, preferably less than 15cm 2 / Vs or more 50cm 2 / Vs. Therefore, there is no possibility of causing a disturbance in the circuit of the active matrix display device. When the transistor TA1 is used, it is suitable for a drive circuit that requires high speed operation.

[0152] It is also preferable to provide the transistor TA1 in a light-shielded area. By providing a transistor TA1 having a high mobility in the drive circuit, the drive frequency can be increased. Therefore, a display device with higher resolution can be realized.

[0153] The transistors TA2 and TB1, in which the channel formation region is formed of the oxide semiconductor film 33, It has a lower field effect mobility than the transistor TA1 and its size is 3 cm 2 / Vs or more 10 cm 2 The transistors TA2 and TB1 have an oxide semiconductor film 32. Since it is not exposed to light, it is less susceptible to deterioration by light than the transistor TA1. The increase in current is small. Therefore, the channel formation region is formed in the oxide semiconductor film 33. The transistors TA2 and TB1 are suitable for a pixel portion that is irradiated with light.

[0154] The transistor TA1 has the following characteristics in comparison with the transistor TA2 that does not include the oxide semiconductor film 32: When light is irradiated, the current in the off state tends to increase. This is why it is suitable for peripheral driving circuits that are less affected by light than pixel areas where light cannot be sufficiently shielded. Of course, there are transistors with configurations like transistors TA2 and TB1. A capacitor may also be provided in the drive circuit.

[0155] The transistors (TA1, TA2, and TB1) and the oxide semiconductor film 31 to the oxide semiconductor film However, the present invention is not limited to this, and any other suitable material may be used depending on the semiconductor characteristics and other properties of the transistor. The structure of the transistor can be changed according to the back gate voltage and electrical characteristics. The presence or absence of a gate electrode, the stacked structure of the oxide semiconductor film, the oxide semiconductor film, the gate electrode, the source electrode, and The shape, arrangement, etc. of the drain electrode can be changed as appropriate.

[0156] [Structure of oxide semiconductor] Next, the structure of the oxide semiconductor will be described.

[0157] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0158] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0159] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors are divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0160] As the non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors made of crystalline oxides include semiconductors made of microcrystalline oxides and amorphous oxides. The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0161] First, we will explain the CAAC-OS film.

[0162] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0163] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be confirmed. On the other hand, the high-resolution TEM image also shows clear boundaries between crystals, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0164] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. Each layer of metal atoms is The CAAC-OS film is formed on the surface (also called the surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0165] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0166] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. From this, it can be seen that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0167] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0168] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0169] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0170] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0171] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0172] Next, a microcrystalline oxide semiconductor film will be described.

[0173] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a region where a crystal part is not clearly observed and a region where a crystal part is not clearly observed. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fineness is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In the nc-OS film, for example, the grain boundaries are clearly identified in high-resolution TEM images. It may not be possible to recognize

[0174] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nano-beam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. When this is done, a circular (ring-shaped) area of ​​high brightness may be observed. Nanobeam electron diffraction of the nc-OS film revealed multiple spots within the ring-shaped region. It may be observed.

[0175] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0176] Next, the amorphous oxide semiconductor film will be described.

[0177] The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0178] In the amorphous oxide semiconductor film, no crystalline parts can be confirmed in a high-resolution TEM image.

[0179] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the lane analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0180] Note that the oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may have a structure such as the following. Amorphous-like Oxide Semiconductor (a-like OS) The conductor membrane is called the endothelium.

[0181] In the a-like OS film, voids are observed in the high-resolution TEM image. In addition, crystals may be clearly visible in high-resolution TEM images. The a-like OS film has a region in which a crystal part is not observed and a region in which a crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed in TEM observations, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be observed. Almost no crystallization due to electron irradiation was observed.

[0182] The size of the crystals in the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. Unit cell of the InGaZnO4 crystal The layer has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is therefore the (009) plane. This is approximately the same as the lattice spacing (also called the d value), and crystal structure analysis has determined that this value is 0.29 nm Therefore, we focused on the lattice fringes in high-resolution TEM images and In the region where the distance is between 0.28 nm and 0.30 nm, the lattice fringes are InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0183] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal of the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0184] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the ratio of the number of ZnO atoms to the number of ZnO atoms, single crystal InGaZnO4 with a rhombohedral crystal structure is The density of is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1 In the oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film that satisfies the atomic ratio of 1, the density of the nc-OS film and the CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0185] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0186] Note that the oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a microcrystalline oxide semiconductor film. The semiconductor layer may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0187] As described above, the OS transistor can achieve extremely excellent off-state current characteristics.

[0188] [Substrate 30] Various substrates can be used as the substrate 30, and it is not limited to a specific one. Examples of the substrate 30 include a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), a SO I substrate, glass substrate, quartz substrate, plastic substrate, metal substrate, stainless steel substrate , Substrate with Stainless Steel Foil, Tungsten Substrate, Tungsten Foil A substrate having a fibrous material, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film Examples of glass substrates include barium borosilicate glass and aluminophore. silicate glass, or soda lime glass. Flexible substrates, lamination films Examples of the materials and base films are as follows: Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulf For example, there are plastics such as polyether ether sulphate (PES). Synthetic resins, etc. Examples include polypropylene, polyester, and polyfluorine. Examples of such materials include polyvinyl chloride, polyvinyl chloride, and polyamide. Imide, aramid, epoxy, inorganic deposition film, paper, etc. In particular, semiconductor By manufacturing transistors using substrates, single crystal substrates, or SOI substrates, etc. , small variation in characteristics, size, or shape, high current capability, small size It is possible to manufacture transistors. Circuits are constructed using such transistors. As a result, it is possible to reduce the power consumption of the circuit or to increase the degree of integration of the circuit.

[0189] Before forming the gate electrodes (GE1, GE2, GE3), a base insulating film is formed on the substrate 30. The base insulating film may be made of silicon oxide, silicon oxynitride, silicon nitride, or nitride. Silicon oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide The insulating film may be made of silicon nitride, gallium oxide, or aluminum oxide nitride. By using tantalum oxide, hafnium oxide, yttrium oxide, aluminum oxide, etc., the substrate 30 Impurities (typically alkali metals, water, hydrogen, etc.) are removed from the oxide semiconductor film (OS1-OS3 ) can be suppressed.

[0190] [Gate electrodes (GE1, GE2, GE3)] The gate electrodes (GE1, GE2, GE3) are made of a single layer of conductive film or a stack of two or more conductive films. It is a multi-layered film. It is formed as gate electrodes (GE1, GE2, GE3). The conductive film is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten. or an alloy containing the above-mentioned metal elements or the above-mentioned metal elements. It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. Alternatively, one or more metal elements selected from the above may be used. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of the above may be used. Indium tin oxide, indium oxide with tungsten oxide, indium oxide with tungsten oxide Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Oxide, indium zinc oxide, indium tin oxide containing silicon oxide, etc. A conductive material that is suitable for the purpose may also be applied.

[0191] For example, the gate electrodes (GE1, GE2, GE3) are aluminum films containing silicon. When the gate electrodes (GE1, GE2, GE3) have a two-layer structure, For example, a titanium film is formed on an aluminum film, or a titanium film is formed on a titanium nitride film. forming a tungsten film on a titanium nitride film; forming a tantalum nitride film or a tungsten nitride film A tungsten film is formed on the tungsten film. The gate electrodes (GE1, GE2, GE 3) In the case of a three-layer structure, for example, a titanium film and an aluminum film on the titanium film are The titanium film may be formed on the first and second layers.

[0192] By sputtering, vacuum deposition, pulsed laser deposition (PLD), thermal CVD, etc. Gate electrodes (GE1, GE2, GE3) are formed.

[0193] The tungsten film can be formed using a film forming apparatus that uses ALD. In this case, WF6 gas and B2H6 gas are introduced in sequence to form the initial tungsten film. Then, a tungsten film is formed using WF6 gas and H2 gas. Alternatively, SiH4 gas may be used instead of gas.

[0194] The gate electrodes GE1-GE3 can be formed by the above-mentioned method, as well as by electrolytic plating, printing, ink jet printing, etc. This can be done by the coujet method or the like.

[0195] [Insulating film 34 (gate insulating film)] An insulating film 34 is formed to cover the gate electrodes GE1-GE3. The insulating film 34 is a single-layer insulating film. The insulating film formed as the insulating film 34 is a multi-layer insulating film having a structure of two or more layers. Examples of the insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. In this specification, an oxynitride is a material that contains more oxygen than nitrogen. A peroxide is a material that contains more nitrogen than oxygen.

[0196] The insulating film formed as the insulating film 34 may be, for example, silicon oxide or silicon oxynitride. , silicon oxide nitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide Alternatively, an insulating film made of Ga-Zn-based metal oxide or the like can be formed. Hafnium silicate (HfSiO x ), nitrogen-added Hafniu HfSi x O y N z ), nitrogen-doped hafnium aluminate (Hf Al x O y N z ), hafnium oxide, yttrium oxide, and other high-k materials By using high-k materials, the gate leakage of transistors can be reduced. can be reduced.

[0197] The insulating film 34 is a film that constitutes a gate insulating film, and therefore is an oxide semiconductor film (OS1, OS2, In order to improve the interface characteristics between the OS3) and the gate insulating film, the insulating film 34 is The area in contact with (OS1, OS2, OS3) is formed with an oxide insulating film or an oxynitride insulating film. For example, the top layer of the insulating film 34 is preferably a silicon oxide film or an oxide A silicon nitride film may be used.

[0198] The thickness of the insulating film 34 may be, for example, 5 nm to 400 nm. Alternatively, it is 10 nm or more and 300 nm or less, and more preferably, it is 50 nm or more and 250 nm or less. It is.

[0199] When oxide semiconductor films (OS1, OS2, and OS3) are formed by sputtering, The power supply for generating the radiator can be an RF power supply, an AC power supply, a DC power supply, etc. It can be used.

[0200] The sputtering gas is a rare gas (typically argon) atmosphere, an oxygen atmosphere, a rare gas and In the case of a mixed gas of rare gas and oxygen, the rare gas is It is preferable to increase the gas ratio of oxygen.

[0201] The target is selected according to the composition of the oxide semiconductor film (OS1, OS2, OS3) to be formed. It is sufficient to select an appropriate one based on the above.

[0202] Note that when a sputtering method is used to form the oxide semiconductor films (OS1, OS2, and OS3), In this case, the substrate temperature is set to 150° C. or higher and 750° C. or lower, preferably 150° C. or higher and 450° C. or lower, and The oxide semiconductor films 31 and 32 can be formed by heating at a temperature of preferably 200° C. or higher and 350° C. or lower. A CAAC-OS film can be formed.

[0203] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0204] By suppressing the inclusion of impurities during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber is In addition, the impurity concentration in the deposition gas may be reduced. A deposition gas having a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0205] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and 100% by volume or more is preferably 100% by volume or more. Product % is more preferred.

[0206] The oxide semiconductor film is formed while being heated, or after the oxide semiconductor film is formed, By the heat treatment, the hydrogen concentration in the oxide semiconductor film was increased to 2 × 10 20 atoms / cm 3 Below Lower, preferably 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 at oms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 a toms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Below are some more Preferably 1×10 16 atoms / cm 3 It can be as follows:

[0207] The heat treatment is carried out at a temperature higher than 350°C and lower than 650°C, preferably at a temperature higher than 450°C and lower than 600°C. By carrying out the above steps, the CAAC conversion rate described below is 70% or more but less than 100%, preferably 80%. More preferably, the ratio is 90% or more and less than 100%, more preferably 95% or more and less than 98%. % or less. In addition, the content of hydrogen, water, and the like is reduced. That is, it is possible to obtain an oxide semiconductor film having a low impurity concentration and a low defect state density. In this way, an oxide semiconductor film with low thermal conductivity can be formed.

[0208] An oxide semiconductor film can be formed using a deposition system that uses ALD. For example, InG aZnO X When forming a (X>0) film, In(CH3)3 gas and O3 gas are sequentially repeated. The InO2 layer is formed by repeatedly introducing Ga(CH3)3 gas and O3 gas. A GaO layer is formed, and then a ZnO layer is formed using Zn(CH3)2 gas and O3 gas. The order of these layers is not limited to this example. Mixed compounds such as aO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Alternatively, a layer of H may be formed by bubbling inert gas such as Ar instead of O gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of the CH3)3 gas, In(C2H5)3 gas may be used. Ga(C2H5)3 gas may be used instead of Zn(CH3)2 gas. A suction cup may also be used.

[0209] The oxide semiconductor film 32 and the oxide semiconductor film 33 are used as a gate insulating film. The thickness of the film can be 3 nm or more and 200 nm or less. , preferably 3 nm to 100 nm, and more preferably 30 nm to 50 nm. The thickness of the oxide semiconductor film 31 is, for example, 3 nm to 100 nm. It is preferably 3 nm or more and 30 nm or less, and more preferably 3 nm or more and 15 nm or less. The oxide semiconductor film 31 is thinner than the oxide semiconductor film 32 and the oxide semiconductor film 33. It is preferable to form the

[0210] Here, the oxide semiconductor films 31, 32, and 33 are formed by sputtering In-Ga-Zn films. The atomic ratio of the metal elements in the targets used for these films (In:G a:Zn) is, for example, 1:3:6 for the oxide semiconductor film 31, and The oxide semiconductor film 33 has a thickness of 1:1:1.2 or 1:1:1. The oxide semiconductor films 31, 32, and 33 have thicknesses of 5 nm and 35 nm, respectively. m, 35 nm.

[0211] [Source electrode, drain electrode] The electrodes (SE1, DE1, SE2, DE2, SE3, DE3) are gate electrodes (GE1, GE 2, GE3) can be formed in the same manner.

[0212] For example, a copper-manganese alloy film having a thickness of 50 nm, a copper film having a thickness of 400 nm, and a copper film having a thickness of 100 nm thick copper-manganese alloy film was laminated by sputtering. , forming a three-layered electrode (SE1, DE1, SE2, DE2, SE3, DE3) can be done.

[0213] Transistors that operate at high speed, such as those used in the driver circuits of light-emitting devices, The saturation transistors are transistors (TA1, TA2) or transistors (TA3, TA4, It is preferable to shorten the channel length, as in the case of TC1. The channel length is preferably less than 2.5 μm. For example, it is preferable to set the channel length to 2.2 μm or less. In the transistor of this embodiment, the channel length is the distance between the source electrode and the drain electrode. Therefore, the minimum channel length is determined by the number of electrodes (SE1, DE1, SE2, DE2, S The transistor of this embodiment is limited by the precision of processing the conductive film that becomes the transistor E3, DE3). For example, the channel length can be 0.5 μm or more, or 1.0 μm or more. do.

[0214] [Insulating film 35, 36] For example, a two-layer insulating film can be formed as "35". The first layer of the film of ".5" is called insulating film 35a, and the second layer is called insulating film 35b.

[0215] The insulating film 35a may be, for example, an oxide insulating film made of silicon oxide or the like, or a film containing nitrogen. It is possible to form an oxide insulating film containing nitrogen and having few defects. Typical examples of oxide insulating films with low oxidation resistance include a silicon oxynitride film and an aluminum oxynitride film. etc.

[0216] The oxide insulating film with few defects shows a high ESR spectrum below 100K. The first signal has a g value between 2.037 and 2.039, and the second signal has a g value between 2.001 and 2. A second signal with a g value of 0.003 or less, and a third signal with a g value of 1.964 to 1.966 or less. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is The g value is about 5 mT. The first signal has a g value of 2.037 to 2.039. A second signal between 2.001 and 2.003, and a g value between 1.964 and 1.96 The sum of the spin densities of the third signals that are 6 or less is 1 × 10 18 spins / cm 3 Not yet is typically 1×10 17 spins / cm 3 More than 1×10 18 spins / c m 3is less than.

[0217] In addition, in the ESR spectrum below 100K, the g value is 2.037 to 2.039. The first signal, the second signal with a g value between 2.001 and 2.003, and the g value between 1 The third signal, between .964 and 1.966, is nitrogen oxides (NOx, x is between 0 and 2). Representative examples of nitrogen oxides include: , nitrogen monoxide, nitrogen dioxide, etc. That is, the first group with a g value of 2.037 to 2.039. signal, a second signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1. The lower the sum of the spin densities of the third signal, which is greater than or equal to 964 and less than or equal to 1.966, the more acidic the signal is. This means that the nitride insulating film contains a small amount of nitrogen oxide.

[0218] Since the insulating film 35a is a film with a low content of nitrogen oxides, the insulating film 35a and the layer (OS It is possible to reduce carrier traps at the interface with As a result, it is possible to reduce the shift in the threshold voltage of the transistor. This can reduce the fluctuation in the electrical characteristics of the transistor.

[0219] In order to improve the reliability of the transistor, the insulating film 35a is formed by SIMS (Secondary The nitrogen concentration measured by y Ion Mass Spectrometry is 6×10 2 0 / cm 3 This is because the insulating film 35 is This is because nitrogen oxides are less likely to be produced in a.

[0220] As an example of the insulating film 35a, an oxide insulating film containing nitrogen and having a small amount of defects is CV A silicon oxynitride film can be formed by the method D. In this case, the source gas is It is preferable to use a silicon-containing deposition gas and an oxidizing gas. Representative examples of reactive gases include silane, disilane, trisilane, and fluorinated silane. Chemical gases include nitrous oxide, nitrogen dioxide, and the like.

[0221] In addition, the flow rate of the oxidizing gas is preferably more than 20 times and less than 100 times the flow rate of the deposition gas. The pressure in the treatment chamber is preferably less than 100 Pa, more preferably less than 50 By using a CVD method at a temperature of 0.1 Pa or less, the insulating film 35a contains nitrogen and has a low defect amount. In this way, an oxide insulating film with little damage can be formed.

[0222] For example, the insulating film 35b is made of an oxide film containing more oxygen than the oxygen required for the stoichiometric composition. The insulating film can be formed by using a material having more oxygen than the stoichiometric composition. When the oxide insulating film containing oxygen is heated, part of the oxygen is released. The oxide insulating film containing more oxygen than The amount of desorption is 1.0×10 18 atoms / cm 3 More than 3.0×10 20 ato ms / cm 3 The oxide insulating film is as described above. The temperature is preferably in the range of 100°C to 700°C, or 100°C to 500°C. It is nice.

[0223] The insulating film 35b has a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm. The insulating film 35 may be made of silicon oxide, silicon oxynitride, or the like having a thickness of 00 nm or less. b) is formed by using an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. When the oxide insulating film is formed, the oxide insulating film contains more oxygen than the oxygen that satisfies the stoichiometric composition. The silicon nitride film can be formed by using a CVD method.

[0224] When a silicon oxide film or a silicon oxynitride film is formed as the insulating film 35b, the following is performed. The deposition can be performed under the following conditions. The substrate is heated to a temperature of 180° C. or higher and 280° C. or lower, more preferably 200° C. or higher and 240° C. or lower. The pressure in the processing chamber is maintained at 100 Pa or more and 250 Pa or less by introducing the raw material gas into the processing chamber. a or less, more preferably 100 Pa or more and 200 Pa or less, and 0.17W / cm at pole 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 More than 0.35W / cm 2 The following high frequency power is supplied:

[0225] The insulating film 36 is made of a film having at least a blocking effect against hydrogen and oxygen. Furthermore, it is preferable to use a blocker such as oxygen, hydrogen, water, an alkali metal, or an alkaline earth metal. Typically, a nitride insulating film such as silicon nitride may be formed. In addition to silicon nitride films, silicon oxynitride films, aluminum nitride films, and aluminum oxynitride films are also available. Membranes and the like can also be used.

[0226] In addition, the insulating film 36 is made of a material having a blocking effect against oxygen, hydrogen, water, etc. Such an oxide insulating film may be formed using an aluminum oxide or Aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, oxynitride Examples include yttrium, hafnium oxide, and hafnium oxynitride.

[0227] The thickness of the insulating film 36 may be set to 50 nm or more and 300 nm or less, and preferably 100 The insulating film has a blocking effect against oxygen, hydrogen, water, etc. The insulating film 36 is formed to prevent the oxide semiconductor films 31 to 33 from escaping from the oxide semiconductor films 31 to 33 to the outside. In addition, hydrogen and water are prevented from being diffused from the outside into the oxide semiconductor films 31 to 33. It is possible to prevent intrusions such as

[0228] When a silicon nitride film is formed as the insulating film 36 by the plasma CVD method, the silicon-containing It is preferable to use deposition gases such as nitrogen and ammonia as source gases. By using this source gas, ammonia dissociates in the plasma and active species are generated. The active species is a bond between silicon and hydrogen contained in the silicon-containing deposition gas, and nitrogen. This breaks the triple bond between silicon and nitrogen, promoting the bonding of silicon and nitrogen. Therefore, a dense silicon nitride film having few hydrogen bonds and few defects can be formed. On the other hand, if the amount of ammonia relative to nitrogen in the source gas is high, the deposition properties including silicon are deteriorated. The decomposition of gas and nitrogen does not proceed, and silicon and hydrogen bonds remain, resulting in defects. The silicon nitride film formed is rough and has large defects. In the above, the flow rate ratio of nitrogen to ammonia is set to 5 or more and 50 or less, preferably 10 or more and 50 or less. It is preferable to set it to lower.

[0229] After the insulating film 35 is formed, heat treatment may be performed. The temperature of the heat treatment is typically 150°C or higher and lower than the substrate distortion point, preferably 200°C or higher and 450°C or lower, more preferably 3 The temperature is set to 00° C. or higher and 450° C. or lower. By this heat treatment, the oxide constituting the second layer of the insulating film 35 is Oxygen contained in the oxide insulating film is transferred to the oxide semiconductor films 31 to 33. The heat treatment can reduce the oxygen vacancies contained in these. The heating temperature is 350° C. and the heating time is 1 hour in an oxygen-containing mixed gas atmosphere.

[0230] After the insulating film 36 is formed, hydrogen or the like is removed from the oxide semiconductor films 31 to 33. Heat treatment may be carried out in order to release nitrogen. The heating temperature is 350° C. for 1 hour in a mixed gas atmosphere containing oxygen and nitrogen.

[0231] [Backgate electrode] The back gate electrodes (BGE1, BGE2) are the same as the gate electrodes (GE1, GE2, GE3). It can be formed in the same manner.

[0232] Below, some other examples of transistor configurations are shown.

[0233] (Transistors TA3 and TA4) FIG. 26(A) and FIG. 26(B) show the transistors TA3 and TA4, respectively. The top view (layout diagram) and its circuit symbol are shown in Fig. 27(A) and Fig. 27(B). 4 is a cross-sectional view of the transistor TA3 taken along the lines a7-a8 and b7-b8, and FIG. Cross-sectional views taken along lines a9-a10 and b9-b10 of A4 are shown.

[0234] The transistor TA3 includes a gate electrode GE4, an oxide semiconductor film OS4, a source electrode SE4, The transistor TA3 has a drain electrode DE4 and a back gate electrode BGE4. , a variant of the transistor TA1, in which the electrode BGE4 is located in the two openings CG4, CG5. The transistor TA1 is different from the transistor TA1 in that it is in contact with the electrode GE4. As shown in FIG. 27(B), the film OS4 is connected to the electrode GE4 in the channel width direction. and the electrode BGE4, which can further improve the strength of the transistor TA3. do.

[0235] The transistor TA4 includes a gate electrode GE5, an oxide semiconductor film OS5, a source electrode SE5, The transistor TA4 has a drain electrode DE5 and a back gate electrode BGE5. , a modified example of the transistor TA2, in which the electrode BGE5 is not connected to the electrode GE5, and the electrode BG E5 and electrode GE5 can be input with different signals or potentials. For example, A signal to control the conductive state of the transistor TA4 is input to the electrode BGE5. It is possible to input a signal or potential that corrects the threshold voltage of the transistor.

[0236] (Transistors TC1, TB2, TD1) 28(A), 28(B), and 28(C) show transistors TC1 and TC2, respectively. The top view (layout diagram) of the transistors TB2 and TD1 and their circuit symbols are shown below. 29(A) and 29(B) show the a11-a12 line and b Cross-sectional view taken along line 11b12, lines a13-a14 and b13-b1 of transistor TB2 A cross-sectional view taken along line 4, and lines a15-a16 and b15-b16 of transistor TD1 A cross-sectional view along a line is shown.

[0237] The transistor TC1 includes a gate electrode GE6, an oxide semiconductor film OS6, a source electrode SE6, The drain electrode DE6 and the back gate electrode BGE6 are provided. At G6, the transistor TC1 is in contact with the electrode GE6. This is an example of a two-layer structure of the OS6 membrane. The OS6 membrane consists of "32" and "33". Like the transistor TA1, the channel formation region of the transistor TC1 is also composed of "32". Therefore, the transistor TC1 is also a transistor that is connected to the transistor TA1. A transistor with a field effect mobility as high as 10 m 2 / Vs > 60cm 2 / Vs, preferably less than 15cm 2 / Vs or more 50cm 2 / Vs. Therefore, the transistor TC1 and the transistor TA1 Similarly, the present invention is suitable for transistors that are operated at high speeds, such as in driving circuits.

[0238] The transistor TB2 includes a gate electrode GE7, an oxide semiconductor film OS7, a source electrode SE7, The drain electrode DE7 and the back gate electrode BGE7 are provided. At G7, the transistor TB2 is in contact with the electrode GE7. This is an example, and differs from the transistor TB2 in that it has an electrode BGE7. 2 has an electrode BGE7 connected to the electrode GE7, so that the The on-state current is also high, and the mechanical strength is improved.

[0239] The transistor TD1 includes a gate electrode GE8, an oxide semiconductor film OS8, a source electrode SE8, and a drain electrode DE8. The transistor TD1 is a variant of the transistor TB1. In this example, the entire membrane OS8 overlaps the electrode GE8, and the part outside the edge of the electrode GE8 Thus, the transistor TD1 does not have a film OS8 that is connected to the transistor TB1. Since the SiO 2 film has a structure that is less exposed to light than the SiO 2 film, the SiO 2 film is suitable for use in a pixel portion.

[0240] The films constituting the transistors TA1, TA2 and TB1 are (Insulating film, oxide semiconductor film, metal oxide film, conductive film, etc.) are deposited by sputtering or chemical vapor deposition. Formed using deposition (CVD), vacuum deposition, or pulsed laser deposition (PLD) methods Alternatively, the film can be formed by a coating method or a printing method. The most representative methods are the galvanic deposition method and the plasma enhanced chemical vapor deposition (PECVD) method, but the thermal CVD method Examples of thermal CVD methods include MOCVD (metal organic chemical vapor deposition) and ALD (atomic layer deposition). The membrane method may also be used.

[0241] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The film is formed by feeding the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that no defects are created due to damage.

[0242] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially Next, the gas is introduced into the chamber, and the gas introduction sequence is repeated to form a film. For example, By switching each switching valve (also called high-speed valve), two or more types of raw material gas can be The first and second source gases are supplied to the chamber in order to prevent the multiple source gases from mixing. At the same time or afterwards, an inert gas (argon, nitrogen, etc.) is introduced to If an inert gas is introduced at the same time, the inert gas is introduced as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. A source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer. The first monolayer is then reacted with the second source gas introduced later, and the second monolayer is formed on the first monolayer. The layers are then stacked together to form a thin film.

[0243] This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film can be increased by repeating the gas introduction sequence. This allows precise film thickness control, making it possible to fabricate fine transistors. This is suitable for manufacturing.

[0244] <Transistor configuration example 2> The transistor used in the display device according to one embodiment of the present invention may be an amorphous, microcrystalline, or polycrystalline or a semiconductor film or substrate of single crystal silicon or germanium, The transistor may have a channel formation region. In this case, the thin film is formed by a vapor phase growth method such as a plasma CVD method or a sputtering method. The amorphous silicon produced is crystallized by processes such as laser annealing. Hydrogen ions were injected into the polycrystalline silicon and single crystal silicon wafers to remove the surface layer. Single crystal silicon or the like can be used.

[0245] 30A and 30B show a thin film that can be used in a display device according to one embodiment of the present invention. 30A and 30B are cross-sectional views of a transistor using a silicon film of n 2, a n-channel transistor 70 and a p-channel transistor 71 are shown.

[0246] The transistor 70 is formed on a substrate 72 having an insulating surface, and a conductive film 73 serving as a gate. an insulating film 74 on the conductive film 73; and a semiconductor layer overlapping the conductive film 73 with the insulating film 74 interposed therebetween. A film 75, an insulating film 76 on the semiconductor film 75, and a semiconductor film 75 overlapping the insulating film 76 therebetween. The conductive films 77a and 77b function as gates, and the conductive films 77a and and an insulating film 78 on the conductive film 77b, an insulating film 79 on the insulating film 78, and a The insulating film 79 is electrically connected to the semiconductor film 75 through an opening formed therein, and the insulating film 79 is also electrically connected to the source The conductive film 80 and the conductive film 81 function as a gate or drain.

[0247] The conductive film 77b has a length in the channel length direction shorter than that of the conductive film 77a. The conductive film 77b is laminated in order from the insulating film 76 side. A channel forming region 82 is formed at a position overlapping with 77b, and the channel forming region 82 is sandwiched between the A pair of LDD (Light Doped Drain) regions 83 located at the channel A pair of impurity regions 84 are disposed so as to sandwich an LDD region 83 therebetween. The pair of impurity regions 84 function as a source region or a drain region. The D region 83 and the impurity region 84 are impurity sources that impart n-type conductivity to the semiconductor film 75. Elements such as phosphorus (P) and arsenic (As) are added.

[0248] The transistor 71 has a conductive layer functioning as a gate on a substrate 72 having an insulating surface. The conductive film 85 is overlapped with the insulating film 74 on the conductive film 85 via the insulating film 74. A semiconductor film 86, an insulating film 76 on the semiconductor film 86, and a semiconductor film 86 with the insulating film 76 interposed therebetween. A conductive film 87a and a conductive film 87b overlap with each other and function as a gate. 7a and the insulating film 78 on the conductive film 87b, an insulating film 79 on the insulating film 78, and and electrically connected to the semiconductor film 86 in an opening provided in the insulating film 79, The conductive film 88 and the conductive film 89 function as a source and a drain.

[0249] The conductive film 87b is shorter in length in the channel length direction than the conductive film 87a. The conductive film 87b is laminated in order from the insulating film 76 side. A channel forming region 90 is formed at a position overlapping with 87b, and the channel forming region 90 is sandwiched between the The pair of impurity regions 91 are a source region or The impurity region 91 functions as a drain region. Impurity elements to be added, such as boron (B), aluminum (Al), and gallium (Ga) etc. have been added.

[0250] The semiconductor film 75 or the semiconductor film 86 may be crystallized by various techniques. Crystallization methods include laser crystallization using laser light and crystallization using catalytic elements. Alternatively, the crystallization method using a catalytic element and the laser crystallization method can be used in combination. In addition, when a substrate having excellent heat resistance such as quartz is used as the substrate 72, the substrate can be heated in an electric furnace. The thermal crystallization method using a thermal annealing method using infrared light, the lamp annealing crystallization method using a catalytic element, A crystallization method in which a high-temperature annealing at about 950° C. is combined with the crystallization method may be used.

[0251] In FIG. 30A, conductive films 77a and 77b functioning as gates and a back gate electrode Although a configuration having a conductive film 73 functioning as an electrode is shown, other configurations are also possible. For example, As shown in FIG. 30B, the conductive film 73 functioning as a back gate electrode is omitted. In FIG. 30A, conductive films 87a and 87b functioning as gates and Although the structure having the conductive film 73 functioning as a gate electrode is shown, other structures may be used. For example, as shown in FIG. 30B, a conductive film 85 functioning as a back gate electrode 30B may be omitted. Note that the structure in FIG.

[0252] FIG. 51A shows a transistor corresponding to the n-channel transistor 70 shown in FIG. FIG. 51(B) shows a top view of the transistor 70A. FIG. 51C is a cross-sectional view taken along line L1-L2, which shows the length direction of the transistor 70A. 1 is a cross-sectional view taken along line W1-W2, which represents the channel width direction.

[0253] In FIG. 51A, a conductive film 77, a conductive film 73, a semiconductor film 75, a conductive film 80, a conductive film 81, The conductive film 77 is formed as a gate. The conductive film 73 functions as a back gate. The details of the components with the same reference numerals are the same as those in FIG. 30(A), so The openings 93 and 94 connect the semiconductor film 75 to the conductive film 80 and the conductive film 81. The openings 95 and 96 are openings for electrically connecting the conductive film 77 and the conductive film 73. It is an opening for

[0254] In FIG. 51B, a conductive film 73, an insulating film 74, and a semiconductor device having a semiconductor device with the insulating film 74 interposed therebetween are provided on a substrate 72. A semiconductor film 75 overlapping with the conductive film 73, an insulating film 76 on the semiconductor film 75, and the insulating film 76 are A conductive film 77a and a conductive film 77b overlapping the semiconductor film 75 and functioning as a gate are provided between the conductive film 77a and the semiconductor film 75. a conductive film 77b; an insulating film 78 on the conductive films 77a and 77b; and an insulating film on the insulating film 78. The insulating film 78 and the semiconductor film 7 are formed in the openings 93 and 94 in the insulating film 79. 5 and a conductive film 80 that functions as a source or drain; The semiconductor film 75 includes a channel forming region 82 and an LDD region 83. 51(B), the semiconductor device has a channel forming region 83, a channel forming region 82, and an impurity region 84. In the above, the details of the configurations to which the same reference numerals are assigned are the same as those in FIG. Therefore, we will omit it here.

[0255] In FIG. 51C, a conductive film 73, an insulating film 74, and a channel forming region 82 are formed on a substrate 72. , an insulating film 76, and a conductive film 77 electrically connected to the conductive film 73 in the openings 95 and 96. a and a conductive film 77b, an insulating film 78 on the conductive film 77a and the conductive film 77b, and an insulating film 7 8 and an insulating film 79 are provided on the insulating film 79. The details of the configuration are the same as those explained in FIG. 30(A), and therefore will be omitted here.

[0256] In the top view and cross-sectional view shown in FIGS. 51A to 51C, the conductive film 77 which is a gate, The conductive film 73, which is a back gate electrically connected to the conductive film 77, The channel width direction of the channel forming region 82 is electrically surrounded by the The structure envelops the channel formation region from the upper surface, the lower surface, and the side surface of the channel formation region. Therefore, the on-current can be increased, and the size in the channel width direction can be reduced. In addition, since the channel formation region is surrounded by a conductive film, In this way, the channel formation region can be easily shielded from light, and unintended light does not enter the channel formation region. Photoexcitation caused by irradiation can be suppressed.

[0257] In the top view and cross-sectional view shown in FIGS. 51A to 51C, the semiconductor layer 75 To suppress a conductive state due to an unintended increase in conductivity at the side end in the W1-W2 direction In addition, the influence of the distribution variation of the impurity element added in the semiconductor layer 75 can be reduced. It is possible.

[0258] In the top view and cross-sectional view shown in FIG. 51(A) to (C), the gate and the back gate In the above embodiment, the voltages are electrically connected to each other, but a configuration in which the voltages are different is also effective. This is particularly effective when configuring a circuit with only n-channel transistors. The threshold voltage of the transistor can be controlled by applying a voltage, so transistors with different threshold voltages can be It is possible to configure logic circuits such as inverter circuits using ED-MOS. By applying such a logic circuit to the driver circuit for driving pixels, the driver circuit can be reduced in size. Since the area that can be covered by the display device can be reduced, a narrower frame of the display device can be realized. In addition, the back gate voltage is set to a voltage that turns off the transistor. Therefore, the off-state current when the transistor is turned off can be reduced. Even if the refresh rate is increased, the written voltage can be maintained. Therefore, it is expected that the power consumption of the display device can be reduced by reducing the number of times the data is written. can be done.

[0259] Note that the top views and cross-sectional views shown in FIGS. 51(A) to 51(C) are merely examples and may be of other configurations. For example, FIGS. 52(A) to (C) show top views different from those in FIGS. and a cross-sectional view.

[0260] The configuration shown in FIGS. 52(A) to (C) differs from the configuration shown in FIGS. 51(A) to (C) in the following points. The conductive layer 77 serving as the gate is formed as a single layer. The advantage of this is that the channel-shaped region 82 is closer to the channel-shaped region 82. To make it easier to apply an electric field from the upper surface, lower surface and side surface of the channel formation region toward the channel formation region. This configuration also has the same effects as those shown in Figs. 51(A) to (C). can be done.

[0261] As another configuration, FIGS. 53(A) to 53(C) are used. 1A) to 1C) show different top views and cross-sectional views.

[0262] The configuration shown in Figs. 53(A) to (C) is the same as that shown in Figs. 51(A) to (C) and Figs. The difference from the configuration shown in FIG. 1C is that the conductive layer 73 serving as the back gate is formed of a conductive film 73a and a conductive 13. The point is that the conductive film 73b is surrounded by the conductive film 73a. This configuration can also provide the same effects as those in FIGS. 51(A) to (C).

[0263] In addition, in the configurations of FIGS. 53(A) to 53(C), the conductive film 73b contains a mobile element (e.g., copper ( Even when Cu) is used, a mobile element penetrates into the semiconductor layer 75 and the semiconductor layer 75 Deterioration can be prevented.

[0264] The conductive film 73a on the surface on which the wiring is to be formed and functions as a barrier film is made of a material having a high melting point. The point materials are tungsten (W), molybdenum (Mo), chromium (Cr), and titanium (Ti ), tantalum (Ta), or their alloys (e.g., W-Mo, Mo-Cr, Ta-Mo), or its nitrides (e.g., tungsten nitride (WNx), titanium nitride (TiNx), tantalum nitride (TaNx), TiSiNx, etc. can be used. The conductive film 73b may be formed by sputtering, CVD, or the like. The material is preferably copper (Cu), but is not particularly limited as long as it is a low resistance material. For example, silver ( Also usable are Ag), aluminum (Al), gold (Au), and alloys thereof. The conductive film 73b is preferably formed by sputtering. A CVD method can also be used by selecting conditions that do not damage the substrate.

[0265] <Layout in which transistors are applied to pixels> 31 to 35 are top views and cross-sectional views of pixels to which the above transistor can be applied. An example of the surface view will be described.

[0266] [About top view 1] FIG. 31A shows an example of a top view corresponding to the pixel 100C shown in FIG. 8B. FIG. 31B shows a light emitting element 104 stacked in the pixel 100C. This is shown separately from (A).

[0267] In the top view shown in FIG. 31A, a transistor 101A, a transistor 102, a capacitor In addition, in the top view shown in FIG. 31(A), the gate The gate line GL, the data line DL, the current supply line PL, and the capacitance line CSL are illustrated. In the top view shown in FIG. 1(A), an opening CH1 and an opening CH2 are illustrated.

[0268] In the top view shown in FIG. 31(B), an electrode PE functioning as an anode electrode of the light-emitting element, The wall layer RL is also shown. The light-emitting layer and the electrode functioning as the cathode side electrode of the light-emitting element are also shown. Although omitted, the electrodes PE, the light emitting layer, and the light emitting element are provided in the openings of the partition layer RL. The region where the electrodes functioning as the cathode electrodes overlap is illustrated as a light emitting element 104. do.

[0269] The dashed lines AA', BB', and 32(A) to 32(C) are schematic cross-sectional views taken along dashed line CC'.

[0270] 32(A) to (C), a substrate 301, an insulating film 303, a gate electrode 305, an insulating film 306, and a gate electrode 307 are shown. 07, semiconductor film 309, electrode 311, insulating film 313, insulating film 315, insulating film 317, electrode PE, a partition layer RL, a light-emitting layer 323, an electrode 325, an opening CH1, and an opening CH2 are illustrated. .

[0271] The insulating film 303 functions as a base film. The insulating film 307 functions as a gate insulating film. The electrode 311 functions as a source electrode and a drain electrode. The insulating film 317 functions as a planarizing film. The electrode PE functions as a reflecting electrode. The details of the configuration of the transistor may be the same as those of the transistor described above. See Example 1.

[0272] The opening CH1 is provided in the insulating film 303. The opening CH1 is provided with a gate electrode 305. The opening CH2 is an opening for connecting a layer on which the insulating film 312 is formed to a layer on which the electrode 311 is formed. The opening CH2 is provided in the film 313, the insulating film 315, and the insulating film 317. The opening is for connecting the layer to be provided and the layer on which the electrode 311 is provided.

[0273] The size of the semiconductor film may be different for each color emitted by the light emitting element. For example, in FIG. 33A, a pixel 100C_R emits red light, a pixel 100C emits green light, _G, a pixel 100C_B that emits blue light is illustrated. A pixel 100C_B that emits red light is illustrated. The pixel 100C_G that emits green light has a transistor 102R. The pixel 100C_B that emits blue light has a transistor 102R. The other configurations may be the same for each pixel or may be different.

[0274] In the transistor 102R, the transistor 102G, and the transistor 102B, The distances L1, L2, and L3 between the light emitting elements are different. The current that flows can be adjusted for each color, resulting in a display device with excellent display quality. It is possible.

[0275] The capacitance of the capacitor 103 and the capacitor 105 is set for each color emitted by the light emitting element. For example, in FIG. 33(B), the ratio of the sizes may be different. ), a pixel 100C_R that emits red light, a pixel 100C_G that emits green light, and a pixel 100C_G that emits blue light. 3 shows a pixel 100C_B that emits light.

[0276] The pixel 100C_R that emits red light has a layer in which the gate electrode 305 is provided and an electrode 311. A capacitor C is provided overlapping the layer provided 103R It also emits red light. The pixel 100C_R includes a layer in which a gate electrode 305 is provided and a layer in which an electrode 311 is provided. The capacitor C 105R Similarly, pixel 1 emitting green light 00C_G is the capacitor C 103G and capacitor C 105G Similarly, blue The pixel 100C_B that emits the color 103B and capacitor C 105B of Yes.

[0277] As shown in FIG. 33(B), a capacitor C 103R and capacitor C 105R The ratio of the areas is , capacitor C 103G and capacitor C 105G The ratio of the areas of the capacitors C 103 B and capacitor C 105B It is preferable to make the ratio of the areas different from that of the areas of the The anode of the light emitting element changes according to the capacitance ratio during the data voltage writing period. The increase in the potential on the side of the pixel can be adjusted for each color. As a result, a display device with excellent display quality can be obtained. It is possible.

[0278] [About top view 3] FIG. 34A shows an example of a top view corresponding to the pixel 100B shown in FIG. 8A. FIG. 34B shows a light-emitting element 104 stacked in the pixel 100B. This is shown separately from (A).

[0279] In the top view shown in FIG. 34A, a transistor 101A, a transistor 102, a capacitor In addition, in the top view shown in FIG. 34(A), the gate The gate line GL, the data line DL, and the current supply line PL are illustrated. In the top view, an opening CH1, an opening CH2, an opening CH3, and an opening CH4 are illustrated.

[0280] In the top view shown in FIG. 34(B), an electrode PE functioning as an anode electrode of the light-emitting element, The wall layer RL is also shown. The light-emitting layer and the electrode functioning as the cathode side electrode of the light-emitting element are also shown. Although omitted, the electrode PE is provided in an opening of the partition layer RL that overlaps the electrode PE. The light emitting layer and the electrode that functions as the cathode electrode of the light emitting element are overlapped to form the light emitting element 104. In addition, in the top view shown in FIG. 34B, an opening provided in the partition layer RL is is illustrated as an opening CH5.

[0281] The dashed lines AA', BB', and 35(A) to (C) show schematic cross-sectional views taken along dashed line CC'.

[0282] 35(A) to (C), a substrate 301, an insulating film 303, a gate electrode 305, an insulating film 306, and a gate electrode 307 are shown. 07, semiconductor film 309, electrode 311, insulating film 313, insulating film 315, insulating film 317, electrode PE, an electrode 319, a partition layer RL, a light-emitting layer 323, an electrode 325, an opening CH1, an opening CH2, An aperture CH3, an aperture CH4, and an aperture CH5 are shown.

[0283] The insulating film 303 functions as a base film. The insulating film 307 functions as a gate insulating film. The electrode 311 functions as a source electrode and a drain electrode. The insulating film 317 functions as a planarizing film. The electrode PE functions as a reflecting electrode. The details of the configuration of the transistor may be the same as those of the transistor described above. See Example 1.

[0284] The opening CH1 is provided in the insulating film 303. The opening CH1 is provided with a gate electrode 305. The opening CH2 is an opening for connecting a layer on which the insulating film 312 is formed to a layer on which the electrode 311 is formed. The opening CH2 is provided in the film 313, the insulating film 315, and the insulating film 317. The opening CH3 is an opening for connecting a layer on which the electrode 311 is provided to a layer on which the electrode 311 is provided. The opening CH1 is provided in the insulating film 303. The opening CH4 is an opening for connecting the insulating film 313 and the layer on which the electrode 311 is provided. The opening CH4 is provided in the insulating film 315 and the insulating film 317. The opening CH4 is provided with the electrode PE. The opening CH5 is an opening for connecting the barrier layer to a layer on which the electrode 311 is provided. The opening CH5 is provided in the layer on which the electrode PE is provided and the layer on which the electrode 325 is provided. These are openings for connecting layers.

[0285] In the top view and cross-sectional schematic diagrams shown in FIGS. 34 and 35, the size of the semiconductor film is As in FIG. 33(A), the light emitting elements may be configured to emit different colors. In the configurations shown in the top view and the schematic cross-sectional view of FIG. 34 and FIG. 35, the capacitor 103 and The ratio of the areas of the light emitting elements 102 and 105 is different for each color emitted by the light emitting element, as in FIG. 33(B). It may also be composed of.

[0286] (Embodiment 3) In this embodiment mode, an example of a manufacturing method of a display device will be described with reference to FIGS. In particular, in this embodiment mode, a manufacturing method of a flexible display device will be described.

[0287] <Display device manufacturing method 1> First, an insulating film 420 is formed on a substrate 462, and a first element layer 410 is formed on the insulating film 420. (See FIG. 36A). The first element layer 410 is provided with a semiconductor element. Alternatively, the first element layer 410 may include a display element or a pixel electrode in addition to the semiconductor element. A part of the display element may be provided.

[0288] The substrate 462 must have at least sufficient heat resistance to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 4. It may also be used as 62.

[0289] When a glass substrate is used as the substrate 462, a silicon oxide film is formed between the substrate 462 and the insulating film 420. When an insulating film such as a silicon oxide nitride film, a silicon nitride film, or a silicon nitride oxide film is formed, the glass This is preferable because it can prevent contamination from the substrate.

[0290] The insulating film 420 may be made of, for example, epoxy resin, aramid resin, acrylic resin, or polyimide resin. An organic resin film such as a resin, a polyamide resin, or a polyamide-imide resin can be used. In particular, it is preferable to use a polyimide resin because of its high heat resistance. When a polyimide resin is used, the thickness of the polyimide resin is preferably 3 nm or more and 20 μm or less. The thickness is preferably 500 nm or more and 2 μm or less. In this case, the coating method may be a spin coating method, a dip coating method, a doctor blade method, or the like. For example, when a polyimide resin is used as the insulating film 420, By removing a portion of the film using the polyimide resin by the method, a film having a desired thickness can be obtained. An insulating film 420 can be obtained.

[0291] The first element layer 410 is fabricated at a temperature of room temperature or higher and 300° C. or lower. For example, the insulating film or conductive film using an inorganic material included in the first element layer 410 is preferably The conductive film is formed at a film formation temperature of 150°C to 300°C, and more preferably 200°C to 270°C. In addition, the organic resin material contained in the first element layer 410 is preferably used. The insulating film or the like is preferably formed at a film formation temperature of from room temperature to 100° C. or less.

[0292] In addition, the oxide semiconductor film of the transistor included in the first element layer 410 is It is preferable to use AC-OS for the oxide semiconductor film of the transistor. When S is used, for example, when the display device 400 is folded, cracks are prevented from occurring in the channel formation region. This makes it difficult for defects such as the above to enter the material, and makes it possible to increase resistance to bending.

[0293] The conductive film included in the first element layer 410 is made of indium tin oxide to which silicon oxide is added. If tin oxide is used, cracks or the like may occur in the conductive film when the display device 400 is bent. This is preferable because it makes things more difficult.

[0294] Next, the first element layer 410 and a temporary support substrate 466 are bonded together using a peeling adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the substrate 462. The first element layer 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 36(B)). .

[0295] The temporary support substrate 466 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, A metal substrate or the like can be used. In addition, a substrate having heat resistance capable of withstanding the processing temperature of this embodiment is also suitable. A plastic substrate having a thickness of 100 nm or a flexible substrate such as a film may be used. .

[0296] The peeling adhesive 464 may be soluble in water or solvent, or plasticized by exposure to ultraviolet light, etc. The temporary support substrate 466 and the element layer 410 can be bonded together as needed, for example. Use an adhesive that can be chemically or physically separated.

[0297] In addition, the transfer step onto the temporary support substrate 466 can be performed by using various methods as appropriate. For example, 36B, the side of the substrate 462 on which the insulating film 420 is not formed, that is, the lower side shown in FIG. By irradiating the insulating film 420 with the laser light 468, the insulating film 420 is weakened. The substrate 462 and the insulating film 420 can be peeled off by the laser beam 468. By adjusting the energy density, it is possible to obtain a region where the substrate 462 and the insulating film 420 have high adhesion and a region where the substrate 462 and the insulating film 420 have high adhesion. Alternatively, regions where the plate 462 and the insulating film 420 have low adhesion may be created and then peeled off.

[0298] In this embodiment, the method of peeling off the substrate 462 and the insulating film 420 at the interface is as follows. However, the present invention is not limited to this. For example, the boundary between the insulating film 420 and the first element layer 410 may be It may be peeled off at the surface.

[0299] In addition, a liquid is permeated into the interface between the substrate 462 and the insulating film 420 to remove the insulating film 420 from the substrate 462. Alternatively, a liquid may be permeated into the interface between the insulating film 420 and the first element layer 410. The first element layer 410 may be peeled off from the insulating film 420 by removing the liquid. For example, water, a polar solvent, or the like can be used. The liquid is formed at the interface between the plate 462 and the insulating film 420 or at the interface between the insulating film 420 and the first element layer 410. The electrostatic charge generated by the peeling applied to the first element layer 410 by penetrating the body The effects of heat and other factors can be suppressed.

[0300] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (FIG. 36( See C).

[0301] The release adhesive 464 is then dissolved or plasticized to remove the release adhesive from the first element layer 410. The adhesive 464 and the temporary support substrate 466 are removed (see FIG. 36(D)).

[0302] The peeling adhesive 464 is removed by removing water or a solvent so that the surface of the first element layer 410 is exposed. It is preferable to remove it.

[0303] Through the above steps, the first element layer 410 can be manufactured over the first substrate 401 .

[0304] Next, the second substrate 4 is formed by the same method as the steps shown in FIG. 36(A) to FIG. 36(D). 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and An element layer 411 is formed (see FIG. 37A).

[0305] The insulating film 440 of the second element layer 411 is made of the same material as the insulating film 420. can be formed using an organic resin.

[0306] Next, a sealing layer 432 is filled between the first element layer 410 and the second element layer 411. The element layer 410 and the second element layer 411 are bonded to each other (see FIG. 37B).

[0307] The sealing layer 432 can provide, for example, solid sealing. The sealing layer 432 is preferably made of, for example, glass frit. Glass materials such as these, two-part resins that harden at room temperature, and photocurable resins For example, a resin material such as a thermosetting resin can be used.

[0308] In this manner, the display device 400 can be manufactured.

[0309] <Display device manufacturing method 2> Next, another method for manufacturing the display device 400 according to one embodiment of the present invention will be described with reference to FIG. In FIG. 38, an inorganic insulating film is used as the insulating film 420 and the insulating film 440. The configuration used will be explained below.

[0310] First, a separation layer 463 is formed over a substrate 462. Next, an insulating film 420 is formed over the separation layer 463. A first element layer 410 is formed over the insulating film 420 (see FIG. 38A).

[0311] The peeling layer 463 may be made of, for example, tungsten, molybdenum, titanium, tantalum, or niobium. , Nickel, Cobalt, Zirconium, Zinc, Ruthenium, Rhodium, Palladium, Os An element selected from the group consisting of tungsten, iridium, and silicon, an alloy material containing the element, or The material may be a compound material containing silicon, and may be a single layer or a laminated structure. In the case of a layer containing silicon, the crystal structure of the layer containing silicon may be amorphous, microcrystalline, polycrystalline, or the like. The crystal may be either a single crystal or a single crystal.

[0312] The release layer 463 can be formed by a sputtering method, a PECVD method, a coating method, a printing method, or the like. The coating method includes a spin coating method, a droplet ejection method, and a dispense method.

[0313] When the release layer 463 has a single layer structure, it is made of tungsten, molybdenum, or tungsten and molybdenum. It is preferable to form a layer containing a mixture of tungsten and butenone. a layer containing an oxynitride, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of stainless steel and molybdenum may be formed. A mixture of tungsten and molybdenum is, for example, an alloy of tungsten and molybdenum. is equivalent to.

[0314] The peeling layer 463 may be a stack of a layer containing tungsten and a layer containing an oxide of tungsten. When forming a layered structure, a layer containing tungsten is formed, and an upper layer made of oxide is formed. By forming an insulating layer, tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. In addition, the surface of the layer containing tungsten may be treated with a thermal acid. Chemical treatment, oxygen plasma treatment, nitrous oxide (N2O) plasma treatment, ozone water, etc. A layer containing tungsten oxide may be formed by treatment with a strong solution or the like. Zuma treatment and heat treatment can be performed using oxygen, nitrogen, or nitrous oxide alone or in combination with other gases. The above-mentioned plasma treatment or heat treatment may be performed under a mixed gas atmosphere. By changing the surface condition of the peeling layer 463, the adhesion between the peeling layer 463 and the insulating film 420 to be formed later can be improved. It is possible to control the

[0315] The insulating film 420 may be, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Inorganic insulating films with low moisture permeability, such as silicon films and aluminum oxide films, can be used. The inorganic insulating film can be formed by using, for example, a sputtering method, a PECVD method, or the like. Cut.

[0316] Next, the first element layer 410 and a temporary support substrate 466 are bonded together using a peeling adhesive 464. Then, the insulating film 420 and the first element layer 410 are peeled off from the peeling layer 463. The film 420 and the first element layer 410 are provided on the temporary support substrate 466 side (see FIG. 38(B)). ).

[0317] In addition, the transfer step onto the temporary support substrate 466 can be performed by using various methods as appropriate. For example, When a layer including a metal oxide film is formed at the interface between the peeling layer 463 and the insulating film 420, the metal The oxide film is weakened by crystallization, and the insulating film 420 can be peeled off from the peeling layer 463. In addition, when the peeling layer 463 is formed using a tungsten film, ammonia water and hydrogen peroxide are used. The tungsten film may be removed while being etched with a mixed solution of water.

[0318] In addition, a liquid is permeated into the interface between the peeling layer 463 and the insulating film 420 to remove the insulating film from the peeling layer 463. The liquid may be, for example, water, a polar solvent, or the like. At the interface where the insulating film 420 is peeled off, specifically, at the interface between the peeling layer 463 and the insulating film 420, By infiltrating the liquid, the static electricity generated by the peeling applied to the first element layer 410 is reduced. The effects of electricity, etc. can be suppressed.

[0319] Next, the first substrate 401 is bonded to the insulating film 420 using the adhesive layer 418 (FIG. 38(C) reference).

[0320] The release adhesive 464 is then dissolved or plasticized to remove the release adhesive from the first element layer 410. The adhesive 464 and the temporary support substrate 466 are removed (see FIG. 38(D)).

[0321] The peeling adhesive 464 is removed by removing water or a solvent so that the surface of the first element layer 410 is exposed. It is preferable to remove it.

[0322] Through the above steps, the first element layer 410 can be manufactured over the first substrate 401 .

[0323] Next, a second substrate 4 is formed by the same method as the steps shown in FIG. 38(A) to FIG. 38(D). 05, an adhesive layer 412 on the second substrate 405, an insulating film 440 on the adhesive layer 412, and Then, the first element layer 410 and the second element layer 411 are formed. A sealing layer 432 is filled in the gap, and the first element layer 410 and the second element layer 411 are bonded together. do.

[0324] Finally, the anisotropic conductive film 380 and the FPC 408 are attached to the connection electrodes 360. For example, an IC chip or the like may be mounted.

[0325] In this manner, the display device 400 can be manufactured.

[0326] (Embodiment 4) In this embodiment, a display device according to one embodiment of the present invention and an input device provided in the display device are provided. The attached electronic devices will be described with reference to FIGS.

[0327] <Touch panel explanation> In the present embodiment, an electronic device that combines a display device and an input device is used as an example of the electronic device. A touch panel 2000 having the touch sensor 2000 will be described. The case where the .

[0328] 39(A) and (B) are perspective views of the touch panel 2000. In B), representative components of touch panel 2000 are shown for clarity.

[0329] The touch panel 2000 includes a display device 2501 and a touch sensor 2595 (see FIG. 3). 9(B)). The touch panel 2000 also includes a substrate 2510, a substrate 2570, and The substrate 2590 is a substrate 2510, a substrate 2570, and a substrate 2590. However, any of the substrates 2510, 2570, and 2590 may be flexible. Any one or all of these may be configured to have no flexibility.

[0330] The display device 2501 includes a plurality of pixels on a substrate 2510 and a display device for supplying signals to the pixels. The plurality of wirings 2511 are arranged on the outer periphery of the substrate 2510. The terminal 2519 is connected to the FPC 250 9(1) and electrically connected.

[0331] The substrate 2590 is electrically connected to the touch sensor 2595. The plurality of wirings 2598 are routed around the periphery of the substrate 2590. A part of the terminal is electrically connected to the FPC2509(2). In FIG. 39(B), for clarity, the back side of the substrate 2590 (substrate 2510) is shown. The electrodes and wiring of the touch sensor 2595 provided on the surface opposite to the touch panel 2591 are shown by solid lines. .

[0332] As the touch sensor 2595, for example, a capacitive touch sensor can be used. The capacitive type includes a surface type capacitive type and a projected type capacitive type.

[0333] The projected capacitive type is classified into self-capacitance type, mutual capacitance type, etc., mainly based on the difference in the driving method. The mutual capacitance method is preferable because it enables simultaneous multi-point detection.

[0334] The touch sensor 2595 shown in FIG. 39(B) is a projected capacitive touch sensor. This is a configuration in which the .

[0335] The touch sensor 2595 can detect the proximity or contact of a detection target such as a finger. Various sensors can be applied.

[0336] The projected capacitive touch sensor 2595 has an electrode 2591 and an electrode 2592. The electrode 2591 is electrically connected to one of a plurality of wirings 2598, and the electrode 2592 is It is electrically connected to any other of the multiple wirings 2598.

[0337] As shown in FIG. 39(A)(B), the electrodes 2592 are arranged in a single direction. The shape is such that the four quadrilaterals are connected at their corners.

[0338] The electrode 2591 is quadrilateral and is repeated in a direction intersecting the direction in which the electrode 2592 extends. are placed.

[0339] The wiring 2594 is electrically connected to the two electrodes 2591 that sandwich the electrode 2592. In this case, it is preferable that the area of ​​the intersection between the electrode 2592 and the wiring 2594 is as small as possible. This reduces the area of ​​the region where no electrodes are provided, reducing variations in transmittance. As a result, the variation in the brightness of the light passing through the touch sensor 2595 can be reduced. can be done.

[0340] The shapes of the electrodes 2591 and 2592 are not limited to this, and various shapes may be used. For example, multiple electrodes 2591 are arranged with as few gaps as possible, and an insulating layer is A plurality of electrodes 2592 are provided at intervals so that there is an area where the electrodes 2592 do not overlap with the electrodes 2591. In this case, a structure in which the adjacent two electrodes 2592 are electrically connected to each other may be used. It is preferable to provide an insulated dummy electrode on the substrate so that the area of ​​the region having different transmittance can be reduced. stomach.

[0341] In addition, the conductive films such as the electrodes 2591, the electrodes 2592, and the wiring 2598, that is, the touch panel Materials that can be used for the wiring and electrodes that make up the filter include indium oxide, tin oxide, and oxide. Examples of the transparent conductive film include a transparent conductive film having zinc oxide or the like (e.g., ITO, etc.). As a material that can be used for the wiring and electrodes that constitute the device, for example, a material with a low resistance value is preferable. Examples include silver, copper, aluminum, carbon nanotubes, graphene, and halogens. Metal halide (silver halide, etc.) may also be used. Even if metal nanowires (diameters of several nanometers) are used, which are made up of multiple conductors, Alternatively, a metal mesh made of a conductor may be used. Nanowires, Cu nanowires, Al nanowires, Ag mesh, Cu mesh, Al plate For example, Ag nanowires may be used for the wiring and electrodes that make up the touch panel. When using a material with a visible light transmittance of 89% or more and a sheet resistance of 40 Ω / cm 2 End 100Ω / cm 2 The wiring constituting the above-mentioned touch panel can be as follows. Examples of materials that can be used for the electrodes include metal nanowires, metal meshes, and carbon nanotubes. Nanotubes and graphene have high transmittance in visible light, so they are used in display elements. It may also be used as an electrode (for example, a pixel electrode or a common electrode).

[0342] <Explanation about the display device> Next, the display device 2501 will be described in detail with reference to FIGS. 40(A) and (B) correspond to cross-sectional views taken along dashed line X1-X2 shown in FIG. 39(B).

[0343] The display device 2501 has a plurality of pixels arranged in a matrix. The display device has a display element and a pixel circuit for driving the display element.

[0344] In the cross-sectional view shown in FIG. 40(A), an EL element that emits white light is used as a display element. However, the EL element is not limited to this. As shown in Figure 2B, adjacent pixels emit different colors of light. In the following explanation, the EL element that emits white light can be painted differently for each pixel. An example in which an emitting EL element is used as a display element will be described.

[0345] The substrate 2510 and the substrate 2570 are, for example, a substrate having a water vapor permeability of 10 -5 g / ( m 2 ·day) or less, preferably 10 -6 g / (m 2 ·Day) or less flexibility Alternatively, a material having a thermal expansion coefficient of the substrate 2510 and a material having a thermal expansion coefficient of the substrate 2570 may be preferably used. For example, a material with a linear expansion coefficient of 1×10 -3 / K or less, preferably 5×10 -5 / K or less, preferably 1×10 -5 / K or less It is possible to suitably use a material in which

[0346] The substrate 2510 is made of an insulating layer 2510a for preventing impurities from diffusing into the EL element, and a flexible A substrate 2510b and an adhesive layer that bonds the insulating layer 2510a and the flexible substrate 2510b together The substrate 2570 is a laminate having a thickness of 100 nm and a thickness of 100 nm. A dielectric layer 2570a for preventing diffusion, a flexible substrate 2570b, and a dielectric layer 2570a and a flexible substrate 2570b are provided. and an adhesive layer 2570c for bonding the substrate 2570b, thereby forming a laminate.

[0347] The adhesive layer 2510c and the adhesive layer 2570c may be made of, for example, polyester or polyolefin. Fins, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, poly Materials containing styrene, acrylic resin, epoxy resin, or resin with siloxane bonds It can be used.

[0348] In addition, a sealing layer 2560 is provided between the substrate 2510 and the substrate 2570. It is preferable that the refractive index of the sealing material is larger than that of air. When light is extracted to the layer 2560 side, the sealing layer 2560 can also serve as an optical element.

[0349] A sealant may be formed on the outer periphery of the sealing layer 2560. As a result, the area surrounded by the substrate 2510, the substrate 2570, the sealing layer 2560, and the sealant The sealing layer 2560 may include an EL element 2550. An inert gas (such as nitrogen or argon) may be filled. In addition, a desiccant may be added to the inert gas. In addition, the above-mentioned sealing material may be, for example, For example, it is preferable to use epoxy resin or glass frit. As the material, it is preferable to use a material that is impermeable to moisture and oxygen.

[0350] The display device 2501 shown in FIG. 40A includes a pixel 2505. 505 is a light emitting module 2580, an EL element 2550, and a The transistor 2502t can supply the 2t functions as a part of the pixel circuit.

[0351] The light emitting module 2580 also includes an EL element 2550 and a coloring layer 2567 . The EL element 2550 has a lower electrode, an upper electrode, and an EL element between the lower electrode and the upper electrode. The layer.

[0352] In addition, when the sealing layer 2560 is provided on the side from which light is extracted, the sealing layer 2560 has a property of E The LED element 2550 is in contact with the colored layer 2567. The colored layer 2567 is made of EL elements having different luminescent colors. When the elements are colored for each pixel, they can be omitted as shown in FIG. do.

[0353] The colored layer 2567 is located so as to overlap the EL element 2550. A part of the light emitted by the light emitting module 50 passes through the colored layer 2567 and travels in the direction of the arrow shown in the figure. It is ejected outside of the ball 2580.

[0354] Furthermore, the display device 2501 is provided with a light-shielding layer 2568 in the light-emitting direction. A layer 2568 is provided surrounding the colored layer 2567 .

[0355] The colored layer 2567 may have a function of transmitting light of a specific wavelength band. For example, For example, a color filter that transmits light in the red wavelength band, a color filter that transmits light in the green wavelength band, A color filter that transmits light in the blue wavelength range, a color filter that transmits light in the yellow wavelength range, Each color filter can be made of various materials. Printing method, inkjet method, etching method using photolithography technology, etc. It can be formed with.

[0356] The display device 2501 is provided with an insulating layer 2521. The insulating layer 2521 covers the transistor 2502t and the like. In addition, the insulating layer 2521 has a function of suppressing diffusion of impurities. This prevents the reliability of the transistors 2502t and the like from being deteriorated due to the diffusion of impurities. can be suppressed.

[0357] The EL element 2550 is formed above the insulating layer 2521. The lower electrode of 50 is provided with a partition wall 2528 that overlaps with an edge of the lower electrode. A spacer for controlling the distance between the substrate 2510 and the substrate 2570 is formed on the partition wall 2528. You may do so.

[0358] The gate line driver circuit 2504 includes a transistor 2503t and a capacitor 2503c. The driver circuit and the pixel circuit can be formed on the same substrate in the same process. do.

[0359] Moreover, wiring 2511 capable of supplying signals is provided on the substrate 2510 . A terminal 2519 is provided on the wiring 2511. C2509(1) is electrically connected to FPC2509(1). FPC2509(1) also transmits video signals, It has the function of supplying clock signals, start signals, reset signals, etc. 509(1) may have a printed wiring board (PWB) attached.

[0360] In addition, either one or both of the transistors 2502t and 2503t The transistor described in the above embodiment may be used for the other transistor. The transistor includes a highly purified oxide semiconductor film with high crystallinity. Therefore, the current value in the OFF state (off-state current value) can be reduced. The signal retention time can be extended, and the write interval can also be set longer when the power is on. This reduces the frequency of refresh operations, which is effective in reducing power consumption. The refresh operation will be described in detail later.

[0361] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a display device. By using this in the device 2501, the switching transistor of the pixel circuit and the In other words, a separate driver circuit can be formed on the same substrate. Since it is not necessary to use a semiconductor device formed of a silicon wafer or the like, The number of parts in the device can be reduced. Also, the pixel circuit can be driven at high speed. By using a transistor, a high-quality image can be provided.

[0362] <Explanation about touch sensor> Next, the touch sensor 2595 will be described in detail with reference to FIG. 39(B) along dashed line X3-X4.

[0363] The touch sensor 2595 includes electrodes 2591 and electrodes 2592 arranged in a staggered pattern on a substrate 2590. An electrode 2592, an insulating layer 2593 covering the electrodes 2591 and 2592, and adjacent electrodes 2591 and wiring 2594 that electrically connects them.

[0364] The electrode 2591 and the electrode 2592 are formed using a light-transmitting conductive material. Examples of conductive materials having this property include indium oxide, indium tin oxide, and indium zinc oxide. Conductive oxides such as zinc oxide, zinc oxide doped with gallium, etc. can be used. A film containing graphene may also be used. The film containing graphene is, for example, a film The graphene oxide film can be formed by reducing a film containing the graphene oxide formed in a shape. Examples of the method include a method of applying heat.

[0365] For example, a light-transmitting conductive material is formed on the substrate 2590 by a sputtering method. After that, various patterning techniques such as photolithography are used to remove unnecessary parts. , an electrode 2591 and an electrode 2592 can be formed.

[0366] The material used for the insulating layer 2593 is, for example, a resin such as acrylic or epoxy. In addition to resins with siloxane bonds, silicon oxide, silicon oxynitride, aluminum oxide, Alternatively, inorganic insulating materials such as rubber may be used.

[0367] In addition, an opening reaching the electrode 2591 is provided in the insulating layer 2593, and a wiring 2594 is adjacent to the insulating layer 2593. The transparent conductive material is used to increase the aperture ratio of the touch panel. Since the electrode 2591 can be formed by the above-mentioned method, it can be suitably used for the wiring 2594. A material with higher electrical conductivity than the electrode 2592 can be used for the wiring 2594 because it can reduce electrical resistance. It can be suitably used.

[0368] The electrodes 2592 extend in one direction, and a plurality of electrodes 2592 are provided in a stripe pattern. In addition, the wiring 2594 is provided so as to intersect with the electrode 2592.

[0369] A pair of electrodes 2591 are provided with one electrode 2592 interposed therebetween. A pair of electrodes 2591 are electrically connected.

[0370] In addition, the multiple electrodes 2591 are arranged in a direction that is not necessarily perpendicular to one electrode 2592. The angle does not have to be 0 degrees, and may be greater than 0 degrees but less than 90 degrees.

[0371] The wiring 2598 is electrically connected to the electrode 2591 or the electrode 2592. A part of the wiring 2598 functions as a terminal. The wiring 2598 is made of, for example, aluminum. Aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, Use of metal materials such as ballast, copper, or palladium, or alloy materials containing such metal materials. can be done.

[0372] An insulating layer is provided to cover the insulating layer 2593 and the wiring 2594. 5 may be protected.

[0373] The connection layer 2599 electrically connects the wiring 2598 and the FPC 2509(2). .

[0374] The connection layer 2599 is made of an anisotropic conductive film (ACF). conductive film) and anisotropic conductive paste (ACP) Conductive Paste) can be used.

[0375] <Touch panel explanation> Next, the touch panel 2000 will be described in detail with reference to FIG. 34(A) corresponds to a cross-sectional view taken along dashed line X5-X6 shown in 34(A).

[0376] The touch panel 2000 shown in FIG. 42A is a display device 250 described in FIG. 41. The touch sensor 2595 shown in FIG.

[0377] In addition, the touch panel 2000 shown in FIG. 42(A) has the following configuration in addition to that described in FIG. , an adhesive layer 2597 and an anti-reflective layer 2569 .

[0378] The adhesive layer 2597 is provided in contact with the wiring 2594. The substrate 2590 is attached to the substrate 2570 so that the sensor 2595 overlaps the display device 2501. In addition, it is preferable that the adhesive layer 2597 is transparent. The material 597 may be a thermosetting resin or an ultraviolet-curing resin. For example, Acrylic resin, urethane resin, epoxy resin, or siloxane resin can be used. This can be done.

[0379] The anti-reflection layer 2569 is provided at a position overlapping the pixel. For example, a circular polarizer can be used.

[0380] Next, for a touch panel having a different configuration from that shown in FIG. 42(A), I will use this to explain.

[0381] FIG. 42(B) is a cross-sectional view of the touch panel 2001. The panel 2001 is a touch panel 2000 shown in FIG. The location of the touch sensor 2595 is different. The different configurations are described in detail here. The description of touch panel 2000 is cited for the parts in which such a configuration can be used.

[0382] The colored layer 2567 is located below the EL element 2550. The L element 2550 emits light to the side where the transistor 2502t is provided. As a result, a part of the light emitted by the EL element 2550 is transmitted through the colored layer 2567 and is reflected by the light emitting diode 2566 as shown by the arrows in the figure. The light is emitted to the outside of the light emitting module 2580 in the direction of the mark.

[0383] The touch sensor 2595 is provided on the substrate 2510 side of the display device 2501. .

[0384] The adhesive layer 2597 is between the substrate 2510 and the substrate 2590 and is in contact with the display device 2501. Stick the Chisensor 2595 together.

[0385] As shown in FIGS. 42(A) and 42(B), the light emitted from the light emitting element is guided by the substrate 2510 and It may be emitted through either or both of the substrates 2570 .

[0386] <Explanation of how to drive the touch panel> Next, an example of a method for driving a touch panel will be described with reference to FIG.

[0387] FIG. 43A is a block diagram showing the configuration of a mutual capacitance type touch sensor. In (A), a pulse voltage output circuit 2601 and a current detection circuit 2602 are shown. In FIG. 43(A), the electrodes 2621 to which the pulse voltage is applied are designated as X1-X6, and the change in current The electrodes 2622 for detecting the change are shown as Y1-Y6, each having six wires. FIG. 43(A) shows a capacitance formed by overlapping an electrode 2621 and an electrode 2622. 2603. The electrodes 2621 and 2622 are interchangeable in function. It may be possible.

[0388] The pulse voltage output circuit 2601 is a circuit for applying pulses to the wirings X1-X6 in sequence. When a pulse voltage is applied to the wiring of X1-X6, the voltage that forms the capacitance 2603 An electric field is generated between the electrodes 2621 and 2622. The electric field generated between the electrodes is blocked by By using the change in the mutual capacitance of the capacitance 2603, the proximity of the object to be detected or A contact can be detected.

[0389] The current detection circuit 2602 detects the change in mutual capacitance of the capacitor 2603 and the currents of the wires Y1 to Y6. This is a circuit to detect changes in current at the sensor. The wiring of Y1-Y6 detects the proximity of the object to be detected, Or, if there is no contact, the detected current value will not change, but the proximity of the object to be detected, or When the mutual capacitance decreases due to contact, a change in the current value is detected. The detection may be performed using an integrating circuit or the like.

[0390] Next, FIG. 43B shows the input of the mutual capacitance type touch sensor shown in FIG. The output waveform timing chart is shown in FIG. 43(B). In FIG. 43(B), the case where the object is not detected ( Two cases are shown: when the sensor detects a target object (touch) and when the sensor detects a target object (non-touch). For the wiring Y1-Y6, the waveform is shown as a voltage value corresponding to the detected current value. There are.

[0391] A pulse voltage is applied to the wires X1-X6 in sequence, and the The waveform in the Y6 wiring changes. When there is no proximity or contact of the object to be detected, X1-X6 The waveforms of Y1-Y6 change uniformly according to the change in the voltage of the wiring. Or, at the point of contact, the current value decreases, and the corresponding voltage waveform also changes. do.

[0392] In this way, by detecting the change in mutual capacitance, the proximity or contact of the object to be detected can be detected. It is possible.

[0393] <Sensor circuit explanation> In FIG. 43A, only a capacitor 2603 is provided at the intersection of the wiring as a touch sensor. Although the configuration of a passive touch sensor has been shown, an active touch sensor having a transistor and a capacitor may also be used. One of the sensor circuits included in the active type touch sensor may be a An example is shown in Figure 44.

[0394] The sensor circuit shown in FIG. 44 includes a capacitor 2603, a transistor 2611, and a transistor 2612 and a transistor 2613.

[0395] A signal G2 is applied to the gate of the transistor 2613, and a voltage is applied to either the source or drain of the transistor 2613. A voltage VRES is applied to one electrode of a capacitor 2603 and a transistor 2611. The transistor 2611 has a source and a drain that are electrically connected to each other. One of the source and drain of the transistor 2612 is electrically connected to the other of the source and drain of the transistor 2612. A signal G1 is applied to the gate of the transistor 2612, and a signal S is applied to the source or The other electrode of the drain is electrically connected to the wiring ML. The other electrode of the capacitor 2603 is connected to a voltage VS S is given.

[0396] Next, the operation of the sensor circuit shown in FIG. 44 will be described. First, the signal G2 is When a potential is applied to turn on the transistor 2613, the gate of the transistor 2611 is turned on. A potential corresponding to the voltage VRES is applied to the node n to which the input is connected. When a potential that turns off the transistor 2613 is applied, the potential of the node n is Retained.

[0397] Next, the mutual capacitance of the capacitor 2603 changes due to the proximity or contact of a detection object such as a finger. Accordingly, the potential of the node n changes from VRES.

[0398] The read operation applies a potential to the signal G1 that turns on the transistor 2612. A current flows through the transistor 2611 in accordance with the potential of the node n, that is, a current flows through the wiring ML. By detecting this current, the proximity or contact of the object to be detected can be detected. This can be done.

[0399] The transistors 2611, 2612, and 2613 are In particular, the transistor 2613 may be used. By using the transistor shown in the embodiment, the potential of the node n can be maintained for a long period of time. This allows node n to be supplied with VRES again (refresh operation). This can reduce the frequency of such operations.

[0400] (Embodiment 5) In this embodiment, a display method that can be used by a display device according to one embodiment of the present invention will be described with reference to FIGS. The following description will be given with reference to Figures 45 to 48.

[0401] Note that the display device of one embodiment of the present invention includes an information processing unit, a calculation unit, a storage unit, a display unit, and an input unit. It may also have a force portion.

[0402] In addition, in the display device according to one embodiment of the present invention, the same image (still image) is continuously displayed. In this case, by reducing the number of times the same image signal is written (also called refreshing), This allows for a reduction in power consumption. The frequency of refreshing can be set as the refresh rate. The refresh rate is also called the scanning frequency or vertical synchronization frequency. The present invention describes a display device that reduces image distortion and reduces eye fatigue.

[0403] There are two types of eye fatigue: nervous fatigue and muscular fatigue. Staring at the light-emitting or flashing screen of the device for a long period of time can cause the brightness to irritate the retina, nerves, and brain. Muscular fatigue is caused by the ciliary muscles, which are used to adjust the focus. It tires the flesh by overworking it.

[0404] FIG. 45(A) is a schematic diagram showing a display of a conventional display device. As shown in FIG. In contrast, conventional display devices rewrite images 60 times per second. Looking at a screen for a long time can stimulate the retina, nerves, and brain of the user's eyes, causing eye fatigue. There was a risk of being woken up.

[0405] In the display device of one embodiment of the present invention, a transistor using an oxide semiconductor is provided in a pixel portion of the display device. A transistor using CAAC-OS, for example, is applied. The off-state current of the transistor is extremely small. Therefore, even if the refresh rate of the display device is lowered, the display This makes it possible to maintain the brightness of the display device.

[0406] In other words, as shown in FIG. 45(B), for example, an image can be rewritten once every five seconds. This allows the user to watch the same image for as long as possible, and the screen that is visible to the user is This reduces the stimulation of the retina, nerves, and brain of the user's eyes, and improves the nerve function. System fatigue is reduced.

[0407] Also, as shown in FIG. 46(A), when the size of one pixel is large (for example, when the resolution is 15 If the resolution is less than 100 ppi, the characters displayed on the display device will be blurred. When you look at blurry, blurry text for a long time, your ciliary muscles work constantly to bring the image into focus. Even if you are using your eyesight, you may still have difficulty focusing, which can cause strain on your eyes. There is a risk that this will happen.

[0408] In contrast, as shown in FIG. 46B, in a display device according to one embodiment of the present invention, The small size of the image allows for high-definition display, resulting in a detailed and smooth display. This allows the ciliary muscles to focus more easily, reducing fatigue in the user's muscular system. The display resolution should be 150 ppi or more, preferably 200 ppi or more. More preferably, the value is set to 300 ppi or more to effectively alleviate fatigue in the user's muscular system. can be reduced.

[0409] Methods for quantitatively measuring eye fatigue are currently being considered. The value index is the Critical Flicker Frequency (CFF). In addition, the evaluation index of muscle fatigue is known as Known examples of such factors include adjustment time and adjustment near point distance.

[0410] Other methods for assessing eye fatigue include electroencephalography, thermography, and blink count. Measurement of eye movement, tear volume evaluation, pupil contraction reaction rate evaluation, questionnaire to investigate subjective symptoms There are also other projects.

[0411] For example, the driving method of the display device according to one embodiment of the present invention can be evaluated by the above-mentioned various methods. This can be done.

[0412] <Display method of the display device> Here, a display method of a display device of one embodiment of the present invention is described with reference to FIG.

[0413] [Image information display example] The following is an example of moving and displaying an image containing two different image information. .

[0414] FIG. 47A shows a window 451 on a display unit 450 and 4 shows an example in which a first image 452a, which is a still image, is displayed.

[0415] At this time, it is preferable that the display is performed at the first refresh rate. The refresh rate is 1.16 x 10 -5 Hz (approximately once a day) or more Hz or less, or 2.78 x 10 -4 Hz (approximately once per hour) to 0.5 Hz , or 1.67 × 10 -2 Hz (approximately once per minute) or more and 0.1 Hz or less. This can be done.

[0416] In this way, the first refresh rate is set to a very small value, and the screen rewriting Reducing the frequency allows for a virtually flicker-free display, making it more effective to use. This can reduce eye fatigue for the user.

[0417] The window 451 is used to execute, for example, an image display application software. The display includes a display area for displaying an image.

[0418] Also at the bottom of window 451 are buttons for switching the display to different image information. The user selects the button 453 to move the image. A command to operate the display device can be given to the information processor of the display device.

[0419] The operation method of the user may be set according to the input means. When a touch panel is used that is provided over the display unit 450, the touch panel is operated by a finger, a stylus, etc. You can input the image by touching the button 453 or by using a gesture such as sliding the image. When using gesture input or voice input, The button 453 does not have to be displayed.

[0420] When the information processing unit of the display device receives a command to move the image, the image is displayed in the window 451. The displayed image begins to move (FIG. 47(B)).

[0421] If the display is performed at the first refresh rate at the time of FIG. 47(A), Before the image movement, it is preferable to change the refresh rate to a second refresh rate. The second refresh rate is a value required for displaying moving images. For example, The second refresh rate is between 30 Hz and 960 Hz, preferably between 60 Hz and 960 Hz. 60Hz or less, more preferably 75Hz to 960Hz, more preferably 120Hz and 960 Hz or less, more preferably 240 Hz or more and 960 Hz or less. .

[0422] Setting the second refresh rate to a value higher than the first refresh rate. This allows moving images to be displayed more smoothly and naturally. This reduces eye fatigue by suppressing the visibility of flickering (also known as flicker) to the user. can be reduced.

[0423] At this time, the images displayed in the window 451 are the first image 452a and the next image The resulting image is a combined image with the first image 452b to be combined. A portion of the image is displayed so that the merged image moves in one direction (here, to the left).

[0424] Also, as the combined image moves, the brightness of the image displayed in the window 451 changes for the first time. The luminance gradually decreases compared to the luminance at the time of the light emission (at the time of FIG. 47(A)).

[0425] FIG. 47C shows the time when the image displayed in the window 451 reaches a predetermined coordinate. Therefore, at this point, the brightness of the image displayed in the window 451 is the highest. low.

[0426] In FIG. 47C, the first image 452a and the second image 452b are located at predetermined coordinates. Each of the coordinates is displayed half at a time, but this is not limited to this and the user can freely It is preferable to make it configurable.

[0427] For example, the ratio of the distance from the initial coordinates to the distance from the final coordinates of the image is A coordinate greater than 0 and less than 1 may be set as the predetermined coordinate.

[0428] In addition, the brightness when the image reaches a specified coordinate can also be freely set by the user. For example, the ratio of the brightness when the image reaches a predetermined coordinate to the initial brightness is preferably 0. or more and less than 1, preferably 0 to 0.8, more preferably 0 to 0.5, etc. Just do that.

[0429] Next, within the window 451, the combined image moves and the brightness increases step by step. (Figure 47(D)

[0430] FIG. 47(E) shows the point when the coordinates of the combined image reach their final coordinates. Within the dot 451, only the second image 452b is displayed with a brightness equal to the initial brightness. do.

[0431] After the image movement is complete, the refresh rate is changed from the second refresh rate to the It is preferable to change the refresh rate to the first refresh rate.

[0432] By displaying the image in this way, even if the user tries to follow the movement of the image with his / her eyes, the image Since the brightness of the display is reduced, eye fatigue of the user can be reduced. By using such a driving method, a display that is easy on the eyes can be realized.

[0433] [Example of document information display] Next, let's look at an example where you scroll through document information that is larger than the display window. We will explain about this.

[0434] FIG. 48A shows a window 455 on a display unit 450 and 4 shows an example in which a part of document information 456, which is a still image, is displayed.

[0435] At this time, it is preferable that the display is performed at the above-mentioned first refresh rate.

[0436] The window 455 is, for example, a document display application software, a document creation application software, etc. It includes a display area that is displayed by executing application software, etc., and displays document information.

[0437] The document information 456 is a document whose image size is larger vertically than the display area of ​​the window 455. Therefore, only a part of the area is displayed in the window 455. As shown in FIG. 48(A), a window 455 shows which area of ​​document information 456 is displayed. The display may include a scroll bar 457 that indicates whether the

[0438] A command to move an image (also called a scroll command here) is input to the display device via the input unit. When the command is given to the document information 456, the document information 456 starts to move (FIG. 48(B)). The brightness of the image being displayed decreases in stages.

[0439] If the display is performed at the first refresh rate at the time of FIG. 48(A), Before the document information 456 is moved, the refresh rate is changed to the second refresh rate. It is preferable to do so.

[0440] Here, not only the brightness of the image displayed in the window 455 but also the brightness of the image displayed on the display unit 450 Illustrated is a decrease in brightness across the displayed image.

[0441] FIG. 48(C) shows the time when the coordinates of the document information 456 reach the predetermined coordinates. At this time, the brightness of the entire image displayed on display unit 450 becomes the lowest.

[0442] Next, document information 456 is displayed while moving within window 455 (see FIG. 48). At this time, the brightness of the entire image displayed on the display unit 450 increases stepwise.

[0443] FIG. 48(E) shows the point in time when the coordinates of the document information 456 reach the final coordinates. In the document 455, an area different from the initially displayed area of ​​the document information 456 is displayed. It is displayed with a brightness equal to the

[0444] After the movement of the document information 456 is completed, the refresh rate is changed to the first refresh rate. It is preferable to change the format to a scalable format.

[0445] By displaying the image in this way, even if the user tries to follow the movement of the image with his / her eyes, the image Since the brightness of the display is reduced, eye fatigue of the user can be reduced. By using such a driving method, a display that is easy on the eyes can be realized.

[0446] In particular, high contrast displays such as document information can cause eye fatigue. Therefore, it is more preferable to apply such a driving method to displaying document information.

[0447] (Embodiment 6) In this embodiment mode, the appearance and display of a display device having the pixels described in the above embodiment mode will be described. An example of an electronic device equipped with the device will be described.

[0448] <Appearance of the display device> FIG. 49(A) is a perspective view showing an example of the appearance of a display device. The device is composed of a panel 1601, a controller, a power supply circuit, an image processing circuit, an image memory, and a CP. The panel 160 includes a circuit board 1602 on which a U or the like is provided, and a connection portion 1603. 1 is a pixel portion 1604 having a plurality of pixels and a driver circuit for selecting the plurality of pixels for each row. 1605, and a driver circuit 1606 for controlling the input of data voltages to the pixels in a selected row. has.

[0449] Various signals and a power supply potential are transmitted from the circuit board 1602 to the panel via the connection portion 1603. The connection part 1603 is connected to an FPC (Flexible Printer The FPC with the chip mounted on it is called CO This is called F tape, and the use of COF tape allows for higher density mounting in a smaller area. In addition, when a COF tape is used for the connection portion 1603, A part of the circuit, or a part of the driver circuit 1605 or the driver circuit 1606 of the panel 1601 The above is formed on a separately prepared chip and then the COF (Chip On Film) method is used. The chip may be connected to the COF tape in advance.

[0450] FIG. 49(B) is a perspective view showing an example of the appearance of a display device using the COF tape 1607. As shown in.

[0451] The chip 1608 is a semiconductor bare chip (such as an IC or LSI) having terminals such as bumps on its surface. In addition, CR components can also be mounted on the COF tape 1607, and the circuit board 1602 The wiring pattern of the flexible board corresponds to the terminals of the chip to be mounted. The chip 1608 is bonded to a substrate having a wiring pattern by a bonder device or the like. The chip is positioned and placed on a flexible substrate and then mounted by thermocompression bonding.

[0452] FIG. 49(B) shows an example of one COF tape 1607 on which one chip 1608 is mounted. However, it is not particularly limited. A single COF tape 1607 may have multiple rows of chips on one or both sides. However, to reduce costs, it is necessary to reduce the number of chips to be mounted. It is preferable to have a single row, and more preferably, to have only one.

[0453] <Examples of electronic device configurations> Next, an electronic device equipped with a display device will be described.

[0454] A display device according to one aspect of the present invention is a display device, a notebook personal computer, a recording medium, Image playback devices equipped with a DVD player (typically DVD: Digital Versatile Digital Used for devices that play recording media such as ISC and have a display that can display the images. In addition, an electronic device in which the display device according to one embodiment of the present invention can be used As containers, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, digital Cameras such as still cameras, goggle-type displays (head-mounted displays) , navigation systems, audio playback devices (car audio, digital audio players) Copiers, fax machines, printers, printer-combination machines, automated teller machines, Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 50. .

[0455] FIG. 50A shows a display device, which includes a housing 5001, a display unit 5002, a support stand 5003, etc. The display device according to one embodiment of the present invention can be used for the display portion 5002. Display devices include all information displays, such as those for personal computers, TV broadcast reception, and advertisement displays. A display device for displaying information is included.

[0456] FIG. 50B shows a portable information terminal, which includes a housing 5101, a display unit 5102, and operation keys 5103. The display device according to one embodiment of the present invention can be used for the display portion 5102.

[0457] FIG. 50C shows a display device having a curved housing 5701, a display portion 5702, etc. By using a flexible substrate in the display device according to one embodiment of the present invention, a curved case can be easily formed. The display device can be used for a display portion 5702 supported by a body 5701. It is therefore possible to provide a display device that is compact, lightweight, and easy to use.

[0458] FIG. 50D shows a portable game machine. The portable game machine includes a housing 5301, a housing 5302, a display portion 5303, A display unit 5304, a microphone 5305, a speaker 5306, an operation key 5307, a star The display device according to one embodiment of the present invention includes the display portion 5303 or the display The display portion 5303 or the display portion 5304 may be used as one of the display devices of the present invention. By using the display device according to the embodiment, the user experience is excellent and deterioration of quality is unlikely to occur. It is possible to provide a portable game machine that can be used with a portable game machine shown in FIG. The display device has two display areas 5303 and 5304. The number of display units is not limited to this.

[0459] FIG. 50E shows an electronic book having a housing 5601, a display portion 5602, and the like. The display device according to the embodiment can be used for the display portion 5602. By using a substrate, the display device can be made flexible, making it possible to display a flexible and To provide a light and easy-to-use e-book.

[0460] FIG. 50F shows a mobile phone. A housing 5901 includes a display unit 5902, a microphone 5907, and a speaker. Speaker 5904, camera 5903, external connection part 5906, and operation button 5905 are provided. The display device according to one embodiment of the present invention can be used for the display portion 5902. In addition, when the display device according to one embodiment of the present invention is formed on a flexible substrate, The display device can be applied to a display unit 5902 having a curved surface as shown in FIG. do.

[0461] (Additional notes regarding the present specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0462] <Additional Notes on One Aspect of the Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to form one embodiment of the present invention. In addition, when multiple configuration examples are shown in one embodiment, The configuration examples can be appropriately combined with each other.

[0463] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or even a part of it) described in the form, and / or one or more other The contents (or a part of the contents) described in the embodiment may be applied, combined, or replaced. It is possible to change the settings, etc.

[0464] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to what is stated or what is stated using the text in the specification.

[0465] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment, and / or one or The drawings (or a part thereof) described in a plurality of different embodiments may be combined. More diagrams can be constructed.

[0466] Although one aspect of the present invention has been described in each embodiment, the present invention is not limited thereto. For example, in the second embodiment of the present invention, the transistor 102, etc.

[0023] In the case where a channel formation region of the transistor includes an oxide semiconductor or silicon, However, one aspect of the present invention is not limited thereto. Accordingly, various transistors and channel formation regions of the transistors according to one embodiment of the present invention , or the source / drain regions of the transistors may comprise various semiconductors. For example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, silicon, aluminum gallium arsenide, indium phosphide, gallium nitride, or organic semiconductors. The embodiment may have at least one of the above.

[0467] <Notes on the description explaining the drawings> In this specification, the words "above" and "below" that indicate the positional relationship between components are used. are used for convenience in describing the drawings. Therefore, the terms indicating the arrangement may be changed as appropriate depending on the direction in which the arrangement is depicted. The above description is not limited to the above, and may be rephrased appropriately depending on the situation.

[0468] In addition, the terms "above" and "below" refer to the positional relationship of a component directly above or below and directly connected to it. For example, if the expression is "electrode B on insulating layer A," It is not necessary that the electrode B is formed directly on the insulating layer A. This does not exclude the inclusion of other components in between.

[0469] In the present specification and the like, in the block diagrams, components are classified by function and are independent of each other. However, in actual circuits, the components are divided into blocks according to their functions. In some cases, it is difficult to separate the circuits, and multiple functions are involved in one circuit, or multiple circuits are involved. Therefore, the blocks in the block diagram may be different from those described in the specification. The present invention is not limited to the above-described components, and may be rephrased appropriately depending on the situation.

[0470] In addition, in the drawings, the size, layer thickness, and area are shown arbitrarily for convenience of explanation. The drawings are not necessarily limited to the scale shown. The drawings are merely schematic illustrations for the purpose of illustration only, and are not limited to the shapes or values ​​shown in the drawings. For example, signal, voltage, or current variations due to noise, or timing errors The variations may include variations in signals, voltages, or currents.

[0471] In addition, in the drawings, in top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0472] <Notes on possible alternative descriptions> In the present specification and the like, when describing the connection relationship of a transistor, is referred to as "either the source or drain" (or the first electrode, or the first terminal), The other of the source and drain is called the "other of the source or drain" (or the second electrode, or the first The source and drain of a transistor are called two terminals. This is because it varies depending on the structure or operating conditions. The name may be changed to source (drain) terminal, source (drain) electrode, etc., depending on the situation. can be appropriately rephrased.

[0473] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as a single unit.

[0474] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. For example, the reference potential is the ground voltage (earth potential). If we define the voltage as the potential, the ground potential does not necessarily mean 0V. Note that the potential is relative, and the arrangement may differ depending on the reference potential. The potential applied to the wires may be changed.

[0475] In this specification, the terms "film" and "layer" may be used depending on the circumstances. For example, the term "conductive layer" can be used interchangeably with "conductive layer" depending on the application. Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term "insulating layer" to the term "insulating layer."

[0476] In this specification, one pixel is provided with two transistors and one capacitance element. Although the circuit configuration shown in FIG. 1 has a 2T-1C structure, the present embodiment is not limited to this. A circuit configuration in which each pixel has three or more transistors and three or more capacitor elements. Alternatively, separate wiring may be formed to provide various circuit configurations.

[0477] <Notes on definitions of terms> The following provides definitions of terms not mentioned in the above embodiments.

[0478] [About Switch] In this specification, a switch refers to a device that is in a conductive state (on state) or a non-conductive state (off state). A switch that is in a "switchable state" and has the function of controlling whether or not current flows. A switch is a device that has the function of selecting and switching the path through which a current flows.

[0479] As an example, an electrical switch or a mechanical switch can be used. In other words, the switch is not limited to a specific one as long as it can control the current.

[0480] An example of an electrical switch is a transistor (e.g., a bipolar transistor, M OS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) diode , MIS (Metal Insulator Semiconductor) diode diode-connected transistors, or logic circuits that combine these There is.

[0481] When a transistor is used as a switch, the "conduction state" of the transistor is This refers to a state in which the source and drain of a transistor can be considered to be electrically shorted. The "non-conducting state" of a transistor is when the source and drain of the transistor are electrically isolated. In addition, when a transistor is operated simply as a switch, In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0482] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. The switch has an electrode that can be mechanically moved, and the movement of the electrode causes Thus, the device operates by controlling conduction and non-conduction.

[0483] [Channel length] In this specification and the like, the channel length is, for example, the length of a semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The distance between the source and drain in the overlapping region, or the region where the channel is formed This refers to.

[0484] In addition, the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as the length of any one of the regions in which the channel is formed. The value may be a maximum, minimum or average value.

[0485] [About channel width] In this specification, the channel width is, for example, the width of a semiconductor (or a transistor) when it is in an on-state. The area where the gate electrode overlaps with the gate electrode (the part of the semiconductor through which current flows when the This refers to the length of the portion where the source and drain face each other in the region where the source and drain are formed.

[0486] In addition, the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a transistor may not be fixed to a single value. Therefore, in this specification, the channel width refers to any one of the widths in the region where the channel is formed. The value, maximum, minimum or average value.

[0487] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may vary. The effective channel width (hereinafter referred to as the effective channel width) shown in the top view of the transistor The channel width (hereinafter referred to as the apparent channel width) may be different. For example, In a transistor having a three-dimensional structure, the effective channel width is The effect of the channel width becomes larger than the apparent channel width shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. In that case, The effective channel width of the channel is smaller than the apparent channel width. The larger the size, the larger the

[0488] By the way, in a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. Unless k is precisely known, it is difficult to accurately measure the effective channel width.

[0489] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The width of the channel is called the surrounded channel width (SCW). In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when the term "channel width" is used, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width, etc., can be determined by acquiring cross-sectional TEM images and analyzing those images. A value can be determined.

[0490] In addition, the field effect mobility of the transistor and the current value per channel width are calculated. In some cases, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0491] [About pixels] In this specification, a pixel refers to, for example, one element whose brightness can be controlled. Therefore, as an example, one pixel refers to one color element, and one color element Therefore, the brightness is expressed by the color components R (red), G (green), and B (blue). In the case of a color display device, the smallest unit of an image is a triplet of R, G, and B pixels. It is assumed that it is composed of elements.

[0492] The color elements are not limited to three colors, and may be more than three. For example, RGBW (W is white) , and RGB with the addition of yellow, cyan, and magenta.

[0493] [Display element] In this specification, a display element such as the light-emitting element 104 is an element that displays an electric or magnetic light. The display medium has a change in contrast, brightness, reflectance, transmittance, etc. Examples of display elements include EL (electroluminescence) elements and LED chips ( White LED chip, red LED chip, green LED chip, blue LED chip, etc.), Transistors (transistors that emit light according to the current), electron emitters, carbon nanotubes Display elements using ink jet printers, liquid crystal elements, electronic ink, electrowetting elements, electrophoresis Elements, plasma displays (PDP), MEMS (microelectromechanical Display elements using a Grating Light Valve (GLV), digital Digital Micromirror Device (DMD), Digital Micro Shutter (DMS), MIRASOL(R), an IMOD (Interference Modulation) element Shutter-type MEMS display element, optical interference-type MEMS display element, piezoelectric ceramic Examples include organic EL display, carbon nanotubes, or quantum dots. An example of a display device using an electron-emitting element is an EL display. An example of the display device used is a field emission display (FED) or S ED type flat panel display (SED: Surface-conduction Electrodes) Display devices using liquid crystal elements. One example is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). (a) Reflective LCD, Direct-view LCD, Projection LCD, etc. One of the display devices using electronic ink, electronic liquid powder, or electrophoretic elements is An example of a display device that uses quantum dots in each pixel is electronic paper. Examples of quantum dot displays include quantum dot displays. The use of quantum dots allows for high color purity. It is possible to display images using semi-transmissive and reflective LCD displays. In this case, a part or the whole of the pixel electrode should function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This can further reduce power consumption. When using an LED chip, graphene is placed under the electrodes of the LED chip and the nitride semiconductor. Graphene or graphite can be arranged in layers. In this way, by providing graphene or graphite, In addition, it is possible to easily form a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal. Furthermore, a p-type GaN semiconductor layer having crystals can be formed on top of it to form an LED chip. In addition, graphene and graphite can be used to form n-type GaN with crystals. An AlN layer may be provided between the GaN semiconductor layer and the GaN semiconductor layer. The conductive layer may be formed by MOCVD. However, by providing graphene, the LE The GaN semiconductor layer of the M chip can also be formed by sputtering. In display elements using EMS (microelectromechanical systems), The space in which the display element is sealed (for example, the element substrate on which the display element is disposed and the space between the element substrate and the display element) A desiccant may be disposed between the substrate and the opposing substrate. By placing the MEMS in a place where moisture can cause it to become difficult to move or to deteriorate. This can prevent the above from happening.

[0494] [About connection] In this specification, "A and B are connected" means that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. Being connected means that there is an object between A and B that has some electrical effect. A means a device that enables the transmission and reception of electrical signals between A and B.

[0495] The source (or first terminal, etc.) of the transistor is connected to X through (or without) Z1. and the drain (or second terminal, etc.) of the transistor is electrically connected to It may be electrically connected to Y through (or without) the source of the transistor (or is the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to part of Z2. When a part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0496] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc., of the transistor are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. "The source of the transistor is electrically connected to the (or the first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor, The transistor's drain (or second terminal, etc.), and Y are electrically connected in that order. "X is connected to the source ( or the first terminal, etc.) and the drain (or the second terminal, etc.) X is the source (or first terminal, etc.) of the transistor, and The second terminal (or terminal 2, etc.), Y, is provided in this connection order. Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal.

[0497] Or, as another way of expressing it, for example, "the source (or first terminal, etc.) of a transistor" ) is electrically connected to X through at least a first connection path, and the first connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second The first connection path is a path via Z1, and the second connection path is a path between the The drain (or second terminal, etc.) of the transistor is connected to the Y, the third connection path does not have the second connection path, and The third connection path is a path via Z2." or " The source (or first terminal, etc.) of the transistor is connected to the , electrically connected to X via Z1, and the first connection path has a second connection path the second connection path has a connection path passing through a transistor, The drain (or second terminal, etc.) of and the third connection path does not include the second connection path. "The source (or first terminal) of the transistor is etc.) is electrically connected to X through Z1 by at least a first electrical path; The first electrical path does not have a second electrical path, and the second electrical path is The source (or first terminal, etc.) of a transistor is connected to the drain (or third terminal, etc.) of a transistor. 2) and the drain (or second terminal, etc.) of the transistor. ) is electrically connected to Y through Z2 by at least a third electrical path, The third electrical path does not have a fourth electrical path, and the fourth electrical path is a The drain (or second terminal, etc.) of a transistor is connected to the source (or first terminal, etc.) of a transistor. The electrical path to the terminal of the By using the current method, the connection paths in the circuit configuration are defined, and the transistor Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of The technical scope can be determined based on the above.

[0498] Note that these expression methods are merely examples, and the present invention is not limited to these expression methods. , Y, Z1, and Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.). [Explanation of symbols]

[0499] BGE1 Back gate electrode BGE2 Back gate electrode BGE4 Back gate electrode BGE5 Back gate electrode BGE6 Back gate electrode BGE7 Back gate electrode CG1 opening CG2 opening CG4 opening CG6 opening CG7 opening CH1 opening CH2 opening CH3 opening CH4 opening CH5 opening DE1 Drain electrode DE2 Drain electrode DE3 Drain electrode DE4 Drain electrode DE5 Drain electrode DE6 Drain electrode DE7 Drain electrode DE8 Drain electrode DL1 Data line DLn Data line G1 signal G2 signal GE1 Gate electrode GE2 Gate electrode GE3 Gate electrode GE4 Gate electrode GE5 Gate electrode GE6 Gate electrode GE7 Gate electrode GE8 Gate electrode GL1 Gate line GLm Gate line OS1 Oxide semiconductor film OS2 Oxide semiconductor film OS3 Oxide semiconductor film OS4 Oxide semiconductor film OS5 Oxide semiconductor film OS6 Oxide semiconductor film OS7 Oxide semiconductor film OS8 Oxide semiconductor film P11 Light Emitting Period P12 Initialization period P13 Initialization completion period P14 Threshold voltage correction period P15 Data voltage input period P16 Data voltage input completion period P21 Light Emitting Period P22 Initialization period P23 Initialization completion period P24 Threshold voltage correction period P25 Data voltage input period P26 Data voltage input completion period PL1 current supply line PLm current supply line SE1 source electrode SE2 source electrode SE3 source electrode SE4 Source Electrode SE5 Source Electrode SE6 Source Electrode SE7 Source Electrode SE8 Source Electrode TA1 Transistor TA2 transistor TA3 Transistor TA4 Transistor TB1 Transistor TB2 Transistor TC1 Transistor TD1 Transistor 30 Substrate 31 Oxide semiconductor film 32 Oxide semiconductor film 33 Oxide Semiconductor Film 34 Insulating film 35 Insulating film 35a Insulating film 35b Insulating film 36 Insulating Film 70 Transistor 71 Transistor 72 Substrate 73 Conductive Film 73a Conductive film 73b Conductive film 74 Insulating Film 75 Semiconductor Film 76 Insulating Film 77a Conductive film 77b Conductive film 78 Insulating Film 79 Insulating Film 80 Conductive Film 81 Conductive Film 82 Channel formation region 83 LDD area 84 Impurity region 85 Conductive Film 86 Semiconductor Film 87a Conductive film 87b Conductive film 88 Conductive Film 89 Conductive Film 90 Channel formation region 91 Impurity region 93 Aperture 94 Aperture 95 Aperture 96 Aperture 100 pixels 100A pixels 100B pixels 100C pixels 100C_B pixels 100C_G pixels 100C_R pixels 100D pixels 100E pixels 100F pixels 100G pixels 100H pixels 101 Switch 101A Transistor 101B Transistor 101C Transistor 102 Transistor 102B Transistor 102D Transistor 102E Transistor 102F Transistor 102G Transistor 102R Transistor 103 Capacitor 104 Light emitting element 105 Capacitor 106 Switch 106_1 Switch 106_2 Switch 106A Transistor 106B Switch 106C Switch 106D Switch 106E Switch 107 Switch 107A Transistor 108 Switch 108A Transistor 109A Circuit 110 Gate line side driving circuit 120 Data line side driving circuit 130 Current supply line control circuit 133 Resistance element 140 Pixel section 301 Substrate 303 Insulating film 305 Gate electrode 307 Insulating Film 309 Semiconductor Film 311 Electrode 313 Insulating film 315 Insulating Film 317 Insulating Film 319 Electrode 323 Light-emitting layer 325 Electrode 360 Connection electrode 380 Anisotropic Conductive Film 400 display device 401 Substrate 405 Substrate 408 FPC 410 Element Layer 411 Element Layer 412 Adhesive layer 418 Adhesive layer 420 Insulating film 432 Sealing layer 440 Insulating film 450 Display section 451 Window 452a Image 452b Image 453 Button 455 Window 456 Document Information 457 Scrollbar 462 Substrate 463 Peeling layer 464 Peeling adhesive 466 Temporary Support Substrate 468 Laser Light 1601 Panel 1602 Circuit Board 1603 Connection 1604 Pixel section 1605 Drive circuit 1606 Drive circuit 1607 COF Tape 1608 Chip 2000 Touch Panel 2001 Touch Panel 2501 Display device 2502t transistor 2503c Capacitive element 2503t Transistor 2504 Gate line driver circuit 2505 pixels 2509 FPC 2510 Board 2510a Insulating layer 2510b flexible substrate 2510c adhesive layer 2511 Wiring 2519 Terminal 2521 Insulating layer 2528 Bulkhead 2550 EL element 2560 Sealing layer 2567 Colored layer 2568 Light blocking layer 2569 Anti-reflection layer 2570 PCB 2570a Insulating layer 2570b flexible substrate 2570c adhesive layer 2580 Light Emitting Module 2590 Board 2591 Electrode 2592 Electrode 2593 Insulation layer 2594 Wiring 2595 Touch Sensor 2597 Adhesive layer 2598 Wiring 2599 Connection Layer 2601 Pulse voltage output circuit 2602 Current detection circuit 2603 Capacity 2611 Transistor 2612 Transistor 2613 Transistor 2621 Electrode 2622 Electrode 5001 Case 5002 Display section 5003 Support stand 5101 Case 5102 Display section 5103 Operation key 5301 Case 5302 Case 5303 Display section 5304 Display section 5305 Microphone 5306 Speaker 5307 Operation key 5308 Stylus 5601 Case 5602 Display section 5701 Case 5702 Display section 5901 Case 5902 Display section 5903 Camera 5904 Speaker 5905 Button 5906 External connection part 5907 Mike

Claims

1. a pixel having a first switch, a transistor, a capacitor, and a light emitting element; a second switch provided outside the pixel, a first electrode of the capacitor electrically connected to a gate of the transistor and to one terminal of the first switch; a second electrode of the capacitor is electrically connected to one of the source and the drain of the transistor and a first electrode of the light-emitting element; the other terminal of the first switch is electrically connected to a data line; the other of the source and the drain of the transistor is electrically connected to one terminal of the second switch; the other terminal of the second switch is electrically connected to a current supply line; a first period, a second period after the first period, a third period after the second period, and a fourth period after the third period; during the first period, the first switch is off and the second switch is on; during the second period, the first switch is on and the second switch is on; during the third period, the first switch is on and the second switch is off; The display device, in the fourth period, the first switch is off and the second switch is on.

2. a pixel having a first switch, a transistor, a capacitor, and a light emitting element; a second switch provided outside the pixel, a first electrode of the capacitor electrically connected to a gate of the transistor and to one terminal of the first switch; a second electrode of the capacitor is electrically connected to one of the source and the drain of the transistor and a first electrode of the light-emitting element; the other terminal of the first switch is electrically connected to a data line; the other of the source and the drain of the transistor is electrically connected to one terminal of the second switch; the other terminal of the second switch is electrically connected to a current supply line; the transistor includes an oxide semiconductor film in a channel formation region, a first period, a second period after the first period, a third period after the second period, and a fourth period after the third period; during the first period, the first switch is off and the second switch is on; during the second period, the first switch is on and the second switch is on; during the third period, the first switch is on and the second switch is off; The display device, in the fourth period, the first switch is off and the second switch is on.

Images