Shift register circuit, method for driving the same, and gate driving circuit, and display apparatus

Abstract

SOLUTION: A shift register circuit (RS) includes a noise elimination control sub-circuit (20) and a noise elimination sub-circuit (30), wherein the noise elimination control sub-circuit (20) is configured to generate an alternating voltage signal from voltage of a first voltage terminal (VSS) and a signal from a second clock signal terminal (CB1) in response to a signal from a first clock signal terminal (CK1), and rectify the alternating voltage signal and then output the signal to a first noise elimination control node (PD-ox), so that voltage of the first noise elimination control node (PD-ox) is maintained to be voltage that enables the noise elimination sub-circuit (30) to be started, and the noise elimination sub-circuit (30) is configured to continuously be started under the control of the voltage of the first noise elimination control node (PD-ox), so as to eliminate noise from a scanning signal output terminal (Oput).EFFECT: A shift register circuit is provided which solves the problem that screen display becomes unstable.SELECTED DRAWING: Figure 11

Description

[Technical field]

[0001] This application claims priority from a Chinese patent application bearing application number 202010356184.0, filed on April 29, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register circuit and a control method thereof, a gate driving circuit, and a display device. [Background technology]

[0003] With the advancement of display technology, semiconductor device technology, which is the core of display devices, has also made great progress. Organic Light Emitting Diode (OLED) is a type of current light emitting device that is capable of self-emitting light, has fast response, wide viewing angle, and can be fabricated on flexible substrates, and is therefore increasingly being applied to high-performance display devices. Summary of the Invention [Means for solving the problem]

[0004] In a first aspect, a shift register circuit is provided. The shift register circuit includes a noise cancellation control subcircuit and a noise cancellation subcircuit, wherein the noise cancellation control subcircuit is coupled to a first voltage terminal, a first clock signal terminal, a second clock signal terminal, and a first noise cancellation control node. In response to a signal at the first clock signal terminal, the noise cancellation control subcircuit generates an alternating voltage signal from the voltage at the first voltage terminal and the signal at the second clock signal terminal, rectifies the alternating voltage signal, and outputs a signal to the first noise cancellation control node, thereby maintaining the voltage at the first noise cancellation control node at a voltage that turns on the noise cancellation subcircuit. The noise cancellation subcircuit is coupled to the first noise cancellation control node and a scan signal output terminal. In response to the voltage at the first noise cancellation control node being a voltage that turns on the noise cancellation subcircuit, the noise cancellation subcircuit is configured to perform noise cancellation on the scan signal output terminal.

[0005] In some embodiments, the noise reduction control subcircuit includes a first on control subcircuit and a second on control subcircuit, where the first on control subcircuit is coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and a second noise reduction control node, and is configured to, in response to a signal at the first clock signal terminal, periodically output a voltage at the first voltage terminal to the second noise reduction control node and periodically adjust a voltage at the second noise reduction control node based on the signal at the second clock signal terminal, thereby causing the second noise reduction control node to provide an alternating voltage signal, and the second on control subcircuit is coupled to the first noise reduction control node and the second noise reduction control node, and is configured to, in response to the alternating voltage signal provided by the second noise reduction control node, rectify the alternating voltage signal and output the signal to the first noise reduction control node.

[0006] In some embodiments, the first on control subcircuit includes a first transistor and a first capacitor, and / or the second on control subcircuit includes a second transistor and a second capacitor. A control electrode of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the first voltage terminal, and a second electrode of the first transistor is coupled to a second noise reduction control node. A first terminal of the first capacitor is coupled to a second clock signal terminal, and a second terminal of the first capacitor is coupled to a second noise reduction control node. A control electrode of the second transistor is coupled to the second noise reduction control node, a first electrode of the second transistor is coupled to the first noise reduction control node, and a second electrode of the second transistor is coupled to the second noise reduction control node. A first terminal of the second capacitor is coupled to the first signal terminal, and a second terminal of the second capacitor is coupled to the first noise reduction control node.

[0007] In some embodiments, the noise cancellation control sub-circuit is further coupled to the cascade signal output terminal and the second signal terminal, and is further configured to control the noise cancellation sub-circuit to be turned off based on a signal at the second signal terminal in response to a voltage at the cascade signal output terminal.

[0008] In some embodiments, the noise reduction control subcircuit includes a first on control subcircuit, a second on control subcircuit, and an off control unit. The first on control subcircuit is coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and a second noise reduction control node, and is configured to periodically output a voltage of the first voltage terminal to the second noise reduction control node in response to a signal of the first clock signal terminal, and periodically adjust a voltage of the second noise reduction control node based on a signal of the second clock signal terminal, thereby causing the second noise reduction control node to provide an alternating voltage signal. The second on control subcircuit is coupled to the first noise reduction control node and the second noise reduction control node, and is configured to rectify the alternating voltage signal in response to the alternating voltage signal provided by the second noise reduction control node, and output the signal to the first noise reduction control node. The off control unit is coupled to the cascade signal output terminal and a second signal terminal, and further includes a third transistor and a fourth transistor. A control electrode of the third transistor is coupled to the cascade signal output terminal, a first electrode of the third transistor is coupled to the second signal terminal, and a second electrode of the third transistor is coupled to the second noise reduction control node. A control electrode of the fourth transistor is coupled to the cascade signal output terminal, a first electrode of the fourth transistor is coupled to the second signal terminal, and a second electrode of the fourth transistor is coupled to the first noise reduction control node.

[0009] In some embodiments, the first on-control sub-circuit further includes a fifth transistor, a first terminal of a first capacitor is coupled to the second clock signal terminal through the fifth transistor, a control electrode of the fifth transistor is coupled to the scan signal output terminal, a first electrode of the fifth transistor is coupled to the second clock signal terminal, and a second electrode of the fifth transistor is coupled to the first terminal of the first capacitor.

[0010] In some embodiments, the first signal terminal is coupled to the first voltage terminal or the first clock signal terminal.

[0011] In some embodiments, the noise reduction subcircuit includes a sixth transistor, a control electrode of the sixth transistor coupled to the first noise reduction control node, a first electrode of the sixth transistor coupled to the first voltage terminal, and a second electrode of the sixth transistor coupled to the scan signal output terminal.

[0012] In some embodiments, the shift register circuit further includes an input subcircuit and an output subcircuit, where the input subcircuit and the noise reduction subcircuit are both coupled to a cascade signal output terminal, the input subcircuit is further coupled to an output subcircuit, the noise reduction control subcircuit is configured to control a voltage at the cascade signal output terminal to turn on or off the noise reduction subcircuit, and is further configured to transmit an ON signal to the output subcircuit, the output subcircuit is further coupled to the second voltage terminal or the fifth clock signal terminal, and the output subcircuit is further coupled to the scan signal output terminal, and the output subcircuit is configured to transmit a signal at the second voltage terminal or the fifth clock signal terminal to the scan signal output terminal in response to an ON signal transmitted from the input subcircuit.

[0013] In some embodiments, the input sub-circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a third capacitor, an eleventh transistor, a fourth capacitor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, where a control electrode of the seventh transistor is coupled to the third clock signal terminal, a first electrode of the seventh transistor is coupled to the input signal terminal, and a second electrode of the seventh transistor is coupled to the first node.

[0014] A control electrode of the eighth transistor is coupled to the first node, a first electrode of the eighth transistor is coupled to the third clock signal terminal, and a second electrode of the eighth transistor is coupled to the second node.

[0015] A control electrode of the ninth transistor is coupled to the third clock signal terminal, a first electrode of the ninth transistor is coupled to the first voltage terminal, and a second electrode of the ninth transistor is coupled to the second node.

[0016] A control electrode of the tenth transistor is coupled to the second node, a first electrode of the tenth transistor is coupled to the second voltage terminal, and a second electrode of the tenth transistor is coupled to the cascade signal output terminal.

[0017] A first terminal of the third capacitor is coupled to the second node, and a second terminal of the third capacitor is coupled to the first electrode and the second voltage terminal of the tenth transistor.

[0018] A control electrode of the eleventh transistor is coupled to the third node, a first electrode of the eleventh transistor is coupled to the fourth clock signal terminal, and a second electrode of the eleventh transistor is coupled to the cascade signal output terminal.

[0019] A first terminal of the fourth capacitor is coupled to the third node, and a second terminal of the fourth capacitor is coupled to the second electrode of the eleventh transistor and to the cascade signal output terminal.

[0020] A control electrode of the twelfth transistor is coupled to the first voltage terminal, a second electrode of the twelfth transistor is coupled to the third node, and a first electrode of the twelfth transistor is coupled to the first node.

[0021] A control electrode of the thirteenth transistor is coupled to the fourth clock signal terminal, a first electrode of the thirteenth transistor is coupled to the first node, and a second electrode of the thirteenth transistor is coupled to the fourth node.

[0022] A control electrode of the fourteenth transistor is coupled to the second node, a first electrode of the fourteenth transistor is coupled to the second voltage terminal, and a second electrode of the fourteenth transistor is coupled to the fourth node.

[0023] The output subcircuit includes a fifteenth transistor, a control electrode of which is coupled to the cascade signal output terminal or the third node, a first electrode of which is coupled to the second voltage terminal or the fifth clock signal terminal, and a second electrode of which is coupled to the scan signal output terminal.

[0024] In some embodiments, the second signal terminal is coupled to a second voltage terminal, or the second signal terminal is coupled to a second node.

[0025] In some embodiments, the third clock signal terminal is coupled to the first clock signal terminal and the fourth clock signal terminal is coupled to the second clock signal terminal.

[0026] In a second aspect, there is provided a gate drive circuit, the gate drive circuit comprising a plurality of cascaded shift register circuits, the shift register circuit being the shift register circuit according to any one of the above embodiments.

[0027] In a third aspect, there is provided a display device comprising a plurality of gate lines and the gate drive circuit according to the second aspect, wherein each shift register circuit in the gate drive circuit is coupled to at least one gate line.

[0028] In some embodiments, the scan signal output terminal of each shift register circuit in the gate drive circuit is coupled to at least one gate line.

[0029] In some embodiments, the plurality of gate lines include a plurality of first gate lines and a plurality of second gate lines, a scanning signal output terminal of each shift register circuit in the gate driving circuit is coupled to at least one of the first gate lines, and a cascade signal output terminal of each shift register circuit in the gate driving circuit is coupled to at least one of the second gate lines.

[0030] In a fourth aspect, there is provided a method for driving the shift register circuit according to any one of the above embodiments, the method including, in a holding step, a noise reduction control subcircuit of the shift register circuit generates an alternating voltage signal from a voltage of the first voltage terminal and a signal of the second clock signal terminal in response to a signal of a first clock signal terminal, rectifies the generated alternating voltage signal, and outputs the signal to a first noise reduction control node, thereby holding the voltage of the first noise reduction control node at a voltage that turns on the noise reduction subcircuit, and the noise reduction subcircuit performs noise reduction on the scan signal output terminal in response to the voltage of the first noise reduction control node being the voltage that turns on the noise reduction subcircuit.

[0031] In some embodiments, the driving method further includes, when the shift register circuit further includes an input subcircuit and an output subcircuit, the input subcircuit and the noise cancellation control subcircuit are both coupled to a cascade signal output terminal, and in the input stage, the input subcircuit controls the voltage of the cascade signal output terminal to a first control voltage in response to a signal of a third clock signal terminal coupled to it, thereby causing the noise cancellation control subcircuit to turn on the noise cancellation subcircuit and transmit an on signal to the output subcircuit, and in the output stage, the input subcircuit controls the voltage of the cascade signal output terminal to a second control voltage, thereby causing the noise cancellation control subcircuit to turn off the noise cancellation subcircuit and continue to transmit an on signal to the output subcircuit. In a fifth aspect, there is provided a shift register circuit including a first transistor, a first capacitor, a second transistor, a second capacitor, and a sixth transistor. A control electrode of the first transistor is coupled to a first clock signal terminal, a first electrode of the first transistor is coupled to a first voltage terminal, and a second electrode of the first transistor is coupled to a second noise reduction control node. A first terminal of the first capacitor is coupled to a second clock signal terminal, and a second terminal of the first capacitor is coupled to the second noise reduction control node. A control electrode of the second transistor is coupled to the second noise reduction control node, a first electrode of the second transistor is coupled to the first noise reduction control node, and a second electrode of the second transistor is coupled to the second noise reduction control node. A first terminal of the second capacitor is coupled to a first signal terminal, and a second terminal of the second capacitor is coupled to the first noise reduction control node. A control electrode of the sixth transistor is coupled to the first noise reduction control node, a first electrode of the sixth transistor is coupled to the first voltage terminal, and a second electrode of the sixth transistor is coupled to a scan signal output terminal. In some embodiments, the shift register circuit further includes a third transistor and a fourth transistor, a control electrode of the third transistor is coupled to a cascade signal output terminal, a first electrode of the third transistor is coupled to a second signal terminal, and a second electrode of the third transistor is coupled to the second noise reduction control node, a control electrode of the fourth transistor is coupled to the cascade signal output terminal, a first electrode of the fourth transistor is coupled to the second signal terminal, and a second electrode of the fourth transistor is coupled to the first noise reduction control node. [Brief description of the drawings]

[0032] In order to more clearly describe the technical solutions in the present disclosure, the following briefly describes the accompanying drawings that may be used in some embodiments of the present disclosure. It is obvious that the drawings in the following description are only the accompanying drawings of some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products, the actual processes of the methods, the actual sequences of the signals, etc., according to the embodiments of the present disclosure.

[0033] [Figure 1A] FIG. 2 is a configuration diagram of a display panel according to an embodiment of the present disclosure.

[0034] [Figure 1B] FIG. 2 is a gate drive architecture diagram of a display panel according to an embodiment of the present disclosure.

[0035] [Diagram 2] FIG. 1 is a configuration diagram of a pixel circuit according to a related art.

[0036] [Diagram 3] FIG. 1 is a partial configuration diagram of a shift register circuit according to a related art.

[0037] [Figure 4] FIG. 11 is a partial driving sequence diagram of a shift register circuit according to a related art.

[0038] [Diagram 5] FIG. 13 is a diagram illustrating output noise of a shift register circuit according to the related art.

[0039] [Figure 6] FIG. 2 is a configuration diagram of a shift register circuit according to an embodiment of the present disclosure.

[0040] [Figure 7] FIG. 13 is a configuration diagram of another shift register circuit according to an embodiment of the present disclosure.

[0041] [Figure 8] FIG. 13 is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0042] [Figure 9] FIG. 13 is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0043] [Figure 10] FIG. 13 is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0044] [Figure 11] FIG. 13 is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0045] [Figure 12] FIG. 4 is a driving sequence diagram of a shift register circuit according to an embodiment of the present disclosure.

[0046] [Figure 13] FIG. 13 is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0047] [Figure 14] FIG. 13 is a configuration diagram of yet another shift register circuit according to an embodiment of the present disclosure.

[0048] [Figure 15] FIG. 4 is a driving sequence diagram of a shift register circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Hereinafter, the technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the drawings. It is clear that the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art shall be included in the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout this specification and the claims, the term "comprise" and other forms, such as the third person singular "comprises" and the present participle form "comprising" should be interpreted in an open, inclusive sense, i.e., "including but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "examples," "specific examples," "some examples," and the like, are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. General expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, a particular feature, structure, material, or characteristic described may be included in any one or more embodiments or examples in any suitable manner.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as expressing or implying a relative importance or a number of technical features being presented. Thus, a feature qualified with "first" or "second" may explicitly or implicitly include one or more of the feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] In describing some embodiments, the terms "coupled," "connected," and expressions derived therefrom may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. Also, for example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact with each other. However, the terms "coupled" or "communicatively coupled" may also indicate that two or more components are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this specification.

[0053] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and all of them include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0054] "A and / or B" includes the three combinations of A only, B only, and a combination of A and B.

[0055] As used herein, the term "and" is optionally interpreted to mean "when" or "upon" or "in response to determining that" or "in response to detecting that," depending on the context. Similarly, the phrase "if ... is determined" or "if [a described condition or event] is detected" is optionally interpreted to mean "when ... is determined" or "in response to determining ..." or "when [a described condition or event] is detected" or "in response to detecting [a described condition or event]," depending on the context.

[0056] In this specification, use of "applied to" or "configured to" is intended to be open and inclusive language that does not exclude apparatus being adapted or configured to perform additional tasks or steps.

[0057] Additionally, the use of "based on" is meant to be open and inclusive, as a process, step, calculation, or other action performed "based on" one or more of the conditions or values ​​may, in fact, be based on additional conditions or beyond the values.

[0058] As used herein, "about," "approximately," or "approximate" includes the stated value and the average within an acceptable range of deviation of the particular value, where the acceptable range of deviation is determined taking into account the measurement contemplated by one of ordinary skill in the art and the error associated with measuring the particular quantity (i.e., limitations of the measurement system).

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances, can be expected. Thus, the exemplary embodiments are not limited to the shapes of the regions illustrated herein, but should be construed to include deviations in shape due to manufacturing, etc. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions shown in the drawings are exemplary in nature, and their shapes are not intended to represent the actual shape of a region of a device, nor are they intended to limit the scope of the exemplary embodiments.

[0060] Some embodiments of the present disclosure provide a display device. The display device means a product having an image display function, and for example, the display device may be a television, a mobile phone, a computer, a notebook computer, a tablet, a personal digital assistant (PDA), an in-vehicle computer, a display, a signboard, a digital photo frame, a laser printer having a display function, a telephone, a digital camera, a portable video recorder, a viewfinder, a monitor, a navigation device, a vehicle, a large-area wall, a home appliance, an information inquiry device (e.g., a business inquiry device for e-government, a bank, a hospital, a power department, a monitor, etc.), etc. The display device includes a frame, a display panel provided in the frame, a circuit board, a display driving integrated circuit (abbreviated as IC), and other electronic components, etc.

[0061] The display panel may be a liquid crystal display panel (LCD), an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro LED (including mini LED or micro LED) display panel, etc., and the present disclosure is not specifically limited thereto.

[0062] In the following embodiments of the present disclosure, the display panel is an OLED display panel.

[0063] As shown in Fig. 1A, the display panel 100 includes a display area AA (Active Area) and a peripheral area BB located on at least one side of the display area AA. Fig. 1A shows that the peripheral area BB goes around the display area AA.

[0064] The display panel 100 includes multiple color sub-pixels P arranged in a display area AA, the multiple color sub-pixels including at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, and the first color, the second color, and the third color may be three primary colors (e.g., red, green, and blue).

[0065] For ease of explanation, the present disclosure will be described taking as an example a case where the plurality of sub-pixels P are arranged in a matrix. In this case, the sub-pixels P aligned in a row in the horizontal direction X are referred to as sub-pixels in the same row, and the sub-pixels P aligned in a column in the vertical direction Y are referred to as sub-pixels in the same column.

[0066] As shown in FIG. 1B, each sub-pixel P is provided with a pixel circuit (also referred to as a pixel driving circuit) S including a plurality of transistors (FIG. 1B shows that the sub-pixel P includes two transistors). The pixel circuit S is coupled to a light-emitting element L and drives the light-emitting element L to emit light. The pixel circuits S located in the same row are connected (i.e., coupled) to the same gate line GL, and the pixel circuits S located in the same column are connected to the same data line DL. The arrangement of the sub-pixels P depends on the arrangement of the pixel circuits S in the sub-pixels P, regardless of the positions of the light-emitting elements L in the sub-pixels P.

[0067] The transistors included in the pixel circuit S may all be N-type transistors, all be P-type transistors, or may include both N-type and P-type transistors, and may be designed according to actual needs.

[0068] In addition, the pixel circuit S may include at least one of a low temperature polysilicon (LTPS) transistor and an oxide transistor. For example, the transistors in the pixel circuit S may all be LTPS transistors, or all be oxide transistors, or may include both LTPS transistors and oxide transistors.

[0069] In some embodiments, since the voltage controlling the brightness of the sub-pixel changes over time due to the leakage current of the transistor in the pixel circuit S, it is still necessary to refresh the data when displaying a still image in order to keep the brightness fluctuation of the sub-pixel within an appropriate range. In order to reduce the power consumption when displaying a still image, it is effective to reduce the refresh frequency, but since it is necessary to maintain the display quality while reducing the refresh frequency, it is necessary to reduce the leakage speed of the transistor in the pixel circuit S. Since oxide semiconductors have ultra-low leakage characteristics, by making the transistor in the pixel circuit S an oxide transistor, it is possible to reduce the leakage of the transistor in the pixel circuit S in the process of the display panel displaying the screen. Low-temperature polysilicon has high carrier mobility. When an LTPS transistor is used in the pixel circuit S, the response speed of the transistor can be significantly improved, thereby ensuring the charging speed of the sub-pixel. In addition, since the source and drain of the LTPS transistor are formed by automatic alignment using the ion implantation method, the parasitic capacitance generated between the gate and the source and drain is significantly smaller than that of an amorphous silicon transistor, and further, the capacitive coupling effect is significantly reduced. In order to ensure the charging speed and small parasitic capacitance of the sub-pixel while reducing the leakage of the transistors in the pixel circuit, the advantages of LTPS and oxide may be combined to adopt a low temperature polycrystalline oxide (LTPO) process. Exemplarily, the pixel circuit S includes both an LTPS transistor and an oxide transistor, for example, the pixel circuit S includes a P-type LTPS transistor and an N-type oxide transistor.

[0070] Continuing to refer to FIG. 1A and FIG. 1B, the display device may further include a gate driving circuit 01 and a data driving circuit 02. Exemplarily, the gate driving circuit 01 may be provided in the peripheral region BB of the display panel 100, for example, in a side located at one end of the gate line GL in the peripheral region BB (for example, the left side of the peripheral region BB in FIG. 1A). Exemplarily, the data driving circuit 02 may be provided in the peripheral region BB of the display panel 100. For example, the data driving circuit 02 is provided in a side located at one end of the data line DL in the peripheral region BB (for example, the lower side of the peripheral region BB in FIG. 1A). In this way, the pixel circuit S in the display panel 100 is driven, and the light-emitting element L is driven to emit light, so that the corresponding sub-pixel P can display a color to be displayed.

[0071] In some embodiments, the gate driving circuit 01 may be a gate driving IC bonded to an array substrate (also called a driving backplane) in the display panel 100. In other embodiments, the gate driving circuit 01 may be a GOA (Gate Driver on Array, where a gate driver is integrated on an array substrate) circuit and may be included in the display panel 100. In this case, the gate driving circuit 01 is directly integrated on the array substrate of the display panel 100. Here, providing the gate driving circuit 01 on the array substrate can reduce the manufacturing cost of the display panel 100 compared to bonding the gate driving circuit 01 to the array substrate in the form of a gate driving IC, and can also narrow the frame width of the display device. In the following embodiments, the case where the gate driving circuit 01 is a GOA circuit will be described as an example.

[0072] 1A and 1B show an example in which the gate driving circuit 01 is provided only on one side of the peripheral region BB of the display panel 100, and each gate line GL is driven row by row from one side, that is, one-sided driving. In some other embodiments, a gate driving circuit may be provided along two sides in the extension direction of the gate lines GL in the peripheral region BB of the display panel 100, and each gate line GL may be driven row by row from both sides simultaneously by the two gate driving circuits, that is, two-sided driving. In some other embodiments, a gate driving circuit may be provided along two sides in the extension direction of the gate lines GL in the peripheral region BB of the display panel 100, and each gate line GL may be driven row by row from both sides alternately by the two gate driving circuits, for example, one gate driving circuit drives the gate lines GL of odd rows, and another gate driving circuit drives the gate lines GL of even rows, that is, alternate driving. The following embodiments of the present disclosure will be described using one-sided driving as an example.

[0073] In some embodiments of the present disclosure, as shown in FIG. 1B, the gate drive circuit 01 includes N stages (where N is a positive integer) of cascaded shift register circuits (RS1, RS2, ..., RS(N)), and the N stages of cascaded shift register circuits (RS1, RS2, ..., RS(N)) are connected in one-to-one correspondence with N gate lines (G1, G2, ..., G(N)).

[0074] For example, the circuit structures of the shift register circuits (RS1, RS2, ..., RS(N)) of each stage may be the same, and the shift register circuits (RS1, RS2, ..., RS(N)) of each stage are sequentially connected so that the shift register circuits of each stage sequentially output an on-voltage (an active level in a scanning signal, e.g., also called a high level), thereby realizing scanning of a plurality of gate lines in a display panel row by row, and charging sub-pixels of each row coupled to the gate lines.

[0075] For example, as shown in Fig. 1B, a single-stage shift register circuit in the gate drive circuit 01 is denoted as RS(i) (where i = 1, 2, ..., N). The shift register circuit RS(i) includes a scanning signal output terminal Output (Output will be abbreviated to Oput in the following description and drawings). This outputs a gate scanning signal to the gate line GL connected thereto via the scanning signal output terminal Oput.

[0076] The shift register circuit RS(i) of each stage of the gate drive circuit 01 is further provided with a signal input terminal Input (abbreviated as Iput in both the drawings and the following description) so as to supply a start signal to the shift register circuit RS(i) of each stage.

[0077] In addition, the shift register circuit RS(i) of each stage of the gate drive circuit 01 further includes a cascade signal output terminal GP, which is connectable to the shift register circuit of the next stage, thereby transmitting a cascade signal to the shift register circuit of the next stage as a start signal for the shift register circuit of the next stage.

[0078] Based on this, the cascade connection configuration of the shift register circuits RS(i) in each stage in the gate drive circuit 01 can be configured as follows.

[0079] The signal input terminal Iput of the first-stage shift register circuit RS1 is connected to the start signal terminal STV, and the signal input terminal Iput of the shift register circuit RS(i) of any stage other than the first-stage shift register circuit RS1 is connected to the cascade signal output terminal GP of the shift register circuit RS(i-1) located in the previous stage.

[0080] Based on the above cascade connection configuration, the scanning signal output terminal Oput of the shift register circuit RS(i) in each stage is coupled to at least one gate line GL.

[0081] In some embodiments, for example, when the pixel circuit S includes not only a P-type LTPS transistor but also an N-type oxide transistor, the cascade signal output terminal GP may be connected to the P-type transistor in the pixel circuit S via a gate line and transmit a signal (this signal may be referred to as a control signal) to the P-type transistor to control the on / off of the P-type transistor.

[0082] Based on this, the connection relationship between each stage of the shift register circuit (RS1, RS2, . . . , RS(N)) in the gate drive circuit 01 and the multiple gate lines GL can be as follows.

[0083] The pixel circuits in the same row may be coupled to at least two gate lines including at least one first gate line and at least one second gate line. The scanning signal output terminal Oput of each shift register circuit in the gate drive circuit is coupled to at least one first gate line, and the cascade signal output terminal GP of each shift register circuit in the gate drive circuit is coupled to at least one second gate line. Here, since the gate line connected to the scanning signal output terminal Oput and the gate line connected to the cascade signal output terminal GP are not the same line, for ease of distinction, the gate line coupled to the scanning signal output terminal Oput is referred to as the first gate line, and the gate line coupled to the cascade signal output terminal GP is referred to as the second gate line.

[0084] With reference to the 7T1C pixel circuit shown in FIG. 2, a method for controlling an LTPO pixel circuit will be described using this pixel circuit as an example. As shown in FIG. 2, a pixel circuit S' includes seven transistors D1 to D7 and one capacitor Cst. Here, the transistors D3 and D4 are N-type transistors, for example, N-type oxide transistors, and the transistors D2 and D7 are P-type transistors, for example, P-type LTPS transistors. Then, in any pixel circuit S' in the i-th row, the transistors D3 and D4 can be coupled to the scanning signal output terminal Oput(i) of the current stage and the scanning signal output terminal Oput(i-1) of the previous stage, respectively, via two first gate lines, and the transistors D2 and D7 can be coupled to the cascade signal output terminal GP(i) of the current stage and the cascade signal output terminal GP(i-1) of the previous stage, respectively, via two second gate lines.

[0085] Through the first gate line and the second gate line, the shift register circuit controls the oxide transistor and the LTPS transistor in the LTPO pixel circuit respectively, which can greatly improve the response time of this control process.

[0086] In some related art, in the process of driving one row of gate lines within one frame period, a first stage of the shift register circuit first outputs an on-voltage (also called an active voltage or operating voltage) in the scanning signal to the gate line coupled thereto, thereby turning on one row of sub-pixels coupled to this gate line. This stage is called an output stage. After that, the shift register circuit of this stage outputs an off-voltage (also called a non-operating voltage) in the scanning signal to the gate line coupled thereto, thereby ensuring that the sub-pixels coupled to this gate line are turned off. That is, the stage enters a holding stage. However, in the holding stage, noise in the scanning signal output terminal coupled to the gate line in the shift register circuit is large, resulting in an unstable screen displayed on the display device.

[0087] The inventors of the present disclosure have discovered through their investigation that one of the causes of the above problem is as follows.

[0088] As shown in Figures 3 and 4, Figure 3 shows a partial circuit configuration of a shift register circuit RS' in the related art, and Figure 4 shows a partial driving sequence of the shift register circuit RS'. In Figure 3, 30' is a noise elimination sub-circuit, and the noise elimination sub-circuit 30' includes a transistor T03.

[0089] In the driving process of one row of gate lines, in the output stage P2', the potential of the cascade signal output terminal GP is low, the transistor T04 is turned on, the scanning signal output terminal Oput outputs a high level, i.e., outputs the scanning signal, the transistor T02 is turned on, and the potential of the node PD-ox' is high, so that the transistor T03 in the noise elimination sub-circuit 30' is turned off.

[0090] During a period P31' of the holding stage P3', the potential of the clock signal terminal CK1 is low, the transistor T01 is turned on, and the potential of the node PD-ox' becomes low potential V SS +|V th | (where V th is the threshold voltage of the transistor T01). As a result, the transistor T03 in the noise elimination subcircuit 30' is turned on, and the potential of the scanning signal output terminal Oput becomes the low potential V SS +|V th |, and the scanning signal output terminal Oput is reset.

[0091] During a period P32' of the holding stage P3', the potential of the clock signal terminal CK1 is high, the transistor T01 is off, the potential of the cascade signal output terminal GP is high, and the transistor T02 is off, so that the potential of the node PD-ox' is floating. The potential of the clock signal terminal CB1 becomes low, and the potential of the node PD_ox' is further pulled down by the coupling action of the capacitor C01, the transistor T03 in the noise elimination subcircuit 30' is further turned on, the potential of the scanning signal output terminal Oput becomes low, and further resetting of the scanning signal output terminal Oput is realized.

[0092] During a period P33' of the holding stage P3', the potential of the clock signal terminal CK1 is low, but PD_ox' is also low, and the threshold voltage V of a PMOS (Positive-channel Metal Oxide Semiconductor) transistor is low. th Since is generally negative, the gate-source voltage difference V gs >V th It is. gs <V th In this case, the PMOS transistor is on, and the transistor T01 is off. Also, since the potential of the cascade signal output terminal GP is high and the transistors T02 and T04 are off, the potentials of the node PD-ox' and the scanning signal output terminal Oput are floating. The potential of the clock signal terminal CB1 is high. Due to the coupling action of the capacitor C01, the potential of the node PD_ox' is pulled up slightly, which turns off the transistor T03 in the noise elimination subcircuit 30' and makes it impossible to eliminate noise from the scanning signal output terminal Oput.

[0093] In this way, the clock signals CK1 and CB1 alternate between high and low levels, and thereafter, the periods P32' and P33' alternate. Therefore, in the holding stage, in nearly half of the period (i.e., the period P33' of the holding stage P3'), the noise removal sub-circuit 30' cannot remove noise from the scanning signal output terminal Oput, and therefore, when disturbance occurs, the shift register circuit RS' cannot remove noise in a timely manner in the holding stage P3', and large noise may occur in the scanning signal output terminal Oput. As shown in FIG. 5, the result of the simulation test shows that the noise of the scanning signal output terminal Oput can reach 2V in the holding stage P3'.

[0094] Some embodiments of the present disclosure provide a shift register circuit that solves the problem that the noise of the scanning signal output terminal coupled to the gate line in the shift register circuit is large during the holding stage, which causes the screen display to become unstable. As shown in FIG. 6, the shift register circuit RS includes a noise elimination control subcircuit 20 and a noise elimination subcircuit 30.

[0095] Here, the noise reduction control subcircuit 20 is coupled to a first voltage terminal VSS, a first clock signal terminal CK1, a second clock signal terminal CB1, and a first noise reduction control node PD-ox. The noise reduction control subcircuit 20 is configured to rectify the charge of the first voltage terminal VSS to the first noise reduction control node PD-ox under the control of the signal of the first clock signal terminal CK1. Thereby, by adjusting (pulling up or down) the voltage of the first noise reduction control node PD-ox, the voltage of the first noise reduction control node PD-ox can be maintained at a voltage that turns on the noise reduction subcircuit 30. Specifically, the noise removal control subcircuit 20 is configured to generate an alternating voltage signal (in other words, an oscillation signal) from the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1 in response to a signal of the first clock signal terminal CK1, rectify the generated alternating voltage signal, output the signal to the first noise removal control node PD-ox, and hold the voltage of the first noise removal control node PD-ox at a voltage that turns on the noise removal subcircuit 30. For example, the voltage of the first noise removal control node PD-ox can be gradually changed (gradually pulled up or down) and finally reached, for example, a steady state.

[0096] Here, the alternating voltage signal refers to a signal whose voltage magnitude changes periodically. For example, the alternating voltage signal may be a signal in which high voltage and low voltage alternate, such as a square wave signal. Here, the duration of the high voltage and the duration of the low voltage in one period may be the same or different. The amplitude value of the alternating voltage signal may be kept constant, for example, the high voltage and the low voltage in multiple periods may be equal.

[0097] Rectification refers to outputting an alternating voltage signal as a direct voltage signal. In the embodiment of the present disclosure, the direct voltage signal may be a signal defined relative to the alternating voltage signal, whose voltage does not change over time. It may also include a signal whose amplitude value (voltage) gradually increases or decreases over time, which may eventually reach, for example, a steady state (i.e., the voltage does not change any more). For example, the direct voltage signal may include multiple periods, with the magnitude of the voltage in each period being constant, and the voltage in any period being higher than the voltage value in the previous period, or the voltage in any period being lower than the voltage value in the previous period.

[0098] It should be understood that the above-mentioned "voltage that turns on the noise elimination subcircuit 30" refers to a voltage that can operate the noise elimination subcircuit 30, and this voltage specifically depends on the type of transistor included in the noise elimination subcircuit 30. For example, if the transistor included in the noise elimination subcircuit 30 is a P-type, this voltage is a low-level voltage, and if the transistor included in the noise elimination subcircuit 30 is an N-type, this voltage is a high-level voltage. The noise elimination subcircuit 30 is coupled to a first noise elimination control node PD-ox and a scanning signal output terminal Oput. The noise elimination subcircuit 30 is configured to perform noise elimination for the scanning signal output terminal Oput in response to the voltage of the first noise elimination control node being a voltage that turns on the noise elimination subcircuit.

[0099] In the above shift register circuit RS, the noise removal control subcircuit 20, under the control of the signal of the first clock signal terminal CK1, adjusts the voltage of the first noise removal control node PD-ox based on the received signal (which may include, for example, the signal of the first voltage terminal VSS and the signal of the second clock signal terminal CB1, etc.) so that the voltage of the first noise removal control node PD-ox is stabilized, that is, the voltage of the first noise removal control node PD-ox can be stabilized at a voltage (high level or low level) that turns on the noise removal subcircuit 30. The noise removal control subcircuit 20 outputs the adjusted voltage to the noise removal subcircuit 30 and controls the noise removal subcircuit 30 to maintain a continuously on state, thereby realizing the noise removal subcircuit 30 to continue to output a stable non-operating voltage and continue to perform noise removal for the scanning signal output terminal Oput, thereby improving the stability of the screen display.

[0100] In some embodiments, as shown in FIG. 7, the noise reduction control subcircuit 20 includes an ON control unit 21 and an OFF control unit 22. Here, the ON control unit 21 is coupled to a first voltage terminal VSS, a first clock signal terminal CK1, a second clock signal terminal CB1, and a first noise reduction control node PD-ox. The ON control unit 21 is configured to rectify the charge of the first voltage terminal VSS and the charge of the second clock signal terminal CB1 to the first noise reduction control node PD-ox under the control of the signal of the first clock signal terminal CK1. Thereby, the voltage of the first noise reduction control node PD-ox can be pulled up or down to keep the voltage of the first noise reduction control node PD-ox at a voltage that turns on the noise reduction subcircuit 30.

[0101] Specifically, the on-control unit 21 generates an alternating voltage signal from the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1 in response to a signal of the first clock signal terminal CK1, rectifies the generated alternating voltage signal, and outputs the signal to the first noise reduction control node PD-ox, thereby maintaining the voltage of the first noise reduction control node PD-ox at a voltage that turns on the noise reduction sub-circuit 30. Exemplarily, the on-control unit 21 may be coupled to a second noise reduction control node PD-ox-i, and the generated alternating voltage signal is the signal of the second noise reduction control node PD-ox-i.

[0102] Here, the first voltage terminal VSS is configured to transmit, for example, a DC low-level signal. For example, the first voltage terminal VSS is grounded. In some embodiments, as shown in FIG. 8 , the on-control unit 21 of the noise removal control sub-circuit 20 includes a first on-control sub-circuit 211 and a second on-control sub-circuit 212.

[0103] Here, the first on-control sub-circuit 211 is coupled to the first clock signal terminal CK1, the second clock signal terminal CB1, the first voltage terminal VSS, and the second noise cancellation control node PD-ox-i, and is configured to periodically output the voltage of the first voltage terminal VSS to the second noise cancellation control node PD-ox-i in response to a signal from the first clock signal terminal CK1, and to periodically adjust the voltage of the second noise cancellation control node PD-ox-i based on the signal from the second clock signal terminal CB1, thereby supplying an alternating voltage signal to the second noise cancellation control node PD-ox-i.

[0104] Exemplarily, referring to FIG. 8, the first on-control sub-circuit 211 includes a first transistor T1 and a first capacitor C1.

[0105] Here, a control electrode of the first transistor T1 is coupled to a first clock signal terminal CK1, a first electrode of the first transistor T1 is coupled to a first voltage terminal VSS, and a second electrode of the first transistor T1 is coupled to a second noise removal control node PD-ox-i.

[0106] A first terminal of the first capacitor C1 is coupled to the second clock signal terminal CB1, and a second terminal of the first capacitor C1 is coupled to the second noise removal control node PD-ox-i.

[0107] For example, when the first transistor T1 is turned on by the signal control of the first clock signal terminal CK1, the voltage of the first voltage terminal VSS is transmitted to the second noise reduction control node PD-ox-i through the first transistor T1. When the first transistor T1 is turned off by the signal control of the first clock signal terminal CK1, the voltage of the first voltage terminal VSS cannot be transmitted to the second noise reduction control node PD-ox-i, but the voltage of the second noise reduction control node PD-ox-i can be further adjusted in response to the signal of the second clock signal terminal CB1 and through the coupling effect of the first capacitor C1. For example, when the first transistor T1 is turned on by the signal control of the first clock signal terminal CK1, the second clock signal terminal CB1 outputs a low level. When the first transistor T1 is turned off by the signal control of the first clock signal terminal CK1, the second clock signal terminal CB1 outputs a high level, thereby pulling up the voltage of the second noise reduction control node PD-ox-i. The first transistor T1 is periodically turned on and off under signal control of the first clock signal terminal CK1, and the second clock signal terminal CB1 periodically adjusts the voltage of the second noise removal control node PD-ox-i, so that the voltage of the second noise removal control node PD-ox-i becomes an alternating voltage through the joint action of both.

[0108] The second on-control subcircuit 212 is coupled to the first noise removal control node PD-ox and the second noise removal control node PD-ox-i, and rectifies the alternating voltage signal and outputs the signal to the first noise removal control node PD-ox, thereby maintaining the voltage of the first noise removal control node PD-ox at a voltage that turns on the noise removal subcircuit 30.

[0109] Exemplarily, referring to FIG. 8, the second on-control sub-circuit 212 includes a second transistor T2 and a second capacitor C2.

[0110] Here, a control electrode of the second transistor T2 is coupled to the second noise reduction control node PD-ox-i, a first electrode of the second transistor T2 is coupled to the first noise reduction control node PD-ox, and a second electrode of the second transistor T2 is coupled to the second noise reduction control node PD-ox-i.

[0111] A first terminal of the second capacitor C2 is coupled to the first clock signal terminal ST, and a second terminal of the second capacitor C2 is coupled to the first noise removal control node PD-ox.

[0112] Exemplarily, the alternating voltage signal provided by the second noise reduction control node PD-ox-i can turn on the second transistor T2. When the first transistor T1 is turned on, it transmits the voltage of the first voltage terminal VSS to the second noise reduction control node PD-ox-i. At this time, since there is no coupling effect of the first capacitor C1, the charge on its second terminal does not change. On the other hand, when the first transistor T1 is turned off, it cannot transmit the voltage of the first voltage terminal VSS to the second noise reduction control node PD-ox-i. At this time, due to the coupling effect of the first capacitor C1, the voltage of the second terminal of the first capacitor C1 is pulled down by the second clock signal terminal CB1, so that the charge amount on the second terminal of the first capacitor C1 is smaller than the charge amount on the second terminal of the second capacitor C2. Then, the charge on the second terminal of the second capacitor C2 can be transmitted to the second terminal of the first capacitor C1 via the second transistor T2. Also, since the above process cycles periodically, the charge on the second terminal of the second capacitor C2 is constantly transferred to the second terminal of the first capacitor C1, so that the charge on the second terminal of the second capacitor C2 gradually decreases and finally stabilizes at a fixed value. For example, the voltage on the second terminal of the first capacitor C1 stabilizes to the same value as the charge on the second terminal of the first capacitor C1 when it is pulled down by the second clock signal terminal CB1, and further stabilizes the voltage of the first noise reduction control node PD-ox coupled to the second capacitor C2 to a fixed voltage, which keeps the noise reduction subcircuit 30 on.

[0113] In the shift register circuit RS according to the embodiment of the present disclosure, the first noise elimination control node PD-ox, the second noise elimination control node PD-ox-i, the cascade signal output terminal GP, and the first node n1, the second node n2, the third node n3, and the fourth node n4 described below do not represent components that actually exist, but represent connection points of related electrical connections in the circuit diagram. In other words, these nodes are nodes that equivalently represent the connection points of related electrical connections in the circuit diagram. In addition, the first signal terminal (also called a constant voltage signal terminal) ST may be coupled to the first voltage terminal VSS or the first clock signal terminal CK1.

[0114] Exemplarily, when the first signal terminal ST is coupled to the first voltage terminal VSS, the first terminal of the second capacitor C2 is connected to the first voltage terminal VSS, so that the second capacitor C2 provides a voltage stabilization function for the first noise removal control node PD-ox and prevents leakage from occurring at the first noise removal control node PD-ox.

[0115] Exemplarily, when the first signal terminal ST is coupled to the first clock signal terminal CK1, the first terminal of the second capacitor C2 is connected to the first clock signal terminal CK1. Thus, in addition to the second capacitor C2 being able to stabilize the voltage of the first noise reduction control node PD-ox, the second capacitor C2 can further adjust the voltage of the first noise reduction control node PD-ox when the voltage of the signal of the first clock signal terminal CK1 changes, and can quickly stabilize the voltage of the first noise reduction control node PD-ox to a potential that can turn on the noise reduction subcircuit 30, which is favorable for improving the noise reduction speed of the noise reduction subcircuit 30. For example, when the potential that turns on the noise reduction subcircuit 30 is a low potential, when the voltage of the signal of the first clock signal terminal CK1 becomes low, the second capacitor C2 can further pull down the potential of the first noise reduction control node PD-ox, which is favorable for improving the noise reduction speed of the noise reduction subcircuit 30.

[0116] The first transistor T1, the first capacitor C1, the second transistor T2, and the second capacitor C2 included in the on-control unit 21 form a charge pump structure. Through the voltage regulation effect of the charge pump structure, the voltage of the first noise reduction control node PD-ox is stabilized to a voltage that can turn on the noise reduction sub-circuit 30, thereby ensuring that the noise reduction sub-circuit 30 continues to be turned on during the holding stage in the driving process of one row of gate lines, and continues to perform noise reduction for the scanning signal output terminal Oput.

[0117] In some embodiments, the off-control unit 22 of the noise reduction control sub-circuit 20 is coupled to the cascade signal output terminal GP, the second signal terminal (also referred to as the control signal terminal) CN, the first noise reduction control node PD-ox, and the second noise reduction control node PD-ox-i, and is configured to control the noise reduction sub-circuit 30 to be off by transmitting a signal at the second signal terminal CN to the first noise reduction control node PD-ox in response to a voltage at the cascade signal output terminal GP.

[0118] Illustratively, and still referring to FIG. 8, the off control unit 22 includes a third transistor T3 and a fourth transistor T4.

[0119] Here, the control electrode of the third transistor T3 is coupled to the cascade signal output terminal GP, the first electrode of the third transistor T3 is coupled to the second signal terminal CN, and the second electrode of the third transistor T3 is coupled to the second noise removal control node PD-ox-i.

[0120] A control electrode of the fourth transistor T4 is coupled to the cascade signal output terminal GP, a first electrode of the fourth transistor T4 is coupled to the second signal terminal CN, and a second electrode of the fourth transistor T4 is coupled to the first noise removal control node PD-ox.

[0121] The second signal terminal CN may be coupled to a second voltage terminal VDD or a second node n2. Here, for example, the second voltage terminal VDD is configured to transmit a DC high-level signal. For example, the voltage value of this DC high-level signal is higher than the voltage value of the DC low-level signal transmitted from the first voltage terminal VSS. Here, the second node n2 is a node in the input subcircuit 10 described later, and for example, the voltage of this node is high in the output stage and low in the hold stage in the driving process of one row of gate lines.

[0122] For example, when the second signal terminal CN is coupled to the second voltage terminal VDD, in the output stage, the third transistor T3 and the fourth transistor T4 are turned on under the control of the voltage of the cascade signal output terminal GP, and the voltages of the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i are both the voltage of the second voltage terminal VDD, i.e., high level. Thus, the noise reduction sub-circuit 30 is held off in the output stage and does not affect the output of the scanning signal at the scanning signal output terminal Oput. In the hold stage, the third transistor T3 and the fourth transistor T4 are held off under the control of the voltage of the cascade signal output terminal GP, so that the high level of the second signal terminal CN has almost no effect on the voltages of the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i.

[0123] For example, taking the case where the third transistor T3 and the fourth transistor T4 are both P-type transistors, when the second signal terminal CN is coupled to the second node n2, the voltage of the second node n2 is at a high level in the output stage and at a low level in the hold stage. Therefore, in the output stage, the third transistor T3 and the fourth transistor T4 are turned on under the control of the voltage of the cascade signal output terminal GP, and the voltages of the first noise reduction control node PD-ox and the second noise reduction control node PD-ox-i are both at the voltage of the second node n2, i.e., at a high level. As a result, the noise reduction sub-circuit 30 is held off in the output stage and does not affect the output of the scanning signal at the scanning signal output terminal Oput. In the hold stage, the third transistor T3 and the fourth transistor T4 are held off under the control of the voltage of the cascade signal output terminal GP, and the voltage of the second signal terminal CN is at a low level. This is advantageous to reduce the amount of leakage current from the third transistor T3 and the fourth transistor T4, reduce the impact of the leakage current from the third transistor T3 and the fourth transistor T4 on the voltage of the first noise removal control node PD-ox, and speed up the adjustment speed of the voltage of the first noise removal control node PD-ox, so that the voltage of the first noise removal control node PD-ox can reach a stable voltage value in a shorter time, and further improve the noise removal speed of the noise removal sub-circuit 30.

[0124] 9, the first on-control sub-circuit 211 further includes a fifth transistor T5. A first terminal of the first capacitor C1 is coupled to the second clock signal terminal CB1 via the fifth transistor T5. A control electrode of the fifth transistor T5 is coupled to the scan signal output terminal Oput, a first electrode of the fifth transistor T5 is coupled to the second clock signal terminal CB1, and a second electrode of the fifth transistor T5 is coupled to the first terminal of the first capacitor C1.

[0125] Taking the fifth transistor T5 as an example, the control electrode of the fifth transistor T5 is coupled to the scanning signal output terminal Oput, so that in the output stage, the fifth transistor T5 is turned off under the control of the high-level signal output from the scanning signal output terminal Oput, thereby cutting off the connection between the second clock signal terminal CB1 and the first capacitor C1, thereby preventing the potential change of the second clock signal terminal CB1 from affecting the first capacitor C1, thereby eliminating the coupling effect of the potential change of the second clock signal terminal CB1 on the first capacitor C1, and also eliminating the resulting effect on the potential of the second noise removal control node PD-ox-i.

[0126] 11, the noise reduction subcircuit 30 includes a sixth transistor T6. A control electrode of the sixth transistor T6 is coupled to the first noise reduction control node PD-ox, a first electrode of the sixth transistor T6 is coupled to the first voltage terminal VSS, and a second electrode of the sixth transistor T6 is coupled to the scan signal output terminal Oput.

[0127] In the above embodiment, in the holding stage, the noise removal control subcircuit 20 can hold the voltage of the first noise removal control node PD-ox at a stable voltage that turns on the noise removal subcircuit 30. Therefore, the sixth transistor T6 of the noise removal subcircuit 30 continues to be turned on. This allows the voltage of the first voltage terminal VSS to be continuously transmitted to the scanning signal output terminal Oput, ensuring that noise removal is continuously performed for the scanning signal output terminal Oput.

[0128] In some embodiments, the shift register circuit RS further includes an input sub-circuit 10 and an output sub-circuit 40, as shown in FIG.

[0129] Both the input subcircuit 10 and the noise cancellation control subcircuit 20 are coupled to a cascade signal output terminal GP, and the noise cancellation control subcircuit is configured to control the voltage of the cascade signal output terminal GP to turn the noise cancellation subcircuit on or off. The input subcircuit 10 is further coupled to an output subcircuit 40, and is further configured to transmit an ON signal to the output subcircuit 40.

[0130] Exemplarily, in the output stage, the input subcircuit 10 can control the voltage of the cascade signal output terminal GP to a voltage that turns on the off control unit 22. In response to the voltage of the cascade signal output terminal GP, the off control unit 22 transmits a signal of the second signal terminal CN to the first noise removal control node PD-ox to turn off the noise removal subcircuit 30, ensuring that the output of the scanning signal at the scanning signal output terminal Oput is not affected. In the hold stage, the input subcircuit 10 can control the voltage of the cascade signal output terminal GP to a voltage that turns off the off control unit 22, so that the noise removal subcircuit 30 continues to be turned on by the action of the on control unit 21.

[0131] The input sub-circuit 10 is further coupled to an input signal terminal Iput, a third clock signal terminal CK3, a fourth clock signal terminal CB3, a first voltage terminal VSS, and a second voltage terminal VDD. Under control of the signal at the third clock signal terminal CK3, the input sub-circuit 10 can also write a signal at the input signal terminal Iput. Under control of the voltage at the first voltage terminal VSS, the input sub-circuit 10 transmits an ON signal to the output sub-circuit 40 in response to the written signal.

[0132] Here, exemplarily, the signal transmitted by the third clock signal terminal CK3 coupled to the input subcircuit 10 may be the same as the signal transmitted by the first clock signal terminal CK1. For example, the third clock signal terminal CK3 is coupled to the first clock signal terminal CK1. The signal transmitted by the fourth clock signal terminal CB3 may be the same as the signal transmitted by the second clock signal terminal CB1. For example, the fourth clock signal terminal CB3 is coupled to the second clock signal terminal CB1. In this case, as shown in FIG. 13, it can be considered that the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input subcircuit 10 may be coupled to the first clock signal terminal CK1 and the second clock signal terminal CB1, respectively.

[0133] Exemplarily, the signal transmitted by the third clock signal terminal CK3 coupled to the input subcircuit 10 is different from the signal transmitted by the first clock signal terminal CK1, and the signal transmitted by the fourth clock signal terminal CB3 is different from the signal transmitted by the second clock signal terminal CB1. That is, as shown in FIG. 10, the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input subcircuit 10 are different from the first clock signal terminal CK1 and the second clock signal terminal CB1 coupled to the noise reduction control subcircuit 20. That is, the input subcircuit 10 and the noise reduction control subcircuit 20 are controlled by clock signals of different groups, respectively. In this way, it is possible to realize independent control of each of the input subcircuit 10 and the noise reduction control subcircuit 20, and it is possible to further ensure effective control of the voltage of the first noise reduction control node PD-ox by the noise reduction control subcircuit 20. In addition, the falling edge of the signal of the first clock signal terminal CK1 can be synchronized with the rising edge of the signal of the fourth clock signal terminal CB3 and the falling edge of the signal of the scan signal output terminal Oput. In this way, after the scanning signal is output from the scanning signal output terminal Oput, it is possible to reset the voltage of the scanning signal output terminal Oput at an appropriate time.

[0134] The output sub-circuit 40 is coupled to the second voltage terminal VDD or the fifth clock signal terminal CK2. Fig. 10 shows that the output sub-circuit 40 is coupled to the fifth clock signal terminal CK2. The output sub-circuit 40 is further coupled to the scan signal output terminal Oput. In response to an on signal transmitted from the input sub-circuit 10, the output sub-circuit 40 is configured to transmit a signal of the second voltage terminal VDD or the fifth clock signal terminal CK2 to the scan signal output terminal Oput to scan the gate line coupled to the scan signal output terminal Oput.

[0135] Illustratively, referring to FIG. 11, the input sub-circuit 10 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a third capacitor C3, an eleventh transistor T11, a fourth capacitor C4, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0136] Here, a control electrode of the seventh transistor T7 is coupled to the third clock signal terminal CK3, a first electrode of the seventh transistor T7 is coupled to the input signal terminal Iput, and a second electrode of the seventh transistor T7 is coupled to the first node n1.

[0137] A control electrode of the eighth transistor T8 is coupled to the first node n1, a first electrode of the eighth transistor T8 is coupled to the third clock signal terminal CK3, and a second electrode of the eighth transistor T8 is coupled to the second node n2.

[0138] A control electrode of the ninth transistor T9 is coupled to the third clock signal terminal CK3, a first electrode of the ninth transistor T9 is coupled to the first voltage terminal VSS, and a second electrode of the ninth transistor T9 is coupled to the second node n2.

[0139] A control electrode of the tenth transistor T10 is coupled to the second node n2, a first electrode of the tenth transistor T10 is coupled to the second voltage terminal VDD, and a second electrode of the tenth transistor T10 is coupled to the cascade signal output terminal GP.

[0140] A first terminal of the third capacitor C3 is coupled to the second node n2, and a second terminal of the third capacitor C3 is coupled to a first electrode of the tenth transistor T10 and to the second voltage terminal VDD.

[0141] A control electrode of the eleventh transistor T11 is coupled to the third node n3, a first electrode of the eleventh transistor T11 is coupled to the fourth clock signal terminal CB3, and a second electrode of the eleventh transistor T11 is coupled to the cascade signal output terminal GP.

[0142] A first terminal of the fourth capacitor C4 is coupled to the third node n3, and a second terminal of the fourth capacitor C4 is coupled to the second electrode of the eleventh transistor T11 and the cascade signal output terminal GP.

[0143] A control electrode of the twelfth transistor T12 is coupled to the first voltage terminal VSS, a second electrode of the twelfth transistor T12 is coupled to the third node n3, and a first electrode of the twelfth transistor T12 is coupled to the first node n1.

[0144] A control electrode of the thirteenth transistor T13 is coupled to a fourth clock signal terminal CB3, a first electrode of the thirteenth transistor T13 is coupled to the first node n1, and a second electrode of the thirteenth transistor T13 is coupled to a fourth node n4.

[0145] A control electrode of the fourteenth transistor T14 is coupled to the second node n2, a first electrode of the fourteenth transistor T14 is coupled to the second voltage terminal VDD, and a second electrode of the fourteenth transistor T14 is coupled to the fourth node n4.

[0146] Based on the above embodiment, the signal transmitted by the third clock signal terminal CK3 coupled to the input sub-circuit 10 is the same as the signal transmitted by the first clock signal terminal CK1, and the signal transmitted by the fourth clock signal terminal CB3 is the same as the signal transmitted by the second clock signal terminal CB1. That is, when the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 are respectively coupled to the first clock signal terminal CK1 and the second clock signal terminal CB1, as shown in Figure 14, the control electrode of the seventh transistor T7 included in the input sub-circuit 10 is coupled to the first clock signal terminal CK1, the first electrode of the eighth transistor T8 is coupled to the first clock signal terminal CK1, the control electrode of the ninth transistor T9 is coupled to the first clock signal terminal CK1, and the control electrode of the thirteenth transistor T13 is coupled to the second clock signal terminal CB1. In addition, the connection relationship between the other electrodes of the above transistors and the other transistors included in the input sub-circuit 10 can refer to the above embodiment corresponding to Figure 11.

[0147] 11, by way of example, the output sub-circuit 40 includes a fifteenth transistor T15. A control electrode of the fifteenth transistor T15 is coupled to the cascade signal output terminal GP or the third node n3 (FIG. 11 shows the case where the control electrode of the fifteenth transistor T15 is coupled to the third node n3), a first electrode of the fifteenth transistor T15 is coupled to the second voltage terminal VDD or the fifth clock signal terminal CK2 (FIG. 11 shows the case where the control electrode of the fifteenth transistor T15 is coupled to the fifth clock signal terminal CK2), and a second electrode of the fifteenth transistor T15 is coupled to the scan signal output terminal Oput.

[0148] The transistors used in the shift register circuit RS according to the embodiments of the present disclosure may be thin film transistors (TFTs), field effect transistors (FETs), or other switching elements having the same characteristics, and in the embodiments of the present disclosure, thin film transistors will be used as examples.

[0149] The control electrode of each thin film transistor used in the shift register circuit RS is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. The source and drain of the thin film transistor may be structurally symmetrical, so the source and drain may be structurally indistinguishable. That is, the first electrode and the second electrode of the thin film transistor in the embodiment of the present disclosure may be structurally indistinguishable. Exemplarily, when the thin film transistor is a P-type transistor, the first electrode of the thin film transistor is the source, and the second electrode is the drain. Exemplarily, when the thin film transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0150] In the shift register circuit RS according to the embodiment of the present disclosure, the thin film transistors are all P-type transistors. The embodiment of the present disclosure includes but is not limited to the above. For example, one or more thin film transistors in the shift register circuit RS according to the embodiment of the present disclosure can be N-type transistors, and the electrodes of the selected type of thin film transistor can be connected correspondingly with reference to the electrodes of the corresponding thin film transistors according to the embodiment of the present disclosure, and the corresponding voltage terminals provide the corresponding high-level voltage or low-level voltage.

[0151] In the embodiment of the present disclosure, the specific implementation forms of the input sub-circuit 10, the noise removal control sub-circuit 20, the noise removal sub-circuit 30, and the output sub-circuit 40 are not limited to those described above, and may be any implementation form for any purpose, such as a normal connection form known to those skilled in the art, as long as it can ensure that the corresponding functions can be realized. The above examples are not intended to limit the scope of protection of the present disclosure. In practical applications, those skilled in the art can choose to use or not apply one or more of the above circuits according to the situation, and various combinations and modifications of the above circuits do not deviate from the principle of the present disclosure, and will not be further described herein.

[0152] In the embodiments of the present disclosure, the capacitors (e.g., the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 in FIG. 11) may be capacitor elements individually fabricated by a process step, and may be realized by fabricating dedicated capacitor electrodes, and each capacitor electrode of the capacitor may be realized by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor may be a parasitic capacitance between transistors, or may be realized by the transistor itself and another device or wiring, or may be realized by the parasitic capacitance between wiring of the circuit itself.

[0153] Based on the configuration of the shift register circuit RS according to the above embodiments, some embodiments of the present disclosure provide a driving method for the shift register circuit RS.

[0154] As shown in FIGS. 10 and 12, the driving process of one row of gate lines includes an input stage P1, an output stage P2 and a holding stage P3.

[0155] When the shift register circuit RS includes an input subcircuit 10, a noise reduction control subcircuit 20, a noise reduction subcircuit 30, and an output subcircuit 40, in the input stage P1, the input subcircuit 10 controls the voltage of the cascade signal output terminal GP to a first control voltage, so that the noise reduction control subcircuit 20 turns on the noise reduction subcircuit 30. Here, the first control voltage means a voltage that the cascade signal output terminal GP can turn on the noise reduction subcircuit 30 by controlling the noise reduction control subcircuit 20, for example, the first control voltage is equal to the voltage value output by the second voltage terminal. Thereby, the noise reduction control subcircuit 20 turns on the noise reduction subcircuit 30 by controlling the voltage of the first noise reduction control node PD-ox to a voltage that turns on the noise reduction subcircuit 30. In addition, the input subcircuit 10 further transmits an on signal to the output subcircuit 40. For example, the input sub-circuit 10 writes a signal to the input signal terminal Iput under the control of the signal from the third clock signal terminal CK3, and turns on the output sub-circuit 40 by the signal written to the input signal terminal Iput.

[0156] In the output stage P2, the input subcircuit 10 controls the voltage of the cascade signal output terminal GP to a second control voltage, so that the noise reduction control subcircuit 20 turns off the noise reduction subcircuit 30. Here, the second control voltage means a voltage at which the cascade signal output terminal GP can control the noise reduction control subcircuit 20 to turn off the noise reduction subcircuit 30, for example, the second control voltage is equal to the voltage value output by the first voltage terminal. Thereby, the noise reduction control subcircuit 20 controls the voltage of the first noise reduction control node PD-ox to a voltage that turns off the noise reduction subcircuit 30. Also, the input subcircuit 10 continues to transmit an ON signal to the output subcircuit 40.

[0157] Exemplarily, in the output stage, under the control of this on signal, the output sub-circuit 40 can transmit a signal from the second voltage terminal VDD or the fifth clock signal terminal CK2 (FIG. 10 shows the case where the output sub-circuit 40 is coupled to the fifth clock signal terminal CK2) to the scanning signal output terminal Oput to scan the gate line coupled to the scanning signal output terminal Oput.

[0158] In the holding stage P3, the noise removal control subcircuit 20 generates an alternating voltage signal from the voltage of the first voltage terminal VSS and the signal of the second clock signal terminal CB1 in response to the signal of the first clock signal terminal CK1, rectifies the generated alternating voltage signal, and outputs the signal to the first noise removal control node PD-ox, thereby holding the voltage of the first noise removal control node PD-ox at a voltage that turns on the noise removal subcircuit 30. The noise removal subcircuit 30 continues to be turned on under the control of the voltage of the first noise removal control node PD-ox, and performs noise removal for the scan signal output terminal Oput.

[0159] For example, a specific operation process in driving one row of the gate lines of the shift register circuit RS shown in Fig. 11 will be described in detail below with reference to Fig. 12. In the following description, an example will be described in which each transistor in the shift register circuit RS is a P-type transistor (the influence of the threshold voltage of the transistor is not taken into consideration), the voltage transmitted by the first voltage terminal VSS is a low-level voltage, and the voltage transmitted by the second voltage terminal VDD is a high-level voltage.

[0160] In the following description, the control electrode of the fifteenth transistor T15 is coupled to the third node n3, and the first electrode of the fifteenth transistor T15 is coupled to the fifth clock signal terminal CK2. In some other embodiments, the control electrode and the first electrode of the fifteenth transistor T15 may be coupled to other nodes or signal terminals, for example, the control electrode of the fifteenth transistor T15 is coupled to the cascade signal output terminal GP, and the first electrode of the fifteenth transistor T15 is coupled to the second voltage terminal VDD.

[0161] 12, a driving process of one row of gate lines includes at least an input stage P1, an output stage P2, and a holding stage P3, where the holding stage P3 includes at least a first holding period P31 and a second holding period P32.

[0162] For illustrative purposes, in the following description, "0" represents a low level and "1" represents a high level.

[0163] At the input stage P1, Iput=0, CK1=0, CB1=1, CK2=0, CK3=0, CB3=1.

[0164] In this case, the seventh transistor T7 is turned on under the control of a low-level signal from the third clock signal terminal CK3, and the input signal terminal Iput outputs a low-level signal to the first node n1. The eighth transistor T8 is turned on under the control of a low-level voltage from the first node n1, and the ninth transistor T9 is turned on under the control of a low-level signal from the third clock signal terminal CK3. Therefore, the voltage of the second node n2 is a low-level voltage.

[0165] The tenth transistor T10 is turned on under the control of the low-level voltage of the second node n2 and is connected to the high-level voltage V DD is transmitted to the cascade signal output terminal GP via the tenth transistor T10. The twelfth transistor T12 is turned on under the control of the first voltage terminal VSS, and transmits the low-level voltage of the first node n1 to the third node n3 and the control electrode of the eleventh transistor T11, so that the eleventh transistor T11 is turned on. As a result, the eleventh transistor T11 transmits the high-level signal of the fourth clock signal terminal CB3 to the cascade signal output terminal GP. Therefore, the voltage of the cascade signal output terminal GP becomes the high-level voltage V DD It is.

[0166] At this time, the fourth capacitor C4 is charged, the voltage of one end thereof coupled to the third node n3 is a low-level voltage, and the voltage of one end thereof coupled to the first electrode of the eleventh transistor T11 is a high-level voltage, thereby realizing the writing of a signal transmitted to the input signal terminal Iput.

[0167] Both the third transistor T3 and the fourth transistor T4 are turned off under the control of the high-level voltage of the cascade signal output terminal GP.

[0168] The first transistor T1 is turned on under the control of a low-level signal output from the first clock signal terminal CK1, and the voltage of the second noise elimination control node PD-ox-i is set to a low-level voltage V SS and the second transistor T2 is connected to the low-level voltage V SS The voltage of the first noise elimination control node PD-ox is turned on under the control of the low-level voltage V SS As a result, the sixth transistor T6 is turned on, and the voltage of the scanning signal output terminal Oput becomes the low-level voltage V SS Thus, the noise elimination subcircuit 30 realizes noise elimination for the scanning signal output terminal Oput.

[0169] The fourteenth transistor T14 is connected to the low-level voltage V SS The fourteenth transistor T14 is turned on under the control of the high-level signal of the fourth clock signal terminal CB3. The fourteenth transistor T14 transmits the high-level voltage of the second voltage terminal VDD coupled to its first electrode to the fourth node n4. At this time, the thirteenth transistor T13 is turned off under the control of the high-level signal of the fourth clock signal terminal CB3. As a result, the voltage of the fourth node n4 becomes equal to the high-level voltage V DD It is.

[0170] The fifteenth transistor T15 is turned on under the control of the low-level voltage of the third node n3, and the low-level voltage output from the fifth clock signal terminal CK2 is transmitted to the scanning signal output terminal Oput via the fifteenth transistor T15, so that a low-level scanning signal is output from the scanning signal output terminal Oput.

[0171] At the output stage P2, Iput=1, CK1=1, CB1=0, CK2=1, CK3=1, CB3=0.

[0172] In this case, the seventh transistor T7 is turned off under the control of the high-level signal of the third clock signal terminal CK3, and the voltage of the first node n1 is still a low-level voltage. The eighth transistor T8 is turned on under the control of the low-level voltage of the first node n1, and the high-level signal of the third clock signal terminal CK3 is transmitted to the second node n2 through the eighth transistor T8. The ninth transistor T9 is turned off under the control of the high-level signal of the third clock signal terminal CK3. Therefore, the voltage of the second node n2 is a high-level voltage.

[0173] The tenth transistor T10 is turned off under the control of the high-level voltage of the second node n2. The twelfth transistor T12 is turned on under the control of the first voltage terminal VSS to transmit the low-level voltage of the first node n1 to the third node n3 and the control electrode of the eleventh transistor T11, and the eleventh transistor T11 is turned on. As a result, the eleventh transistor T11 transmits the low-level signal of the fourth clock signal terminal CB3 to the cascade signal output terminal GP. Therefore, the voltage of the cascade signal output terminal GP is a low-level voltage.

[0174] At this time, the voltage of one end of the fourth capacitor C4 coupled to the first electrode of the eleventh transistor T11 is a low-level voltage. SS , the voltage of the high-level signal is V DD Then, the voltage at one end of the fourth capacitor C4 coupled to the first electrode of the eleventh transistor T11 is V DD From V SS The voltage drop is V DD -V SS Due to the capacitive bootstrap effect of the fourth capacitor C4, the voltage of the third node n3 coupled to the other terminal of the fourth capacitor C4 is further increased by V DD -V SS The voltage at the third node n3 is pulled down by 100 ms, and the ... SS to 2V SS -V DD Descend to.

[0175] The fifteenth transistor T15 is turned on under the control of the low-level voltage of the third node n3, and the high-level voltage output from the fifth clock signal terminal CK2 is transmitted to the scanning signal output terminal Oput via the fifteenth transistor T15, whereby a high-level scanning signal is output from the scanning signal output terminal Oput, thereby achieving scanning of the gate lines.

[0176] The third transistor T3 and the fourth transistor T4 are both turned on under the control of the low-level voltage of the cascade signal output terminal GP. Then, the signal of the second signal terminal CN is transmitted to the second noise removal control node PD-ox-i via the third transistor T3, and transmitted to the first noise removal control node PD-ox via the fourth transistor T4. Since the second signal terminal CN is the second voltage terminal VDD or the second node n2 (the voltage at the output stage P2 of the second node n2 is a high-level voltage), the voltages of the second noise removal control node PD-ox-i and the first noise removal control node PD-ox are both high-level voltages. As a result, the sixth transistor T6 is turned off, and does not affect the output of a high-level scanning signal from the scanning signal output terminal Oput.

[0177] At this time, the first transistor T1 is turned off under the control of a high-level signal output from the first clock signal terminal CK1, and the second transistor T2 is also turned off under the control of the high-level voltage of the second noise removal control node PD-ox-i.

[0178] Also, the fourteenth transistor T14 is turned off under the control of the high-level voltage of the second node n2. The thirteenth transistor T13 is turned on under the control of the low-level signal of the fourth clock signal terminal CB3. Therefore, the voltage of the fourth node n4 is equal to the voltage of the first node n1, that is, a low-level voltage.

[0179] In the first hold period P31 of the hold stage P3, Iput=1, CK1=0, CB1=1, CK2=0, CK3=0, and CB3=1.

[0180] In this case, the seventh transistor T7 is turned on under the control of a low-level signal from the third clock signal terminal CK3, and a high-level signal from the input signal terminal Iput is transmitted to the first node n1 via the seventh transistor T7. This causes the voltage of the first node n1 to become a high-level voltage. The eighth transistor T8 is turned off under the control of the high-level voltage from the first node n1. The ninth transistor T9 is turned on under the control of a low-level signal from the third clock signal terminal CK3, and a low-level signal from the first signal terminal VSS is transmitted to the second node n2 via the ninth transistor T9. This causes the voltage of the second node n2 to become a low-level voltage V SS to.

[0181] The tenth transistor T10 is turned on under the control of the low-level voltage of the second node n2, and the high-level voltage of the second voltage terminal VDD is transmitted to the cascade signal output terminal GP via the tenth transistor T10. The twelfth transistor T12 is turned on under the control of the first voltage terminal VSS, and transmits the high-level voltage of the first node n1 to the third node n3 and the control electrode of the eleventh transistor T11, and the eleventh transistor T11 is turned off. Therefore, the voltage of the cascade signal output terminal GP is a high-level voltage.

[0182] At this time, both the third transistor T3 and the fourth transistor T4 are turned off under the control of the high-level voltage of the cascade signal output terminal GP.

[0183] The first transistor T1 is turned on under the control of a low-level signal output from the first clock signal terminal CK1. Then, the voltage of the second noise removal control node PD-ox-i becomes a low-level voltage V SS The voltage at one end of the first capacitor C1, which is connected to the second noise removal control node PD-ox-i, is the low-level voltage V SS The voltage of the first capacitor C1 at one end connected to the second clock signal terminal CB1 is the voltage of the high-level signal at the second clock signal terminal CB1. The voltage of the high-level signal output from the second clock signal terminal CB1 is set to the high-level voltage V DDThen, the voltage at the end of the first capacitor C1 connected to the second clock signal terminal CB1 is the high-level voltage V DD It is.

[0184] The second transistor T2 is connected to the low-level voltage V SS The voltage of the first noise elimination control node PD-ox is turned on under the control of the low-level voltage V SS As a result, the sixth transistor T6 is turned on, and the voltage of the scanning signal output terminal Oput becomes the low-level voltage V SS Thus, the noise elimination subcircuit 30 realizes noise elimination for the scanning signal output terminal Oput.

[0185] The fourteenth transistor T14 is connected to the low-level voltage V SS The fourteenth transistor T14 is turned on under the control of the high-level voltage V DD to the fourth node n4. At this time, the thirteenth transistor T13 is turned off under the control of the high-level signal of the fourth clock signal terminal CB3. As a result, the voltage of the fourth node n4 becomes the high-level voltage V DD It is.

[0186] The fifteenth transistor T15 is turned off under the control of the high-level voltage of the third node n3.

[0187] In the second holding stage P32 of the holding stage P3, Iput=1, CK1=1, CB1=0, CK2=1, CK3=1, CB3=0.

[0188] In this case, the seventh transistor T7 is turned off under the control of the high-level signal of the third clock signal terminal CK3, the voltage of the first node n1 is still at a high-level voltage, the eighth transistor T8 is turned off under the control of the high-level voltage of the first node n1, the ninth transistor T9 is turned off under the control of the high-level signal of the third clock signal terminal CK3, and the voltage of the second node n2 is still at a low-level voltage.

[0189] The tenth transistor T10 is turned on under the control of the low-level voltage of the second node n2, and the high-level voltage of the second voltage terminal VDD is transmitted to the cascade signal output terminal GP via the tenth transistor T10. The twelfth transistor T12 is turned on under the control of the first voltage terminal VSS, and transmits the high-level voltage of the first node n1 to the third node n3 and the control electrode of the eleventh transistor T11, and the eleventh transistor T11 is turned off. Therefore, the voltage of the cascade signal output terminal GP is a high-level voltage.

[0190] At this time, both the third transistor T3 and the fourth transistor T4 are turned off under the control of the high-level voltage of the cascade signal output terminal GP.

[0191] The first transistor T1 is turned off under the control of the high-level signal output from the first clock signal terminal CK1, and the second noise removal control node PD-ox-i is in a floating state. The voltage of one end of the first capacitor C1 connected to the second clock signal terminal CB1 is the voltage of the low-level signal of the second clock signal terminal CB1, that is, the low-level voltage V SS Then, the voltage at the end of the first capacitor C1 connected to the second clock signal terminal CB1 is V DD to low level voltage V SS The voltage drop is V SS -V DD It is.

[0192] Due to the coupling effect of the first capacitor C1, the voltage of the second noise removal control node PD-ox-i shifts, and the offset amount is

number

number

[0193] At this time, the voltage of the first noise elimination control node PD-ox is the low-level voltage V SS and the voltage of the second noise removal control node PD-ox-i is

number

number

number

[0194] After that, the signals of the first clock signal terminal CK1 and the second clock signal terminal CB1 alternately become high level signals and low level signals, that is, in the holding stage P3, the first holding period P31 and the second holding period P32 alternate, so that the coupling of the first noise removal control node PD-ox and the second noise removal control node PD-ox-i is performed multiple times, and the voltage is averaged multiple times. Eventually, the voltage of the first noise removal control node PD-ox stabilizes near a certain voltage. The voltage change of the first noise removal control node PD-ox is as shown in the waveform in FIG. 12. As a result, the sixth transistor T6 continues to be on in the holding stage P3 and continues to perform noise removal for the scanning signal output terminal Oput.

[0195] For example, C 1 is large enough, C PD-ox-i ≒C 1 If it is considered that 1 C PD-ox-i The proportion of the above is relatively large, for example, the proportion can be understood to be 90% or more), and the numerical values ​​related to the above derivation process can be referred to the following explanation.

[0196] Due to the coupling effect of the first capacitor C1, the voltage offset of the second noise elimination control node PD-ox-i is V SS -V DD Therefore, the voltage of the second noise removal control node PD-ox-i is V SS From V SS +(V SS -V DD )=2V SS -V DD Descend to.

[0197] At this time, the voltage of the first noise elimination control node PD-ox is the low-level voltage V SS and the voltage of the second noise elimination control node PD-ox-i is 2V SS -V DDTherefore, the second transistor T2 is turned on, and about half of the charge flows from the first noise removal control node PD-ox to the second noise removal control node PD-ox-i. Therefore, the voltage of the first noise removal control node PD-ox becomes [(2V SS -V DD )+V SS ] / 2=(3V SS -V DD ) / 2, that is, the voltage of the first noise removal control node PD-ox is V SS From (3V SS -V DD ) / 2.

[0198] Thereafter, the signals at the first clock signal terminal CK1 and the second clock signal terminal CB1 alternate between high level and low level signals, i.e., in the holding stage P3, the first holding period P31 and the second holding period P32 alternate. Therefore, the coupling between the first noise removal control node PD-ox and the second noise removal control node PD-ox-i is performed multiple times, and the voltage is averaged multiple times. Finally, the voltage at the first noise removal control node PD-ox reaches 2V SS -V DD As a result, the sixth transistor T6 continues to be on during the holding stage P3, and continues to perform noise removal for the scanning signal output terminal Oput.

[0199] In the second hold period P32, the fourteenth transistor T14 is turned on under the control of the low-level voltage of the second node n2. The fourteenth transistor T14 is turned on under the control of the high-level voltage V DD to the fourth node n4. At this time, the thirteenth transistor T13 is turned on under the control of the low-level signal of the fourth clock signal terminal CB3. As a result, the voltage of the fourth node n4 becomes the high-level voltage V DD In this way, the thirteenth transistor T13 and the fourteenth transistor T14 both control the second voltage terminal VDD to charge the first node n1, thereby keeping the first node n1 at a high level voltage and ensuring that the eleventh transistor T11 is in an off state.

[0200] The fifteenth transistor T15 is turned off under the control of the high-level voltage of the third node n3.

[0201] In some other embodiments, as shown in Figures 13 and 14, when the third clock signal terminal CK3 and the fourth clock signal terminal CB3 coupled to the input sub-circuit 10 in the shift register circuit RS are respectively coupled to the first clock signal terminal CK1 and the second clock signal terminal CB1, the driving sequence of the shift register circuit RS may be as shown in Figure 15, and the specific driving process of the circuit may refer to the previous description, so that it will not be further described here.

[0202] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto, and any modifications or replacements that can be conceived by a person skilled in the art within the technical scope of the present disclosure are included within the technical scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be governed by the scope of protection described in the claims.

Claims

1. A shift register circuit, comprising: a noise reduction control subcircuit and a noise reduction subcircuit; the noise rejection control subcircuit is coupled to a first voltage terminal, a first clock signal terminal, a second clock signal terminal, and a first noise rejection control node; the noise reduction control subcircuit is configured to generate an alternating voltage signal from the voltage of the first voltage terminal and the signal of the second clock signal terminal in response to a signal of the first clock signal terminal, rectify the alternating voltage signal, and output a signal to the first noise reduction control node, thereby maintaining the voltage of the first noise reduction control node at a voltage that turns on the noise reduction subcircuit; the noise reduction subcircuit is coupled to the first noise reduction control node and a scan signal output terminal; The noise reduction subcircuit is configured to provide noise reduction to the scan signal output terminal in response to a voltage at the first noise reduction control node.

2. The noise reduction control subcircuit comprises: a first on-control sub-circuit coupled to the first clock signal terminal, the second clock signal terminal, the first voltage terminal, and a second noise reduction control node, the first on-control sub-circuit configured to periodically output a first level voltage to the second noise reduction control node in response to a signal at the first clock signal terminal, and to adjust the voltage of the second noise reduction control node based on the signal at the second clock signal terminal, thereby causing an alternating voltage signal to be provided to the second noise reduction control node; 2. The shift register circuit of claim 1, further comprising: a second on control sub-circuit coupled to the first noise reduction control node and the second noise reduction control node, the second on control sub-circuit configured to rectify the alternating voltage signal provided by the second noise reduction control node and output a signal to the first noise reduction control node in response to the alternating voltage signal provided by the second noise reduction control node.

3. The first on-control sub-circuit comprises: a first capacitor having a first terminal coupled to the second clock signal terminal and a second terminal coupled to the second noise rejection control node; and / or The second on-control sub-circuit includes:

3. The shift register circuit of claim 2 including a second transistor having a control electrode coupled to the second noise reduction control node, a first electrode coupled to the first noise reduction control node, and a second electrode coupled to the second noise reduction control node.

4. The first on-control sub-circuit comprises:

4. The shift register circuit of claim 3, further comprising a first transistor having a control electrode coupled to said first clock signal terminal, a first electrode receiving said first level, and a second electrode coupled to said second noise rejection control node.

5. The noise reduction subcircuit comprises:

2. The shift register circuit of claim 1, further comprising a sixth transistor having a control electrode coupled to said first noise filtering control node, a first electrode coupled to said first voltage terminal, and a second electrode coupled to said scan signal output terminal.

6. The shift register circuit of any one of claims 1 to 5, further comprising an output subcircuit coupled to a second voltage terminal or a fifth clock signal terminal, further coupled to the scan signal output terminal, and configured to transmit a signal of the second voltage terminal or the fifth clock signal terminal to the scan signal output terminal in response to an on signal transmitted from an input subcircuit.

7. 7. The shift register circuit of claim 6, further comprising: an input sub-circuit coupled to a cascade signal output terminal and to the output sub-circuit, the input sub-circuit configured to control a voltage of the cascade signal output terminal and further configured to transmit an on signal to the output sub-circuit.

8. The input subcircuit comprises: a tenth transistor having a control electrode coupled to a second node, a first electrode coupled to the second voltage terminal, and a second electrode coupled to the cascade signal output terminal; 8. The shift register circuit of claim 7 further comprising: a third capacitor having a first terminal coupled to the second node and a second terminal coupled to the first electrode of the tenth transistor and to the second voltage terminal.

9. 1. A gate drive circuit comprising a plurality of cascaded shift register circuits, The shift register circuit is a gate drive circuit according to any one of claims 1 to 5.

10. A plurality of gate lines; A display device including the gate drive circuit according to claim 9, A display device, wherein each shift register circuit in the gate drive circuit is coupled to at least one gate line.

11. The display device according to claim 10 , wherein a scanning signal output terminal of each shift register circuit in the gate drive circuit is coupled to at least one gate line.

12. A method for driving the shift register circuit according to any one of claims 1 to 5, comprising: In the holding phase, a noise reduction control subcircuit of the shift register circuit, in response to a signal at a first clock signal terminal, generates an alternating voltage signal from the voltage at the first voltage terminal and the signal at the second clock signal terminal, rectifies the generated alternating voltage signal, and outputs the signal to a first noise reduction control node, thereby maintaining the voltage of the first noise reduction control node at a voltage that turns on the noise reduction subcircuit; The noise reduction sub-circuit performs noise reduction on the scan signal output terminal in response to a voltage at the first noise reduction control node being a voltage that turns on the noise reduction sub-circuit.

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