Shift register and drive method of the same, gate drive circuit, and display device

Abstract

To provide a shift register and a drive method of the shift register, a gate drive circuit, and a display device.SOLUTION: A shift register 10 includes a blanking input circuit 100, a blanking control circuit 200, a blanking pull-down circuit 300, and a shift register circuit 1000. The blanking input circuit provides a first control node H with a blanking input signal STU1 on the basis of a second clock signal CLKB. The blanking control circuit provides a second control node N with a first clock signal CLKA on the basis of a voltage of the first control node, and retains a voltage difference between the first control node and second control node. The blanking pull-down circuit provides a pull-down node Q with a voltage of the second control node on the basis of the first clock signal. The shift register circuit provides a shift signal via a shift signal output terminal CR on the basis of a voltage of the pull-down node, and provides a first drive signal via a first drive signal output terminal OUT1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit and a display device. [Background technology]

[0002] With the development of display technology, compared with traditional liquid crystal display (LCD) devices, the new generation of organic light emitting diode (OLED) display devices have the advantages of lower manufacturing costs, faster response speed, higher contrast, wider viewing angle, wider operating temperature range, no need for a backlight unit, vivid colors, lighter and thinner, etc. Therefore, OLED display technology has become the display technology with the fastest development speed at present.

[0003] In order to improve the process integration of OLED panels and reduce costs, gate driver on array (GOA) technology is generally used to integrate thin film transistor (TFT) gate driving circuits on the array substrate of the display panel, thereby achieving scanning drive for the display panel. The gate driving circuits integrated on the array substrate using this GOA technology are also called GOA units or shift registers. Display devices using GOA circuits can reduce costs in two aspects: material costs and manufacturing processes, as parts related to the driving circuits are omitted. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. [Means for solving the problem]

[0005] A first aspect of the present disclosure provides a shift register. The shift register may include a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit. The blanking input circuit can provide a blanking input signal from the blanking input signal terminal to a first control node based on a second clock signal from the second clock signal terminal. The blanking control circuit can provide a first clock signal from the first clock signal terminal to a second control node based on a voltage of the first control node, and can hold a voltage difference between the first control node and the second control node. The blanking pull-down circuit can provide a voltage of the second control node to the pull-down node based on the first clock signal. The shift register circuit is configured to provide a shift signal via the shift signal output terminal and provide a first drive signal via the first drive signal output terminal based on a voltage of the pull-down node.

[0006] In an embodiment of the present disclosure, the blanking control circuit may include a second transistor and a first capacitor, a control electrode of the second transistor coupled to the first control node, a first electrode of the second transistor coupled to the first clock signal terminal, and a second electrode of the second transistor coupled to the second control node, and the first capacitor coupled between the first control node and the second control node.

[0007] In an embodiment of the present disclosure, the blanking input circuit may comprise a first transistor, a control electrode of the first transistor coupled to the second clock signal terminal, a first electrode of the first transistor coupled to the blanking input signal terminal, and a second electrode of the first transistor coupled to the first control node.

[0008] In an embodiment of the present disclosure, the blanking pull-down circuit may include a third transistor, a control electrode of the third transistor coupled to the first clock signal terminal, a first electrode of the third transistor coupled to the second control node, and a second electrode of the third transistor coupled to the pull-down node.

[0009] In an embodiment of the present disclosure, the shift register may further include a display input circuit and an output circuit. The display input circuit can provide a first voltage from a first voltage terminal to the pull-down node based on a display input signal from a display input signal terminal. The output circuit can output a shift signal from a shift signal output terminal and output a first drive signal from a first drive signal output terminal based on the voltage of the pull-down node.

[0010] In an embodiment of the present disclosure, the display input circuit may include a fourth transistor, a control electrode of the fourth transistor coupled to the display input signal terminal, a first electrode of the fourth transistor coupled to the first voltage terminal, and a second electrode of the fourth transistor coupled to the pull-down node.

[0011] In an embodiment of the present disclosure, the output circuit may include a 19th transistor, a 22nd transistor, and a second capacitor. A control electrode of the 19th transistor is coupled to the pull-down node, a first electrode of the 19th transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal, and a second electrode of the 19th transistor is coupled to the shift signal output terminal. A control electrode of the 22nd transistor is coupled to the pull-down node, a first electrode of the 22nd transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal, and a second electrode of the 22nd transistor is coupled to the first drive signal output terminal. A second capacitor is coupled between the pull-down node and the shift signal output terminal.

[0012] In an embodiment of the present disclosure, the shift register circuit may further include a first control circuit, a pull-up circuit, and a second control circuit. The first control circuit can control the voltage of the pull-up node based on the voltage of the pull-down node. The pull-up circuit can provide a second voltage from a second voltage terminal to the pull-down node, the shift signal output terminal, and the drive signal output terminal based on the voltage of the pull-up node. The second control circuit can control the voltage of the pull-up node based on the first clock signal and the voltage of the first control node, and control the voltage of the pull-up node based on the indication input signal.

[0013] In an embodiment of the present disclosure, the pull-up node may comprise a first pull-up node. The first control circuit may comprise a seventh transistor and an eighth transistor. A control electrode and a first electrode of the seventh transistor are coupled to a third voltage terminal, and a second electrode of the seventh transistor is coupled to the first pull-up node. A control electrode of the eighth transistor is coupled to the pull-down node, a first electrode of the eighth transistor is coupled to the first pull-up node, and a second electrode of the eighth transistor is coupled to the second voltage terminal. The pull-up circuit may comprise a ninth transistor, a twentieth transistor, and a twenty-third transistor. A control electrode of the ninth transistor is coupled to the first pull-up node, a first electrode of the ninth transistor is coupled to the pull-down node, and a second electrode of the ninth transistor is coupled to the second voltage terminal. A control electrode of the twentieth transistor is coupled to the first pull-up node, a first electrode of the twentieth transistor is coupled to the shift signal output terminal, and a second electrode of the twentieth transistor is coupled to the second voltage terminal. A control electrode of the twenty-third transistor is coupled to the first pull-up node, a first electrode of the twenty-third transistor is coupled to the first drive signal output terminal, and a second electrode of the twenty-third transistor is coupled to the second voltage terminal. The second control circuit may comprise a thirteenth transistor, a fourteenth transistor and a fifteenth transistor. A control electrode of the thirteenth transistor is coupled to the first clock signal terminal and a first electrode of the thirteenth transistor is coupled to the first pull-up node. A control electrode of the fourteenth transistor is coupled to the first control node, a first electrode of the fourteenth transistor is coupled to the second electrode of the thirteenth transistor and a second electrode of the fourteenth transistor is coupled to the second voltage terminal. A control electrode of the fifteenth transistor is coupled to the display input signal terminal, a first electrode of the fifteenth transistor is coupled to the first pull-up node and a second electrode of the fifteenth transistor is coupled to the second voltage terminal.

[0014] In an embodiment of the present disclosure, the pull-up node may further comprise a second pull-up node. The first control circuit further comprises a tenth transistor and an eleventh transistor. A control electrode and a first electrode of the tenth transistor are coupled to a fourth voltage terminal, and a second electrode of the tenth transistor is coupled to the second pull-up node. A control electrode of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the second pull-up node, and a second electrode of the eleventh transistor is coupled to the second voltage terminal. The pull-up circuit may further comprise a twelfth transistor, a twenty-first transistor, and a twenty-fourth transistor. A control electrode of the twelfth transistor is coupled to the second pull-up node, a first electrode of the twelfth transistor is coupled to the pull-down node, and a second electrode of the twelfth transistor is coupled to the second voltage terminal. A control electrode of the twenty-first transistor is coupled to the second pull-up node, a first electrode of the twenty-first transistor is coupled to the shift signal output terminal, and a second electrode of the twenty-first transistor is coupled to the second voltage terminal. A control electrode of the 24th transistor is coupled to the second pull-up node, a first electrode of the 24th transistor is coupled to the first drive signal output terminal, and a second electrode of the 24th transistor is coupled to the second voltage terminal. The second control circuit may further comprise a 16th transistor, a 17th transistor, and an 18th transistor. A control electrode of the 16th transistor is coupled to the first clock signal terminal, and a first electrode of the 16th transistor is coupled to the second pull-up node. A control electrode of the 17th transistor is coupled to the first control node, a first electrode of the 17th transistor is coupled to the second electrode of the 16th transistor, and a second electrode of the 17th transistor is coupled to the second voltage terminal. A control electrode of the 18th transistor is coupled to the display input signal terminal, a first electrode of the 18th transistor is coupled to the second pull-up node, and a second electrode of the 18th transistor is coupled to the second voltage terminal.

[0015] In an embodiment of the present disclosure, the shift register circuit may further include a reset circuit, which can reset the pull-down node based on a blanking reset signal from a blanking reset signal terminal, and can reset the pull-down node based on a display reset signal from a display reset signal terminal.

[0016] In an embodiment of the present disclosure, the reset circuit may include a fifth transistor and a sixth transistor, a control electrode of the fifth transistor is coupled to the blanking reset signal terminal, a first electrode of the fifth transistor is coupled to the pull-down node, and a second electrode of the fifth transistor is coupled to the second voltage terminal, a control electrode of the sixth transistor is coupled to the display reset signal terminal, a first electrode of the sixth transistor is coupled to the pull-down node, and a second electrode of the sixth transistor is coupled to the second voltage terminal.

[0017] In an embodiment of the present disclosure, the output circuit may further comprise a 25th transistor and a third capacitor. A control electrode of the 25th transistor is coupled to the pull-down node, a first electrode of the 25th transistor is coupled to the fifth clock signal terminal for receiving a fifth clock signal, and a second electrode of the 25th transistor is coupled to the second drive signal output terminal. The third capacitor is coupled between the pull-down node and the second drive signal output terminal.

[0018] In an embodiment of the present disclosure, the pull-up circuit may further comprise a 26th transistor and a 27th transistor, a control electrode of the 26th transistor coupled to the first pull-up node, a first electrode of the 26th transistor coupled to the second drive signal output terminal, and a second electrode of the 26th transistor coupled to the second voltage terminal, a control electrode of the 27th transistor coupled to the second pull-up node, a first electrode of the 27th transistor coupled to the second drive signal output terminal, and a second electrode of the 27th transistor coupled to the second voltage terminal.

[0019] A second aspect of the present disclosure provides a gate driver circuit. The gate driver circuit may comprise N cascaded shift registers according to the first aspect of the present disclosure, a first sub-clock signal line and a second sub-clock signal line. A blanking input signal terminal of the (i+1)th level shift register is coupled to a shift signal output terminal of the i-th level shift register. A first clock signal terminal of the shift register of each level is coupled to the first sub-clock signal line. A second clock signal terminal of the shift register of each level is coupled to the second sub-clock signal line.

[0020] In an embodiment of the present disclosure, the gate driver circuit may further include a blanking reset signal line, a first sub-clock signal line and a second sub-clock signal line. The display input signal terminal of the shift register of the (i+2)th level is coupled to the shift signal output terminal of the shift register of the (i)th level. The blanking reset signal terminal of the shift register of each level is coupled to the blanking reset signal line. The display reset signal terminal of the shift register of the (i+3)th level is coupled to the shift signal output terminal of the shift register of the (i+3)th level.

[0021] In an embodiment of the present disclosure, the gate driver circuit may further include a third sub-clock signal line, a fourth sub-clock signal line, a fifth sub-clock signal line and a sixth sub-clock signal line. The fourth clock signal terminal of the shift register of the 4i-3th level is coupled to the third sub-clock signal line. The fourth clock signal terminal of the shift register of the 4i-2th level is coupled to the fourth sub-clock signal line. The fourth clock signal terminal of the shift register of the 4i-1th level is coupled to the fifth sub-clock signal line. The fourth clock signal terminal of the shift register of the 4ith level is coupled to the sixth sub-clock signal line.

[0022] In an embodiment of the present disclosure, the gate driver circuit may further include a seventh sub-clock signal line, an eighth sub-clock signal line, a ninth sub-clock signal line and a tenth sub-clock signal line. The fifth clock signal terminal of the shift register of the 4i-3th level is coupled to the seventh sub-clock signal line. The fifth clock signal terminal of the shift register of the 4i-2th level is coupled to the eighth sub-clock signal line. The fifth clock signal terminal of the shift register of the 4i-1th level is coupled to the ninth sub-clock signal line. The fifth clock signal terminal of the shift register of the 4ith level is coupled to the tenth sub-clock signal line.

[0023] A third aspect of the present disclosure provides a display device comprising a gate drive circuit according to the second aspect of the present disclosure.

[0024] A fourth aspect of the present disclosure provides a method for driving the shift register according to the first aspect of the present disclosure, the method including: providing a blanking input signal to a first control node, maintaining a voltage difference between the first control node and a second control node, providing a first clock signal to the second control node based on the voltage of the first control node, and controlling the voltage of the first control node according to the voltage difference, providing the voltage of the second control node to a pull-down node based on the first clock signal, and outputting a shift signal and a first drive signal based on the voltage of the pull-down node. [Brief description of the drawings]

[0025] In order to more clearly describe the technical solutions of the present disclosure, the drawings of the embodiments are briefly described below. It should be understood that the drawings described below are merely some embodiments of the present disclosure, and are not intended to limit the present disclosure, and the same drawing designations represent the same elements or signals.

[0026] [Figure 1] FIG. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure. [Diagram 3]FIG. 3 illustrates an example circuit diagram of a shift register according to an embodiment of the present disclosure. [Figure 4] 4(1), 4(2), and 4(3) each show an exemplary circuit diagram of a display input circuit according to an embodiment of the present disclosure. [Diagram 5] 5(1) and 5(2) each show an exemplary circuit diagram of a second control circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure. [Figure 7] FIG. 7 shows a schematic diagram of a gate drive circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 shows a timing chart of each signal during the operation of the gate driving circuit according to the embodiment of the present disclosure. [Figure 9] FIG. 9 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Of course, the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on the described embodiments, all other embodiments that can be obtained by those skilled in the art without creative efforts belong to the scope of the present disclosure.

[0028] Unless otherwise defined, technical or scientific terms used in this disclosure should have the common meaning understood by a person skilled in the art to which this disclosure belongs. The terms "first", "second" and similar terms used in this disclosure are only for the purpose of distinguishing different components without indicating any order, number or importance. Similarly, similar terms such as "one", "one" or "the" are not used for the purpose of limiting the number, but indicate that there is at least one. The term "comprises" or similar terms means the inclusion of the listed object element or object and its equivalents, but does not exclude other elements or objects. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, and may be directly connected or indirectly connected through an intermediate medium. The terms "upper", "lower", "left", "right" and the like are used merely to indicate relative positional relationships, and if the absolute position of the described object is changed, the relative positional relationships may change accordingly.

[0029] In the display field, especially in organic light-emitting diode (OLED) display technology, the gate driver circuit is generally integrated into the integrated circuit IC. In the design of the integrated circuit IC, the chip area is the main factor that affects the chip cost. Generally, the gate driver circuit includes a detection circuit, a display circuit, and a connection circuit (or a gate circuit) that outputs a composite pulse of them. Such a circuit has a very complicated structure, which makes it difficult to meet the requirements of high resolution and narrow frame.

[0030] When compensating a subpixel of an OLED display panel, in addition to performing internal compensation by providing a pixel compensation circuit in the subpixel, external compensation can also be performed by providing a sense transistor. When performing external compensation, a gate driver circuit made of a shift register needs to provide driving signals for the scan transistor and the sense transistor to the subpixel of the display panel, respectively. For example, it provides a scan driving signal for the scan transistor in the display period of one frame, and provides a sense driving signal for the sense transistor in the blanking period of one frame.

[0031] In the embodiments of the present disclosure, "one frame", "each frame" or "a frame" includes a display period and a blanking period that are performed in sequence. For example, in the display period, the gate driving circuit outputs a display output signal, which can be used to drive a scanning transistor in the display panel, so as to perform scanning from the first row to the last row, so that the display panel performs display. In the blanking period, the gate driving circuit outputs a blanking output signal, which can be used to drive a sense transistor in a certain row of sub-pixels in the display panel to sense the driving current of the sub-pixels in the row, so as to perform compensation based on the sensed driving current.

[0032] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure provides a shift register, a driving method thereof, a gate driving circuit, and a display device.

[0033] 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure. As shown in FIG. 1, the shift register 10 may include a blanking input circuit 100, a blanking control circuit 200, a blanking pull-down circuit 300 and a shift register circuit 1000.

[0034] In an embodiment of the present disclosure, the blanking input circuit 100 can provide a blanking input signal STU1 from the blanking input signal terminal to the first control node H based on a second clock signal CLKB from the second clock signal terminal, so as to control the voltage of the first control node H. For example, the blanking input circuit 100 may be coupled to the second clock signal terminal to receive the second clock signal CLKB, and coupled to the blanking input signal terminal to receive the blanking input signal STU1.

[0035] The blanking control circuit 200 can provide a first clock signal CLKA from a first clock signal terminal to the second control node N based on the voltage of the first control node H, so as to control the voltage of the second control node N. The blanking control circuit 200 can further maintain a voltage difference between the first control node H and the second control node N. For example, the blanking control circuit 200 can be coupled to the first clock signal terminal to receive the first clock signal CLKA.

[0036] The blanking pull-down circuit 300 may provide a voltage of the second control node N to the pull-down node Q based on the first clock signal CLKA to control the voltage of the pull-down node Q. For example, the blanking pull-down circuit 300 may be coupled to a first clock signal terminal to receive the first clock signal CLKA.

[0037] In the embodiment, the blanking control circuit 200 can maintain a voltage difference between the first control node H and the second control node N, so that when the voltage of the second control node N changes, the voltage of the first control node H changes correspondingly, thereby providing the first clock signal CLKA to the second control node N losslessly. In this case, the blanking pull-down circuit 300 can provide the first clock signal CLKA (i.e., the voltage of the second control node N) to the pull-down node Q losslessly. This can eliminate the loss of the threshold voltage of the transistor when writing a low potential to the pull-down node Q during the blanking period.

[0038] In addition, since the blanking control circuit 200 and the blanking pull-down circuit 300 are installed between the first control node H and the pull-down node Q, it is possible to prevent the voltages of the first control node H and the second control node N from affecting the voltage of the pull-down node Q.

[0039] The shift register circuit 1000 can provide a shift signal through a shift signal output terminal and provide a first driving signal through a first driving signal output terminal under the control of the pull-down node Q. In a display period of one frame, the shift signal can be used for example for scanning shift of upper and lower level shift register units. The driving signal can be used for driving the scanning transistor in the display panel to drive the display panel to display. In a blanking period of one frame, the shift signal can be used for example for scanning shift of upper and lower level shift register units. The driving signal can be used for driving the sense transistor in the sub-pixel of the display panel, thereby performing external compensation of the sub-pixel of the row.

[0040] 2 shows a schematic block diagram of a shift register according to another embodiment of the present disclosure. As shown in FIG. 2, the shift register 20 may include a blanking input circuit 100, a blanking control circuit 200, a blanking pull-down circuit 300, and a shift register circuit 1000. In an embodiment, the shift register circuit 1000 may include a display input circuit 400 and an output circuit 500. In some other embodiments, the shift register circuit 1000 may further include a first control circuit 600, a pull-up circuit 700, and a second control circuit 800. In some other embodiments, the shift register circuit 1000 may further include a reset circuit 900.

[0041] 2 shows an example of a shift register circuit 1000 including a display input circuit 400, an output circuit 500, a first control circuit 600, a pull-up circuit 700, a second control circuit 800, and a reset circuit 900. The blanking input circuit 100, the blanking control circuit 200, and the blanking pull-down circuit 300 have already been described in detail above, so detailed description is omitted here. Each partial circuit in the shift register circuit 1000 will be mainly described below.

[0042] 2, the display input circuit 400 can provide a first voltage V1 from a first voltage terminal to the pull-down node Q according to a display input signal STU2 from the display input signal terminal, so as to control the voltage of the pull-down node Q. For example, the display input circuit 400 can be coupled to the display input signal terminal to receive the display input signal STU2, and coupled to the first voltage terminal to receive the first voltage V1. In an embodiment, the first voltage terminal can provide a DC low level signal, that is, the first voltage V1 is low level.

[0043] The output circuit 500 can output a shift signal from the shift signal output terminal CR and output a first drive signal from the first drive signal output terminal OUT1 based on the voltage of the pull-down node Q. For example, the output circuit 500 can be coupled to a fourth clock signal terminal to receive a fourth clock signal CLKD. The output circuit 500 can provide the fourth clock signal CLKD to the shift signal output terminal CR based on the voltage of the pull-down node Q to output the fourth clock signal CLKD as the shift signal, and provide the fourth clock signal CLKD to the first drive signal output terminal OUT1 to output the fourth clock signal CLKD as the first drive signal.

[0044] In an embodiment, the output circuit 500 can also output a second driving signal from the second driving signal output terminal OUT2 based on the voltage of the pull-down node Q. For example, the output circuit 500 can be coupled to a fifth clock signal terminal to receive a fifth clock signal CLKE. In an embodiment, the output circuit 500 can further provide a fifth clock signal CLKE to the second driving signal output terminal OUT2 based on the voltage of the pull-down node Q, so as to output the fifth clock signal CLKE as the second output signal. As can be understood by those skilled in the art, the number of driving signal output terminals is not limited to two, and may be more than two, and the output circuit can output a corresponding driving signal based on a corresponding clock signal. In an embodiment, in a display period, the shift signal and the corresponding driving signal can be collectively referred to as a display output signal, and in a blanking period, the shift signal and the corresponding driving signal can be collectively referred to as a blanking output signal.

[0045] The first control circuit 600 may control the voltage of the pull-up node QB based on the voltage of the pull-down node Q. For example, the first control circuit 600 may be coupled to a second voltage terminal to receive the second voltage V2 and coupled to a third voltage terminal to receive the third voltage V3. In an embodiment, the second voltage terminal may provide a DC high level signal, i.e., the second voltage V2 is high. The first control circuit 600 may control the voltage of the pull-up node QB based on the second voltage V2 and the third voltage V3 under the control of the voltage of the pull-down node Q.

[0046] In addition, the first control circuit 600 may be further coupled to a fourth voltage terminal to receive a fourth voltage V4. The third voltage terminal and the fourth voltage terminal may provide alternating DC and low level signals, for example, one of the third voltage V3 and the fourth voltage V4 is low level and the other is high level. In an embodiment, the first control circuit 600 may control the voltage of the pull-up node QB based on the second voltage V2 and the third voltage V3 (or the fourth voltage) under the control of the voltage of the pull-down node Q.

[0047] The pull-up circuit 700 can provide a second voltage V2 from a second voltage terminal to the pull-down node Q, the shift signal output terminal CR, the first drive signal output terminal OUT1, and the second drive signal output terminal OUT2 based on the voltage of the pull-up node QB. For example, the pull-up circuit 700 may be coupled to the second voltage terminal to receive the second voltage V2. Thus, the pull-up circuit 700 reduces noise at each terminal by pulling up the pull-down node Q, the shift signal output terminal CR, and the corresponding drive signal output terminal.

[0048] The second control circuit 800 can control the voltage of the pull-up node QB based on the first clock signal CLKA and the voltage of the first control node H. For example, the second control circuit 800 can be coupled to a first clock signal terminal to receive the first clock signal CLKA and coupled to a second voltage terminal to receive the second voltage. In an embodiment, the second control circuit 800 can provide a second voltage to the pull-up node QB under the control of the first clock signal CLKA and the voltage of the first control node H. In addition, the second control circuit 800 can further control the voltage of the pull-up node QB based on the display input signal STU2. For example, the second control circuit 800 can be coupled to a display input signal terminal to receive the display input signal STU2. In an embodiment, the second control circuit 800 can provide a second voltage to the pull-up node QB under the control of the display input signal STU. In this way, the second control circuit 800 can pull up the pull-up node QB.

[0049] It should be noted that the reset circuit 900 can reset the pull-down node Q based on a blanking reset signal TRST from a blanking reset signal terminal, and can reset the pull-down node Q based on a display reset signal STD from a display reset signal terminal. For example, the reset circuit 900 can be coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, coupled to the display reset signal terminal to receive the display reset signal STD, and coupled to the second voltage terminal to receive the second voltage V2. In an embodiment, the reset circuit 900 can provide the second voltage V2 to the pull-down node Q based on the blanking reset signal TRST, and provide the second voltage V2 to the pull-down node Q based on the display reset signal STD.

[0050] As can be understood by those skilled in the art, the shift register circuit 1000 in Fig. 2 includes a display input circuit 400, an output circuit 500, a first control circuit 600, a pull-up circuit 700, a second control circuit 800 and a reset circuit 900, but the above examples are not intended to limit the scope of protection of the present disclosure. In practical applications, those skilled in the art may use or not use one or more of the above circuits according to circumstances, and various combinations and modifications of the above circuits do not deviate from the principles of the present disclosure, and detailed descriptions are omitted here.

[0051] The shift register according to the present disclosure will now be described with reference to an exemplary circuit structure.

[0052] 3 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure. The shift register is, for example, the shift register 20 shown in FIG 2. As shown in FIG 3, the shift register may include a first transistor M1 to a twenty-seventh transistor M27 and a first capacitor C1 to a third capacitor C3.

[0053] As described, any transistor used in the embodiments of the present disclosure may be a thin film transistor or a field effect transistor or other switching device with the same characteristics. In the embodiments of the present disclosure, any transistor is described as an example. The source electrode and the drain electrode of the transistor used here may be structurally symmetrical, and therefore, the source electrode and the drain electrode may not be structurally distinguished. In the embodiments of the present disclosure, in order to distinguish two electrodes excluding the grid electrode of the transistor, one is directly described as a first electrode and the other is a second electrode. The grid electrode of the transistor may be referred to as a control electrode. In addition, if classified according to the characteristics of the transistor, the transistor may be divided into N-type and P-type transistors. When the transistor is a P-type transistor, the on voltage is a low level voltage (e.g., 0V, -5V, -10V or other suitable voltage), and the off voltage is a high level voltage (e.g., 5V, 10V or other suitable voltage). If the transistor is an N-type transistor, the on voltage is a high-level voltage (eg, 5V, 10V, or other suitable voltage) and the off voltage is a low-level voltage (eg, 0V, -5V, -10V, or other suitable voltage).

[0054] As described, the transistors used in the shift register according to the embodiment of the present disclosure are all P-type transistors, but the embodiment of the present disclosure is not limited thereto, and for example, at least some of the transistors in the shift register may be N-type transistors to change the potential of the corresponding voltages (first voltage, second voltage, etc.).

[0055] In the embodiment of the present disclosure, the pull-up node QB may include at least one of a first pull-up node QB_A and a second pull-up node QB_B. Figure 3 illustrates a situation where the pull-up node QB includes both the first pull-up node QB_A and the second pull-up node QB_B. It can be understood that the pull-up node QB may include only one of the first pull-up node QB_A and the second pull-up node QB_B, and the related circuitry can be adjusted accordingly.

[0056] 3, the blanking input circuit 100 includes a first transistor M1. A control electrode of the first transistor M1 is coupled to a second clock signal terminal to receive a second clock signal CLKB, a first electrode of the first transistor M1 is coupled to a blanking input signal terminal to receive a blanking input signal STU1, and a second electrode of the first transistor M1 is coupled to a first control node H. In an embodiment, when the second clock signal CLKB is at a low level, the first transistor M1 is turned on, thereby providing the blanking input signal to the first control node H to control the voltage of the first control node H.

[0057] The blanking control circuit 200 includes a second transistor M2 and a first capacitor C1. A control electrode of the second transistor M2 is coupled to a first control node H, a first electrode of the second transistor M2 is coupled to a first clock signal terminal to receive a first clock signal CLKA, and a second electrode of the second transistor M2 is coupled to a second control node N. A first terminal of the first capacitor is coupled to the first control node H, and a second terminal of the first capacitor is coupled to the second control node N. In an embodiment, when the voltage of the first control node H is at a low level, the second transistor M2 is turned on and provides the first clock signal CLKA to the second control node N to control the voltage of the second control node N. When the voltage of the second control node N changes, the voltage of the first control node H changes correspondingly because the first capacitor C1 holds the voltage difference between the first control node H and the second control node N.

[0058] The blanking pull-down circuit 300 includes a third transistor M3. A control electrode of the third transistor M3 is coupled to the first clock signal terminal to receive the first clock signal CLKA, a first electrode of the third transistor M3 is coupled to the second control node N, and a second electrode of the third transistor M3 is coupled to the pull-down node Q. In an embodiment, when the first clock signal CLKA is at a low level, the third transistor M3 is turned on and provides the voltage of the second control node N to the pull-down node Q.

[0059] The display input circuit 400 includes a fourth transistor M4. A control electrode of the fourth transistor M4 is coupled to a display input signal terminal to receive a display input signal STU2, a first electrode of the fourth transistor M4 is coupled to a first voltage terminal to receive a first voltage V1, and a second electrode of the fourth transistor M4 is coupled to a pull-down node Q. In an embodiment, when the display input signal STU2 is at a low level, the fourth transistor M4 is turned on and provides the first voltage V1 to the pull-down node Q, causing the voltage of the pull-down node Q to be at a low level.

[0060] The output circuit 500 includes a 19th transistor M19, a 22nd transistor M22, and a second capacitor C2. A control electrode of the 19th transistor M19 is coupled to the pull-down node Q, a first electrode of the 19th transistor M19 is coupled to the fourth clock signal terminal to receive the fourth clock signal CLKD, and a second electrode of the 19th transistor M19 is coupled to the shift signal output terminal CR. A control electrode of the 22nd transistor M22 is coupled to the pull-down node Q, a first electrode of the 22nd transistor M22 is coupled to the fourth clock signal terminal to receive the fourth clock signal CLKD, and a second electrode of the 22nd transistor M22 is coupled to the first drive signal output terminal OUT1. A first terminal of the second capacitor C2 is coupled to the pull-down node Q, and a second terminal of the second capacitor C2 is coupled to the shift signal output terminal CR.

[0061] In addition, the output circuit 500 may further include a 25th transistor M25 and a third capacitor C3. A control electrode of the 25th transistor M25 is coupled to the pull-down node Q, a first electrode of the 25th transistor M25 is coupled to the fifth clock signal terminal to receive the fifth clock signal CLKE, and a second electrode of the 25th transistor M25 is coupled to the second drive signal output terminal OUT2. A first terminal of the third capacitor C3 is coupled to the pull-down node Q, and a second terminal of the third capacitor C3 is coupled to the second drive signal output terminal OUT2.

[0062] In the embodiment, when the pull-down node Q is at a low level, the 19th transistor M19, the 22nd transistor M22, and the 25th transistor M25 are turned on to provide the fourth clock signal CLKD to the shift signal output terminal CR and the first drive signal output terminal OUT1, and provide the fifth clock signal CLKE to the second drive signal output terminal OUT2.

[0063] The first control circuit 600 includes a seventh transistor M7, an eighth transistor M8, a tenth transistor M10, and an eleventh transistor M11. A control electrode and a first electrode of the seventh transistor M7 are coupled to a third voltage terminal to receive a third voltage V3, and a second electrode of the seventh transistor M7 is coupled to a first pull-up node QB_A. A control electrode of the eighth transistor M8 is coupled to the pull-down node Q, a first electrode of the eighth transistor M8 is coupled to the first pull-up node QB_A, and a second electrode of the eighth transistor M8 is coupled to a second voltage terminal to receive a second voltage V2. A control electrode and a first electrode of the tenth transistor M10 are coupled to a fourth voltage terminal V4, and a second electrode of the tenth transistor M10 is coupled to a second pull-up node QB_B. A control electrode of the eleventh transistor M11 is coupled to the pull-down node Q, a first electrode of the eleventh transistor M11 is coupled to the second pull-up node QB_B, and a second electrode of the eleventh transistor M11 is coupled to a second voltage terminal V2 for receiving a second voltage V2.

[0064] It can be understood that when the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the first control circuit 600 may include the seventh transistor M7 and the eighth transistor M8 (or the tenth transistor M10 and the eleventh transistor M11). Since the specific circuit structures are similar, detailed description is omitted here.

[0065] In an embodiment, the third voltage terminal V3 and the fourth voltage terminal V4 may be configured to alternately provide a low level. That is, when the third voltage terminal V3 provides a high level, the fourth voltage terminal V4 provides a low level, and the tenth transistor M10 is turned on. When the third voltage terminal V3 provides a low level, the fourth voltage terminal V4 provides a high level, and the seventh transistor M7 is turned on. Thus, only one of the seventh transistor M7 and the tenth transistor M10 is in an on state. This can avoid performance drift caused by the transistor being turned on for a long period of time.

[0066] When the seventh transistor M7 is turned on, the third voltage can charge the first pull-up node QB_A, and when the tenth transistor M10 is turned on, the fourth voltage can charge the second pull-up node QB_B, thereby controlling the voltage of the first pull-up node QB_A or the second pull-up node QB_B to a low level. When the voltage of the pull-down node Q is at a low level, the eighth transistor M8 and the eleventh transistor M11 are turned on. For example, in the transistor design, the seventh transistor M7 and the eighth transistor M8 (e.g., their dimensional ratio, threshold voltage, etc.) may be configured such that when M7 and M8 are both turned on, the voltage of the first pull-up node QB_A is pulled up to a high level, which can keep the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor M26 off. Meanwhile, the tenth transistor M10 and the eleventh transistor M11 (e.g., their dimensional ratios, threshold voltages, etc.) may be configured such that when M10 and M11 are both on, the voltage of the second pull-up node QB_B is pulled up to a high level, which can hold the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 off.

[0067] As shown in FIG. 3, the pull-up circuit 700 includes a ninth transistor M9, a twentieth transistor M20, a twenty-third transistor M23, a twelfth transistor M12, a twenty-first transistor M21, a twenty-fourth transistor M24, a twenty-sixth transistor M26, and a twenty-seventh transistor M27.

[0068] A control electrode of the ninth transistor M9 is coupled to the first pull-up node QB_A, a first electrode of the ninth transistor M9 is coupled to the pull-down node Q, and a second electrode of the ninth transistor M9 is coupled to the second voltage terminal V2. A control electrode of the twentieth transistor M20 is coupled to the first pull-up node QB_A, a first electrode of the twentieth transistor M20 is coupled to the shift signal output terminal CR, and a second electrode of the twentieth transistor M20 is coupled to the second voltage terminal V2. A control electrode of the twenty-third transistor M23 is coupled to the first pull-up node QB_A, a first electrode of the twenty-third transistor M23 is coupled to the first drive signal output terminal OUT1, and a second electrode of the twenty-third transistor M23 is coupled to the second voltage terminal V2. A control electrode of the twenty-sixth transistor M26 is coupled to the first pull-up node QB_A, a first electrode of the twenty-sixth transistor M26 is coupled to the second drive signal output terminal OUT2, and a second electrode of the twenty-sixth transistor M26 is coupled to the second voltage terminal V2. In the embodiment, when the voltage of the first pull-up node QB_A is at a low level, the ninth transistor M9, the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor M24 are turned on to pull up the pull-down node Q, the shift signal output terminal CR, the first driving signal output terminal OUT1, and the second driving signal output terminal OUT2.

[0069] A control electrode of the twelfth transistor M12 is coupled to the second pull-up node QB_B, a first electrode of the twelfth transistor M12 is coupled to the pull-down node Q, and a second electrode of the twelfth transistor M12 is coupled to the second voltage terminal V2. A control electrode of the twenty-first transistor M21 is coupled to the second pull-up node QB_B, a first electrode of the twenty-first transistor M21 is coupled to the shift signal output terminal CR, and a second electrode of the twenty-first transistor M21 is coupled to the second voltage terminal V2. A control electrode of the twenty-fourth transistor M24 is coupled to the second pull-up node QB_B, a first electrode of the twenty-fourth transistor M24 is coupled to the first drive signal output terminal OUT1, and a second electrode of the twenty-fourth transistor M24 is coupled to the second voltage terminal V2. A control electrode of the twenty-seventh transistor M27 is coupled to the second pull-up node QB_B, a first electrode of the twenty-seventh transistor M27 is coupled to the second drive signal output terminal OUT2, and a second electrode of the twenty-seventh transistor M27 is coupled to the second voltage terminal V2. In the embodiment, when the voltage of the second pull-up node QB_B is at a low level, the twelfth transistor M12, the twenty-first transistor M21, the twenty-fourth transistor M24 and the twenty-seventh transistor M27 are turned on to pull up the pull-down node Q, the shift signal output terminal CR, the first driving signal output terminal OUT1 and the second driving signal output terminal OUT2.

[0070] It can be understood that when the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the pull-up circuit 700 may include the ninth transistor M9, the twentieth transistor M20, the twenty-third transistor M23, and the twenty-sixth transistor M26 (or the twelfth transistor M12, the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27). Since the specific circuit structures are the same, detailed description will be omitted here.

[0071] As shown in FIG. 3, the second control circuit 800 may include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18.

[0072] A control electrode of the thirteenth transistor M13 is coupled to the first clock signal terminal to receive the first clock signal CLKA, and a first electrode of the thirteenth transistor M13 is coupled to the first pull-up node QB_A. A control electrode of the fourteenth transistor M14 is coupled to the first control node H, a first electrode of the fourteenth transistor M14 is coupled to the second electrode of the thirteenth transistor M13, and a second electrode of the fourteenth transistor M14 is coupled to the second voltage terminal V2. A control electrode of the fifteenth transistor M15 is coupled to the display input signal terminal to receive the display input signal STU2, a first electrode of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and a second electrode of the fifteenth transistor M15 is coupled to the second voltage terminal to receive the second voltage V2. In the embodiment, when the voltages of the first clock signal CLKA and the first control node H are both at a low level, a second voltage is provided to the first pull-up node QB_A. Additionally, when the display input signal STU2 is at a low level, the second voltage is provided to the first pull-up node QB_A.

[0073] A control electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal to receive the first clock signal CLKA, and a first electrode of the sixteenth transistor M16 is coupled to the second pull-up node QB_B. A control electrode of the seventeenth transistor M17 is coupled to the first control node H, a first electrode of the seventeenth transistor M17 is coupled to the second electrode of the sixteenth transistor M16, and a second electrode of the seventeenth transistor M17 is coupled to the second voltage terminal to receive the second voltage V2. A control electrode of the eighteenth transistor M18 is coupled to the display input signal terminal to receive the display input signal STU2, a first electrode of the eighteenth transistor M18 is coupled to the second pull-up node QB_B, and a second electrode of the eighteenth transistor M18 is coupled to the second voltage terminal to receive the second voltage V2. In an embodiment, when the first clock signal CLKA and the voltage of the first control node H are both at a low level, a second voltage is provided to the second pull-up node QB_B. Additionally, when the display input signal STU2 is at a low level, a second voltage is provided to the second pull-up node QB_B.

[0074] It can be understood that when the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the pull-up circuit 700 may also include a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 (or a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18). Since the specific circuit structure is the same, a detailed description is omitted here.

[0075] 3, the reset circuit 900 may include a fifth transistor M5 and a sixth transistor M6. A control electrode of the fifth transistor M5 is coupled to a blanking reset signal terminal to receive a blanking reset signal TRST, a first electrode of the fifth transistor M5 is coupled to a pull-down node Q, and a second electrode of the fifth transistor M5 is coupled to a second voltage terminal to receive a second voltage V2. In an embodiment, when the blanking reset signal TRST is at a low level, the fifth transistor M5 is turned on and provides the second voltage V2 to the pull-down node Q. A control electrode of the sixth transistor M6 is coupled to a display reset signal terminal to receive a display reset signal STD, a first electrode of the sixth transistor M6 is coupled to the pull-down node Q, and a second electrode of the sixth transistor M6 is coupled to a second voltage terminal V2. In an embodiment, when the display reset signal STD is at a low level, the sixth transistor M6 is turned on and provides the second voltage V2 to the pull-down node Q.

[0076] As can be understood, in the embodiments of the present disclosure, each circuit in the shift register is not limited to the above circuit structure, and the following schematic explanation of selectable circuit variations is given with reference to the drawings, and the variations are not intended to be limiting.

[0077] 4(1), 4(2), and 4(3) show exemplary circuit diagrams of display input circuit 410, display input circuit 420, and display input circuit 430, respectively, according to embodiments of the present disclosure.

[0078] 4(1), the display input circuit 410 may include a fourth transistor M4 and a fourth leakage prevention transistor M4_b. A control electrode of the fourth transistor M4, a first electrode of the fourth leakage prevention transistor M4_b and a control electrode of the fourth leakage prevention transistor M4_b are coupled to a display input signal terminal to receive a display input signal STU2, a second electrode of the fourth transistor M4 is coupled to a first electrode of the fourth leakage prevention transistor M4_b, and a second electrode of the fourth leakage prevention transistor M4_b is coupled to a pull-down node Q.

[0079] 4(2), the display input circuit 420 may include a fourth transistor M4 and a fourth leakage prevention transistor M4_b. A control electrode of the fourth transistor M4 is coupled to a display input signal terminal for receiving a display input signal STU2, and a first electrode of the fourth leakage prevention transistor M4_b is coupled to a first voltage terminal for receiving a first voltage V1. A control electrode and a first electrode of the fourth leakage prevention transistor M4_b are coupled to a second electrode of the fourth transistor M4, and a second electrode of the fourth leakage prevention transistor M4_b is coupled to a pull-down node Q.

[0080] 4(3), the display input circuit 430 may include a fourth transistor M4. The control electrode and the first electrode of the fourth transistor are coupled to the display input signal terminal to receive a display input signal STU2, and the second electrode is coupled to the pull-down node Q.

[0081] 5(1) and 5(2) each show an exemplary circuit diagram of a second control circuit 800 according to an embodiment of the present disclosure.

[0082] As shown in FIG. 5(1), the second control circuit 810 includes a thirteenth transistor M13, a fifteenth transistor M15, a sixteenth transistor M16, and an eighteenth transistor M18. A control electrode of the thirteenth transistor M13 is coupled to the first clock signal terminal CLKA, a first electrode of the thirteenth transistor M13 is coupled to the first pull-up node QB_A, and a second electrode of the thirteenth transistor M13 is coupled to the second voltage terminal V2. A control electrode of the fifteenth transistor M15 is coupled to the display input signal terminal STU2, a first electrode of the fifteenth transistor M15 is coupled to the first pull-up node QB_A, and a second electrode of the fifteenth transistor M15 is coupled to the second voltage terminal V2. A control electrode of the sixteenth transistor M16 is coupled to the first clock signal terminal CLKA, a first electrode of the sixteenth transistor M16 is coupled to the second pull-up node QB_B, and a second electrode of the sixteenth transistor M16 is coupled to the second voltage terminal V2. A control electrode of the 18th transistor M18 is coupled to the display input signal terminal, a first electrode of the 18th transistor M18 is coupled to the second pull-up node QB_B, and a second electrode of the 18th transistor M18 is coupled to the second voltage terminal V2. Compared with the second control circuit 800 of the shift register 20 in FIG. 3, the second control circuit 810 does not include the 14th transistor M14 and the 17th transistor M17.

[0083] As shown in FIG. 5(2), the second control circuit 820 includes a fifteenth transistor M15 and an eighteenth transistor M18. A control electrode of the fifteenth transistor M15 is coupled to a display input signal terminal STU2, a first electrode of the fifteenth transistor M15 is coupled to a first pull-up node QB_A, and a second electrode of the fifteenth transistor M15 is coupled to a second voltage terminal V2. A control electrode of the eighteenth transistor M18 is coupled to a display input signal terminal, a first electrode of the eighteenth transistor M18 is coupled to a second pull-up node QB_B, and a second electrode of the eighteenth transistor M18 is coupled to a second voltage terminal V2. Compared with the second control circuit 800 of the shift register 20 in FIG. 3, the second control circuit 820 does not include a thirteenth transistor M13, a fourteenth transistor M14, a sixteenth transistor M16, and a seventeenth transistor M17.

[0084] 6 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure. As shown in FIG. 6, the shift register is different from the shift register in FIG. 3 in that the second control circuit 800 is replaced with a second control circuit 810, and a first leakage prevention transistor M1_b, a third leakage prevention transistor M3_b, a fifth leakage prevention transistor M5_b, a sixth leakage prevention transistor M6_b, a ninth leakage prevention transistor M9_b, a twelfth leakage prevention transistor M12_b, a 28th transistor M28, and a 29th transistor M29 are added. Hereinafter, the operation principle of preventing leakage will be described by taking the first leakage prevention transistor M1_b as an example.

[0085] A control electrode of the first leakage prevention transistor M1_b is coupled to the second clock signal terminal CLKB, a first electrode of the first leakage prevention transistor M1_b is coupled to the second electrode of the 28th transistor M28, and a second electrode of the first leakage prevention transistor M1_b is coupled to the first control node H. A control electrode of the 28th transistor M28 is coupled to the first control node H, and a first electrode of the 28th transistor M28 is coupled to the fifth voltage terminal V5 to receive a fifth voltage of a low level. When the first control node H is at a low level, the 28th transistor M28 is turned on under the control of the level of the first control node H, so that a low level signal input from the fifth voltage terminal V5 can be input to the first electrode of the first leakage prevention transistor M1_b, so that the first and second electrodes of the first leakage prevention transistor M1_b are both in a low level state, and the charge at the first control node H is prevented from leaking from the first leakage prevention transistor M1_b. In this case, the control electrode of the first leakage prevention transistor M1_b is coupled to the control electrode of the first transistor M1, so that the coupling between the first transistor M1 and the first leakage prevention transistor M1_b can achieve the same effect as the aforementioned first transistor M1 and also has a leakage prevention effect.

[0086] Similarly, the third leakage prevention transistor M3_b, the fifth leakage prevention transistor M5_b, the sixth leakage prevention transistor M6_b, the ninth leakage prevention transistor M9_b, and the twelfth leakage prevention transistor M12_b are each coupled to the 29th transistor M29 to realize a leakage prevention structure, thereby preventing leakage of charge at the pull-down node Q. The operating principle for preventing leakage at the pull-down node Q is the same as the operating principle for preventing leakage at the first control node H, and a detailed description thereof will be omitted here.

[0087] The embodiment of the present disclosure further provides a gate driver circuit comprising a shift register. As shown in Fig. 7, the gate driver circuit 30 may include a plurality of cascaded shift registers (e.g., N), and any one or more of the shift registers may use the structure or a modification of the shift register according to the embodiment of the present disclosure, such as the shift register 10 or the shift register 20. As will be explained, Fig. 7 shows only the upper four levels of shift registers (A1, A2, A3, and A4) of the gate driver circuit 30 in a schematic manner.

[0088] As shown in Fig. 7, the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first level shift register A1 and the display input signal terminal STU2 of the second level shift register A2 all receive the input signal STU. Note that the blanking input signal terminal STU1 of the (i+1)th level shift register is coupled to the shift signal output terminal CR of the (i)th level shift register. Note that the display input signal terminal STU2 of the (i+2)th level shift register is coupled to the shift signal output terminal CR of the (i)th level shift register. Except for the last three levels of shift registers, the display reset signal terminal STD of the (i)th level shift register is connected to the shift signal output terminal CR of the (i+3)th level shift register. Note that the blanking reset signal terminal TRST of the shift registers of each level is coupled to the blanking reset signal line TRST.

[0089] In an embodiment, the gate driving circuit 30 may further include a first sub-clock signal line CLK_1 and a second sub-clock signal line CLK_2. As shown in Fig. 7, the first clock signal terminals CLKA of the shift registers of each level are all coupled to the first sub-clock signal line CLK_1. The second clock signal terminals CLKB of the shift registers of each level are all coupled to the second sub-clock signal line CLK_2.

[0090] 7, the gate driving circuit 30 may further include a third sub-clock signal line CLKD_1, a fourth sub-clock signal line CLKD_2, a fifth sub-clock signal line CLKD_3 and a sixth sub-clock signal line CLKD_4. When the shift register includes a fourth clock signal terminal CLKD, the fourth clock signal terminal CLKD of the shift register of the 4i-3th level is coupled to the third sub-clock signal line CLKD_1, the fourth clock signal terminal CLKD of the shift register of the 4i-2th level is coupled to the fourth sub-clock signal line CLKD_2, the fourth clock signal terminal CLKD of the shift register of the 4i-1th level is coupled to the fifth sub-clock signal line CLKD_3, and the fourth clock signal terminal CLKD of the shift register of the 4ith level is coupled to the sixth sub-clock signal line CLKD_4. For example, the third sub-clock signal line CLKD_1 provides a fourth clock signal to the first level shift register, the fourth sub-clock signal line CLKD_2 provides a fourth clock signal to the second level shift register, the fifth sub-clock signal line CLKD_3 provides a fourth clock signal to the third level shift register, and the sixth sub-clock signal line CLKD_4 provides a fourth clock signal to the fourth level shift register.

[0091] In addition, the gate driving circuit 30 may further include a seventh sub-clock signal line CLKE_1, an eighth sub-clock signal line CLKE_2, a ninth sub-clock signal line CLKE_3, and a tenth sub-clock signal line CLKE_4. When the shift register includes the fifth clock signal terminal CLKE, the fifth clock signal terminal CLKE of the shift register of the 4i-3th level is coupled to the seventh sub-clock signal line CLKE_1, the fifth clock signal terminal CLKE of the shift register of the 4i-2th level is coupled to the eighth sub-clock signal line CLKE_2, the fifth clock signal terminal CLKE of the shift register of the 4i-1th level is coupled to the ninth sub-clock signal line CLKE_3, and the fifth clock signal terminal CLKE of the shift register of the 4ith level is coupled to the tenth sub-clock signal line CLKE_4. For example, the seventh sub-clock signal line CLKE_1 provides a fifth clock signal to the first level shift register, the eighth sub-clock signal line CLKE_2 provides a fifth clock signal to the second level shift register, the ninth sub-clock signal line CLKE_3 provides a fifth clock signal to the third level shift register, and the tenth sub-clock signal line CLKE_4 provides a fifth clock signal to the fourth level shift register.

[0092] The operation process of the gate drive circuit 30 shown in Fig. 7 will be described below with reference to the signal timing chart in Fig. 8. The shift register in the gate drive circuit 30 is, for example, the shift register shown in Fig. 3.

[0093] Fig. 8 shows a timing chart of signals when the gate drive circuit 30 shown in Fig. 7 performs compensation row by row. In Fig. 9, 1F and 2F respectively indicate the first and second frames. Display indicates a display period in one frame, and Blank indicates a blanking period in one frame.

[0094] Signal STU indicates an input signal STU. TRST indicates a signal provided to a blanking reset signal line TRST. Signals V3 and V4 indicate signals provided to a third voltage terminal and a fourth voltage terminal of a shift register in the gate drive circuit 30, respectively. Signals CLK_1 and CLK_2 indicate signals provided to a first sub-clock signal line CLK_1 and a second sub-clock signal line CLK_2, respectively. Signals CLKD_1, CLKD_2, CLKD_3, and CLKD_4 indicate signals provided to a third sub-clock signal line CLKD_1, a fourth sub-clock signal line CLKD_2, a fifth sub-clock signal line CLKD_3, and a sixth sub-clock signal line CLKD_4, respectively. Signals CLKE_1, CLKE_2, CLKE_3, and CLKE_4 indicate signals provided to a seventh sub-clock signal line CLKE_1, an eighth sub-clock signal line CLKE_2, a ninth sub-clock signal line CLKE_3, and a tenth sub-clock signal line CLKE_4, respectively.

[0095] H <1> and H <2> respectively indicate the voltages of the first control node H in the first level shift register A1 and the second level shift register A2 in the gate drive circuit 30. <1> , N <2> Q denotes the voltage of the second control node N in the first level shift register A1 and the second level shift register A2, respectively. <1> and Q <2> OUT1 and OUT2 respectively represent the voltages of the pull-down nodes Q in the first-level shift register A1 and the second-level shift register A2 in the gate drive circuit 30. <1> , OUT1 <2> , OUT1 <3> and OUT1 <4> indicate the corresponding first drive signal output terminals OUT1 in the first level shift register A1, the second level shift register A2, the third level shift register A3, and the fourth level shift register A4 in the gate drive circuit 30. <1> , OUT2 <2> respectively indicate the corresponding second drive signal output terminal OUT2 in the first level shift register A1 and the second level shift register A2 in the gate drive circuit 30. As will be described, the voltages of the shift signal output terminal CR and the drive signal output terminal OUT1 in the shift registers of each level are the same, so the shift signal output terminal CR is not shown in FIG.

[0096] As will be explained, the signal levels in the signal timing diagram shown in FIG. 8 are only schematic and do not represent true level values.

[0097] Hereinafter, the operation principle when the gate drive circuit 30 shown in FIG. 7 is used to perform compensation sequentially row by row will be described with reference to the signal timing chart in FIG. 8. For example, the shift register in the gate drive circuit 20 shown in FIG. 7 may be the shift register shown in FIG. 3.

[0098] Before the first frame 1F starts, the blanking reset signal line TRST and the second sub-clock signal line CLK_2 both provide a low level to provide a low level to the blanking reset signal terminal TRST and the second clock signal terminal CLKB of the shift register of each level, turning on the first transistor M1 and the fifth transistor M5 in the shift register of each level. Provide a blanking input signal STU1 (high level input signal STU) to the first control node H, the voltage of the first control node H is high level, and provide a second voltage V2 (high level) to the pull-down node Q, the voltage of the pull-down node Q is high level. This resets the first control node H and the pull-down node Q of each level to realize a global reset.

[0099] Next, the first frame 1F starts, the third voltage V3 is at a high level, the fourth voltage V4 is at a low level, the signal provided by the blanking reset signal line TRST becomes a high level, and the fifth transistor M5 is turned off.

[0100] The operation process of the first level shift register A1 during the display period Display of the first frame 1F is as follows.

[0101] In the first period, the blanking input signal terminal STU1 and the display input signal terminal STU2 of the first level shift register are both connected to the input signal line STU, so that the blanking input signal terminal STU1 and the display input signal terminal STU2 both provide low level signals. The second clock signal terminal CLKB provides a low level signal, turning on the first transistor M1, thereby driving the blanking input signal STU1 to the first control node H. <1> In this case, the first control node H <1> is at a low level, and the first clock signal CLKA (coupled to the first sub-clock signal line CLK_1) is at a high level, so that the second transistor M2 is turned on and couples the first clock signal CLKA to the second control node N <1> and a second control node N <1> The voltage at the first control node H <1> and the second control node N <1> Pull-down node Q <1> The first clock signal CLKA is at a high level and the third transistor M3 is turned off to isolate the effect on the first control node H. Until the blanking period begins, the first capacitor C1 is connected to the first control node H. <1> and the second control node N <1> The voltage difference between

[0102] Meanwhile, the fourth voltage V4 is at a low level, so as to control the voltage of the control electrode of the twelfth transistor M12 to a low level, and the tenth transistor M10 is turned on. Thus, the twelfth transistor M12 is turned on, and pulls the second voltage V2 to the pull-down node Q <1> and pull down node Q <1> In the first period, the display input signal STU2 is at a low level, and the fourth transistor M4 is turned on, so that the first voltage V1 is applied to the pull-down node Q <1> and pull down node Q <1> This causes the voltage at the pull-down node QB_A to change to a low level. This causes the eighth transistor M8 and the eleventh transistor M11 to turn on, pulling up the first pull-up node QB_A and the second pull-up node QB_B. <1> is at a low level, turning on the 19th transistor M19, the 22nd transistor M22, and the 25th transistor M25, and outputting the fourth clock signal CLKD (coupled to the third sub-clock signal line CLKD_1) and the fifth clock signal CLKE (coupled to the seventh sub-clock signal line CLKE_1) to the shift signal output terminal CR <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> , thereby outputting a high level signal, respectively.

[0103] Furthermore, since the display input signal STU2 is at a low level, the 15th transistor M15 and the 18th transistor M18 are turned on and provide a high-level second voltage V2 to the first pull-up node QB_A and the second pull-up node QB_B, respectively, thereby performing auxiliary pull-up for the first pull-up node QB_A and the second pull-up node QB_B.

[0104] In the second period, a low-level signal is provided to the fourth clock signal terminal CLKD via the third sub-clock signal line CLKD_1, and a low-level signal is provided to the fifth clock signal terminal CLKE via the seventh sub-clock signal line CLKE_1. Due to the presence of the second capacitor C2, the pull-down node Q <1> The voltage at the shift signal output terminal CR is further pulled down by the bootstrap effect. The 19th transistor M19, the 22nd transistor M22 and the 25th transistor M25 are kept on, so that the voltage at the shift signal output terminal CR <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> For example, the low-level signal output from the shift signal output terminal can be used for scanning shift of upper and lower level shift registers, and the low-level signals output from the two driving signal output terminals can be used for driving sub-pixels of a display panel to display.

[0105] In the third period, pull-down node Q <1> is held at a low level, and the 19th transistor M19, the 22nd transistor M22 and the 25th transistor M25 are held on. A high level signal is provided to the fourth clock signal terminal CLKD via the third sub-clock signal line CLKD_1, and a high level signal is provided to the fifth clock signal terminal CLKE via the seventh sub-clock signal line CLKE_1, so that the shift signal output terminal CR, the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 all output high level signals. <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> is reset to a high level, so that the transistors are coupled together to pull down the pull-down node Q <1> The voltage of the display reset signal terminal STD of the first level shift register A1 rises by one step. <4> (i.e. OUT1 <4> ) and at this time, the shift signal output terminal CR of the fourth level shift register A4 is connected to <4> Since the pull-down node Q is not yet outputting a low-level signal, <1> Without pulling up the pull-up node Q <1> can be kept at a relatively low level.

[0106] In the fourth period, the shift signal output terminal CR of the fourth level shift register A4 <4> outputs a low level signal, providing a low level signal to the display reset signal terminal STD of the first-level shift register A1, so that the sixth transistor M6 is turned on, and the pull-down node Q <1> The voltage at the pull-down node Q <1> The pull-down node Q <1> Since the voltage at the pull-down node QB_B is high, the eleventh transistor M11 is turned off and the voltage at the second pull-up node QB_B is pulled down to a low level by the tenth transistor M10. <1> The twelfth transistor M12 is turned on to remove noise from the shift signal output terminal CR. <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> , the twenty-first transistor M21, the twenty-fourth transistor M24 and the twenty-seventh transistor M27 are turned on, thereby respectively outputting a high level signal.

[0107] During the display period of the first frame, the first clock signal CLKA is always held at a low level, so that the third transistor M3 is held off. <1> and the second control node N <1> This allows the effect of the voltage at on the pull-down node Q during the display period to be isolated.

[0108] After the first level shift register drives the sub-pixels of the first row of the display panel to complete display, the second level, third level, etc. shift registers similarly drive the sub-pixels of the display panel row by row to complete one frame of display drive, at which point the display period of the first frame ends.

[0109] When the display period Display starts, the first control node H <1> A low level is written to the second control node N and held until the blanking period BLANK. The second transistor is turned on, the first clock signal CLKA is high, and therefore the second control node N <1> A high level is written to and held until the blanking period, Blank.

[0110] The operation process of the first level shift register A1 during the blanking period Blank of the first frame 1F is described as follows.

[0111] In the fifth period, the first sub-clock signal line CLK_1 provides a low level signal to the first clock signal CLKA, and the first control node H <1> The second control node N <1> The first clock signal CLKA is applied to the second control node N <1> A first capacitor C1 is provided to the first control node H <1> and the second control node N <1> In order to maintain the voltage difference between <1> The voltage at the second control node N <1> The first clock signal CLKA is coupled to the second control node N so that the voltage of the second control node N realizes a lossless output of the first clock signal CLKA at the lowest potential. <1> The third transistor M3 is turned on, which causes the second control node N <1> The voltage of the lossless first clock signal CLKA is pulled down to the pull-down node Q <1> and pull down node Q <1> During this period, the fourth clock signal CLKD and the fifth clock signal terminal CLKE are all high level signals, so that the shift signal output terminal CR, the first drive signal output terminal OUT1 and the second drive signal output terminal OUT2 all output high level signals.

[0112] In the sixth period, the first sub-clock signal line CLK_1 provides a high level signal to the first clock signal CLKA, and the second control node N <1> The voltage at the first control node H goes high, and the voltage difference held by the first capacitor C1 <1> The voltage at

[0113] In the seventh period, the second sub-clock signal line CLK_2 provides a low level signal to the second clock signal CLKB, and the first transistor M1 is turned on to supply a high level blanking input signal STU1 to the first control node H. <1> , pulling it high. The second transistor M2 is turned off, and the second control node N <1> The voltage at does not change.

[0114] The third transistor M3 is turned off, the fourth clock signal CLKD and the fifth clock signal terminal CLKE are both low level signals, and the shift signal output terminal CR <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> Both of them output a low level signal. Due to the action of the second capacitor C2 and the third capacitor C3, the pull-down node Q <1> The voltage on the input is pulled down again.

[0115] Note that because the second clock signal CLKB is low, the first transistor M1 in the second level shift register is turned on, and the blanking input signal STU1 <2> is the shift signal output terminal CR in the first level shift register A1 <1> , and thus the first control node H <2> The voltage at drops to a low level.

[0116] In the eighth period, the second sub-clock signal line CLK_2 provides a high level signal to the second clock signal CLKB, the third sub-clock signal line CLKD_1 provides a low level signal to the fourth clock signal terminal CLKD, and the seventh sub-clock signal line CLKE_1 provides a high level signal to the fifth clock signal terminal CLKE. <1> , first drive signal output terminal OUT1 <1> outputs a low level signal, and the second drive signal output terminal OUT2 <1> The first transistor M1 in the second level shift register A2 is turned off and the first control node H <2> remains at a low level.

[0117] In the ninth period, the second clock signal CLKB is held at a high level, and the fourth clock signal CLKD and the fifth clock signal CLKE are both at a low level. <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> Both output a low level signal.

[0118] According to the above, in the seventh to ninth periods of the blanking period, the first drive signal output terminal OUT1 <1> outputs a first drive signal at a low level, which enables the sense transistors in the subpixels in the first row to sense the drive currents of the subpixels in that row, and thereby perform compensation based on the sensed drive currents.

[0119] In the tenth period, the fourth clock signal CLKD and the fifth clock signal CLKE are both at high level. <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> both output a high level signal. Under the control of the second capacitor C2 and the third capacitor C3, the voltage of the pull-down node Q increases.

[0120] In the eleventh period, the blanking reset signal line TRST provides a low level signal to the blanking reset signal terminal TRST, the fifth transistor M5 is turned on, and the voltage of the pull-down node Q changes to a high level. The fourth voltage is low, and the tenth transistor M10 is turned on, causing the voltage of the second pull-up node QB_B to change to a low level. Correspondingly, the twenty-first transistor M21, the twenty-fourth transistor M24, and the twenty-seventh transistor M27 are all turned on, causing the shift signal output terminal CR <1> , first drive signal output terminal OUT1 <1> and the second drive signal output terminal OUT2 <1> Each of them outputs a high level signal.

[0121] The above description may be referred to for driving the gate driving circuit in more periods thereafter, such as the second frame 2F, the third frame 3F, etc., and detailed description thereof will be omitted here.

[0122] As described above, during the blanking period of each frame, the blanking output signal output from the gate driving circuit may be used to drive the sense transistors in the sub-pixels of the display panel. As shown, the driving signals are provided in a row-by-row sequence. For example, during the blanking period of the first frame, the gate driving circuit outputs driving signals for the sub-pixels of the first row of the display panel. During the blanking period of the second frame, the gate driving circuit outputs driving signals for the sub-pixels of the second row of the display panel, and so on, for compensation in a row-by-row sequence.

[0123] Meanwhile, the embodiment of the present disclosure further provides an array substrate and a display device including the above-described gate driving circuit 30. In the embodiment, the display device may be any product or component having a display function, such as a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a car navigation system, etc.

[0124] In addition, the embodiment of the present disclosure further provides a method for driving a shift register. Figure 9 shows a flow chart of the method for driving a shift register according to the embodiment of the present disclosure. The shift register can be any applicable shift register according to the embodiment of the present disclosure.

[0125] In a display stage of one frame, in step 910, under the control of the second clock signal CLKB from the second clock signal terminal, a blanking input signal STU1 from the blanking input signal terminal is provided to the first control node H, and a voltage difference between the first control node H and the second control node N is maintained. For example, the description of the first period in FIG. 8 may be referred to.

[0126] In the embodiment, a first voltage V1 from a first voltage terminal can be provided to the pull-down node Q based on a display input signal STU2 from a display input signal terminal. For example, refer to the description of the second period in FIG.

[0127] Correspondingly, an indication output signal can be output based on the voltage of the pull-down node Q. For example, see the description of the third period in FIG.

[0128] The pull-down node Q can be reset based on the display reset signal STD. For example, the description of the fourth period in FIG.

[0129] In a blanking stage of one frame, in step 920, a first clock signal CLKA from a first clock signal terminal is provided to a second control node N based on the voltage of the first control node H, and the voltage of the first control node H can be controlled by a voltage difference maintained based on the voltage of the second control node N. This allows the first clock signal CLKA to be output to the second control node N without loss.

[0130] In step 930, a voltage at the second control node N (ie, the lossless first clock signal CLKA) may be provided to the pull-down node Q based on the first clock signal CLKA.

[0131] Steps 920 and 930 may refer to the description of the fifth period in FIG. 8 above, for example.

[0132] Then, after the first clock signal CLKA changes, the second control node N receives the first clock signal CLKA, so the voltage of the second control node N changes, and controls the voltage of the first control node H by the voltage difference held based on the voltage of the second control node N. For example, you may refer to the description of the sixth period of FIG. 8 above.

[0133] In step 940, a shift signal and a drive signal (e.g., a first drive signal and a second drive signal) are output based on the voltage of the pull-down node Q. Note that under the control of the second clock signal, the blanking input signal STU1 from the blanking input signal terminal is provided to the first control node H, thereby controlling so that the first clock signal is not provided to the second control node N. For example, the description of the seventh to tenth periods in FIG. 8 above may be referred to.

[0134] Next, the pull-down node Q can be reset based on the blanking reset signal TRST. For example, see the description of the eleventh period in FIG.

[0135] As will be appreciated by those skilled in the art, although the above steps are described in order, this is not intended to limit the order of the method, and embodiments of the present disclosure may be performed in any other suitable order. In embodiments, the above steps may occur in different periods of the same frame, or in different periods of different frames. For example, a first step may occur in a blanking period of a first frame, and other steps may occur in a display period and a blanking period of a second frame. The present disclosure is not limited in this respect.

[0136] Although several embodiments of the present disclosure have been described in detail above, the scope of protection of the present disclosure is not limited thereto. Of course, a person skilled in the art can make various modifications, substitutions and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is limited by the scope of the accompanying claims. [Explanation of symbols]

[0137] 10 Shift Registers 100 Blanking Input Circuit 200 Blanking control circuit 300 Blanking Pull-Down Circuit 1000 Shift Register Circuit

Claims

1. A shift register comprising: a blanking input circuit; a blanking control circuit; a blanking pull-down circuit; and a shift register circuit; the blanking input circuit is configured to provide a blanking input signal from a blanking input signal terminal to a first control node; the blanking control circuit comprises a second transistor, a control electrode of the second transistor coupled to the first control node and a second electrode of the second transistor coupled to a second control node; the blanking pull-down circuit is configured to provide a voltage of the second control node to a pull-down node based on a first clock signal, the blanking pull-down circuit comprising a third transistor and a third leakage prevention transistor, a control electrode of the third transistor coupled to a first clock signal terminal, a first electrode of the third transistor coupled to the second control node, a second electrode of the third transistor coupled to a first electrode of the third leakage prevention transistor, a control electrode of the third leakage prevention transistor coupled to the first clock signal terminal, and a second electrode of the third leakage prevention transistor coupled to the pull-down node; the shift register circuit is configured to provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal based on a voltage of the pull-down node; the shift register further comprises a 29th transistor, a control electrode of the 29th transistor coupled to the pull-down node, a first electrode of the 29th transistor coupled to a first voltage terminal, and a second electrode of the 29th transistor coupled to a second electrode of the third transistor; The shift register circuit further comprises a blanking reset signal line and a reset circuit, a blanking reset signal terminal of the shift register of each level is coupled to the blanking reset signal line, and the reset circuit is configured to reset the pull-down node based on a blanking reset signal from the blanking reset signal terminal.

2. 2. The shift register of claim 1, wherein the blanking input circuit comprises a first transistor, a first electrode of the first transistor coupled to the blanking input signal terminal and a second electrode of the first transistor coupled to the first control node.

3. the shift register circuit further comprises an output circuit; 3. The shift register according to claim 2, wherein the output circuit is configured to output a shift signal from the shift signal output terminal and a first drive signal from the first drive signal output terminal based on a voltage of the pull-down node.

4. the shift register circuit further comprises a display input circuit, the display input circuit comprising a fourth transistor; 4. The shift register of claim 3, wherein a control electrode of the fourth transistor and a first electrode of the fourth transistor are coupled to a display input signal terminal for receiving a display input signal, and a second electrode of the fourth transistor is coupled to the pull-down node.

5. the output circuit comprises a 19th transistor and a 22nd transistor; a control electrode of the 19th transistor is coupled to the pull-down node; a first electrode of the 19th transistor is coupled to a fourth clock signal terminal for receiving a fourth clock signal; and a second electrode of the 19th transistor is coupled to the shift signal output terminal; 4. The shift register of claim 3, wherein a control electrode of said second transistor is coupled to said pull-down node, and a second electrode of said second transistor is coupled to said first drive signal output terminal.

6. The shift register circuit further comprises: a first control circuit configured to control a voltage of a pull-up node based on a voltage of the pull-down node; a pull-up circuit configured to provide a second voltage from a second voltage terminal to the pull-down node, the shift signal output terminal, and the drive signal output terminal based on a voltage at the pull-up node; and a second control circuit configured to control the voltage of the pull-up node based on the first clock signal and the voltage of the first control node, and to control the voltage of the pull-up node based on a display input signal.

7. the pull-up node comprises a first pull-up node; The first control circuit is a seventh transistor, a control electrode and a first electrode of the seventh transistor coupled to a third voltage terminal and a second electrode of the seventh transistor coupled to the first pull-up node; an eighth transistor, a control electrode of the eighth transistor coupled to the pull-down node, a first electrode of the eighth transistor coupled to the first pull-up node, and a second electrode of the eighth transistor coupled to the second voltage terminal; The pull-up circuit includes: a ninth transistor, a control electrode of the ninth transistor coupled to the first pull-up node, a first electrode of the ninth transistor coupled to the pull-down node, and a second electrode of the ninth transistor coupled to the second voltage terminal; a twentieth transistor, a control electrode of the twentieth transistor being coupled to the first pull-up node, a first electrode of the twentieth transistor being coupled to the shift signal output terminal, and a second electrode of the twentieth transistor being coupled to the second voltage terminal; a second transistor, a control electrode of the second transistor being coupled to the first pull-up node, a first electrode of the second transistor being coupled to the first drive signal output terminal, and a second electrode of the second transistor being coupled to the second voltage terminal; The second control circuit is a thirteenth transistor, a control electrode of the thirteenth transistor coupled to the first clock signal terminal and a first electrode of the thirteenth transistor coupled to the first pull-up node; a fourteenth transistor having a control electrode coupled to the first control node, a first electrode coupled to the second electrode of the thirteenth transistor, and a second electrode coupled to the second voltage terminal; 7. The shift register of claim 6, comprising: a fifteenth transistor, a control electrode of the fifteenth transistor coupled to a display input signal terminal, a first electrode of the fifteenth transistor coupled to the first pull-up node, and a second electrode of the fifteenth transistor coupled to the second voltage terminal.

8. the pull-up node further comprises a second pull-up node; The pull-up circuit further comprises: a twelfth transistor, a control electrode of the twelfth transistor being coupled to the second pull-up node, a first electrode of the twelfth transistor being coupled to the pull-down node, and a second electrode of the twelfth transistor being coupled to the second voltage terminal; a second transistor, a control electrode of the second transistor being coupled to the second pull-up node, a first electrode of the second transistor being coupled to the shift signal output terminal, and a second electrode of the second transistor being coupled to the second voltage terminal; a second electrode of the second transistor coupled to the first drive signal output terminal; and a second electrode of the second transistor coupled to the second voltage terminal.

9. 7. The shift register of claim 6, wherein the reset circuit is configured to reset the pull-down node based on a display reset signal from a display reset signal terminal.

10. the reset circuit comprises a fifth transistor and a sixth transistor; a control electrode of the fifth transistor is coupled to the blanking reset signal terminal, a first electrode of the fifth transistor is coupled to the pull-down node, and a second electrode of the fifth transistor is coupled to the second voltage terminal; 10. The shift register of claim 9, wherein a control electrode of the sixth transistor is coupled to the display reset signal terminal, a first electrode of the sixth transistor is coupled to the pull-down node, and a second electrode of the sixth transistor is coupled to the second voltage terminal.

11. the output circuit further comprises a twenty-fifth transistor and a third capacitor; a control electrode of the second transistor is coupled to the pull-down node; a first electrode of the second transistor is coupled to a fifth clock signal terminal for receiving a fifth clock signal; and a second electrode of the second transistor is coupled to a second drive signal output terminal; 9. The shift register of claim 8, wherein the third capacitor is coupled between the pull-down node and the second drive signal output terminal.

12. the pull-up circuit further comprises a 26th transistor and a 27th transistor; a control electrode of the 26th transistor is coupled to the first pull-up node, a first electrode of the 26th transistor is coupled to the second drive signal output terminal, and a second electrode of the 26th transistor is coupled to the second voltage terminal; 12. The shift register of claim 11, wherein a control electrode of the second transistor is coupled to the second pull-up node, a first electrode of the second transistor is coupled to the second drive signal output terminal, and a second electrode of the second transistor is coupled to the second voltage terminal.

13. A gate drive circuit, A gate drive circuit comprising N cascaded shift registers according to any one of claims 1 to 12.

14. 14. The gate drive circuit of claim 13, wherein the display reset signal terminal of the i-th level shift register is coupled to the shift signal output terminal of the i+3-th level shift register.

15. A display device comprising the gate drive circuit according to claim 13.

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