Semiconductor device

Abstract

To provide a semiconductor device that operates stably at high temperature.SOLUTION: A semiconductor device includes a metal oxide, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. The metal oxide includes a first region, a second region, and a third region. The first region overlaps with the first conductive layer. The second region overlaps with the second conductive layer. The third region overlaps with the third conductive layer through the insulating layer. The value of the ratio of the carrier concentration of the first region to the carrier concentration of the third region is 100 or more. The value of the ratio of the carrier concentration of the second region to the carrier concentration of the third region is 100 or more.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, imaging device, electronic device etc. may be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an object, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter (-) [Background technology]

[0004] A technology for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. The transistor is used in integrated circuits (ICs) and image display devices (simply called display devices). It is widely used in electronic devices such as transistors. Silicon-based semiconductor materials are widely known as suitable semiconductor thin films, but other materials include oxides. Compound semiconductors have been attracting attention.

[0005] In oxide semiconductors, there are c-axis axial crystals (CAACs), which are neither single crystals nor amorphous. gned crystalline structure and nc (nanocrystalline) ) structure has been found (see Non-Patent Documents 1 and 2).

[0006] In Non-Patent Documents 1 and 2, a transistor was developed using an oxide semiconductor having a CAAC structure. A technique for fabricating a transistor is disclosed.

[0007] In addition, a transistor including an oxide semiconductor has a very low leakage current when it is off. For example, when a transistor using an oxide semiconductor is turned off, A low-power CPU that utilizes the low leakage current characteristic of (See Patent Document 1). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2012-257187 A [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0010] A transistor including an oxide semiconductor has a tendency to degrade as the temperature during operation increases. This increases the off-current and tends to result in normally-on characteristics. The higher the temperature during operation, the lower the threshold voltage of the transistor and the lower the subthreshold voltage. This is because the swing value (also called the S value) becomes larger. Therefore, especially at high temperatures, The electrical characteristics of a semiconductor device having a transistor vary widely, and the reliability of the lid is reduced. Highly likely.

[0011] In view of the above, an object of one embodiment of the present invention is to provide a semiconductor device which can stably operate even at high temperatures. One object of one embodiment of the present invention is to provide a semiconductor device with low off-state current. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation. Another object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. This is one of the topics.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a semiconductor device comprising a metal oxide, an insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer. and a conductive layer having a first region, a second region, and a third region. The first region overlaps the first conductive layer, the second region overlaps the second conductive layer, and the third region overlaps the first conductive layer. The region overlaps with the third conductive layer via the insulating layer, and the first region and the second region are covered with the third conductive layer. The rear concentration is 5×10 17 cm -3 More than 1×10 19 cm -3 Less than 3 The carrier concentration in the region is 1×10 12 cm -3 5×10 or more 17 cm -3 is less than It is a semiconductor device.

[0014] Another aspect of the present invention is a semiconductor device comprising a metal oxide, an insulating layer, a first conductive layer, and a second conductive layer. a first conductive layer and a third conductive layer, the metal oxide being disposed in a first region, a second region and a third region. a first region overlapping the first conductive layer and a second region overlapping the second conductive layer. The third region overlaps with the third conductive layer via the insulating layer, and the carrier concentration of the third region The ratio of the carrier concentration of the first region to the concentration of the second region is 1×10 2 That's it, the third area The ratio of the carrier concentration in the second region to the carrier concentration in the first region is 1×10 2 That's all. , a semiconductor device.

[0015] In the above semiconductor device, a first layer is provided between the first region and the first conductive layer, The second conductive layer is disposed between the first region and the second conductive layer. each of the first layer and the second layer has tantalum nitride, and oxygen, or tantalum and oxygen.

[0016] In the semiconductor device, the hydrogen concentration in the third region is 1×10 18 atoms / cm 3 It is preferable that the .lambda.

[0017] Another embodiment of the present invention is a semiconductor device including a transistor. The substrate includes a metal oxide, a first insulating layer, a second insulating layer, a first conductive layer, and a second conductive layer. a third conductive layer and a fourth conductive layer, and the second insulating layer is provided on the fourth conductive layer. The metal oxide is disposed on the second insulating layer, and the first insulating layer is disposed on the metal oxide. the third conductive layer is disposed on the first insulating layer, and the first conductive layer is disposed on the metal oxide. The second conductive layer is provided on the metal oxide, and the third conductive layer is provided through the metal oxide. The off-state current of the transistor is increased when the temperature is increased to 180° C. or higher and 220° C. or lower. In the range of degrees, it is 1aA or less.

[0018] Another embodiment of the present invention is a semiconductor device including a transistor. The substrate includes a metal oxide, a first insulating layer, a second insulating layer, a first conductive layer, and a second conductive layer. a third conductive layer and a fourth conductive layer, and the second insulating layer is provided on the fourth conductive layer. The metal oxide is disposed on the second insulating layer, and the first insulating layer is disposed on the metal oxide. the third conductive layer is disposed on the first insulating layer, and the first conductive layer is disposed on the metal oxide. The second conductive layer is provided on the metal oxide, and the third conductive layer is provided through the metal oxide. The off-state current of the transistor per 1 μm of channel width is 1 In the temperature range of 80°C or higher and 220°C or lower, it is 10aA / μm or less.

[0019] In the above semiconductor device, the metal oxide is a mixture of indium and an element M (M is aluminum, It is preferable that the metal oxide comprises at least one of gallium, yttrium, or tin, and zinc. Effect of the Invention

[0020] According to one embodiment of the present invention, a semiconductor device that operates stably even at high temperatures can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. A semiconductor device having higher reliability can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. A conductor device can be provided.

[0021] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0022] [Figure 1] 1A and 1B are schematic cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A is a top view of a transistor assumed in the calculation using a device simulator, and FIGS. 2B and 2C are cross-sectional views of the transistor assumed in the calculation using a device simulator. [Diagram 3] FIG. 3 shows the calculation results of the Id-Vg characteristics of a transistor. [Figure 4] 4A to 4D are schematic cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 5] 5A and 5B are diagrams illustrating the drain current of a transistor. [Figure 6] 6A is a top view illustrating a structural example of a transistor according to one embodiment of the present invention, and FIGS. 6B and 6C are cross-sectional views illustrating a structural example of a transistor according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a structural example of a transistor according to one embodiment of the present invention, and FIGS. 7B and 7C are cross-sectional views illustrating a structural example of a transistor according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a structural example of a transistor according to one embodiment of the present invention, and FIGS. 8B and 8C are cross-sectional views illustrating a structural example of a transistor according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a structural example of a transistor according to one embodiment of the present invention, and FIGS. 9B and 9C are cross-sectional views illustrating a structural example of a transistor according to one embodiment of the present invention. [Figure 10] 10A and 10B are block diagrams illustrating configuration examples of a storage device according to one embodiment of the present invention. [Figure 11] 11A to 11H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 12] 12A and 12B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 13] Fig. 13A is a block diagram of a display device, and Fig. 13B and Fig. 13C are circuit diagrams of the display device. [Figure 14] 14A to 14C are circuit diagrams of a display device. [Figure 15] Fig. 15A is a circuit diagram of a display device, Fig. 15B is a timing chart, Fig. 15C and Fig. 15D are circuit diagrams of the display device. [Figure 16] 16A to 16D are diagrams illustrating an electronic device according to one embodiment of the present invention. [Figure 17] 17A to 17H are diagrams illustrating an electronic device according to one embodiment of the present invention. [Figure 18]18A and 18B show the hydrogen concentration and carrier concentration in the metal oxide film of this example. [Figure 19] 19A and 19B show the hydrogen concentration and carrier concentration in the metal oxide film of this example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiments will be described with reference to the drawings. It is understood that the present invention can be practiced in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiment modes.

[0024] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in schematic form, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this is not reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In such cases, the hatch patterns may be the same and no particular reference numbers may be used.

[0025] In addition, the invention is easily understood, particularly in top views (also called "plan views") and perspective views. In order to simplify the description, some of the components may be omitted. The above information may be omitted.

[0026] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second "the" or "third" can be used as appropriate. The ordinal numbers described herein may not coincide with the ordinal numbers used to identify an aspect of the present invention. There are cases where this is the case.

[0027] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship is used for convenience in describing the drawings. The relationship changes accordingly depending on the direction in which each configuration is depicted. The terms are not limited to those described above, and may be rephrased appropriately depending on the situation.

[0028] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification, etc. Therefore, the connection relationship is limited to a specific one, for example, the connection relationship shown in the figure or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0029] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) The channel forming region is formed in the channel. A current can be passed between the source and drain via the channel forming region. In this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0030] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0031] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). A source (source region or source electrode) in a region where the source is formed or a channel forming region This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of the transistor may not be determined to a single value. In the above, the channel length is defined as any one value, maximum value, minimum value or is the average value.

[0032] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part where current flows in the semiconductor when the transistor is on). In the channel forming region, the channel is formed in a direction perpendicular to the channel length direction. The length of the formation region. Note that in one transistor, the channel width is the entire region. In other words, the channel width of a transistor does not always take the same value. Therefore, in this specification, the channel width is determined based on the channel forming region. The value may be any one of the values, the maximum value, the minimum value or the average value.

[0033] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in a top view of the star (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective When the channel width becomes larger than the apparent channel width and its effect cannot be ignored For example, in a transistor that is very small and has a gate electrode that covers the side of the semiconductor, The proportion of the channel formation region formed on the side may become large. In that case, the apparent The effective channel width is larger than the above channel width.

[0034] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0035] In this specification, when the term "channel width" is used, it refers to the apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel The channel length, channel width, effective channel width, apparent channel width, etc. The channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. can.

[0036] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, This can cause problems such as an increase in the density of defect levels in semiconductors and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxides There are transition metals other than the main components of semiconductors, such as hydrogen, lithium, sodium, and silicon. In the case of oxide semiconductors, water also functions as an impurity. In the case of an oxide semiconductor, for example, oxygen vacancies caused by the inclusion of impurities can be eliminated. In addition, when the semiconductor is silicon, there are cases where a defect that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0037] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains more oxygen than silicon. It has a high nitrogen content.

[0038] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0039] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that the two straight lines are arranged at an angle of -30° to 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° to 100°. Therefore, it includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0040] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used for the semiconductor layer of a transistor, Such a metal oxide may be called an oxide semiconductor. In this case, the transistor may be referred to as a transistor having a metal oxide or an oxide semiconductor. can be done.

[0041] In this specification and the like, normally off means that no potential is applied to the gate, or When a ground potential is applied to the gate, the drain current per 1 μm of channel width flows through the transistor. The on-current (also called off-current) is 1×10 -20 A or less, at 85℃ 1×10 -18A or less, or 1×10 at 125°C -16 A or less cormorant.

[0042] (Embodiment 1) In this embodiment, an example of a transistor according to one embodiment of the present invention will be described.

[0043] 1A and 1B are schematic cross-sectional views of a transistor 10 of one embodiment of the present invention. 1A and 1B are cross-sectional views of a transistor 10 taken along the channel length direction.

[0044] As shown in FIG. 1A, transistor 10 is a semiconductor A semiconductor layer 30, a conductive layer 40a, a conductive layer 40b, and an insulating layer 50 disposed on the semiconductor layer 30. and a conductive layer 60 disposed on the insulating layer 50. The semiconductor layer 30 also has a region 3 4, and regions 31a and 31b.

[0045] At least a portion of the conductive layer 60 overlaps with the region 34 of the semiconductor layer 30 via the insulating layer 50. At least a portion of the conductive layer 40a overlaps with the region 31a of the semiconductor layer 30. At least a portion of the conductive layer 40b overlaps with the region 31b of the semiconductor layer 30.

[0046] The conductive layer 60 functions as the gate electrode of the transistor 10, and the insulating layer 50 serves as the The conductive layer 40a functions as a gate insulating layer for the transistor 10, and the conductive layer 40b functions as a source electrode for the transistor 10. The conductive layer 40b serves as one of the source and drain electrodes of the transistor 10. The region 34 of the semiconductor layer 30 serves as the other of the transistor and drain electrodes. The region 31a of the semiconductor layer 30 functions as a channel forming region of the transistor 10. The region 31b of the semiconductor layer 30 functions as either the source region or the drain region of the transistor 10. serves as the other of the source or drain region of transistor 10.

[0047] As shown in FIG. 1B, the transistor 10 includes an insulating layer 30 disposed below the semiconductor layer 30. The insulating layer 70 may include a conductive layer 80 disposed below the insulating layer 70. At least a portion of the insulating layer 70 overlaps with the region 34 of the semiconductor layer 30. The conductive layer 60 serves as the first gate electrode of the transistor 10, and the insulating layer 50 serves as the first gate electrode of the transistor 10. The conductive layer 80 serves as the first gate insulating layer of the transistor 10. 2, and insulating layer 70 serves as the second gate insulating layer of transistor 10. It functions as such.

[0048] In FIG. 1B, the region 34 of the semiconductor layer 30 is on the upper surface (the conductive layer 60 side) of the semiconductor layer 30. However, the present embodiment is not limited to this. For example, the semiconductor layer 3 The region 34 of the semiconductor layer 30 may be formed on the lower surface (the conductive layer 80 side) of the semiconductor layer 30. 0 from its upper surface to its lower surface.

[0049] The channel formation region of a transistor is formed by using a metal oxide (hereafter, oxide It is preferable to use an oxide semiconductor as the channel type of a transistor. By using this in the composition region, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0050] In addition, a transistor including an oxide semiconductor in a channel formation region has a Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Conductors can be formed into films using methods such as sputtering, making them ideal for constructing highly integrated semiconductor devices. The present invention can be used for a transistor.

[0051] For example, an oxide semiconductor is In-M-Zn oxide (where the element M is aluminum or gallium). Sodium, Yttrium, Tin, Copper, Vanadium, Beryllium, Boron, Titanium, Iron, Nickel , Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more of the following materials are selected from the group consisting of aluminum, tantalum, tungsten, magnesium, etc. Metal oxides are preferably used. In particular, the element M is aluminum, gallium, yttrium, Alternatively, tin may be used. In-M oxide and In-Zn oxide are also suitable as oxide semiconductors. Alternatively, M-Zn oxide or M-Zn oxide may be used.

[0052] When a metal oxide is used for the channel formation region of a transistor, hydrogen in the metal oxide can be It is preferable that the amount of hydrogen contained in the metal oxide is reduced as much as possible. This reacts with oxygen to form water, which can cause oxygen vacancies in the metal oxide. If the channel formation region in the oxide contains oxygen vacancies, the transistor will be a normally-on transistor. Furthermore, the defect in which hydrogen is inserted into the oxygen vacancy acts as a donor. In some cases, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with metal atoms. It can combine with oxygen to generate electrons, which are carriers. A transistor using a metal oxide having such a structure tends to have normally-on characteristics.

[0053] The defect where hydrogen has entered the oxygen vacancy can function as a donor in the oxide semiconductor. Therefore, it is difficult to quantitatively evaluate the defects in oxide semiconductors. In some cases, the carrier concentration is used for evaluation, not the donor concentration. As a parameter of the oxide semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification is This can sometimes be rephrased as "donor concentration."

[0054] As described above, a transistor including an oxide semiconductor has a temperature The higher the degree, the lower the threshold voltage of the transistor and the lower the subthreshold swing. The threshold voltage and subthreshold swing of the transistor also increase. The capacitance value is correlated with the carrier concentration of the oxide semiconductor.

[0055] Therefore, when an oxide semiconductor is used for a channel formation region of a transistor, the carrier concentration It is preferable to use an i-type (intrinsic) or substantially i-type oxide semiconductor having a low conductivity. It is desirable to use an oxide semiconductor with a low carrier concentration for a channel formation region of a transistor. Therefore, the off-state current of the transistor can be suppressed to a small value. The reliability of the system can be improved.

[0056] Here, when the donor concentration in the channel formation region of a transistor is changed, This section explains the change in the electrical characteristics of a transistor. When the donor concentration of the semiconductor layer of the transistor is changed, The Id-Vg characteristics were calculated.

[0057] The top view and cross-sectional view of the transistor assumed in the calculations used in the device simulator are shown below. FIG. 2A is a top view of the transistor, and FIG. 2B is a 2B is a cross-sectional view of a portion indicated by a dashed line L1-L2 in FIG. 2A, FIG. 2C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. 2A. 2A is a cross-sectional view of the transistor in the channel width direction. In the top view, some elements have been omitted for clarity.

[0058] As shown in FIGS. 2A to 2C, the transistor is disposed on a substrate (not shown). A conductive layer BGE, an insulating layer BGI1 and an insulating layer BGI2 disposed on the conductive layer BGE, and An insulating layer BGI3, a semiconductor layer SEM1 and a semiconductor layer SE M2, a conductive layer SE and a conductive layer DE disposed on the semiconductor layer SEM2, and a semiconductor layer SE M2, the conductive layer SE, and a semiconductor layer SEM3 disposed on the conductive layer DE; and M3, an insulating layer TGI arranged on the insulating layer TGI, and a conductive layer TGE arranged on the insulating layer TGI. do.

[0059] The conductive layer TGE functions as a first gate (also called a top gate), and the conductive layer BG E functions as a second gate (also called a back gate), and the insulating layer TGI functions as a first The insulating layer BGI1 functions as a gate insulating layer (also called a top gate insulating layer), and the insulating layer BGI2 and the insulating layer BGI3 are a second gate insulating layer (also called a back gate insulating layer). ) and the semiconductor layers SEM1, SEM2, and SEM3 function as semiconductor layers. The conductive layer SE functions as a source, and the conductive layer DE functions as a drain. It works.

[0060] The conductive layer TGE corresponds to the conductive layer 60 of the transistor 10 shown in FIG. 1B, and the insulating layer TGI corresponds to the insulating layer 50 of the transistor 10 shown in FIG. 1B, and the semiconductor layer SEM1 and the semiconductor The semiconductor layer SEM2 corresponds to the semiconductor layer 30 of the transistor 10 shown in FIG. 1B, and the conductive layer SE corresponds to 1B corresponds to the conductive layer 40a of the transistor 10 shown in FIG. 1B. The conductive layer DE corresponds to the conductive layer 40a of the transistor 10 shown in FIG. The conductive layer BGE corresponds to the conductive layer 40b of the transistor 10. The insulating layers BGI1, BGI2, and BGI3 correspond to the conductive layer 80 of the transistor 10. I3 corresponds to insulating layer 70 of transistor 10 shown in FIG. 1B.

[0061] The transistors shown in Figures 2A to 2C have a top gate and a back gate. A transistor having a top gate and a back gate is a transistor having a top gate and a back gate. By applying different potentials to the back gate, the threshold voltage can be controlled. By applying a negative potential to the gate, the threshold voltage of the transistor is increased, and the off-state current In other words, applying a negative potential to the back gate reduces the current. This can reduce the drain current when the potential applied to the top gate is 0V.

[0062] In this calculation, the semiconductor layers SEM1 and SEM2 have different donor concentrations (structure The parameters assumed in the calculations using a device simulator were Among the meter values, the parameter values ​​that differ between Structures 1A to 7A are shown in Table 1.

[0063] [Table 1]

[0064] Calculations were performed using a device simulator for Structures 1A to 7A. The electrical characteristics were calculated using a device simulator manufactured by Silvaco. Atlas3D was used. Each parameter assumed in the calculation using the device simulator Among these values, the parameter values ​​common to Structures 1A to 7A are shown in Table 2.

[0065] [Table 2]

[0066] Specifically, for each of the structures 1A to 7A, the drain voltage Vd=1.2 V In this calculation, a potential was applied to the back gate. not present.

[0067] FIG. 3 shows the calculated Id-Vg characteristics of each of the structures 1A to 7A. In 3, the horizontal axis shows the change in gate voltage Vg [V], and the vertical axis shows the drain current Id [A]. It should be noted that Figure 3 is a semi-logarithmic graph with the vertical axis being logarithmic.

[0068] As shown in FIG. 3, transistor characteristics were obtained in the structures 1A to 6A. The donor concentration of the semiconductor layer SEM1 and the semiconductor layer SEM2 is 1×10 18 cm -3 What to do below In addition, the semiconductor layer SEM1 and the semiconductor layer The lower the donor concentration of SEM2, the more the threshold voltage tends to shift in the positive direction. Therefore, in order for a transistor to have stable electrical characteristics as a normally-off type, the semiconductor layer SEM It can be seen that the donor concentration of 2 is preferably low. The -Vg characteristics were almost the same.

[0069] From the above, the region of the semiconductor layer 30 that functions as the channel formation region of the transistor 10 is The carrier concentration of 34 is 1×10 18 cm -3 Preferably, it is 5×10 or less. 17 cm -3 More preferably, it is less than 2×10 17 cm -3 It is furthermore true that Preferably 2 x 10 16 cm -3 It is more preferable that the thickness of the semiconductor layer 3 is less than 100 nm. The carrier concentration in the region 34 is 1×10 12 cm -3 It is preferable that the concentration is 1× or more. 10 13 cm -3 It is more preferable that the above is satisfied. The threshold voltage of the transistor 10 is high and the subthreshold voltage is low regardless of the temperature at which the transistor operates. Therefore, the off-state current of the transistor 10 can be reduced. This can reduce the resistance of the transistor 10 and improve the reliability of the transistor 10.

[0070] As described above, a transistor using a metal oxide containing hydrogen is Therefore, it is important to reduce the amount of hydrogen in the metal oxide as much as possible. Specifically, it is preferable to measure the area 34 of the semiconductor layer 30 by secondary ion mass spectrometry ( By SIMS (Secondary Ion Mass Spectrometry) The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 a toms / cm 3 less than 5×10 18 atoms / cm 3 Less than or equal to Preferably 1×10 18 atoms / cm 3 less than 2×10 17 atom s / cm 3 The metal oxide with sufficiently reduced hydrogen is used as the channel shape of the transistor. By using it in the composition region, stable electrical properties can be imparted. The relationship between the hydrogen concentration and the carrier concentration will be described later.

[0071] The regions 31a and 31b of the semiconductor layer 30 preferably have low resistance regions. By providing the region 31a having a low resistance region between the conductive layer 40a and the region 34, the conductive The electric field at the junction between layer 40a and region 34 is weakened, suppressing hot carrier degradation and improving reliability. In addition, the low resistance region between the conductive layer 40b and the region 34 can be provided. By providing the region 31b, the electric field at the junction between the conductive layer 40b and the region 34 is weakened, This makes it possible to suppress degradation of hot carriers and improve reliability.

[0072] In addition, the junction between the semiconductor layer 30 and the conductive layer 40a, and the junction between the semiconductor layer 30 and the conductive layer 40b The junction between the semiconductor layer 30 and the conductive layer 40b is often a Schottky contact. In the case of key contact, the region 31a and the region 31b have low resistance regions, so that the semiconductor layer 3 0 and the conductive layer 40a, and between the semiconductor layer 30 and the conductive layer 40b. The wall can be made lower, and the contact resistance can be reduced. The junction with 0a is preferably a Schottky contact as described above, but one embodiment of the present invention is For example, if transistor characteristics are obtained, the semiconductor layer 30 and the conductive layer The junction with the semiconductor layer 40a may be an ohmic contact. Although only the junction between the semiconductor layer 30 and the conductive layer 40a is mentioned, the junction between the semiconductor layer 30 and the conductive layer 40b The junction may also be an ohmic contact.

[0073] In addition, for example, the capacitance of the low resistance region of the region 31a and the region 31b of the semiconductor layer 30 is The rear concentration is 1×10 17 cm -3 More than 1×10 21 cm -3 It is preferable that the , 5×10 17 cm -3 More than 1×10 19 cm -3 It is more preferable that it is less than 1000 .mu.m.

[0074] The carrier concentration of the low resistance regions of the regions 31a and 31b of the semiconductor layer 30 is The region 34 of the semiconductor layer 30 that functions as a channel forming region of the transistor 10 is For example, the carrier concentration in the region 34 of the semiconductor layer 30 is preferably higher than the carrier concentration in the region 34 of the semiconductor layer 30. The ratios of the carrier concentrations of the regions 31a and 31b of the semiconductor layer 30 to This is preferably 10 or more, and 1×10 2 More preferably, 2×10 3 More than 2×10 5 More preferably, the drain current flowing through transistor 10 when it is in a conductive state is: The on-current can be increased.

[0075] In FIG. 1A, the region 34, as well as the regions 31a and 31b of the semiconductor layer 30, The upper surface of the semiconductor layer 30 (the conductive layer 60, the conductive layer 40a, and the conductive layer 40b side) is However, the present embodiment is not limited to this. , region 34, and regions 31a and 31b are formed from the upper surface to the lower surface of the semiconductor layer 30. It may be formed of.

[0076] In addition, in FIG. 1A, the boundary between the region 34 and the region 31a and the boundary between the region 34 and the region 31b are Although the field is shown to be approximately aligned with the sides of the conductive layer 60 and the insulating layer 50, in this embodiment However, the present invention is not limited to this.

[0077] For example, as shown in FIG. 4A, the region 31a and the region 31b are connected via the insulating layer 50. The semiconductor layer 30 may have an area overlapping with the conductive layer 60. A high resistance region is not formed between the channel forming region and the source and drain regions. Therefore, the on-state current and mobility of the transistor 10 can be increased.

[0078] For example, as shown in FIG. 4B, the boundary between the region 34 and the region 31a and the region 34 The boundary between the semiconductor layer 30 and the region 31b is a boundary between the semiconductor layer 30, the conductive layer 60, the conductive layer 40a, and the conductive layer 40. b may be located in a region where they do not overlap. This can reduce the off-state current of the transistor 10.

[0079] As shown in FIG. 4C, the semiconductor layer 30 has a region 32 between the region 34 and the region 31a. a and a region 32b may be provided between the region 34 and the region 31b. Here, the region 32 The carrier concentration of a is higher than that of the region 34 and is higher than that of the region 31a. Similarly, the carrier concentration of region 32b is preferably lower than the carrier concentration of region 34. It is preferable that the carrier concentration of the region 31b is higher than that of the region 31a and lower than that of the region 31b. By this, the difference in carrier concentration between the region 31a and the region 34 and the difference between the region 31b and the region 34 are 4, thereby increasing the on-state current and mobility of the transistor 10. In addition, the short channel effect can be suppressed.

[0080] In addition, when a metal oxide is used for the semiconductor layer 30, the conductive layer 40 (conductive layer 40a and conductive layer 40b) When the conductive layer 40b) is in contact with the semiconductor layer 30, the oxide constituting the metal oxide of the semiconductor layer 30 is The conductive layer 40 may be oxidized by atomic atoms. In addition, oxygen atoms in the semiconductor layer 30 diffuse into the conductive layer 40, As a result, the semiconductor layer 30 near the interface with the conductive layer 40 becomes oxygen deficient. The possibility of causing variations in the electrical characteristics of transistors and reduced reliability of transistors. is high.

[0081] By oxidizing the conductive layer 40, the conductive layer 40a (conductive layer 40b) and A layer 44a (layer 44b) may be formed between the semiconductor layer 30. When 44b has insulating properties, the conductive layer 40a (conductive layer 40b) and the layer 44a (layer 44b) The three-layer structure with the semiconductor layer 30 is a three-layer structure consisting of a metal-insulator-semiconductor, and is called MIS ( This is sometimes called a Metal-Insulator-Semiconductor structure. By having a three-layer structure, the capacitance between the conductive layer 40a (conductive layer 40b) and the semiconductor layer 30 is In addition, the formation of layers 44a and 44b is likely to suppress the movement of the rear. The interface between the conductive layer 40a (conductive layer 40b) and the semiconductor layer 30 is deteriorated by the heat treatment. This can prevent the above from happening.

[0082] For example, when a tantalum nitride film is used for the conductive layer 40 and a metal oxide film is used for the semiconductor layer 30, The layer 44 (layer 44a and layer 44b) is a layer having tantalum, nitrogen, and oxygen, or Alternatively, it will be a layer having tantalum and oxygen.

[0083] Therefore, it is preferable to control the formation of the layer 44 (layer 44a and layer 44b). Specifically, the formation of layer 44 is controlled by reducing the thickness of layer 44 and by controlling the electron affinity of layer 44. and the electron affinity of the conductive layer 40 (conductive layer 40a and conductive layer 40b) (energy barrier 4. The interface state formed at and near the interface between layer 44 and semiconductor layer 30 is reduced. More specifically, the thickness of the layer 44 is set to be 0.1 nm or more and 3 nm or less. , preferably 0.5 nm to 2 nm. By controlling the formation of the layer 44, the conductive layer This makes it easier for current to flow between the semiconductor layer 40 and the semiconductor layer 30, thereby improving the reliability of the transistor. In addition, the transistor becomes thermally stable, and can operate stably even at high temperatures. can.

[0084] The thickness of the layer 44 was measured by observing the cross-sectional shape of the layer 44 and its surroundings using a transmission electron microscope (TEM). :Transmission Electron Microscope) Sometimes it is possible to measure something by observing it.

[0085] The thickness of the layer 44 was measured by energy dispersive X-ray spectroscopy of the layer 44 and its surroundings. It may be possible to calculate the composition by line analysis using EDX. For example, the thickness of the layer 44 is determined by the position (depth) of the interface between the layer 44 and the semiconductor layer 30 and the conductive layer 40. The difference between the position (depth) of the interface with the layer 44 and the depth of the layer 45 is the depth obtained by EDX line analysis. In the profile of the quantitative values ​​of each element with respect to (Depth) is the definition of a metal that is the main component of the semiconductor layer 30 and is not the main component of the conductive layer 40. The position (depth) of the interface between the conductive layer 40 and the layer 44 is the depth at which the amount of the ion implantation reaches half its value. The depth is the depth at which the quantitative value of oxygen in the conductor layer 30 becomes half its value. It is possible.

[0086] To control the formation of layer 44, conductive layer 40 should be made of a material that is resistant to oxidation (is difficult to oxidize). It is preferable to use a conductive material. For example, titanium nitride, titanium nitride, etc., can be used as the conductive layer 40. It is preferable to use metal nitrides such as tungsten nitride, molybdenum nitride, and tungsten nitride. In addition, it is preferable to increase the crystallinity of the conductive layer 40, and it is preferable to increase the film density of the conductive layer 40. In addition, it is preferable to lower the temperature during the heat treatment performed after the formation of the conductive layer 40. This makes the conductive layer 40 less susceptible to oxidation, suppressing the formation of the layer 44 and reducing the thickness of the layer 44. The thickness can be reduced.

[0087] In addition, the formation of layer 44 can be controlled by providing a gap between conductive layer 40a and semiconductor layer 30 and between conductive layer 40b and semiconductor layer 30. A layer may be provided between the conductive layer 40b and the semiconductor layer 30. By providing such a layer, The conductive layer 40a and the semiconductor layer 30, and the conductive layer 40b and the semiconductor layer 30 are not in direct contact with each other. Therefore, it is possible to suppress the conductive layer 40a and the conductive layer 40b from being oxidized. Therefore, the layer has a function of suppressing oxidation of the conductive layers 40a and 40b. It is preferable that the layer has a function of suppressing the transmission of oxygen.

[0088] The layer may be made of a metal oxide having element M. In particular, element M is aluminum. The layer may be made of tungsten, gallium, yttrium, or tin. It is preferable that the concentration of element M is high. In addition, gallium oxide may be used for the above layer. Moreover, metal oxides such as In-M-Zn oxide may be used for the layer. In the metal oxide used in the layer, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In in the layer 30 is larger than that in the layer 30. The thickness of the film is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. In addition, the layer is preferably crystalline. When the layer is crystalline, The layer can be preferably made of a hexagonal crystal. Such a crystal structure may be capable of suppressing the release of oxygen from the semiconductor layer 30.

[0089] So far, we have considered the carrier concentration of the oxide semiconductor used in the channel formation region of a transistor. By reducing the threshold voltage of the transistor, the subthreshold swing is reduced. The off-state current of the transistor can be reduced, improving reliability. It has been described that the threshold voltage of the transistor can be increased, When the subthreshold swing value is reduced, the leakage current of the transistor is reduced. This makes it possible to further reduce the off-state current of the transistor, thereby improving reliability. It can be improved.

[0090] Here, the leakage current of a transistor will be described with reference to FIG. 5A and FIG. 5B. The transistor includes a first gate, a second gate, a first gate insulating layer, a second a gate insulating layer, a semiconductor layer having a channel forming region, a source, and a drain .

[0091] FIG. 5A is a schematic diagram of the current (I)-gate voltage (Vg) characteristics of a transistor. 1B is a schematic diagram of the drain current (Id)-gate voltage (Vg) characteristics of a transistor. In FIG. 5A and FIG. 5B, the horizontal axis represents the change in voltage (Vg) [V] applied to the first gate. The vertical axis shows the change in current (I) [A] or drain current (Id) [A]. Note that Figures 5A and 5B are semi-logarithmic graphs with a logarithmic vertical axis.

[0092] Current A, shown by a solid line in FIG. 5A, flows from the drain to the source through the channel formation region. Current B shown by the dashed line in FIG. 5A is the current flowing from the drain to the first gate. The current C shown by the dotted line in FIG. 5A is the current flowing from the drain to the second gate. Here, the current A in the non-conducting state is sometimes called the subthreshold leakage current. In addition, the current B in the non-conducting state is sometimes called the first leakage current. The current C in this state may be referred to as the second leakage current.

[0093] Also, the voltage Vab shown in Figure 5A is the gate voltage value at which the values ​​of current A and current B are the same. Also, the voltage Vbc shown in FIG. 5A is the gate voltage at which the values ​​of current B and current C are the same. The voltage Vac shown in FIG. 5A is the gate voltage at which the values ​​of current A and current C are the same. is the pressure value.

[0094] The current D shown in FIG. 5B is the drain current of the transistor. , is observed as the sum of current A, current B, and current C.

[0095] In the drain current of a transistor having the Id-Vg characteristics shown in FIG. 5B, the gate voltage When the value of the voltage Vg is less than the voltage Vbc, the ratio of the current B to the drain current is high, and the gate When the voltage Vg is greater than or equal to Vbc and less than Vac, the ratio of the current C to the drain current is When the gate voltage Vg is high and the value of the gate voltage Vac is equal to or higher than the voltage Vac, the ratio of the current A to the drain current is expensive.

[0096] The transistor is in a non-conducting state when no potential is applied to the first gate (Vg=0V). In the case where a potential is not applied to the first gate, the drain current (off current) is mainly Therefore, by increasing the threshold voltage of the transistor, Or, by reducing the subthreshold swing value, the subthreshold This can reduce the on-state current and the off-state current.

[0097] In addition, the threshold voltage of the transistor is increased, or the subthreshold switching If the switching value is reduced, the voltage Vac may become large. When the off-state current is increased, the second leakage current becomes the main component of the off-state current. To reduce this, the second leakage current must be reduced.

[0098] In order to reduce the second leakage current, it is preferable to increase the thickness of the second gate insulating layer. In order to reduce the second leakage current, the interface between the second gate insulating layer and the semiconductor layer and It is advisable to reduce the interface states formed in the vicinity.

[0099] Furthermore, when the current (current C) flowing from the drain to the second gate is reduced, the voltage Vb c may be greater than the voltage Vac. In particular, when the voltage Vbc becomes greater than 0V, Therefore, in order to reduce the off-current, the first leakage current is the main component. It is necessary to reduce the leakage current of 1.

[0100] In order to reduce the first leakage current, it is preferable to increase the thickness of the first gate insulating layer. In order to reduce the first leakage current, the interface between the first gate insulating layer and the semiconductor layer and It is advisable to reduce the interface states formed in the vicinity.

[0101] As described above, the leakage current of the transistor (subthreshold leakage current, first leakage current) By reducing the first leakage current and the second leakage current, the off-state current of the transistor can be reduced. This can further reduce the size of the chip, thereby further improving the reliability.

[0102] For example, in the temperature range of 180°C to 220°C, It is possible to make the off-state current of the transistor 10 1 aA or less. In the temperature range of up to 220° C., the on / off current per 1 μm of channel width of the transistor 10 is It is possible to reduce the f-current to 10 aA / μm or less.

[0103] <Metal oxide> It is preferable to use a metal oxide that functions as a semiconductor for the semiconductor layer 30. Next, metal oxides applicable to the semiconductor layer 30 according to the present invention will be described.

[0104] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, nickel, etc. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide One or more of the following metals selected from the group consisting of fluorine, tantalum, tungsten, magnesium, etc. may be included.

[0105] Here, the metal oxide is an In-M-Zn oxide having indium, element M and zinc. The element M can be aluminum, gallium, yttrium, or The element M is tin. Other elements that can be used for M include boron, titanium, iron, and nickel. Ru, Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium However, the element M is the same as above. In some cases, a combination of multiple elements may be acceptable.

[0106] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0107] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor), and Examples include amorphous oxide semiconductors.

[0108] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0109] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have a lattice arrangement such as a pentagon or heptagon. In the CAAC-OS, clear grain boundaries are not observed even in the vicinity of the strain. It is difficult to confirm the above point. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS has oxygen atoms in the ab-plane direction. The arrangement of the atoms is not dense, and the bond distance between the atoms changes when metal elements are substituted. This is because distortion can be tolerated by the above-mentioned factors.

[0110] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter, the In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). Indium and element M tend to have a layered structure. Therefore, indium may exist at the metal site of the (M,Zn) layer. Furthermore, the element M may be present at the metal site of the In layer.

[0111] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of metal oxides having CAAC-OS are stable. Therefore, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0112] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. Sometimes it is indistinguishable from the body.

[0113] In addition, In-, a type of metal oxide containing indium, gallium, and zinc, Ga-Zn oxide (hereinafter referred to as IGZO) has a stable structure when made into the above-mentioned nanocrystals. In particular, IGZO tends to have difficulty growing crystals in the air, so large crystals may form. A crystal smaller than a crystal (here, a crystal of a few mm or a crystal of a few cm) (for example, the above-mentioned In some cases, a more stable structure may be obtained by forming the material into a nanocrystal.

[0114] The a-like OS is a metal oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has voids or low density regions. The ke-OS has a lower crystallinity than the nc-OS and CAAC-OS.

[0115] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention can be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more kinds.

[0116] [Transistors with metal oxide] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0117] It is preferable to use a metal oxide having a low carrier density for the transistor. In order to reduce the carrier density of a material, the impurity concentration in the metal oxide is reduced, and defects are eliminated. In this specification and the like, the low impurity concentration and the low defect level density are High purity genuine or substantially high purity genuine is also called high purity genuine or substantially high purity genuine. High-purity intrinsic metal oxides have a low defect level density, and therefore a low trap level density. There are cases.

[0118] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0119] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0120] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0121] In addition, when an alkali metal or alkaline earth metal is contained in a metal oxide, a defect level is formed. Therefore, alkali metals or alkaline earth metals may form a carrier. A transistor that uses a metal oxide containing metals in the channel formation region is a normally-on transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide Specifically, it is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 The following are the preferred Or 2×10 16 atoms / cm 3 To the following:

[0122] According to one embodiment of the present invention, a semiconductor device that operates stably even at high temperatures can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. A semiconductor device having higher reliability can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. A conductor device can be provided.

[0123] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments or examples. The method can be used in combination with other methods.

[0124] (Embodiment 2) In this embodiment, a structural example of the transistor described in the above embodiment will be described.

[0125] <Transistor structure example 1> A structural example of a transistor 200A will be described with reference to FIGS. 6A to 6C. 6B is a top view of the resistor 200A and its surroundings. 6C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. In addition, in the top view of FIG. 6A, some elements are omitted for clarity.

[0126] 6A to 6C, a transistor 200A and an insulating layer 210 serving as an interlayer film are , insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 280, insulating layer 282, and insulating layer 284. Also shown is a contact layer 284 electrically connected to the transistor 200A. A conductive layer 246 (conductive layer 246a and conductive layer 246b) functioning as a plug and a wiring A conductive layer 203 that functions as a line is also shown.

[0127] The transistor 200A functions as a first gate (also referred to as a top gate) electrode. A conductive layer 260 (conductive layer 260a and conductive layer 260b) and a second gate (bottom gate) are formed on the conductive layer 260. The conductive layer 205 (conductive layer 205a and conductive layer 205b) functions as an electrode. 5b), an insulating layer 250 serving as a first gate insulating layer, and a second gate insulating layer The insulating layer 220, the insulating layer 222, and the insulating layer 224 function as a channel. Oxide 230 having regions (oxide 230a, oxide 230b, and oxide 230c) and a conductive layer 242a serving as one of a source and a drain. The conductive layer 242b functions as the other of the gates, and an insulating layer 274.

[0128] The insulating layers 210 and 212 function as interlayer films.

[0129] The interlayer film may be silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. , hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZ T), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST) Any of the insulators may be used in a single layer or a multilayer. , aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, acid Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may also be added. Alternatively, these insulators may be nitrided. Silicon or silicon nitride may also be used in a laminated form.

[0130] For example, the insulating layer 210 is formed such that impurities such as water and hydrogen are absorbed from the substrate side of the insulating layer 210. It is preferable that the film functions as a barrier film to prevent the inclusion of the metal oxide in the transistor 200A. Therefore, the insulating layer 210 prevents the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use an insulating material that has a function of suppressing the penetration of the impurities. Alternatively, the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use an insulating material having the above-mentioned function (i.e., being difficult for oxygen to permeate). For example, the insulating layer 210 may be made of aluminum oxide, silicon nitride, or the like. With this configuration, impurities such as water and hydrogen are absorbed from the substrate side of the insulating layer 210 to the transistor 20. It is possible to suppress diffusion to the 0A side.

[0131] For example, the insulating layer 212 preferably has a lower dielectric constant than the insulating layer 210. By using a low-cost material for the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0132] The conductive layer 203 is formed so as to be embedded in the insulating layer 212. The height of the upper surface of the conductive layer 203 can be made to be approximately the same as the height of the upper surface of the insulating layer 212. Although a single-layer structure is shown, the present invention is not limited to this. For example, Alternatively, the conductive layer 203 may have a multilayer structure of two or more layers. It is preferable to use a conductive material having high conductivity, the main component of which is stainless steel, copper, or aluminum. I wish.

[0133] In the transistor 200A, the conductive layer 260 functions as a first gate electrode. In some cases, the conductive layer 205 functions as a second gate electrode. In this case, the potential applied to the conductive layer 205 is not linked to the potential applied to the conductive layer 260 but is independent. By varying the potential, the threshold voltage of the transistor 200A can be controlled. In addition, a negative potential is applied to the conductive layer 205 to lower the threshold voltage of the transistor 200A. Therefore, it is possible to increase the negative voltage and reduce the off-current. The application of a potential is more effective than the application of no potential when the potential applied to the conductive layer 260 is 0 V. This allows the drain current to be reduced.

[0134] In addition, for example, the conductive layer 205 and the conductive layer 260 are provided so as to overlap each other. When a potential is applied to conductive layer 200 and conductive layer 205, the electric field generated by conductive layer 260 and the 05 and covers the channel formation region formed in the oxide 230. That is, the electric field of the conductive layer 260 functioning as the first gate electrode and the electric field of the second The electric field of the conductive layer 205 functioning as a gate electrode electrically separates the channel forming region. It can be surrounded.

[0135] The insulating layer 214 and the insulating layer 216 are interlayer insulating layers similar to the insulating layer 210 and the insulating layer 212. For example, the insulating layer 214 functions as a film to prevent impurities such as water and hydrogen from entering the insulating layer 214. In addition, it functions as a barrier film that prevents foreign matter from entering the transistor 200A from the substrate side. With this configuration, impurities such as water and hydrogen are absorbed from the substrate side rather than the insulating layer 214. In addition, the insulating layer 2 It is preferable that the dielectric constant of the insulating layer 16 is lower than that of the insulating layer 214. This makes it possible to reduce the parasitic capacitance occurring between the wirings.

[0136] The conductive layer 205 functioning as the second gate electrode is disposed between the insulating layer 214 and the insulating layer 216. A conductive layer 205a is formed in contact with the inner wall of the opening, and a conductive layer 205b is formed further inside. Here, the height of the upper surfaces of the conductive layer 205a and the conductive layer 205b and In the transistor 200A, the height of the upper surface of the insulating layer 216 can be made to be approximately the same. The present invention is not limited to the above-described structure in which the conductive layer 205a and the conductive layer 205b are laminated. For example, the conductive layer 205 may be a single layer or a laminated structure of three or more layers. It may be configured so that the

[0137] Here, the conductive layer 205a is a layer formed by diffusing impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. It is preferable to use a conductive material that has a function of suppressing the impurities (i.e., the impurities are less likely to permeate). Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is suppressed. It is preferable to use a conductive material that has the function of preventing oxygen from permeating through the conductive material. In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of the impurities or oxygen. has the function of suppressing the diffusion of any one or all of the oxygen.

[0138] For example, the conductive layer 205a has a function of suppressing the diffusion of oxygen, so that the conductive layer 205 It is possible to suppress the oxidation of b and the decrease in electrical conductivity.

[0139] When the conductive layer 205 also functions as a wiring, the conductive layer 205b is made of tungsten, copper, or the like. It is preferable to use a conductive material having high conductivity, which is mainly composed of aluminum. In this case, the conductive layer 203 is not necessarily provided. However, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. A laminate of the above may also be used.

[0140] Insulating layer 220, insulating layer 222, and insulating layer 224 function as a second gate insulating layer. do.

[0141] Here, it is preferable that the insulating layer 224 in contact with the oxide 230 is heated to release oxygen. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulating layer 224 may be made of silicon oxide or silicon oxynitride. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This can improve the reliability of the transistor 200A.

[0142] Specifically, the insulating layer 224 is made of an oxide material from which oxygen is partially released by heating. The oxide that releases oxygen by heating is called TDS (Thermal Dynamics) oxide. The oxygen in terms of oxygen atoms was analyzed by Esorption Spectroscopy. The amount of desorption is 1.0×10 18 atoms / cm 3 More than 1.0×10 19 at oms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 That's all, is 3.0 x 10 20 atoms / cm 3 The oxides are as above. The surface temperature of the film at this time is 100°C to 700°C or 100°C to 400°C. ° C. or less is preferred.

[0143] In addition, the insulating layer 222 preferably has a barrier property. By having such a structure, it is possible to prevent impurities such as hydrogen from being introduced into the transistor 200A from the peripheral area of ​​the transistor 200A. It functions as a layer that suppresses the inclusion of impurities.

[0144] The insulating layer 222 may be, for example, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide. Oxides containing hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, Lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba, Insulators containing so-called high-k materials such as Sr)TiO3(BST) are used as single layers or stacked layers. As transistors become smaller and more highly integrated, the gate insulation Thinning of the insulating layer may cause problems such as leakage current. By using high-k materials as insulators, the physical thickness can be maintained while The gate potential during operation can be reduced.

[0145] For example, the insulating layer 220 is preferably thermally stable, e.g., silicon oxide. Silicon oxide nitride and silicon oxynitride are preferred because they are thermally stable. By combining the insulating material with silicon oxide or silicon oxynitride, the thermally stable Moreover, it is possible to obtain insulating layer 220 having a laminated structure with a high relative dielectric constant.

[0146] In addition, in FIG. 6B and FIG. 6C, a three-layer laminate structure is shown as the second gate insulating layer. However, it may be a single layer, or a laminated structure of two or four or more layers. In that case, However, the present invention is not limited to a laminated structure made of the above-mentioned materials, and may be a laminated structure made of different materials.

[0147] The oxide 230 having a region that functions as a channel formation region is made up of an oxide 230a and an oxide 2, the first oxide 230b is on the oxide 230a, and the second oxide 230c is on the oxide 230b. By having the oxide 230a under the oxide 230b, the oxide 230a is formed below the oxide 230a. The diffusion of impurities from the structure to the oxide 230b can be suppressed. By having the oxide 230c on the object 230b, the oxide 230c is formed above the oxide 230c. The diffusion of impurities from the structure to the oxide 230b can be suppressed. As the semiconductor, the metal oxide shown in the above embodiment can be used. .

[0148] In addition, the transistor 200A shown in FIG. 6A and FIG. 6B includes a conductive layer 242 (conductive layer 2 42a, and conductive layer 242b), oxide 230c, insulating layer 250, and conductive layer 26 By using this structure, a transistor with high on-state current can be manufactured. In addition, a transistor with high controllability can be provided.

[0149] One of the conductive layers 242 functions as a source electrode and the other functions as a drain electrode. .

[0150] The conductive layer 242 may be made of aluminum, titanium, chromium, nickel, copper, yttrium, or zinc. Metals such as ruthenium, molybdenum, silver, tantalum, and tungsten, or those mainly composed of such metals In particular, a metal nitride film such as tantalum nitride can be used as an alloy containing hydrogen. It is preferable because it has a barrier property against oxygen and has high oxidation resistance.

[0151] Although the conductive layer 242 shown in FIG. 6B has a single-layer structure, it may have a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Alternatively, an aluminum film may be laminated on a tungsten film. A two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film; Two-layer structure with copper film laminated on tungsten film, two-layer structure with copper film laminated on tungsten film Good too.

[0152] Also, a titanium film or a titanium nitride film and an aluminum film on the titanium film or the titanium nitride film A three-layer structure in which a titanium film or titanium nitride film is laminated on top of the aluminum or copper film. Structure, molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film An aluminum film or a copper film is laminated on the film, and a molybdenum film or a molybdenum nitride film is further laminated on the aluminum film or a copper film. In addition, indium oxide, tin oxide, or zinc oxide is used. A transparent conductive material containing the same may be used.

[0153] A barrier layer may be provided over the conductive layer 242. The barrier layer is a layer that is resistant to oxygen or water. It is preferable to use a material having a barrier property against the element. When the conductive layer 242 is formed, oxidation of the conductive layer 242 can be suppressed.

[0154] The barrier layer may be made of, for example, a metal oxide. The insulating film has barrier properties against oxygen and hydrogen, such as gallium oxide, hafnium oxide, and gallium oxide. It is preferable to use chemical vapor deposition (CVD). Silicon nitride formed by the (Si) deposition method may also be used.

[0155] By including the barrier layer, the range of materials that can be selected for the conductive layer 242 can be expanded. For example, the conductive layer 242 may be made of a material having low oxidation resistance but low conductivity, such as tungsten or aluminum. In addition, for example, a conductive material that is easy to form a film or process can be used. It can be used.

[0156] The insulating layer 250 serves as the first gate insulating layer.

[0157] As transistors become smaller and more highly integrated, the gate insulating layer becomes thinner, which reduces the leakage current. In that case, the insulating layer 250 may be used as the second gate insulating layer. The insulator serving as the gate insulating layer may be a high-k By using a laminated structure of a material that is thermally stable, the thickness of the material can be maintained while maintaining the thickness of the material. It is possible to reduce the gate potential during transistor operation. In addition, it is thermally stable and has a high relative dielectric constant. It is possible to obtain a laminated structure.

[0158] The conductive layer 260 functioning as the first gate electrode is made up of a conductive layer 260a and a conductive layer 26 The conductive layer 260a is a hydrogen atom-containing layer, similar to the conductive layer 205a. Conductive materials that have the function of suppressing the diffusion of impurities such as electrons, hydrogen molecules, water molecules, and copper atoms. It is preferable to use at least one of oxygen (e.g., oxygen atom, oxygen molecule, etc.) It is preferable to use a conductive material having a function of suppressing the diffusion of the ions.

[0159] Since the conductive layer 260a has a function of suppressing the diffusion of oxygen, the material of the conductive layer 260b In other words, the conductive layer 260a can improve the selectivity. The oxidation of b is suppressed, and the decrease in electrical conductivity can be prevented.

[0160] Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and tantalum nitride. It is preferable to use ruthenium, ruthenium oxide, or the like. As the oxide 230, an oxide semiconductor can be used. In this case, the conductive layer 260b is formed by sputtering, so that the electrical resistance of the conductive layer 260a is The resistance can be reduced to provide a conductive layer.

[0161] In addition, since the conductive layer 260 functions as a wiring, a conductor having high conductivity can be used. For example, the conductive layer 260b may be made of a material mainly composed of tungsten, copper, or aluminum. The conductive layer 260b may have a layered structure. For example, a laminate of titanium, titanium nitride and the above-mentioned conductive material may be used.

[0162] In addition, the upper surface and side surfaces of the conductive layer 260, the side surfaces of the insulating layer 250, and the oxide 230c It is preferable to provide an insulating layer 274 so as to cover the side surface of the substrate. It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to use aluminum oxide, hafnium oxide, etc. For example, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide Metal oxides such as zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide; Silicon oxide, silicon nitride, etc. can be used.

[0163] By providing the insulating layer 274, oxidation of the conductive layer 260 can be suppressed. By providing the insulating layer 280 with the insulating layer 274, impurities such as water and hydrogen can be prevented from entering the transistor. It is possible to suppress diffusion to 200A.

[0164] The insulating layers 280, 282, and 284 function as interlayer films.

[0165] The insulating layer 282, like the insulating layer 214, prevents impurities such as water and hydrogen from entering the transistor from the outside. It is preferable that the insulating film functions as a barrier insulating film that prevents the metal from being mixed into the photoconductor 200A.

[0166] In addition, the insulating layers 280 and 284, like the insulating layer 216, are thicker than the insulating layer 282. By using a material with a low dielectric constant as the interlayer film, the This can reduce the parasitic capacitance caused by the

[0167] The transistor 200A is also provided with an insulating layer 280, an insulating layer 282, and an insulating layer 284. Electrical connection to other structures may be made through plugs or wiring such as the buried conductive layer 246. good.

[0168] The material of the conductive layer 246 may be a metal material, an alloy material, or a gold material, similar to the conductive layer 205. Conductive materials such as metal nitride materials and metal oxide materials can be used as single layers or laminated layers. For example, high melting point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. It is preferable to use a low-resistance conductive material to reduce the wiring resistance.

[0169] For example, the conductive layer 246 may be made of a material having a barrier property against hydrogen and oxygen. By using a layered structure of conductive tantalum nitride and highly conductive tungsten, It is possible to suppress the diffusion of impurities from the outside while maintaining the electrical conductivity of the wiring. .

[0170] In addition, an insulating layer 276 (insulating layer) having a barrier property is provided between the conductive layer 246 and the insulating layer 280. The insulating layer 276 may be provided on the insulating layer 276. The oxygen in the insulating layer 280 reacts with the conductive layer 246, and the conductive layer 246 is prevented from being oxidized. This can be done.

[0171] In addition, by providing the insulating layer 276 having a barrier property, the conductive material used for the plug and wiring can be For example, the conductive layer 246 may be made of a material that has the property of absorbing oxygen. By using metal materials with high electrical conductivity, a semiconductor device with low power consumption can be provided. Specifically, tungsten and aluminum have low oxidation resistance, while A material having high electrical conductivity can be used. In addition, for example, a conductive material that is easy to form a film or process can be used. An electric body can be used.

[0172] By using the above structure, a semiconductor device having a transistor with a large on-state current is provided. In addition, a semiconductor device including a transistor with low off-state current can be provided. In addition, the fluctuation of the electrical characteristics is suppressed, and the electrical characteristics are stable, and the reliability is high. It is possible to provide a semiconductor device having improved performance.

[0173] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0174] [substrate] The substrate on which the transistor 200A is formed may be, for example, an insulating substrate, a semiconductor substrate, or a As the insulating substrate, for example, a glass substrate, a quartz substrate, Sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin Semiconductor substrates include, for example, silicon and germanium substrates. Semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of gallium oxide, zinc oxide, and arsenic oxide are also available. The semiconductor substrate having an insulating region therein, for example, SOI (Silicon on Insulator) Conductive substrates include graphite substrates and metal substrates. Plates, alloy substrates, conductive resin substrates, etc. Also, substrates with metal nitrides, metal Furthermore, a conductor or semiconductor is provided on an insulating substrate. a substrate having a conductor or insulator provided on a semiconductor substrate; a substrate having a conductor or insulator provided on a conductive substrate; There are also substrates with insulators. The elements provided on the substrate may include a capacitance element, a resistance element, a switching element, a light emitting element, and the like. elements, memory elements, etc.

[0175] [Insulator] Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0176] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. The material should be selected accordingly.

[0177] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum and hafnium, and oxides containing aluminum and hafnium oxide-nitride having silicon and hafnium; oxide-nitride having silicon and hafnium; Examples of suitable materials include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0178] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen, silicon oxide with voids, or resin, etc. be.

[0179] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators (insulating layer 214, insulating layer 222, insulating layer 274, etc.) having a function of suppressing By surrounding the transistor, the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of metals and oxygen include boron, carbon, and nitrogen. Argon, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, Lithium, Germanium, Yttrium, Zirconium, Lanthanum, Neodymium, Hafnium Insulators containing tantalum or tantalum may be used in a single layer or a multilayer structure. Aluminum oxide is an insulator that has the function of suppressing the permeation of impurities such as silicon and oxygen. Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Metal oxides such as lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide Aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxide nitride, nitride Metal nitrides such as silicon can be used.

[0180] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0181] [conductor] Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from aluminum, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. It is preferable because it is a material that maintains its conductivity even if it is oxidized. In addition, it does not contain impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, etc. Silicide may also be used.

[0182] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0183] In the case where an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminate structure in which an oxygen-containing conductive material is used as the It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0184] In particular, the metal oxide in which the channel is formed is a conductor that functions as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the metal. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. In addition, a conductive material containing nitrogen such as indium tin oxide or tungsten oxide may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may be used. By using such a material, the channel is formed In some cases, hydrogen can be captured from the metal oxide that is insulated from the outer In some cases, it may be possible to capture hydrogen that is mixed in from the surroundings, etc.

[0185] <Film formation method> Insulating materials for forming insulating layers, conductive materials for forming electrodes, or semiconductors The semiconductor material for forming the layer is deposited by sputtering, spin coating, CVD (thermal C VD method, MOCVD (Metal Organic CVD) method, PECVD (Plas Enhanced CVD method, High density plasma CVD (High density y plasma CVD) method, LPCVD (low pressure CVD) method, APCVD (atmospheric pressure CVD) method, etc.), atomic Atomic Layer Deposition (ALD) method, molecular beam epitaxy Molecular Beam Epitaxy (MBE) method, pulsed laser deposition PLD (Pulsed Laser Deposition) method, dip method, sp Ray coating method, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset The insulating layer can be formed by using a method such as inkjet printing.

[0186] The plasma CVD method can produce high-quality films at relatively low temperatures. When a deposition method that does not use plasma is used, such as thermal CVD, damage is likely to occur on the deposition surface. For example, wiring, electrodes, and elements (transistors, capacitors, etc.) included in memory devices Some particles (such as electrons) may become charged up by receiving an electric charge from the plasma. When this happens, the accumulated charge destroys the wiring, electrodes, elements, etc. contained in the memory device. On the other hand, in the case of a film formation method that does not use plasma, such plasma damage may occur. This makes it possible to increase the yield of memory devices. Since no image is generated, a film with few defects can be obtained.

[0187] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0188] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition using a vacuum, the time required for deposition is shorter due to the time required for transportation and pressure adjustment. Therefore, the productivity of the storage device may be improved.

[0189] When forming a film by the ALD method, it is recommended to use a gas that does not contain chlorine as the material gas. is preferred.

[0190] <Transistor structure example 2> A structural example of the transistor 200B will be described with reference to FIGS. 7A to 7C. 7B is a top view of the gate 200B and its surroundings. 7C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. In addition, in the top view of FIG. 7A, some elements are omitted for clarity.

[0191] The transistor 200B is a modified example of the transistor 200A. To avoid confusion, the following description will focus mainly on the differences from transistor 200A.

[0192] In addition, in the transistor 200B shown in FIGS. 7A to 7C, the oxide 230c and the insulating layer 2 50 and the conductive layer 260 are formed in the openings in the insulating layer 254 and the insulating layer 280. The oxide 230c, the insulating layer 250, and the conductive layer 260 are disposed on the conductive layer 2. The insulating layer 254 is disposed between the insulating layer 224 and the conductive layer 242b. A part of the surface, the side surfaces of the oxide 230a and the oxide 230b, a part of the side surface of the conductive layer 242a, and and the top surface of the conductive layer 242b, and a part of the side surface and the top surface of the conductive layer 242b.

[0193] The insulating layer 254 prevents impurities such as water and hydrogen from entering the transistor 200B from the insulating layer 280 side. For example, the insulating layer 254 may function as a barrier film to prevent the diffusion of the metal oxide into the semiconductor layer 254. It is preferable that the hydrogen permeability of the insulating layer 224 is lower than that of the insulating layer 224. Furthermore, in the configuration shown in FIG. Thus, the insulating layer 280 is formed by the insulating layer 254, the insulating layer 224, the oxide 230a, and the As a result, the hydrogen contained in the insulating layer 280 is separated from the oxide 230b. Since the diffusion of the ferroelectric material into the oxide 230a and the oxide 230b can be suppressed, the transistor This can provide the capacitor 200B with good electrical characteristics and reliability.

[0194] Further, the insulating layer 254 is formed of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulating layer 254 has a function of suppressing diffusion. It is preferable that the oxygen permeability of the insulating layer 224 is lower than that of the insulating layer 224 .

[0195] The insulating layer 254 may be, for example, an oxide of one or both of aluminum and hafnium. In this case, the insulating layer 254 is formed by the ALD method. Since the ALD method is a film formation method with good coverage, the unevenness of the insulating layer 254 is This can prevent the formation of discontinuities and the like.

[0196] The insulating layer 254 may be, for example, an insulating layer containing aluminum nitride. This makes it possible to produce a film with excellent insulation and thermal conductivity, making it suitable for use in transformers. The heat generated when the resistor 200B is driven can be dissipated more efficiently. Aluminum titanium nitride, titanium nitride, etc. can also be used as 254. In this case, the sputtering method is used for film formation, and the film formation gas contains oxidizing gas such as oxygen or ozone. This is preferable because it is possible to form the film without using a gas with high electrical conductivity. Silicon oxide or the like can also be used.

[0197] The insulating layer 254 may be made of, for example, an oxide containing gallium. The oxide containing ruthenium has the function of suppressing the diffusion of either or both of hydrogen and oxygen. In addition, examples of oxides containing gallium include gallium oxide and gallium zinc oxide. The insulating layer 254 may be formed of a metal oxide, an indium gallium zinc oxide, or the like. When indium gallium zinc oxide is used as the The larger the atomic ratio, the better. By increasing the atomic ratio, the insulating property of the oxide can be improved. It can be made easier.

[0198] The insulating layer 254 may have a multi-layer structure of two or more layers. When the multi-layer structure is made of two or more layers, the multi-layer structure may be made of different materials. For example, Silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride, and hydrogen, etc. A laminated structure may be formed with an insulator having a function of suppressing the permeation of impurities and oxygen. In addition, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: An insulating layer containing oxides of aluminum and / or hafnium can be used. Cut.

[0199] <Transistor structure example 3> A structural example of a transistor 200C will be described with reference to FIGS. 8A to 8C. 8B is a top view of the register 200C and its surroundings. 8C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. In addition, in the top view of FIG. 8A, some elements are omitted for clarity.

[0200] Transistor 200C is a modification of transistor 200A and transistor 200B. Therefore, in order to avoid repetition of the description, the following description will be focused mainly on transistor 200A and transistor The differences from the printer 200B will be described below.

[0201] The transistor 200C shown in FIGS. 8A to 8C is the same as the transistor 200 shown in FIGS. 7A to 7C. Unlike the transistor 200B, the conductive layer 205 may be provided as a single layer. An insulating film that will become the insulating layer 216 is formed on the conductive layer 205 on which the insulating film is formed. The conductive layer 205 is then removed by chemical mechanical polishing (CMP) or the like until the upper surface of the conductive layer 205 is exposed. Here, it is preferable to improve the flatness of the upper surface of the conductive layer 205. The average surface roughness (Ra) of the upper surface of the conductive layer 205 is set to 1 nm or less, preferably 0.5 nm or less, and more preferably The thickness is preferably 0.3 nm or less. Improve the flatness of the layer and improve the crystallinity of the oxide 230b and the oxide 230c. can be done.

[0202] In FIG. 8A to FIG. 8C, the conductive layer 203 is not provided, and the conductive layer 204 functions as the second gate. 205 also functions as wiring. In addition, an insulating layer 250 is provided on the oxide 230c. A metal oxide layer 252 is formed on the insulating layer 250. A conductive layer 260 is formed on the metal oxide layer 252. (conductive layer 260a and conductive layer 260b), and an insulating layer 270 is provided on the conductive layer 260. Moreover, an insulating layer 271 is provided on the insulating layer 270.

[0203] The metal oxide 252 preferably has a function of suppressing the diffusion of oxygen. By providing a metal oxide 252 that suppresses the diffusion of oxygen between the conductive layer 260 and the insulating layer 260, The diffusion of oxygen into the conductive layer 260 is suppressed. In other words, the amount of oxygen supplied to the oxide layer 230 is reduced. In addition, the oxidation of the conductive layer 260 due to oxygen can be suppressed. do.

[0204] The metal oxide 252 may function as a part of the first gate electrode. For example, An oxide semiconductor that can be used as the oxide 230 is used as the metal oxide 252. In this case, the conductive layer 260 can be formed by sputtering. The electrical resistance of the object 252 can be reduced to form a conductive layer.

[0205] The metal oxide 252 may also function as part of the first gate insulating layer. Therefore, when silicon oxide or silicon oxynitride is used for the insulating layer 250, The object 252 is preferably made of a metal oxide, which is a high-k material having a high dielectric constant. This laminated structure is stable against heat and has a high dielectric constant. Therefore, the gate voltage applied during transistor operation can be adjusted while maintaining the physical film thickness. In addition, the equivalent oxide thickness ( It is possible to reduce the thickness of the EOT.

[0206] In the transistor 200C, the metal oxide 252 is shown as a single layer. For example, a metal oxide that functions as a part of the first gate electrode and a first A metal oxide layer functioning as a part of the gate insulating layer may be laminated thereon.

[0207] When the metal oxide 252 functions as a first gate electrode, the conductive layer 2 To improve the on-current of the transistor 200C without weakening the effect of the electric field from 60. Alternatively, the insulating layer 250 and the gold layer may function as the first gate insulating layer. The physical thickness of the metal oxide 252 determines the distance between the conductive layer 260 and the oxide 230. By maintaining the above-mentioned structure, leakage current between the conductive layer 260 and the oxide 230 can be suppressed. Therefore, by providing a laminated structure of the insulating layer 250 and the metal oxide 252, the conductive layer 260 and The physical distance between the oxide 230 and the electric field from the conductive layer 260 to the oxide 230 The strength can be easily adjusted as needed.

[0208] Specifically, by reducing the resistance of an oxide semiconductor that can be used for the oxide 230, Metal oxide 252 can be used. Alternatively, hafnium, aluminum, gallium, tungsten, titanium, tantalum, nickel, gel Metal oxides containing one or more metals selected from the group consisting of arsenic, manganese, etc. It can be used.

[0209] In particular, the insulating layer contains oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide, ha ... It is preferable to use hafnium aluminate. In particular, hafnium aluminate is It has higher heat resistance than hafnium oxide. Therefore, the crystals are not easily damaged during the heat treatment in the later process. It is preferable because the metal oxide 252 is not essential. It is sufficient to design appropriately according to the transistor characteristics.

[0210] The insulating layer 270 is an insulating material having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. It is recommended to use insulating materials such as aluminum oxide and hafnium oxide. This prevents the conductive layer 260 from being oxidized by oxygen from above the insulating layer 270. In addition, impurities such as water and hydrogen from above the insulating layer 270 can be prevented. is prevented from being mixed into the oxide 230 via the conductive layer 260 and the insulating layer 250. It is possible.

[0211] The insulating layer 271 functions as a hard mask. During the processing of 60, the side of the conductive layer 260 is approximately vertical. The angle of the plate surface is set to 75 degrees or more and 100 degrees or less, preferably 80 degrees or more and 95 degrees or less. This can be done.

[0212] The insulating layer 271 has a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. By using an insulating material having a high insulating property, the insulating material may also function as a barrier layer. The insulating layer 270 is not necessarily provided.

[0213] Using the insulating layer 271 as a hard mask, the insulating layer 270, the conductive layer 260, the metal oxide 252, insulating layer 250, and oxide 230c are selectively removed to remove these The sides of the oxide 230b can be made substantially flush with each other and a portion of the surface of the oxide 230b can be exposed.

[0214] Transistor 200C also has regions 231a and 231b on the exposed oxide 230b surface. and region 231b. Either region 231a or region 231b is used as a source region. one serves as a drain region, and the other serves as a drain region.

[0215] The regions 231a and 231b are formed by, for example, ion implantation or ion doping. The exposed oxide 2 is then removed using a process such as plasma immersion ion implantation or plasma treatment. This can be achieved by introducing impurity elements such as phosphorus and boron into the surface of 30b. In the above form, "impurity elements" refer to elements other than the main component elements.

[0216] In addition, after exposing a part of the surface of the oxide 230b, a metal film is formed and then heat-treated. By this, the elements contained in the metal film are diffused into the oxide 230b, and the regions 231a and It is also possible to form region 231b.

[0217] The region of the oxide 230b into which the impurity element is introduced has a reduced electrical resistivity. The regions 231a and 231b may be referred to as "impurity regions" or "low resistance regions." do.

[0218] By using the insulating layer 271 or the conductive layer 260 as a mask, the regions 231a and The region 231b can be formed in a self-aligned manner. Since the region 231a or the region 231b does not overlap with the conductive layer 260, the parasitic capacitance can be reduced. In addition, the channel forming region and the source region or drain region (region 231a or No offset region is formed between region 231a and region 231b. By forming 1b in a self-aligned manner, the on-current is increased, the threshold voltage is reduced, and the operating frequency is reduced. It is possible to achieve an improvement in wave number, etc.

[0219] In order to further reduce the off-current, the channel forming region and the source region or drain region are An offset region may be provided between the first and second regions. The offset region is a region in which the above-mentioned impurity element is not introduced. This can be achieved by introducing the above-mentioned impurity element after forming the insulating layer 275. In this case, the insulating layer 275 also functions as a mask in the same manner as the insulating layer 271. Impurity elements are not introduced into the region of 230b that overlaps with the insulating layer 275, and the electrical resistivity of the region is It can remain high.

[0220] The transistor 200C also includes an insulating layer 270, a conductive layer 260, a metal oxide 252, and an insulating The edge layer 250 and the oxide 230c have an insulating layer 275 on the side thereof. The insulating layer 275 is It is preferable to use an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, Silicon oxynitride, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon Silicon, silicon oxide doped with carbon and nitrogen, silicon oxide with voids, resin, etc. In particular, silicon oxide, silicon oxynitride, silicon nitride oxide, If silicon oxide having voids is used for the insulating layer 275, excess silicon dioxide may be generated in the insulating layer 275 in a later process. It is preferable because the oxygen region can be easily formed. In addition, silicon oxide and silicon oxynitride are is preferable because it is thermally stable. In addition, the insulating layer 275 has a function of diffusing oxygen. It is preferable that

[0221] The transistor 200C also includes an insulating layer 275 and an insulating layer 274 on the oxide 230. The insulating layer 274 is preferably formed by a sputtering method. By using the deposition method, it is possible to form an insulator film with few impurities such as water and hydrogen. For example, the insulating layer 274 may be made of aluminum oxide.

[0222] In addition, the oxide film formed by the sputtering method may extract hydrogen from the structure on which the film is formed. Therefore, the insulating layer 274 absorbs hydrogen and water from the oxide 230 and the insulating layer 275. This allows the hydrogen concentration in the oxide 230 and the insulating layer 275 to be reduced.

[0223] <Transistor structure example 4> A structural example of a transistor 200D will be described with reference to FIGS. 9A to 9C. 9B is a top view of the gate 200D and its surroundings. 9C is a cross-sectional view of the portion indicated by the dashed line W1-W2 in FIG. In addition, in the top view of FIG. 9A, some elements are omitted for clarity.

[0224] The transistor 200D is a modified example of the transistor 200B. To avoid confusion, the following description will focus mainly on the differences from transistor 200B.

[0225] In FIG. 9B, an insulating layer 274 is disposed between insulating layer 280 and transistor 200C. The insulating layer 274 has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is advisable to use an insulating material. For example, aluminum oxide, hafnium oxide, etc. In addition, for example, magnesium oxide, gallium oxide, germanium oxide, etc. tungsten oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide Metal oxides such as silicon nitride, silicon oxide nitride, silicon nitride, etc. can be used.

[0226] By providing the insulating layer 274, impurities such as water and hydrogen contained in the insulating layer 280 are converted into oxide 2 30c, and the insulating layer 250 to suppress diffusion into the oxide 230b. In addition, the conductive layer 260 is prevented from being oxidized due to excess oxygen contained in the insulating layer 280. It is possible.

[0227] Also, transistor 200C shown in FIG. 9B does not include conductive layer 242, but has exposed oxide. The object 230b has a region 231a and a region 231b on a part of the surface. One of the regions 231b functions as a source region, and the other functions as a drain region. In addition, an insulating layer 273 is provided between the oxide 230 b and the insulating layer 274 .

[0228] The region 231 (region 231a and region 231b) shown in FIG. 9B is an oxide 230b. The region 231 is a region where an element that reduces the resistance of the oxide 230b is added to the oxide 230b. , it can be formed by using a dummy gate.

[0229] Specifically, a dummy gate is provided on the oxide 230b, and the dummy gate is used as a mask to It is preferable to add an element that reduces the resistance of the oxide 230b. The element is added to the region not overlapping with the dummy gate, forming a region 231. The element is added by mass-separating the ionized source gas. ion implantation, which adds ionized source gas without mass separation; and ion doping, which adds ionized source gas without mass separation. method, plasma immersion ion implantation method, etc. can be used.

[0230] Representative elements that reduce the resistance of the oxide 230 include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. can be used. Representative examples of rare gases are helium, neon, argon, krypton, and xenon. The concentration of the element can be measured using SIMS or the like.

[0231] In particular, boron and phosphorus are important in the production of amorphous silicon or low-temperature polysilicon. This is preferable because the equipment on the production line can be used. Existing facilities can be repurposed. This will help reduce capital investment.

[0232] Next, an insulating film that will become the insulating layer 273 is formed on the oxide 230b and the dummy gate. An insulating film to be the insulating layer 273 and an insulating film to be the insulating layer 274 may be formed. By laminating an insulating film that becomes the insulating layer 274, the region 231, the oxide 230c, and There may be an area where the insulating layer 250 and the insulating layer 250 overlap.

[0233] Specifically, after forming an insulating film that will become the insulating layer 280 on the insulating film that will become the insulating layer 274, By performing CMP processing on the insulating film that will become the edge layer 280, a part of the insulating film that will become the insulating layer 280 is The dummy gate is then exposed. It is advisable to also remove a part of the insulating film that will become the insulating layer 273 in contact with the dummy gate. The insulating layer 274 and the insulating layer 273 are exposed on the side of the opening provided in the layer 280. A part of the region 231 provided in the oxide 230b is exposed at the bottom of the opening. In the opening, an oxide film which becomes the oxide 230c, an insulating film which becomes the insulating layer 250, and a conductive layer After the conductive film 260 is formed in order, the insulating layer 280 is exposed by CMP or the like. This results in an oxide film that becomes the oxide 230c, an insulating film that becomes the insulating layer 250, and a conductive layer 260. By removing a part of the conductive film, the transistor 200D shown in FIGS. 9A to 9C is formed. It is possible.

[0234] Note that the insulating layer 273 and the insulating layer 274 are not essential components. Appropriate design may be required depending on the characteristics.

[0235] The transistor 200D shown in FIGS. 9A-9C can be adapted from an existing device. Furthermore, since the conductive layer 242 is not provided, costs can be reduced.

[0236] This embodiment may be implemented in appropriate combination with configurations described in other embodiments, examples, etc. It is possible to do so.

[0237] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments or examples. The method can be used in combination with other methods.

[0238] (Embodiment 3) In this embodiment, the present invention will be described with reference to FIGS. 10A, 10B, and 11A to 11H. According to one embodiment of the present invention, a transistor having a metal oxide (hereinafter referred to as an OS transistor) ) and a storage device to which a capacitive element is applied (hereinafter referred to as an OS memory device) The OS memory device includes at least a capacitive element and a The memory device has an OS transistor that controls the charging and discharging of the Since the current is extremely small, the OS memory device has excellent retention characteristics and can be used as a non-volatile memory. It can be made to function.

[0239] <Storage device configuration example> FIG. 10A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 141. 1, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, It has a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. .

[0240] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, write The precharge circuit has a function of precharging the wiring. The amplifier has a function of amplifying the data signal read from the memory cell. The lines are wirings connected to memory cells in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal RDA TA to the outside of the memory device 1400. It has a decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0241] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 The high power supply voltage (VDD) for the 11 and the high power supply voltage (VIL) for the memory cell array 1470 are The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data signal WDATA is input to the write circuit. do.

[0242] The control logic circuit 1460 receives control signals (CE, WE, R E) to generate control signals for the row decoder and column decoder. The control signal WE is a write enable signal, and the control signal R E is a read enable signal. The signal is not limited to this, and other control signals may be input as necessary.

[0243] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the recell MC, the number of memory cells MC in one row, etc.

[0244] In FIG. 10A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. However, the present embodiment is not limited to this. For example, As shown in FIG. 10B, a memory cell array 1470 is overlapped on a part of the peripheral circuit 1411. For example, the memory cell array 1470 may be provided so as to overlap the memory cell array 1470. A sense amplifier may be provided.

[0245] 11A to 11H show examples of memory cell configurations that can be applied to the above-mentioned memory cell MC. He explains.

[0246] [DOSRAM] 11A to 11C show examples of circuit configurations of memory cells in a DRAM. A DRAM using a one-transistor, one-capacitor type memory cell is called a DOSRAM. (Registered Trademark)(Dynamic Oxide Semiconductor Random The memory cell 14 shown in FIG. 71 includes a transistor M1 and a capacitance element CA. The transistor M1 is It has a gate (sometimes called a top gate) and a back gate.

[0247] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0248] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low-level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the transistor The threshold voltage of M1 can be increased or decreased.

[0249] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. The back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 1473 shown in FIG. A transistor M having a single gate structure, i.e., a transistor without a back gate The memory cell may be configured as 1.

[0250] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor M1 can be any of the transistors described in the above embodiments. By using an OS transistor as the first transistor, the leakage current of the transistor M1 is reduced to a very low level. In other words, the written data can be stored for a long time by the transistor M1. This allows the memory cells to be refreshed less frequently. Alternatively, the refresh operation of the memory cells can be eliminated. Because the current is so small, memory cell 1471, memory cell 1472, and memory cell 1473 It is possible to hold multi-value data or analog data.

[0251] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0252] [NOSRAM] 11D to 11G show a circuit diagram of a gain cell type memory cell having two transistors and one capacitor. FIG. 11D shows an example of a circuit configuration. The memory cell 1474 shown in FIG. The transistor M2 has a top gate ( In this specification and the like, A memory device having a gain cell type memory cell using an OS transistor as the transistor M2. The device is manufactured by NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor It is sometimes called inductor RAM.

[0253] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0254] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0255] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be a memory cell 1475 shown in FIG. In addition, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 1476 shown in FIG. As shown in the figure, a transistor with a single gate structure, i.e., a transistor without a back gate, For example, the memory cell MC may be configured as shown in FIG. As shown in FIG. 1G, the wiring WBL and the wiring RBL are connected to one wiring BIL. The configuration may be such that the above-mentioned components are combined together.

[0256] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor M2 can be any of the transistors described in the above embodiments. By using an OS transistor as a This allows the written data to be stored in a long This allows memory cells to be refreshed less frequently. Alternatively, the refresh operation of the memory cells can be eliminated. Since the current is very small, multi-value data or analog data can be stored in the memory cell 1474. The same can be said for memory cells 1475 to 1477.

[0257] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. In some cases, the field effect mobility is higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as the By using a Si transistor for transistor M3, a transistor Since the memory cell can be provided with a transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0258] The transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M3, the memory cell array 1470 is The circuit can be constructed using only transistors.

[0259] FIG. 11H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. The memory cell 1478 includes a wiring and a capacitor CC. The capacitor CC is provided appropriately. Electrically connected to BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL The wiring GNDL is a wiring for applying a low-level potential. , may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

[0260] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0261] The transistors M5 and M6 are n-channel Si transistors. Alternatively, the transistors M4 to M5 may be p-channel Si transistors. The transistor M6 may be an OS transistor. In this case, the memory cell array 1470 is configured as an n-type transistor. The circuit can be constructed using only transistors.

[0262] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor M4 can be any of the transistors described in the above embodiment. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 is extremely small. It can be reduced.

[0263] The configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are However, the above is not limited to the above. The arrangement or functions of road elements, etc. may be changed, deleted, or added as necessary.

[0264] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes, examples, etc. It can be used.

[0265] (Embodiment 4) In this embodiment, the semiconductor device of the present invention is mounted using FIG. 12A and FIG. 12B. The chip 1200 is an example of a chip 1200 having multiple circuits (systems) implemented therein. The technology of integrating multiple circuits (systems) on a single chip is called a system. This is sometimes called System on Chip (SoC).

[0266] As shown in FIG. 12A, the chip 1200 includes a CPU (Central Processor). ing Unit) 1211, GPU (Graphics Processing Un) it) 1212, one or more analog calculation units 1213, one or more memory controllers controller 1214, one or more interfaces 1215, one or more network The circuit 1216 is also included.

[0267] The chip 1200 is provided with bumps (not shown), and as shown in FIG. A first surface of a printed circuit board (PCB) 1201 In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201. 1203.

[0268] The motherboard 1203 is provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be The NOSRAM shown in FIG.

[0269] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CP 212 may have a memory for temporarily storing data. A memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or the like using the oxide semiconductor of the present invention. By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This will be possible.

[0270] In addition, the CPU 1211 and GPU 1212 are integrated on the same chip, The wiring between the CPU1211 and the GPU1212 can be shortened, and the Data transfer from the CPU 1211 to the GPU 1212, memory of the CPU 1211 and the GPU 1212 After data transfer between GPU1212 and calculation in GPU1212, the data is transferred from GPU1212 to CPU12. The calculation results can be transferred to 11 at high speed.

[0271] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit and a digital / analog conversion circuit. The multiply-and-accumulate circuit may be provided in the

[0272] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0273] The interface 1215 includes a display device, a speaker, a microphone, a camera, a The controller has an interface circuit for connecting to external devices such as a Such interfaces include computers, mobile phones, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) There can be.

[0274] The network circuit 1216 is a LAN (Local Area Network) or the like. It also has a circuit for network security. Good too.

[0275] The above circuits (systems) can be formed in the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering process, and the chip 1200 can be produced at low cost.

[0276] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a DRAM 122 1, and the motherboard 1203 on which the flash memory 1222 is provided is a GPU module. It can be called module 1204.

[0277] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, its excellent image processing makes it suitable for smart phones. Phones, tablet devices, laptop PCs, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep Neural Networks (DNNs), Convolutional Neural Networks (CNN), Recurrent Neural Network (RNN), Autoencoder, Deep Boltzmann It can implement techniques such as deep belief networks (DBNs) and deep learning machines (DBMs). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0278] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes, examples, etc. It can be used.

[0279] (Embodiment 5) In this embodiment, a display device which is one embodiment of the present invention will be described.

[0280] The display device shown in FIG. 13A includes a pixel portion 502, a driver circuit portion 504, and a protection circuit 506. , and a terminal portion 507. Note that the protection circuit 506 does not necessarily have to be provided.

[0281] The transistors in the pixel portion 502 and the driver circuit portion 504 are the transistors of one embodiment of the present invention. In addition, the protection circuit 506 can also use the transistor of one embodiment of the present invention. may be applied.

[0282] The pixel section 502 is a multi-layered pixel array arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). The pixel circuit 501 includes a number of pixel circuits 501 for driving a number of display elements.

[0283] The driver circuit unit 504 includes a gate driver that outputs scanning signals to the scanning lines GL_1 to GL_X. 504a, a source driver 50 for supplying data signals to the data lines DL_1 to DL_Y. The gate driver 504a includes at least a shift register. The source driver 504b may be, for example, a plurality of analog switches. Also, the source driver 504b is configured using a shift register, etc. may be configured as follows.

[0284] The terminal unit 507 is used to input power, control signals, image signals, etc. from an external circuit to the display device. This refers to the part where terminals for this purpose are provided.

[0285] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit The protection circuit 506 shown in FIG. For example, the scanning line GL, which is the wiring between the gate driver 504a and the pixel circuit 501, the source driver The data line DL, which is the wiring between the driver 504b and the pixel circuit 501, is connected to the .

[0286] The gate driver 504a and the source driver 504b are connected to the pixel section 502 and The gate driver circuit or the source driver circuit may be provided on the same substrate. A separately formed substrate (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) Plate) to COG (Chip On Glass) or TAB (Tape Automated The semiconductor device may be mounted on a substrate by bonding.

[0287] In addition, the pixel circuits 501 shown in FIG. 13A may be, for example, It can be configured as follows.

[0288] The pixel circuit 501 shown in FIG. 13B includes a liquid crystal element 570, a transistor 550, and a capacitance element. The pixel circuit 501 also includes a data line DL_n, a scanning line GL_m, A potential supply line VL and the like are connected.

[0289] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0290] The pixel circuit 501 shown in FIG. 13C includes a transistor 552 and a transistor 554. The pixel circuit 501 includes a data line DL_n, scanning line GL_m, potential supply line VL_a, potential supply line VL_b, etc. are connected to There are.

[0291] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. A low power supply potential VSS is applied to the gate of the transistor 554. The current flowing through the light-emitting element 572 is controlled in accordance with the potential applied to the light-emitting element 572. The brightness of the light emitted from 72 is controlled.

[0292] As the transistor 554 in the pixel circuit 501 shown in FIG. An example of using a transistor is shown in FIG. 14A. The pixel includes a pixel 552, a transistor 554a, a capacitor 562, and a light-emitting element 572a. The transistor 552 is an n-channel transistor, and the transistor 554a is an n-channel For example, the transistor 552 may be the same as that in the previous embodiment. The transistor having an oxide semiconductor in the channel formation region shown in FIG. 5 is used. A transistor having silicon in a channel formation region can be used as 54a.

[0293] For example, the transistor 552 and the transistor 554a may be the same as those in the above embodiment. The transistor having an oxide semiconductor in a channel formation region shown in FIG. This structure reduces the area that the transistor occupies within the pixel, enabling extremely high-resolution images. The image can be displayed.

[0294] Such display devices have extremely high resolution and are therefore suitable for use in head-mounted displays and other applications. Any virtual reality (VR) device or glasses-type augmented reality (AR) device It can be used effectively in Augmented Reality (AR) devices. For example, even in a configuration in which the display unit of the display device is viewed through a lens, The device has an extremely high-resolution display, so even if you enlarge the display with a lens, the pixels are not visible. In addition, the display device is not limited to this, and a relatively small The present invention can be suitably used in electronic devices having a display unit of this type, such as a smart watch. The display device can be suitably used for the display unit of a wearable electronic device.

[0295] In the pixel circuit 501a shown in FIG. 14A, the source or drain of the transistor 552 One of the sources of the transistors 552 is electrically connected to the data line DL_n. The other of the drains is connected to one electrode of a capacitor 562 and the gate of a transistor 554a. The other electrode of the capacitor 562 is electrically connected to the potential supply line VL_a. The gate of the transistor 552 is electrically connected to the scan line GL_m. One of the source and drain of the transistor 554a is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 554a is connected to the light-emitting element 572a. The other electrode of the light emitting element 572a is electrically connected to the potential supply line VL_b. The potential supply line VL_a is supplied with a low power supply potential VSS, and the potential supply line A high power supply potential VDD is applied to VL_b.

[0296] A configuration different from the pixel circuit 501a shown in FIG. 14A is shown in FIG. In the circuit 501b, one of the source and drain of the transistor 552 is connected to the data line The other of the source and the drain of the transistor 552 is electrically connected to One electrode of the capacitor 562 and the gate of the transistor 554a are electrically connected to The gate of the transistor 552 is electrically connected to the scan line GL_m. One of the source and drain of the transistor 554a is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 554a is connected to the other electrode of the capacitor 562. and electrically connected to one electrode of the light-emitting element 572a. The electrode is electrically connected to the potential supply line VL_b. A power supply potential VDD is applied to the potential supply line VL_b, and a low power supply potential VSS is applied to the potential supply line VL_b.

[0297] The transistor 554 in the pixel circuit 501 shown in FIG. An example of using a transistor is shown in FIG. 14C. The pixel includes a pixel 552, a transistor 554b, a capacitor 562, and a light-emitting element 572a. The transistor 552 is an n-channel transistor, and the transistor 554b is a p-channel transistor. For example, the transistor 552 may be the same as that in the previous embodiment. The transistor having an oxide semiconductor in the channel formation region shown in FIG. 5 is used. A transistor having silicon in a channel formation region can be used as 54b.

[0298] In the pixel circuit 501c shown in FIG. 14C, the source or drain of the transistor 552 One of the sources of the transistors 552 is electrically connected to the data line DL_n. The other of the drains is connected to one electrode of a capacitor 562 and the gate of a transistor 554b. The other electrode of the capacitor 562 is electrically connected to the potential supply line VL_a. The gate of the transistor 552 is electrically connected to the scan line GL_m. One of the source and drain of the transistor 554b is electrically connected to the potential supply line VL_a. The other of the source and the drain of the transistor 554a is connected to the light-emitting element 572a. The other electrode of the light emitting element 572a is electrically connected to the potential supply line VL A high power supply potential VDD is applied to the potential supply line VL_a, and the potential The supply line VL_b is supplied with the low power supply potential VSS.

[0299] The configuration examples exemplified in this embodiment and the corresponding drawings are at least partially The above can be implemented in appropriate combination with other configuration examples or drawings, etc.

[0300] This embodiment may be used in conjunction with other embodiments, at least some of which are described herein. The above embodiment can be implemented in appropriate combination with the above embodiment.

[0301] (Embodiment 6) A pixel circuit having a memory for correcting a gray scale displayed in a pixel and a display device having the pixel circuit The transistors exemplified in the above embodiments are used in the following pixel devices. The present invention can be applied to transistors used in circuits.

[0302] <Circuit configuration> FIG. 15A shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, The pixel circuit 400 includes a transistor M2, a capacitor C1, and a circuit 401. S1, the wiring S2, the wiring G1, and the wiring G2 are connected.

[0303] The transistor M1 has a gate connected to a wiring G1, a source and a drain connected to a wiring S1, The other end is connected to one electrode of the capacitor C1. The gate of the transistor M2 is G2, one of the source and drain is the wiring S2, and the other is the other electrode of the capacitance C1, and 401 and 402, respectively.

[0304] The circuit 401 is a circuit including at least one display element. Representative examples include organic light-emitting devices, LED devices, and other light-emitting devices, liquid crystal devices, etc. element, or MEMS (Micro Electro Mechanical Systems) ems) elements, etc. can be applied.

[0305] The node connecting the transistor M1 and the capacitor C1 is designated as N1, and the transistor M2 and the circuit 40 are designated as Let N2 be the node connecting to 1.

[0306] The pixel circuit 400 maintains the potential of the node N1 by turning off the transistor M1. In addition, by turning off the transistor M2, the voltage of the node N2 can be maintained. In addition, when the transistor M2 is in the off state, the transistor By writing a predetermined potential to node N1 via transistor M1, capacitive coupling via capacitor C1 This makes it possible to change the potential of the node N2 in response to a change in the potential of the node N1.

[0307] Here, the transistor M1, the transistor M2, or both of them may be The transistor including an oxide semiconductor, which is described above as an example, can be used. Therefore, the potentials of the nodes N1 and N2 are kept constant for a long period of time due to the extremely small off-current. In addition, when the period for which the potential of each node is held is short (specifically, In cases where the frame frequency is 30 Hz or more, transistors using semiconductors such as silicon A transistor may also be used.

[0308] <Driving method example> Next, an example of an operation method of the pixel circuit 400 will be described with reference to FIG. 1 is a timing chart relating to the operation of the pixel circuit 400. Therefore, various resistances such as wiring resistance, parasitic capacitance of transistors and wiring, The influence of the threshold voltage, etc. is not taken into consideration.

[0309] In the operation shown in FIG. 15B, one frame period is divided into a period T1 and a period T2. is a period during which a potential is written to node N2, and period T1 is a period during which a potential is written to node N1. It is.

[0310] [Period T1] In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. In addition, the line S1 is connected to a fixed potential V ref The first data is supplied to the wiring S2. Voltage V w supplies.

[0311] The node N1 is connected to a potential V ref is given. The node N2 is supplied with a first data potential V w Given Therefore, the capacitance C1 has a potential difference V w -V ref is held.

[0312] [Period T2] In the next period T2, a potential is applied to the wiring G1 to turn on the transistor M1. A potential for turning off the transistor M2 is applied to the line G2. Data potential V data A predetermined constant potential is applied to the wiring S2, or a floating potential is applied to the wiring S3. It may also be used as a ping.

[0313] A second data potential V data is given. At this time, due to the capacitive coupling of the capacitor C1, the second data potential V data Depending on node N That is, the first data potential Vw and the potential In FIG. 15B, the potential is input with the potential dV added. However, it may be negative. That is, the potential V data is the potential V ref Yo It may be lower.

[0314] Here, the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 401. When the capacitance value of the capacitor C1 is sufficiently larger than the capacitance value of the circuit 401, the potential dV becomes the second Data potential V data The potential becomes close to

[0315] In this way, the pixel circuit 400 is a circuit including a display element that combines two types of data signals. Since the potential to be supplied to the line 401 can be generated, the gray scale correction can be performed within the pixel circuit 400. It will be possible to do so.

[0316] In addition, the pixel circuit 400 generates a potential that exceeds the maximum potential that can be supplied to the wirings S1 and S2. For example, when a light-emitting element is used, a high dynamic range ( In addition, when liquid crystal elements are used, overdriving is possible. It is possible to realize drive such as a spring.

[0317] <Application Examples> [Example using liquid crystal element] The pixel circuit 400LC shown in FIG. 15C includes a circuit 401LC. It has a liquid crystal element LC and a capacitance C2.

[0318] The liquid crystal element LC has one electrode connected to the node N2 and one electrode connected to the capacitance C2, and the other electrode connected to the Potential V com2 The other electrode of the capacitor C2 is connected to the wiring to which the potential V com1 Connect with the wiring given.

[0319] The capacitor C2 functions as a storage capacitor. If the capacitor C2 is not required, it can be omitted. Cut.

[0320] The pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, so that, for example, Achieving high-speed display through overdrive operation and using liquid crystal materials with high drive voltage In addition, by supplying a correction signal to the wiring S1 or wiring S2, The gradation can also be corrected according to the operating temperature and the deterioration state of the liquid crystal element LC.

[0321] [Example using light-emitting element] The pixel circuit 400EL shown in FIG. 15D includes a circuit 401EL. The device includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0322] The transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, and a source and drain connected to the One of the rains is at potential V H The other is one electrode of the light-emitting element EL. The capacitance C2 is connected so that the other electrode is at potential V com Connect to the wiring that gives the The other electrode of the light element EL is at a potential V L Connect with the wiring given.

[0323] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. functions as a storage capacitor. Capacitor C2 can be omitted if not required.

[0324] In this example, the anode side of the light-emitting element EL is connected to the transistor M3. However, a transistor M3 may be connected to the cathode side. In that case, the potential V H and potential V L The value of can be changed appropriately.

[0325] The pixel circuit 400EL generates a light-emitting element by applying a high potential to the gate of the transistor M3. Since a large current can be passed through the child EL, it is possible to realize, for example, HDR display. In addition, by supplying a correction signal to the wiring S1 or the wiring S2, the transistor It is also possible to correct the variations in the electrical characteristics of M3 and the light-emitting element EL.

[0326] In addition, the circuit is not limited to the circuits illustrated in FIG. 15C and FIG. 15D, and may include additional transistors, capacitors, etc. may be added.

[0327] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0328] (Embodiment 7) In this embodiment, a structural example of an electronic device to which a display device of one embodiment of the present invention is applied will be described. Reveal.

[0329] The display device of one embodiment of the present invention can be used as a display portion of an electronic device or the like having a display function. Examples of such electronic devices include television sets and notebook personal computers. Relatively large equipment such as computers, monitors, digital signage, pachinko machines, and game machines In addition to electronic devices with large screens, digital cameras, digital video cameras, digital Examples include display frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices. can be.

[0330] In particular, the display device of one embodiment of the present invention can have a high resolution. The present invention can be suitably used in electronic devices having a display unit. Examples of such electronic devices include For example, wristwatch-type or bracelet-type information terminals (wearable devices) and head-mounted devices Head-mounted devices such as VR devices such as displays, or glasses-type AR devices It can be suitably used in wearable devices, etc.

[0331] FIG. 16A shows a perspective view of a glasses-type electronic device 700. The electronic device 700 has a pair of glasses. The display panel 701, a pair of housings 702, a pair of optical members 703, a pair of mounting parts 704, etc. do.

[0332] The electronic device 700 displays an image on a display panel 701 in a display area 706 of an optical member 703. In addition, since the optical member 703 is translucent, the user can project an image. The image displayed in the display area 706 is superimposed on the transmitted image seen through the optical member 703. Therefore, electronic device 700 is an electronic device capable of AR display.

[0333] In addition, one of the housings 702 is provided with a camera 705 capable of capturing images of the front. Although not shown, a wireless receiver or a cable is connected to one of the housings 702. The connector can be connected to the housing 702 to supply video signals and the like. 702 is equipped with an acceleration sensor such as a gyro sensor to detect the direction of the user's head. It is also possible to detect the orientation of the camera and display an image in accordance with the orientation in the display area 706. It is preferable that the 02 is provided with a battery, which can be charged wirelessly or by wire. It is possible.

[0334] Next, a method of projecting an image onto the display area 706 of the electronic device 700 will be described with reference to FIG. 16B. The inside of the housing 702 contains a display panel 701, a lens 711, a reflector 712, and In addition, a half-frame is provided in a portion of the optical member 703 corresponding to the display area 706. It has a reflective surface 713 that functions as a mirror.

[0335] Light 715 emitted from the display panel 701 passes through the lens 711 and strikes the reflector 712. Inside the optical member 703, the light 715 is reflected by the optical section 704 toward the optical member 703. The light is repeatedly totally reflected at the end surface of the material 703 and reaches the reflecting surface 713. The image is projected. As a result, the user can see the light 715 reflected by the reflective surface 713 and the optical Both the reflected light 716 and the light 717 that has passed through the material 703 (including the reflective surface 713) can be seen. .

[0336] FIG. 16B illustrates an example in which the reflector 712 and the reflecting surface 713 each have a curved surface. This allows greater freedom in optical design compared to when these are flat surfaces. Therefore, the thickness of the optical member 703 can be reduced. may be a plane.

[0337] The reflector 712 may be a member having a mirror surface, and preferably has a high reflectance. Also, a half mirror using reflection from a metal film may be used as the reflecting surface 713. However, if a prism that utilizes total reflection is used, the transmittance of the transmitted light 716 can be increased. can be done.

[0338] Here, the housing 702 controls the distance between the lens 711 and the display panel 701 and the angle between them. It is preferable that the lens has a mechanism for adjusting the focus, enlarging or reducing the size of the image. For example, it is possible to reduce the size of either the lens 711 or the display panel 701. Alternatively, either or both of them may be configured to be movable in the direction of the optical axis.

[0339] Furthermore, the housing 702 preferably has a mechanism for adjusting the angle of the reflector 712. By changing the angle of the reflector 712, the position of the display area 706 where the image is displayed can be changed. This makes it possible to display the display area 706 at an optimal position according to the position of the user's eyes. It becomes possible to place

[0340] The display device of one embodiment of the present invention can be applied to the display panel 701. This makes it possible to provide electronic device 700 that is capable of displaying images with extremely high definition.

[0341] 16C and 16D are perspective views of a goggle-type electronic device 750. FIG. 16D is a perspective view showing the front, top, and left side of the child device 750. FIG. 2 is a perspective view showing the rear, bottom, and right side of the device.

[0342] The electronic device 750 includes a pair of display panels 751, a housing 752, a pair of mounting parts 754, and a buffer. The pair of display panels 751 are disposed in a housing 752. They are provided at positions inside the lens 756 that can be seen through the lens 756 .

[0343] The electronic device 750 is an electronic device for VR. A user wearing the electronic device 750 The image displayed on the display panel 751 can be viewed through the lens 756. By displaying different images on a pair of display panels 751, a 3D display using parallax is performed. It is also possible.

[0344] An input terminal 757 and an output terminal 758 are provided on the rear side of the housing 752. An input terminal 757 receives a video signal from a video output device or the like, and a buffer provided in the housing 752. A cable that supplies power for charging the battery can be connected to the output terminal 7. For example, the 58 can function as an audio output terminal to connect earphones or headphones. In addition, it is possible to output audio data by wireless communication or to use an external When audio is output from the video output device, the audio output terminal does not need to be provided.

[0345] In addition, the housing 752 is configured such that the lens 756 and the display panel 751 can be adjusted according to the position of the user's eyes. It is preferable that the left and right positions of the two be adjusted so that the position is optimal for the user. In addition, the focus can be adjusted by changing the distance between the lens 756 and the display panel 751. It is preferable that the device has a mechanism for

[0346] The display device of one embodiment of the present invention can be applied to the display panel 751. This makes it possible to provide an electronic device 750 capable of displaying images with extremely high resolution. This allows the user to feel a high level of immersion.

[0347] The cushioning member 755 is a portion that comes into contact with the face (forehead, cheeks, etc.) of the user. By fitting closely to the user's face, light leakage is prevented, enhancing the sense of immersion. The cushioning member 755 is in close contact with the user's face when the user wears the electronic device 750. In order to prevent this, it is preferable to use a soft material for the cushioning member 755. For example, rubber, Materials such as silicone rubber, urethane, and sponge can be used. If the surface of the product is covered with cloth or leather (natural or synthetic leather), the user may feel It is difficult for a gap to form between the face and the cushioning member 755, and light leakage can be suitably prevented. Using such materials not only makes them pleasant to the touch, but also makes them comfortable to wear in cold weather. This is preferable because it does not make the user feel cold. The parts that come into contact with the skin of the user can be made removable for easy cleaning and replacement. Therefore, it is preferable.

[0348] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0349] (Embodiment 8) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. 17A to 17H show a CPU and a GPU according to one embodiment of the present invention. The following shows a specific example of an electronic device equipped with a processor, chip, or display device. .

[0350] The electronic devices exemplified below may include the display device according to one embodiment of the present invention in a display portion. By providing a display device according to one embodiment of the present invention in a display section, the electronic device can achieve high resolution. It is also possible to achieve both high resolution and a large screen.

[0351] The display unit of the electronic device may display, for example, full high definition, 4K2K, 8K4K, 16K8K It is possible to display images with a resolution of 100x100x200x100 or higher. The size is 20 inches or more diagonally, 30 inches or more diagonally, or 50 inches or more diagonally. , or a diagonal of 60 inches or more, or a diagonal of 70 inches or more.

[0352] <Electronic equipment and systems> The GPU, chip, or display device according to one embodiment of the present invention can be used in various electronic devices. Examples of electronic devices include television sets, desktop computers, etc. Monitors for tablet or notebook type information terminals, digital signage Signage: electronic billboards, large game machines such as pachinko machines, and other relatively large screens In addition to electronic devices equipped with the electronic book readers, mobile phones, portable game consoles, personal digital assistants, audio playback devices, In addition, the GPU or chip according to one embodiment of the present invention may be provided in an electronic device. This makes it possible to equip electronic devices with artificial intelligence.

[0353] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images and information on the display unit. And if a secondary battery is included, the antenna may be used for contactless power transmission.

[0354] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Numbers, distance, light, liquids, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared rays) It may have.

[0355] The electronic device according to one embodiment of the present invention can have various functions. Functions for displaying still images, videos, text images, etc. on the display, touch panel function, calendar Functions such as displaying date or time, running various software (programs) a function to read out a program or data recorded on a recording medium; The electronic device may have the following functions: Figures 17A to 17H show examples of the electronic device.

[0356] [Information terminal] FIG. 17A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As a user interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101. It is prepared.

[0357] The information terminal 5100 uses the chip according to one embodiment of the present invention to perform a process using artificial intelligence. It can run applications that use artificial intelligence. For example, an application that recognizes a conversation and displays the conversation content on the display unit 5102 The display unit 5102 recognizes characters, figures, etc. input by the user on the touch panel. The application to be displayed on the display unit 5102 and the application to perform biometric authentication such as fingerprint or voiceprint are displayed. Applications, etc.

[0358] FIG. 17B illustrates a notebook type information terminal 5200. 5200 includes a main body 5201 of an information terminal, a display unit 5202, and a keyboard 5203. .

[0359] The notebook type information terminal 5200 is similar to the information terminal 5100 described above, and is an embodiment of the present invention. The chip can be used to run applications that use artificial intelligence. Examples of applications that use artificial intelligence include design support software, text Examples include software for editing meals and software for automatically generating menus. By using the 5200, it is possible to develop new artificial intelligence.

[0360] In the above description, a smartphone and a notebook type information terminal are used as examples of electronic devices. 17A and 17B, respectively, are a smartphone and a notebook type information terminal. The present invention can be applied to information terminals other than smartphones and notebook-type information terminals. Examples of information terminals include PDAs (Personal Digital Assistants). Examples of such terminals include personal computers, desktop information terminals, and workstations.

[0361] [Game consoles] FIG. 17C shows a portable game machine 5300, which is an example of a game machine. 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 53 5305, an operation key 5306, etc. The connector 5305 provided on the housing 5301 can be removed from the housing 5302. By attaching it to a housing (not shown), the image outputted to the display unit 5304 can be displayed on another video device. In this case, the housing 5302 and the housing 5303 can output the signal to a device (not shown). Each of the buttons can function as an operation unit. This allows multiple players to play simultaneously. The boards of the housing 5301, the housing 5302, and the housing 5303 The chip shown in the above embodiment can be incorporated into a chip provided in the semiconductor device.

[0362] FIG. 17D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 by wireless or wired connection. There are.

[0363] One embodiment of the present invention is applied to a game machine such as a portable game machine 5300 or a stationary game machine 5400. By applying the GPU or chip, it is possible to realize a low-power gaming machine. In addition, the low power consumption reduces heat generation from the circuit, so it is possible to reduce heat generation. This reduces the effect on the circuit itself, peripheral circuits, and modules.

[0364] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game machine 5300, Therefore, a portable game device 5300 having artificial intelligence can be realized.

[0365] Originally, the game progress, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 530 By applying artificial intelligence to 0, it is possible to express things in ways that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, the characters that appear in the game, This makes it possible to express things such as a person's behavior changing as they change.

[0366] In addition, when playing a game that requires multiple players on the portable game console 5300, the artificial intelligence This allows you to create anthropomorphic game players, so you can make your opponents artificially intelligent. By making the game a game player, you can play the game by yourself.

[0367] In FIG. 17C and FIG. 17D, a portable game machine and a stationary game machine are shown as examples of game machines. Although the figure shows a game machine, the game machine to which the GPU or chip of one embodiment of the present invention is applied is not shown. Examples of game machines to which the GPU or chip of one embodiment of the present invention can be applied include For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), Examples include pitching machines for batting practice installed at sports facilities.

[0368] [Mainframe computers] The GPU or chip of one embodiment of the present invention can be applied to a large computer.

[0369] FIG. 17E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 17F shows a rack-mounted computer in the supercomputer 5500. A figure showing 5502.

[0370] The Supercomputer 5500 is a rack-mounted computing The computers 5502 are stored in a rack 5501. In addition, the computer 5502 is provided with a plurality of substrates 5504, on which the above-mentioned implementations are It may be equipped with the GPU or chip described in the embodiment.

[0371] The Supercomputer 5500 is a large computer used primarily for scientific and technological calculations. Scientific and technical calculations require high speed processing of huge amounts of calculations, which consumes a lot of power. The chip generates a lot of heat. By applying this chip, it is possible to realize a low-power supercomputer. In addition, the low power consumption reduces heat generation from the circuit, so it is possible to reduce heat generation. This reduces the effect on the circuit itself, peripheral circuits, and modules.

[0372] In Fig. 17E and Fig. 17F, a supercomputer is shown as an example of a large computer. However, a large computer to which the GPU or chip of one embodiment of the present invention is applied is As a large computer to which the GPU or chip of one embodiment of the present invention is applied, it is not limited to the above. For example, a computer that provides a service (a server), a large general-purpose computer (a memory In-frame) etc.

[0373] [Mobile object] The GPU or chip, or the display device according to one embodiment of the present invention is used in a vehicle, It can also be applied to the area around the driver's seat in a car.

[0374] FIG. 17G is a diagram showing the vicinity of a windshield in the interior of an automobile, which is an example of a moving body. In FIG. 17G, a display panel 5701 attached to the dashboard, a display panel 5702, display panel 5703, and display panel 5704 attached to the pillar are shown. is doing.

[0375] The display panels 5701 to 5703 display a speedometer, a tachometer, It provides various information by displaying the distance traveled, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be customized by the user. It can be changed as needed to suit your taste, making it possible to enhance the design. The panels 5701 to 5703 can also be used as lighting devices.

[0376] The display panel 5704 displays an image from an imaging device (not shown) installed in the car. By doing so, it is possible to compensate for the blind spot obstructed by the pillar. , by displaying images from an imaging device installed on the outside of the vehicle, blind spots are compensated for, This can improve safety. Also, by projecting images that complement the invisible parts, The display panel 5704 is a lighting device and It can also be used as such.

[0377] The GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in an autonomous driving system for automobiles. The display panel 5701 can be used in systems that provide road guidance, risk prediction, etc. The display panel 5704 may be configured to display information such as road guidance and risk prediction. .

[0378] In the above description, an automobile is used as an example of a moving object. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, etc.) These include drones, unmanned aerial vehicles (drones), airplanes, and rockets. Applying the chip of one embodiment of the present invention to a moving object and providing a system using artificial intelligence can be done.

[0379] [electric appliances] FIG. 17H shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The refrigerator 5800 includes a housing 5801, a door for a refrigerator compartment 5802, a door for a freezer compartment 5803, and the like.

[0380] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, The Electric Freezer Refrigerator 5800 is a refrigerator that can store food and drink. It also has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients, and the ... It can also have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0381] Although electric refrigerators and freezers have been explained as an example of electrical appliances, other electrical appliances include For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, Servers, heating and cooling appliances including air conditioners, washing machines, dryers, audio equipment Visual equipment, etc.

[0382] Electronic device described in the present embodiment, functions of the electronic device, application examples of artificial intelligence, and effects thereof etc. can be appropriately combined with the descriptions of other electronic devices.

[0383] This embodiment may be implemented in appropriate combination with configurations described in other embodiments, examples, etc. It is possible to do so. EXAMPLES

[0384] In this example, the relationship between the hydrogen concentration and the carrier concentration in the metal oxide described in the first embodiment is Specifically, four samples having a metal oxide film (samples 1B to 4) B) was prepared, and the hydrogen concentration in the metal oxide film obtained by SIMS analysis and the sheet resistance were used to determine the hydrogen concentration. The calculated carrier concentration in the metal oxide film was compared.

[0385] A method for fabricating Sample 1B and Sample 2B will be described below.

[0386] A first metal oxide film is formed on a quartz substrate by sputtering to a thickness of 100 nm. The first metal oxide film was formed using a mixture of In:Ga:Zn=4:2:4.1 [atomic ratio]. An In-Ga-Zn oxide target was used, and the deposition gas was argon gas at 40 sccm. The oxygen gas was 5 sccm, the deposition pressure was 0.7 Pa, and the deposition power was 500 W. The temperature was set to 130° C., and the distance between the target and the substrate was set to 60 mm.

[0387] Next, the first heat treatment was carried out at a temperature of 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. I did.

[0388] Next, a second heat treatment was performed. As the second heat treatment, silane (Si H4) Treatment was performed for 37 seconds at 350°C in an atmosphere where gas was introduced at a flow rate of 1 sccm. In addition, sample 2B was heated at 350°C in an atmosphere containing silane (SiH4) gas. The process took 135 seconds.

[0389] As a result of the above, Sample 1B and Sample 2B were prepared.

[0390] Methods for fabricating Sample 3B and Sample 4B will be described below.

[0391] The surface of the silicon-containing substrate is heat-treated in a hydrogen chloride (HCl) atmosphere, and 100 A silicon oxide film with a thickness of nm was then formed on the silicon oxide film by sputtering. The metal oxide film was formed to a thickness of 500 nm. The deposition gas was an In-Ga-Zn oxide target with an atomic ratio of 4:2:4.1. The deposition pressure was set at 0.7 Pa. The deposition power was 500 W, the substrate temperature was 130° C., and the distance between the target and the substrate was 60 The thickness was set to mm.

[0392] Next, the first heat treatment was carried out at a temperature of 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. I did.

[0393] Next, a silicon nitride film was formed on the metal oxide film by CVD to a thickness of 20 nm. The silicon nitride film was formed using 20 sccm of silane (SiH4) gas and 20 sccm of nitrogen gas. The gas used was 600sccm of nitrogen and 200sccm of ammonia (NH3), and the power was 50W. The pressure was set to 200 Pa, and the substrate temperature was set to 270°C.

[0394] Next, the second heat treatment was performed on the sample 4B. The second heat treatment was performed in a nitrogen atmosphere. The second heat treatment was performed at 400° C. for 1 hour. has not been carried out.

[0395] As a result of the above, Samples 3B and 4B were prepared.

[0396] The hydrogen concentration in the metal oxide film of Samples 1B to 4B was measured using a SIMS analyzer. The analysis was performed from the front side of the sample. The sheet resistance of the metal oxide film was measured using a sheet resistance measuring device. The resistance measuring device has a measurement upper limit of 6.0 x 10 6 Ω / sq. was used.

[0397] Here, the measured sheet resistance of the metal oxide film is converted into the carrier concentration in the metal oxide film. The method will be explained.

[0398] First, the sheet resistance R is calculated using formula (1). s[Ω / sq.] is the metal oxide film thickness after Carrier surface density N(T) [cm2 at film thickness T [nm] -2 ].

[0399]

number

[0400] In formula (1), q is the carrier charge (=1.602×10 -19 C) and μ In this embodiment, the mobility μ is set to 20 cm 2 / (V s).

[0401] The carrier surface density N(T) is the carrier surface density at a distance x [nm] from the bottom of the metal oxide film. Rear concentration n(x) [cm -3 ], this is expressed by equation (2).

[0402]

number

[0403] In addition, the carrier concentration n(x) at a distance x [nm] from the bottom of the metal oxide film is expressed by the formula ( As shown in 3), it can be expressed using the complementary error function erfc(y) (y is a variable). Let's assume that.

[0404]

number

[0405] Here, a, b, and c are parameters. By substituting formula (3) into formula (2), The carrier areal density N(T) can be expressed by the formula (4) using parameters a, b, and c. Cut.

[0406]

number

[0407] Here, the function erf(y) shown in formula (4) is an error function. ) and the complementary error function erfc(y), the relationship expressed by Equation (5) is established.

[0408]

number

[0409] Therefore, the data points of the T dependence of the carrier areal density N(T) converted from the sheet resistance are Fitting is performed by the least squares method using equation (4). At this time, parameters a, b, Let c be the fitting parameter. The obtained parameters a, b, and c are expressed as follows: By substituting the above, the carrier concentration n(x) with respect to the distance x from the bottom of the metal oxynitride film can be calculated as follows: It can be calculated.

[0410] From the above, the measured sheet resistance of the metal oxide film is converted into the carrier concentration in the metal oxide film. It is possible.

[0411] The hydrogen concentration in the metal oxide film obtained by SIMS analysis and the gold content calculated from the sheet resistance The carrier concentration in the metal oxide film is shown in Figures 18A to 19B. The horizontal axis is the depth direction (Depth) [nm] perpendicular to the film surface of the sample, and the vertical axis is the metal oxide Carrier concentration in the film [cm -3 ], or hydrogen concentration in metal oxide film [atoms / cm 3 ].

[0412] FIG. 18A shows the hydrogen concentration and carrier concentration in the metal oxide film of sample 1B. 18B shows the hydrogen concentration and carrier concentration in the metal oxide film of sample 2B. A is the hydrogen concentration and carrier concentration in the metal oxide film of sample 3B. , and the hydrogen concentration and carrier concentration in the metal oxide film of sample 4B.

[0413] 18A to 19B show the profile of the hydrogen concentration in the metal oxide film and the The carrier concentration profiles in the metal oxide film are almost the same. There is a correlation between hydrogen concentration and carrier concentration. It has been found that it is preferable to reduce the hydrogen concentration in this region.

[0414] The configurations, methods, etc. shown in the present embodiment may be at least partially implemented in other embodiments described in this specification. The present invention can be implemented in appropriate combination with the embodiments. [Explanation of symbols]

[0415] 10: transistor, 30: semiconductor layer, 31a: region, 31b: region, 32a: region, 32b: region, 34: region, 40: conductive layer, 40a: conductive layer, 40b: conductive layer, 44: layer , 44a: layer, 44b: layer, 50: insulating layer, 60: conductive layer, 70: insulating layer, 80: conductive layer , 200A: transistor, 200B: transistor, 200C: transistor, 200 D: transistor, 203: conductive layer, 205: conductive layer, 205a: conductive layer, 205b: conductive 210: insulating layer, 212: insulating layer, 214: insulating layer, 216: insulating layer, 220: insulating layer Edge layer, 222: insulating layer, 224: insulating layer, 230: oxide, 230a: oxide, 230b :Oxide, 230c:Oxide, 231:Area, 231a:Area, 231b:Area, 242 : conductive layer, 242a: conductive layer, 242b: conductive layer, 246: conductive layer, 246a: conductive layer, 246b: conductive layer, 250: insulating layer, 252: metal oxide, 254: insulating layer, 260: conductive 260a: conductive layer, 260b: conductive layer, 270: insulating layer, 271: insulating layer, 273 : insulating layer, 274: insulating layer, 275: insulating layer, 276: insulating layer, 276a: insulating layer, 27 6b: insulating layer, 280: insulating layer, 282: insulating layer, 284: insulating layer, 400: pixel circuit, 400EL: pixel circuit, 400LC: pixel circuit, 401: circuit, 401EL: circuit, 40 1LC: circuit, 501: pixel circuit, 501a: pixel circuit, 501b: pixel circuit, 501c : pixel circuit, 502: pixel section, 504: driving circuit section, 504a: gate driver, 504 b: source driver, 506: protection circuit, 507: terminal section, 550: transistor, 55 2: transistor, 554: transistor, 554a: transistor, 554b: transistor 560: Capacitor element, 562: Capacitor element, 570: Liquid crystal element, 572: Light-emitting element, 572a: Light emitting element, 700: Electronic device, 701: Display panel, 702: Housing, 703: Optical member, 704: mounting part, 705: camera, 706: display area, 711: lens, 71 2:Reflector, 713:Reflective surface, 715:Light, 716:Transmitted light, 750:Electronic equipment, 751 : display panel, 752: housing, 754: mounting part, 755: cushioning material, 756: lens, 7 57: Input terminal, 758: Output terminal, 1200: Chip, 1201: PCB, 1202: Bump, 1203: Motherboard, 1204: GPU module, 1211: CPU, 1 212: GPU, 1213: analog computing unit, 1214: memory controller, 1215 : interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 1400: storage device, 1411: peripheral circuit, 1420: row circuit, 143 0: column circuit, 1440: output circuit, 1460: control logic circuit, 1470: memory memory cell array, 1471: memory cell, 1472: memory cell, 1473: memory cell , 1474: memory cell, 1475: memory cell, 1476: memory cell, 1477: memory cell, 1478: memory cell, 5100: information terminal, 5101: housing, 5102: table display unit, 5200: notebook type information terminal, 5201: main body, 5202: display unit, 5203: key board, 5300: portable game machine, 5301: case, 5302: case, 5303: case , 5304: display unit, 5305: connection unit, 5306: operation keys, 5400: type game machine, 5402: Controller, 5500: Supercomputer, 5501: Rack, 550 2: computer, 5504: circuit board, 5701: display panel, 5702: display panel, 5703 : display panel, 5704: display panel, 5800: electric refrigerator-freezer, 5801: housing, 5 802: Refrigerator door, 5803: Freezer door

Claims

[Claim 1] A transistor is included. the transistor comprises a metal oxide, a first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the second insulating layer is provided on the fourth conductive layer; the metal oxide is provided on the second insulating layer; the first insulating layer is provided on the metal oxide; the third conductive layer is provided on the first insulating layer; the first conductive layer is provided on the metal oxide; the second conductive layer is provided on the metal oxide; the third conductive layer overlaps with the fourth conductive layer via the metal oxide; The off-state current of the transistor per 1 μm of channel width is 10 aA / μm or less in a temperature range of 180° C. to 220° C. Semiconductor device.

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