Semiconductor device

Abstract

To provide a semiconductor device that can suppress the risk of wire breakage due to electromigration and minimize performance degradation.SOLUTION: The semiconductor device includes a first substrate on which a semiconductor element is arranged, a first wiring structure disposed on the first substrate, a second substrate on which a semiconductor element is arranged, and a second wiring structure arranged on the second substrate. The first wiring structure has a first wiring layer bonded to a wiring of the second wiring structure, a second wiring layer connected to the first wiring layer by a first via, and a third wiring layer connected to the second wiring layer by a second via. At least a portion of the second via is located in a range away from an axis passing through the center of the first via by at least more than the width of the first via.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices, miniaturization and high functionality are achieved by physically joining two substrates with a joint. Patent Document 1 describes a solid-state imaging device in which a first substrate having a photoelectric conversion element is joined to a second substrate having other circuits. In Patent Document 1, a copper bonding pad is used for the joining. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-019147 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the bonding method described in Patent Document 1 may cause disconnection due to electromigration of metal atoms that make up the wiring. Therefore, it is considered to use the method with reduced performance due to restrictions such as upper limits on current density.

[0005] Furthermore, in the method of Patent Document 1, the diffusion prevention film that prevents the diffusion of metal atoms from the junction must be denser than the interlayer film, making it difficult to finely process the junction. This makes it easy for a difference in processing size to occur at the connection between the junction and the lower wiring. In wiring that has such a size difference, if voids are generated and grow due to electromigration, it can easily cause disconnection of the lower fine wiring.

[0006] SUMMARY OF THE PRESENT EMBODIMENTS In view of the above, an object of the present invention is to provide a semiconductor device capable of suppressing the risk of disconnection due to electromigration. [Means for solving the problem]

[0007] One aspect of the present invention is a first substrate on which a semiconductor element is disposed; a first wiring structure disposed on the first substrate; a second substrate on which a semiconductor element is disposed; a second wiring structure disposed on the second substrate; Including, The first wiring structure is a first wiring layer joined to the wiring of the second wiring structure; a second wiring layer connected to the first wiring layer by a first via; a third wiring layer connected to the second wiring layer by a second via; having At least a portion of the second via is located in a range away from an axis passing through the center of the first via by at least a width of the first via. It is a semiconductor device. Effect of the Invention

[0008] According to the present invention, it is possible to provide a semiconductor device capable of suppressing the risk of disconnection due to electromigration. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating a semiconductor device according to an embodiment; [Diagram 2] 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment; [Diagram 3] 1 is a schematic cross-sectional view of a bonding portion of a semiconductor device according to an embodiment. [Figure 4] FIG. 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Diagram 5] FIG. 1 is a perspective view illustrating a semiconductor device according to an embodiment. [Figure 6] FIG. 2 is an enlarged schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 7] FIG. 2 is a circuit diagram illustrating a pixel circuit of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present invention will be described in detail with reference to the drawings, but the present invention is not limited to the embodiments described below.

[0011] The structure of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1 to FIG. 7. In the following description, the main surface of the first substrate and the main surface of the second substrate are the substrate surfaces on which semiconductor elements are formed. The surfaces opposite to the main surfaces are the back surfaces of the first substrate and the second substrate. The upward direction is the direction from the back surface to the main surface, and the downward direction and the depth direction are the direction from the main surface of the substrate to the back surface. In the following description, the coordinate system has the X-axis and the Y-axis parallel to the main surface, and the Z-axis perpendicular to the main surface. The thickness or height of a certain member is the dimension in the direction perpendicular to the substrate main surface of the member (i.e., the Z-axis direction). The direction in which the first substrate and the second substrate overlap is the overlapping direction (i.e., the Z-axis direction, Z direction). The direction perpendicular to the overlapping direction (Z-axis direction) is the planar direction (i.e., the XY direction, the X-axis direction, the X direction, or the Y-axis direction, Y direction). In the following description, the planar distance between two elements means the distance in the planar direction when the linear distance between the two elements is decomposed into components (vector decomposition) in the overlapping direction and the planar direction.

[0012] First, an overview of the semiconductor device APR will be described below with reference to Fig. 1. Fig. 1 is a schematic diagram illustrating the semiconductor device APR according to the present embodiment.

[0013] The semiconductor device APR includes a semiconductor device IC, and may include a package PKG for mounting the semiconductor device IC in addition to the semiconductor device IC. In this embodiment, the semiconductor device APR is a photoelectric conversion device (solid-state imaging device). The semiconductor device IC has a structure (chip stacking structure) in which a first semiconductor chip (first semiconductor component) in which pixel circuits PXC are arranged in a matrix and a second semiconductor chip (second semiconductor component) in which a peripheral circuit is provided are stacked. In the first semiconductor chip, the region in which the pixel circuits PXC are arranged in a matrix is ​​the pixel region PX. The pixel region PX may include a light-receiving pixel region (effective pixel region) and a light-shielding pixel region. In the peripheral region PR located around the pixel region PX, a part of the peripheral circuit and bonding pads for connecting to the outside via bonding wires are provided.

[0014] The semiconductor device APR is provided in an equipment EQP. The equipment EQP may include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a machine device MCHN. The equipment EQP will be described in detail later.

[0015] 2 is a schematic XZ cross-sectional view of the semiconductor device APR of this embodiment. The semiconductor device APR is a CMOS type image sensor including a first substrate 100 on whose main surface a pixel circuit including a photoelectric conversion element is arranged, and a second substrate 200 on whose main surface a circuit is arranged. The semiconductor device APR may be a CCD image sensor. The circuit arranged on the main surface of the second substrate 200 may be, for example, a photodiode. The semiconductor device APR includes at least a part of a peripheral circuit including a readout circuit and a control circuit for reading out a signal based on the charge of the electric conversion element. An example of the peripheral circuit is a vertical scanning circuit, a horizontal scanning circuit, and an amplifier circuit. When the semiconductor device APR is configured as a CCD image sensor, the circuit arranged on the main surface of the second substrate 200 may include, for example, a vertical transfer CCD provided for each column and a horizontal transfer CCD that horizontally transfers the signal of each row transferred through the vertical transfer CCD.

[0016] The semiconductor device APR is formed by arranging the first substrate 100, the first wiring structure 150, the second wiring structure 250, and the second substrate 200 in this order. The first substrate 100 and the first wiring structure 150 constitute a first semiconductor component (semiconductor chip), and the second substrate 200 and the second wiring structure 250 constitute a second semiconductor component (semiconductor chip). A junction is formed in which the wiring layer 107d of the first wiring structure 150 and the wiring layer 206d of the second wiring structure 250 are joined, and thus the pixel circuit of the first substrate 100 and the peripheral circuit of the second substrate 200 are electrically connected via the junction. The wiring layer 107d included in the first wiring of the first wiring structure 150 and the wiring layer 206d included in the second wiring of the second wiring structure 250 are joined at the junction, and thus the first wiring and the second wiring constitute inter-substrate wiring. The junction of the inter-substrate wiring may be arranged to overlap the pixel region PX, or may be arranged to overlap the peripheral region PR. In the example of FIG. 2, the junction between the wiring layer 107d included in the first wiring and the second wiring (the junction with the wiring layer 206d) overlaps the pixel region PX.

[0017] The first substrate 100 includes a semiconductor region formed on a semiconductor wafer by a known semiconductor manufacturing process. An example of the semiconductor material is silicon (Si). The interface between the semiconductor material and another material is the main surface 010 of the first substrate 100. For example, the other material is a thermal oxide film (not shown) disposed on the first substrate 100 and in contact with the main surface 010 of the first substrate 100. A photoelectric conversion unit 101 and an element isolation 102 are formed in the first substrate 100. A gate electrode 103 and a first wiring structure 150 are disposed on the main surface 010 of the first substrate 100 (downward in FIG. 2).

[0018] The first wiring structure 150 includes contact plugs 106, wiring layers 107a to 107d, insulating films 104a to 104f as interlayer insulating films, insulating films 105a to 105d, and an insulating film 109a. The wiring layer 107d includes a barrier metal 108. The insulating films 105a-105d are diffusion prevention films for the wiring layers 107a-107c and are made of, for example, SiC or SiOC. The insulating film 109 is a diffusion prevention film for the wiring layer 107d and is made of, for example, SiN. The barrier metal 108 covers the copper portion of the wiring layer 107d to prevent the diffusion of copper into the insulating film and is made of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN).

[0019] The second substrate 200 includes a semiconductor region formed on a semiconductor wafer by a known semiconductor manufacturing process. An example of the semiconductor material is silicon (Si). The interface between the semiconductor material and another material is the main surface 020 of the second substrate 200. For example, the other material is a thermal oxide film (not shown) disposed on the second substrate 200 and in contact with the main surface 020 of the second substrate 200. An element isolation 201 is formed in the second substrate 200. A gate electrode 202 and a second wiring structure 250 are disposed on the main surface 020 of the second substrate 200 (upward in FIG. 2).

[0020] The second wiring structure 250 includes contact plugs 205, wiring layers 206a to 206d, and insulating films 203a to 203f, 204a to 204d, and an insulating film 208a as interlayer insulating films. The wiring layer 206d includes a barrier metal 207. The insulating films 204a to 204d are diffusion prevention films for the wiring layers 206a to 206c, and are made of, for example, SiC or SiOC. The insulating film 208 is a diffusion prevention film for the wiring layer 206d, and is made of, for example, SiN. The barrier metal 207 is It covers the copper portion of the wiring layer 206d to prevent the diffusion of copper into the insulating film, and is made of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), or titanium nitride (TiN).

[0021] The wiring layer 107d of the first wiring structure 150 and the wiring layer 206d of the second wiring structure 250 each have a bonding surface, and the wiring layer 107d and the wiring layer 206d are physically and electrically connected via these bonding surfaces. That is, the wiring layer 107d and the wiring layer 206d function as a bonding member. In this embodiment, each of the wiring layer 107d and the wiring layer 206d constituting the bonding portion has a dual damascene structure. However, one or both of the wiring layer 107d and the wiring layer 206d constituting the bonding portion may have a single damascene structure. The dual damascene structure and the single damascene structure are collectively referred to as a damascene structure. Also, in this embodiment, the wiring layer 107c connected to the wiring layer 107d has a dual damascene structure, but the wiring layer 107c may have a single damascene structure.

[0022] A main surface 030 (rear surface) opposite to the main surface 010 of the first substrate 100 is a light incidence surface. On the main surface 030 side of the first substrate 100, insulating films 300a and 300b made of silicon oxide, an insulating film 301 made of silicon nitride, a color filter film 302 made of an organic material, and a condenser lens 303 are arranged on the optical path. Pixels PIX having such a cross-sectional structure are arranged in an array on the first substrate 100, but are omitted in FIG. 2.

[0023] The structure of the junction of the semiconductor device APR will be further described with reference to Fig. 3(A), which shows only a part of the structure shown in Fig. 2.

[0024] As shown in the figure, the wiring layer 107d (first wiring layer) and the wiring layer 107c (second wiring layer) are electrically connected by a first via (Via1) 121. Moreover, the wiring layer 107c (second wiring layer) and the wiring layer 107b (third wiring layer) are electrically connected by a second via (Via2) 122.

[0025] The wiring layer 107d having a dual damascene structure as in this embodiment has a first via 121 including a contact surface with the wiring layer 107c and a pad including a bonding surface with the wiring layer 206d. In FIG. 3(a), for convenience, a portion corresponding to the pad is indicated as the wiring layer 107d. The pad of the wiring layer 107d is provided in a trench provided in the insulating film 104f, and the first via 121 of the wiring layer 107d is provided in a hole provided in the insulating film 104e. The insulating film 109a is used as an etching stopper when forming a trench for the pad in the insulating film 104f. The width of the first via 121 (contact surface with the wiring layer 107c) in the wiring layer 107d is smaller than the width of the pad in the wiring layer 107d. The first via 121 of the wiring layer 107d and the pad of the wiring layer 107d can be integrally formed of the same conductive material (e.g., copper).

[0026] When the wiring layer 107d has a single damascene structure, the portion from the surface of the wiring layer 107d on the wiring layer 107c side to a position where the thickness of the wiring layer 107d is half can be defined as the first via 121. When the wiring layer 107d has a single damascene structure, the portion from the surface (bonding surface) of the wiring layer 107d on the wiring layer 206d side to a position where the thickness of the wiring layer 107d is half can be defined as the pad. Even when the wiring layer 107d has a single damascene structure, the first via 121 includes a contact surface with the wiring layer 107c, and the pad includes a bonding surface with the wiring layer 206d. When the wiring layer 107d has a single damascene structure, the difference between the width of the first via 121 and the width of the pad of the wiring layer 107d is smaller than the thickness of the wiring layer 107d, and typically the width of the first via 121 is approximately the same as the width of the pad. Here, the thickness of the wiring layer 107d may correspond to the distance between the wiring layer 206d joined to the wiring layer 107d and the wiring layer 107c connected to the wiring layer 107d by the first via 121. .

[0027] The wiring layer 107c having a dual damascene structure has a second via 122 including a contact surface with the wiring layer 107b, and a wiring pattern including a contact surface with the first via 121 (wiring layer 107d). In FIG. 3(a), for convenience, the portion corresponding to the wiring pattern is indicated as the wiring layer 107c. The width of the second via 122 (contact surface with the wiring layer 107d) in the wiring layer 107c is smaller than the width of the wiring pattern in the wiring layer 107c. The second via 122 in the wiring layer 107c and the wiring pattern of the wiring layer 107c can be integrally formed of the same conductive material (e.g., copper).

[0028] When the wiring layer 107c has a single damascene structure, the portion from the surface of the wiring layer 107c on the wiring layer 107b side to a position where the thickness of the wiring layer 107c is half can be defined as the second via 122. When the wiring layer 107c has a single damascene structure, the portion from the surface (contact surface) of the wiring layer 107c on the wiring layer 107d side to a position where the thickness of the wiring layer 107c is half can be defined as a pad. When the wiring layer 107c has a single damascene structure, the second via 122 includes a contact surface with the wiring layer 107b, and the wiring pattern includes a contact surface with the first via 121 (wiring layer 107d). When the wiring layer 107c has a single damascene structure, the difference between the width of the second via 122 and the width of the wiring pattern of the wiring layer 107c is smaller than the thickness of the wiring layer 107c, and typically the width of the second via 122 is approximately the same as the width of the wiring pattern. Here, the thickness of the wiring layer 107c can correspond to the distance between the wiring layer 107d in contact with the wiring layer 107c and the wiring layer 107b connected to the wiring layer 107c by the second via 122.

[0029] Here, the wiring layers 107d and 107c have been described, but the pads and vias can be defined for the wiring layer 206d in the same manner as for the wiring layer 107d, and the wiring pattern and vias can be defined for the wiring layer 206c in the same manner.

[0030] In addition, the pads and vias of each wiring layer are not limited to being integrally formed of the same conductive material, and the pads and vias of each wiring layer can be formed of different conductive materials. In addition, the wiring pattern and vias of each wiring layer are not limited to being integrally formed of the same conductive material, and the wiring pattern and vias of each wiring layer can be formed of different conductive materials. For example, the main component of the wiring pattern of each wiring layer can be aluminum, and the main component of the vias can be tungsten.

[0031] The widths (typically diameters) of the first via 121 and the second via 122 are respectively designated as Φ and Φ'. Then, for reasons described below, Φ>Φ', and it is possible that Φ>2Φ' or even Φ>3Φ'. As an example, the width Φ of the first via is 0.38 μm, and the width Φ' of the second via is 0.14 μm. However, the width Φ of the first via may be in the range of 0.19 μm to 0.57 μm, and the width Φ' of the second via may be in the range of 0.07 μm to 0.21 μm.

[0032] For example, the main component of the wiring layers 107a to 107d, 206a, 206b, and 206d, the first via 121, and the second via 122 is copper, and the main component of the wiring layer 206c is copper or aluminum. By making the main component of the wiring layer 206c aluminum, the conductive pattern in the same layer as the wiring layer 206c can be used as a bonding pad for connecting a bonding wire. The conductive material (e.g., copper) contained in the wiring layer is prevented from diffusing into the surrounding insulating film and semiconductor region by the barrier metals 108 and 207 and the diffusion prevention films 105a to 105d, 109a, and 208a. Here, the barrier metal 108 is disposed between a portion of the wiring layer 107d made of a main conductive material (e.g., a portion made mainly of copper) and the insulating films 104f, 109a, and 104e around the wiring layer 107d. The barrier metal 108 is a metal layer that is formed by insulating a portion of the wiring layer 107d that is made of a main conductive material (for example, a portion that is mainly made of copper) from the wiring The insulating film 109a is disposed between the wiring layer 107c and a portion of the wiring layer 107c that is mainly made of a conductive material (e.g., a portion mainly made of copper). Therefore, between the wiring layer 107d and the wiring layer 107c, the diffusion of the main conductive material (copper) is suppressed by the barrier metal 108. When the conductive material (e.g., copper) contained in the wiring layer 206d diffuses into the insulating film 104f, the insulating film 109a suppresses the conductive material diffused into the insulating film 104f from further diffusing into the insulating film 104e. The insulating films 104f and 104e are, for example, silicon oxide films, and the insulating film 109a is, for example, a silicon nitride film or a silicon carbide film. The main components of the wiring layers 107a to 107d, 206a to 206d and the vias connecting these wiring layers are not particularly limited, and may be copper, gold, silver, aluminum, tungsten, or other good conductors.

[0033] In this embodiment, the second via 122 is located in a range away from the axis AXSA passing through the center of the first via 121 by a distance greater than the width (Φ) of the first via 121. The axis AXSA passing through the center of the first via 121 may extend along a direction in which the first substrate 100 and the second substrate 200 overlap (a direction parallel to the Z axis). In other words, the axis AXSA passing through the center of the first via 121 may be parallel to the Z axis, and the axis AXSA passing through the center of the first via 121 may be perpendicular to the main surfaces of the first substrate 100 and the second substrate 200. The second via 122 being located in a specific range may mean that the entire portion of the second via 122 is located in the specific range, or may mean that at least a portion of the second via 122 is located in the specific range. When the cross-sectional shape of the first via 121 is a circle with a diameter Φ, the width of the first via 121 is the diameter Φ. Furthermore, when the cross-sectional shape of the second via 122 is a circle with a diameter Φ', in order for at least a part of the second via 122 to be located in a range away from the axis AXSA passing through the center of the first via 121 to the width of the first via 121, the distance L (planar distance) between the central axis AXSA of the first via 121 and the central axis AXSB of the second via in the planar direction should be greater than Φ-Φ' / 2 (L>Φ-Φ' / 2). Also, when the entire part of the second via 122 is located in a range away from the axis AXSA passing through the center of the first via 121 to the width of the first via, the planar distance L between the central axis AXSA of the first via 121 and the central axis AXSB of the second via 122 should be greater than Φ+Φ' / 2 (L>Φ+Φ' / 2). It is preferable that the entire part of the second via 122 is located in a range away from the axis AXSA passing through the center of the first via 121 to the width of the first via. That is, it is preferable that the second via 122 is not positioned within a range from the axis AXSA passing through the center of the first via 121 to a distance equivalent to the width Φ of the first via 121. In this case, the distance from the axis AXSA passing through the center of the first via 121 to the second via 122 is greater than the width Φ of the first via 121. Also, the distance D (planar distance) between the first via 121 and the second via 122 in the planar direction is greater than half (Φ / 2) of the width Φ of the first via 121 (D>Φ / 2). It is preferable that the distance D (planar distance) between the first via 121 and the second via 122 in the planar direction is greater than the width Φ of the first via 121 (D>Φ). The distance D may be equal to the width Φ.The distance L and / or the distance D may be smaller than the pitch (center-to-center distance) of adjacent junctions among the multiple junctions arranged on the bonding surface. The distance L and / or the distance D may be smaller than the interval between adjacent junctions among the multiple junctions arranged on the bonding surface. For example, if junctions with a width of 3 μm are arranged at intervals of 3 μm, the pitch of the junctions is 6 μm. The distance L and / or the distance D is, for example, 100 nm or more, for example, 500 nm or more, for example, 1 μm or more, for example, 100 μm or less, for example, 10 μm or less, for example, 5 μm or less, for example, 3 μm or less.

[0034] In addition, when the cross-sectional shape of the first via 121 is other than a circle, the width of the first via 121 is defined for each direction from the central axis AXSA of the first via 121. In other words, the width of the first via 121 in a certain direction is defined as the length in that direction passing through the central axis AXSA of the first via 121. The range away from the axis AXSA passing through the center of the first via 121 beyond the width of the first via 121 means the range away in each direction from the central axis AXSA of the first via 121 beyond the width of the first via 121 in that direction.

[0035] With reference to FIG. 3B, the effect of providing the first via 121 and the second via 121 at a distance in plan view will be described. When an electron flow flows from the first via 121 to the second via 122, a void V may be generated in the wiring layer 107c due to thermal and / or electrical stress. As one example, the void V may be formed when metal atoms (e.g., copper) which are a conductive material in the wiring layer 107c move from the first via 121 to the second via 122 due to an electric field. When the metal atoms move, the metal atoms become depleted in the places where the metal atoms were originally present. Although metal atoms are also present in the wiring layer 107d (first via 121), the barrier metal 108 exists between the metal atoms of the wiring layer 107d and the metal atoms of the wiring layer 107c, so that the replenishment of metal atoms from the wiring layer 107d to the wiring layer 107c is hindered. Therefore, there is a deficiency of metal atoms, and there are parts where the metal atoms are not replenished, which are considered to become the void V. 3B, if a void V in the wiring layer 107c grows from the end of the first via 121 to a size approximately equal to the first via diameter Φ, if the entire second via 122 is included within the distance L=Φ from the axis AXSA passing through the center of the first via 121, there is a high concern about disconnection or increased contact resistance between the first via 121 and the wiring layer 107c.

[0036] In particular, the insulating film 109a arranged to prevent diffusion is dense and has a higher stress than the insulating film 104. While a film is necessary, a sufficient thickness is also required, so it is difficult to reduce the processing dimensions of the first via 121 while ensuring wiring reliability. In order to achieve this without increasing the number of wiring layers, the first via diameter Φ is greater than twice the second via diameter Φ' (Φ>Φ'×2), and in more significant cases In this case, the void V is larger than three times (Φ>Φ'×3). There is a concern that the second via 122 or the wiring layer 107c will be filled with the void V more quickly than the first via diameter Φ, which may limit the wiring life. Also, when the thickness H of the wiring layer 107c is smaller than the first via diameter Φ (H<Φ), there is a concern that the wiring layer 107c will be filled with the void V more quickly.

[0037] Therefore, by setting the first via diameter to Φ and providing the second via 122 outside the range of planar distance L=Φ from the axis AXSA passing through the center of the first via 121, the wiring layer 107c can be used as a wiring routing layer while suppressing a decrease in the wiring life, and an increase in the number of wiring layers can be prevented. More preferably, the second via 122 is located outside the range of planar distance L=Φ×1.5 from the axis AXSA passing through the center of the first via 121. By satisfying this condition, reliability can be improved more reliably.

[0038] In this embodiment, in the first wiring structure 150, the first via 121 and the second via 122 connected to the wiring layer 107c are arranged apart from each other as described above. In contrast, in the second wiring structure 250, the via connecting the wiring layer 206d (fourth wiring layer) and the wiring layer 206c (fifth wiring layer) and the via connecting the wiring layer 206c and the wiring layer 206b may be arranged at the same planar position without being arranged apart from each other in the wiring layer 206c. This is because the wiring layer 206c is made of aluminum, and voids are unlikely to occur at the connection between the via and the wiring layer 206c. Note that the wiring layer 206c may be made of copper, and in that case, it is preferable that the via connecting the wiring layer 206d and the wiring layer 206c and the via connecting the wiring layer 206c and the wiring layer 206b are arranged apart from each other in the wiring layer 206c. Furthermore, when the wiring layer 107c of the first wiring structure 150 is made of aluminum, the first via 121 and the second via 122 do not need to be spaced apart from each other in the wiring layer 107c.

[0039] The structure of the semiconductor device APR will be described in more detail with reference to Fig. 4 to Fig. 6. Fig. 4 shows the XY plane structure of the semiconductor device APR, and depicts only the wiring layer 107c, the first via 121, and the second via 122 from Fig. 2.

[0040] The wiring layer 107c has a plurality of wirings. For example, the wiring L1 of the wiring layer 107c is connected to a power supply wiring or a ground wiring (GND wiring), and is connected to the first via 121 and the second via 122 in order to reduce parasitic resistance. There are a plurality of paths between the two vias 122. For example, the wiring L2 of the wiring layer 107c is connected to the pixel signal line, and between the first via 121 and the second via 122, there is a single path.

[0041] 5 is a perspective view of the wiring L2 of the wiring layer 107c, the first via 121, the second via 122 connected thereto, and the wiring layer 107b. FIG. 6 is a plan view of the wiring L2 portion of the wiring layer 107c.

[0042] As shown in the figure, the wiring L2 of the wiring layer 107c has a first portion 41 (via connection pad) to which the first via 121 is connected, and a second portion 42 (drawing wiring) to which the second via 122 is connected. The first via 121 and the second via 122 are aligned in the X direction. Therefore, the direction (X direction) connecting the first via 121 and the second via 122 may be a typical electron flow direction. In this example, two first vias 121 are arranged in parallel in the first portion 41 in a direction (Y direction) perpendicular to the electron flow direction (X direction) in the wiring L2. The number of first vias 121 may be one or three or more, and may be arranged in parallel in the electron flow direction (X direction) or in a matrix.

[0043] 6, range 51 is a range whose planar distance from axis AXSA passing through the center of first via 121 is within first via diameter Φ. Second via 122 is located outside this range 51. As described above, even if void 52 grows from the end of first via 121 toward downstream direction 53 of electron flow to a size equivalent to first via diameter Φ, disconnection due to void 52 can be prevented.

[0044] It is also desirable to impose a certain condition on the width of the wiring L2. Here, the width of the wiring means the length of the wiring in a direction perpendicular to the electron flow flowing through the wiring. First, consider the case where the number of first vias 121 connected to the wiring L2 is one. If the size of the void 52 grows to the same extent as the diameter Φ of the first via 121, if the wiring width is smaller than the first via diameter Φ, a break will occur. Therefore, it is desirable that the width of the wiring L2 is larger than the first via diameter Φ. In addition, considering that the void 52 occurs within a range 52 of the first via diameter Φ from the axis AXSA passing through the center of the first via 121, it is sufficient that the width of the wiring L2 is larger than the first via diameter Φ in the range of distance L = first via diameter Φ from the axis AXSA passing through the center of the first via 121. In order to further improve reliability, it is desirable to satisfy the condition that the width of the wiring L2 is larger than 1.5 times the first via diameter Φ in the range of distance L = first via diameter Φ × 1.5 from the axis AXSA passing through the center of the first via 121.

[0045] In order to satisfy these conditions, the length L1' in the electron flow direction (X direction) between the boundary between the first portion 41 and the second portion 42 and the center of the first via may be set to L1'>Φ or L1'>1.5×Φ, and the width W1 of the first portion 41 may be set to W1>Φ or W1>1.5×Φ. By satisfying these conditions, it is possible to reduce the possibility that the wiring layer 107c will be disconnected before the first via 121 is completely blocked by the void 52.

[0046] The width W2 of the second portion 42 is not particularly limited. For example, the width W2 of the second portion 42 may also be larger than the first via diameter Φ. That is, the wiring L2 may have a wiring width W (=W1 or W2) W>Φ over the entire range of the first via 121 and the second via 122. Alternatively, the width W2 of the second portion 42 may be smaller than the first via diameter Φ, for example, the width W2 may be smaller than 1 / 2 of the first via diameter.

[0047] Next, consider the case where two first vias 121 are connected in parallel to the wiring L2 of the wiring layer 107c in a direction perpendicular to the electron flow direction. In this case, when the distance between the most adjacent first vias 121 is S, it is preferable that the width of the wiring L2 is greater than S within a range of distance L = first via diameter Φ from the axis AXSA passing through the center of the first via 121, more preferably within a range of distance L = first via diameter Φ × 1.5. Similarly, when the wiring is connected to the first vias 121, the wiring width only needs to be larger than the distance S between the most adjacent first vias 121. By applying these structures to wiring with a higher current density or to a larger number of first vias 121, the risk of poor wiring reliability can be reduced probabilistically.

[0048] In order to satisfy the above conditions, in this embodiment, the distance S between the two first vias 121 is 0.57 μm. The width W1 of the first portion 41 is 1.6 μm, and the length L1 is 0.8 μm. The center of the first via 121 is located at the center of the first portion 41 in the X direction, and the length L1' in the X direction between the center of the first via 121 and the boundary between the first portion 41 and the second portion 42 is 0.4 μm (=L1 / 2), which is larger than the diameter Φ (=0.38 μm) of the first via 121. The width W2 of the second portion 42 is 1.0 μm. The length of the second portion 42 is not particularly limited, but it is desirable to set the length between the axis AXSA passing through the center of the first via 121 and the axis AXSB passing through the center of the second via 122 to be smaller than the arrangement pitch of the pixels PIX. The thickness H of the first portion 41 and the second portion 42 is 0.22 μm. Note that the sizes are not limited to the specific values ​​given here, and for example, the width W1 of the first portion 41 may be 0.8 μm or more and 2.4 μm or less, and the length L1 may be 0.4 μm or more and 1.2 μm or less. The width W2 of the second portion 42 may be 0.5 μm or more and 1.5 μm or less. The thickness H of the first portion 41 and the second portion 42 may be 0.11 μm or more and 0.33 μm or less.

[0049] 7 shows an example of a pixel circuit PXC. The pixel circuit PXC includes a photoelectric conversion element PD, a transfer gate TX, and a charge detection capacitance FD. The pixel circuit PXC may also include an amplification transistor SF, a reset transistor RS, and a selection transistor SL. The charge detection capacitance FD is configured by a floating diffusion. The transfer gate TX, the amplification transistor SF, the reset transistor RS, and the selection transistor SL are MIS (Metal-Insulator-Semiconductor) transistors. The amplification transistor SF may be a junction field effect transistor. A plurality of photoelectric conversion elements PD may share one amplification transistor SF.

[0050] The signal charge generated by the photoelectric conversion element PD is transferred to the charge detection capacitance FD via the transfer gate TX. The charge detection capacitance FD is connected to a floating node FN. The gate of the amplification transistor SF, which constitutes a source follower circuit together with the current source CS, is connected to the floating node FN. In other words, the gate of the amplification transistor SF is connected to the charge detection capacitance FD via the floating node FN. A pixel signal as a voltage signal is output to a pixel signal line OUT. The reset transistor RS resets the charge and potential of the floating node FN, and the selection transistor SL switches the connection between the amplification transistor SF and the pixel signal line OUT. The reset transistor RS and the amplification transistor SF are connected to a power supply line VDD. The pixel signal line OUT and the power supply line VDD are provided for each column of the pixel circuit PXC. The pixel signal line OUT transmits the pixel signal.

[0051] Here, for example, in the second portion 42 of the wiring layer 107c (see Figs. 4 to 6), the first via 121 is connected to the pixel signal line OUT, and the second via 122 is connected to the selection transistor SL. The wiring layer 107d (bonding member) is arranged at a constant pitch for substrate bonding, and the wiring layer 107b (pixel signal line) is arranged at the pitch of the pixel circuit PIX. When these pitches are different, for example, the number of wiring layers can be reduced as much as possible by adjusting and connecting the length of the wiring L2 of the wiring layer 107c. On the other hand, when considering voids generated by electromigration in the wiring L2 of the wiring layer 107c, it is preferable to shorten the length of the wiring L2, since microvoids contained in the copper of the wiring layer 107c between the first via 121 and the second via 122 may occur. Copper atoms aggregate at a location where the supply of copper atoms is no longer available near the barrier metal at the bottom of the first via 121, which is upstream of the electron flow, and the longer the length of the wiring L2 of the wiring layer 107c, the more microvoids in the wiring may occur. This is because the number of roboids increases and the voids are likely to become larger. Therefore, it is preferable that the wiring length between the first via 121 and the second via 122 is the same as or shorter than the arrangement pitch of the pixel circuits PXC arranged in an array. This makes it possible to further suppress the growth of voids, while also suppressing parasitic resistance by laying out the power supply lines and ground lines, and physically and electrically connecting the joints between substrates with different pitch arrangements and the vertical signal lines.

[0052] Hereinafter, the equipment EQP including the semiconductor device APR shown in Fig. 1 will be described in detail. As described above, the semiconductor device APR can include a package PKG that houses the semiconductor device IC in addition to the semiconductor device IC having the first substrate 100. The package PKG can include a base body to which the semiconductor device IC is fixed, a cover body such as glass that faces the semiconductor device IC, and a bonding member such as a bonding wire or bump that connects a terminal provided on the base body to a terminal provided on the semiconductor device IC.

[0053] The equipment EQP may include at least one of an optical system OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical system OPT forms an optical image on the semiconductor device APR. The optical system OPT is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the semiconductor device APR. The control device CTRL is, for example, composed of an ASIC.

[0054] The processing device PRCS processes the signal output from the semiconductor device APR. The processing device PRCS is composed of a CPU and an ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0055] The machine MCHN has a moving part or a propulsion part such as a motor or an engine. In the equipment EQP, the signal output from the semiconductor device APR is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) included in the equipment EQP. For this purpose, the equipment EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit and arithmetic circuit included in the semiconductor device APR. The machine MCHN may be controlled based on the signal output from the semiconductor device APR.

[0056] The device EQP is suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable terminals) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device MCHN in the camera can drive components of the optical system OPT for zooming, focusing, and shutter operation.

[0057] The equipment EQP may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device MCHN in the transportation equipment may be used as a moving device. The equipment EQP as a transportation equipment is suitable for transporting the semiconductor device APR or for assisting and / or automating driving (operation) by using a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the semiconductor device APR. Alternatively, the equipment EQP may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, or an office machine such as a copier. In the present embodiment, an example in which the semiconductor device APR is a photoelectric conversion device (solid-state imaging device) has been described, but the semiconductor device APR to which the inter-substrate wiring in the present embodiment can be applied is not particularly limited as long as it is a semiconductor device using inter-substrate wiring. The semiconductor device APR may be, for example, a display device having a pixel area for display, an arithmetic device such as a CPU or a GPU, an SRAM, or the like. The memory may be a storage device such as a DRAM or a non-volatile memory, or a control device such as an ASIC.

[0058] The above-described embodiments can be modified as appropriate without departing from the technical concept. The disclosure of the embodiments includes not only what is clearly stated in this specification, but also all matters that can be understood from this specification and the drawings attached to this specification. [Explanation of symbols]

[0059] 100: First board 150: First wiring structure 200: Second board 250: Second wiring structure 107b, 107c, 107d: wiring layers 121: first via 122: second via

Claims

1. a first substrate on which a semiconductor element is disposed; a first wiring structure disposed on the first substrate; a second substrate on which a semiconductor element is disposed; a second wiring structure disposed on the second substrate; Including, The first wiring structure is a first wiring layer joined to the wiring of the second wiring structure; a second wiring layer connected to the first wiring layer by a first via; a third wiring layer connected to the second wiring layer by a second via; having At least a portion of the second via is located in a range away from an axis passing through the center of the first via by at least a width of the first via. Semiconductor device.

2. The width of the first via is greater than twice the width of the second via; The semiconductor device according to claim 1 .

3. The thickness of the second wiring layer is smaller than the width of the first via.

3. The semiconductor device according to claim 1 or 2.

4. The first wiring layer is mainly composed of copper, The main component of the second wiring layer is copper. The semiconductor device according to claim 1 .

5. the first wiring structure has a barrier metal disposed between a portion of the first via mainly made of copper and a portion of the second wiring layer mainly made of copper; The semiconductor device according to claim 1 .

6. a wiring width of the second wiring layer in a direction perpendicular to a direction connecting the first via and the second via is greater than a width of the first via at least within a range of a planar distance from an axis passing through a center of the first via; The semiconductor device according to claim 1 .

7. the second wiring layer has a wiring width between the first via and the second via that is larger than a width of the first via; The semiconductor device according to claim 6.

8. two or more of the first vias are connected in parallel to the second wiring layer, and when a distance between the nearest adjacent first vias is S, the wiring width of the second wiring layer is greater than S at least within a range of a planar distance from an axis passing through a center of the first via and the width of the first via; The semiconductor device according to claim 6 or 7.

9. the second wiring structure includes a fourth wiring layer joined to the first wiring layer of the first wiring structure, and a fifth wiring layer connected to the fourth wiring layer by a via; The fifth wiring layer is mainly composed of aluminum. The semiconductor device according to claim 1 .

10. At least a part of a pixel circuit is formed by the first substrate and the first wiring structure. And, At least a part of a peripheral circuit is formed by the second substrate and the second wiring structure. the pixel circuit and the peripheral circuit are connected via the wiring; The semiconductor device according to claim 1 .

11. at least a part of a pixel circuit is configured by the second substrate and the second wiring structure, at least a part of a peripheral circuit is formed by the first substrate and the first wiring structure; The pixel circuit and the peripheral circuit are connected via the wiring. The semiconductor device according to claim 1 .

12. The first via and the second via are connected to a ground wiring or a power supply wiring. The semiconductor device according to claim 10 or 11.

13. the pixel circuit has a signal line for transmitting a pixel signal output from the pixel circuit, the first via and the second via are connected to the signal line; The semiconductor device according to claim 10.

14. In the second wiring layer, a length between an axis passing through a center of the first via and an axis passing through a center of the second via is equal to or shorter than an arrangement pitch of the pixel circuits arranged in an array. The semiconductor device according to claim 10 or 13.

15. the pixel circuit has a pixel region arranged in a matrix, and a junction between the first wiring layer and the wiring overlaps the pixel region; The semiconductor device according to claim 10 .

16. a distance from the axis passing through the center of the first via to the second via is greater than the width of the first via; The semiconductor device according to claim 1 .

17. a distance between the first via and the second via in a direction perpendicular to a direction in which the first substrate and the second substrate overlap each other is greater than a width of the first via; The semiconductor device according to claim 1 .

18. the first wiring layer has a damascene structure; The semiconductor device according to claim 1 .

19. the second wiring layer has a dual damascene structure; The semiconductor device according to claim 1 .

20. A semiconductor device according to any one of claims 1 to 19, an optical system for forming an image on the semiconductor device; A control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device that displays information obtained by the semiconductor device; a storage device for storing information obtained by the semiconductor device; Mechanical devices having moving or propelling parts; At least one of the six Equipment comprising:

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