Back-illuminated semiconductor photodetector

Abstract

To provide a back-illuminated semiconductor photodetector that further improves the spectral sensitivity characteristics in the long wavelength range.SOLUTION: A semiconductor substrate 11 has principal surfaces 11a and 11b which face each other. The principal surface 11a is the light incident surface of the semiconductor substrate 11. The semiconductor substrate 11 has a semiconductor region 13 and a plurality of semiconductor regions 15 which are formed on the principal surface 11b side and which form pn junctions with the semiconductor region 13. Each of the semiconductor regions 15 has a region 17 having a textured surface TS, and a region 19. The textured surface TS of the region 17 is located closer to the principal surface 11a than the surface of the region 19 in the thickness direction of the semiconductor substrate 11.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a back-illuminated semiconductor photodetector element. [Background technology]

[0002] A back-illuminated semiconductor photodetector is known that includes a semiconductor substrate having a first principal surface and a second principal surface opposed to each other (see, for example, Patent Documents 1 and 2). In the back-illuminated semiconductor photodetector described in Patent Document 2, the semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The plurality of second semiconductor regions are formed on the second principal surface side and form a pn junction with the first semiconductor region. The first principal surface is a light incidence surface to the semiconductor substrate. The plurality of second semiconductor regions have a textured surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2012 / 0313204 [Patent Document 2] JP 2011-023417 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one aspect of the present invention is to provide a back-illuminated semiconductor photodetector element that has further improved spectral sensitivity characteristics in the long wavelength region (for example, the near-infrared wavelength region). [Means for solving the problem]

[0005] A back-illuminated semiconductor photodetector according to one embodiment of the present invention includes a semiconductor substrate having a first main surface and a second main surface facing each other. The first main surface is a light incidence surface of the semiconductor substrate. The semiconductor substrate has a first semiconductor region of a first conductivity type and a plurality of second semiconductor regions of a second conductivity type. The plurality of second semiconductor regions of the second conductivity type are formed on the second main surface side and form a pn junction with the first semiconductor region. Each of the plurality of second semiconductor regions has a first region having a textured surface and a second region not having a textured surface. The thickness of the first region at the deepest position of the depression in the textured surface is smaller than the distance between the surface and the deepest position of the second region in the thickness direction of the semiconductor substrate.

[0006] In the back-illuminated semiconductor photodetector element according to the one aspect described above, the first region of the second semiconductor region has a textured surface. Light in the long wavelength range has a smaller absorption coefficient than light in the short wavelength range. Therefore, light in the long wavelength range that is incident on the semiconductor substrate from the first main surface travels through the semiconductor substrate and reaches the textured surface. The light that reaches the textured surface is reflected or diffused by the textured surface and travels further through the semiconductor substrate. Light in the long wavelength range travels a longer distance through the semiconductor substrate and is absorbed by the semiconductor substrate. As a result, the one aspect described above improves the spectral sensitivity characteristics in the long wavelength range.

[0007] Carriers generated by light absorption in the semiconductor substrate may recombine in the second semiconductor region. Carriers recombined in the second semiconductor region do not contribute to detection sensitivity, and therefore the spectral sensitivity characteristics may be degraded. When the thickness of the second semiconductor region is large, carrier recombination in the second semiconductor region is more likely to occur than when the thickness of the second semiconductor region is small. That is, when the distance from the surface of the second semiconductor region to the pn junction is large, carrier recombination in the second semiconductor region is more likely to occur than when the distance from the surface of the second semiconductor region to the pn junction is small.

[0008] In the one aspect, the thickness of the first region at the deepest position of the depression on the textured surface is smaller than the distance between the surface and the deepest position of the second region in the thickness direction of the semiconductor substrate. In this case, the distance from the textured surface to the pn junction is smaller than when the thickness of the first region at the deepest position of the depression on the textured surface is equal to or greater than the distance between the surface and the deepest position of the second region in the thickness direction of the semiconductor substrate. Therefore, recombination of carriers in the second semiconductor region caused by light incident on the semiconductor substrate is suppressed. As a result, the one aspect of the invention further improves the spectral sensitivity characteristics in the long wavelength range.

[0009] In the above aspect, the thickness of the second region in the thickness direction of the semiconductor substrate may be greater than the thickness of the first region in the thickness direction of the semiconductor substrate. When stress acts on the semiconductor substrate, carriers not caused by the incidence of light may be generated. Carriers not caused by the incidence of light cause dark current. Stress is more likely to act on the second region than in the first region, and carriers not caused by the incidence of light are more likely to be generated in the second region. In a configuration in which the thickness of the second region is greater than that of the first region, recombination of carriers not caused by the incidence of light is more likely to occur in the second region than in a configuration in which the thickness of the second region is equal to or less than the thickness of the first region. Therefore, this configuration suppresses the generation of dark current.

[0010] The one embodiment may include an electrode disposed in and in contact with the second region. In this configuration, the electrode contacts the second region, which has a thickness greater than that of the first region in the thickness direction of the semiconductor substrate. When the electrode contacts the semiconductor substrate, the material constituting the electrode and the material constituting the semiconductor substrate may be alloyed, causing an alloy spike in the semiconductor substrate. When the alloy spike reaches the p-n junction, the alloy spike increases the leakage current. In a configuration in which the thickness of the second region is greater than that of the first region, the alloy spike is less likely to reach the p-n junction than in a configuration in which the thickness of the second region is equal to or less than that of the first region. Therefore, this configuration suppresses an increase in leakage current.

[0011] In the above aspect, the textured surface of the first region may be located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate. In this case, stress is unlikely to act on the first region. Therefore, in the first region, generation of carriers not caused by the incidence of light is suppressed. As a result, this configuration suppresses the generation of dark current. In this configuration, for example, when a textured surface is formed in the second semiconductor region, the distance from the textured surface to the pn junction can be further reduced. Therefore, this configuration can further improve the spectral sensitivity characteristics in the long wavelength range.

[0012] In the above-mentioned one aspect, an edge region of the textured surface of the first region may be continuous with the surface of the second region and may be inclined with respect to the thickness direction of the semiconductor substrate. When the textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate, stress is more likely to act on the second region. In a configuration in which the edge region of the textured surface of the first region is inclined with respect to the thickness direction of the semiconductor substrate, stress acting on the second region is more likely to be dispersed than in a configuration in which the edge region of the textured surface of the first region is parallel to the thickness direction of the semiconductor substrate. Therefore, even when stress acts on the second region, the concentration of stress on the second region is suppressed. This configuration suppresses the generation of carriers not caused by the incidence of light. As a result, this configuration suppresses the generation of dark current. Effect of the Invention

[0013] According to one aspect of the present invention, there is provided a back-illuminated semiconductor photodetector element that further improves the spectral sensitivity characteristics in the long wavelength region. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a plan view of a back-illuminated semiconductor photodetector element according to an embodiment. [Diagram 2] 1 is a diagram showing a cross-sectional configuration of a back-illuminated semiconductor photodetector according to an embodiment of the present invention. [Diagram 3]1 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to an embodiment of the present invention. [Figure 4] 1 shows an SEM image of the textured surface. [Diagram 5] 1 shows an SEM image of the textured surface. [Figure 6] FIG. 2 is a diagram showing a cross-sectional configuration of one pixel. [Figure 7] FIG. 1 is a diagram showing the distribution of impurity concentrations. [Figure 8] 5A to 5C are schematic diagrams illustrating an example of a manufacturing process for the back-illuminated semiconductor photodetector element according to the embodiment. [Figure 9] 5A to 5C are schematic diagrams illustrating an example of a manufacturing process for the back-illuminated semiconductor photodetector element according to the embodiment. [Figure 10] 5A to 5C are schematic diagrams illustrating an example of a manufacturing process for the back-illuminated semiconductor photodetector element according to the embodiment. [Figure 11] 1 is a diagram showing a cross-sectional configuration of an electronic component device including a back illuminated semiconductor photodetector element according to an embodiment of the present invention. [Figure 12] FIG. 2 is a diagram showing a cross-sectional configuration of a back-illuminated semiconductor photodetector according to a first modified example of the present embodiment. [Figure 13] FIG. 11 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to a first modified example. [Figure 14] FIG. 13 is a diagram showing a cross-sectional configuration of an electronic component device including a back illuminated semiconductor photodetector element according to a first modified example. [Figure 15] FIG. 11 is a diagram showing a cross-sectional configuration of a back-illuminated semiconductor photodetector according to a second modified example of the embodiment. [Figure 16] FIG. 13 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to a second modified example. [Figure 17] FIG. 13 is a diagram showing a cross-sectional configuration of a back-illuminated semiconductor photodetector according to a third modified example of the embodiment. [Figure 18] 13 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to a third modified example of the embodiment. FIG. [Figure 19] FIG. 13 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to a fourth modified example of the embodiment. [Figure 20] FIG. 13 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to a fifth modified example of the embodiment. [Figure 21] FIG. 13 is a plan view showing a configuration of a back-illuminated semiconductor photodetector element according to a sixth modified example of the embodiment. [Figure 22] FIG. 13 is a diagram showing a cross-sectional configuration of a back-illuminated semiconductor photodetector according to a seventh modified example of the embodiment. [Figure 23] FIG. 2 is a diagram showing a cross-sectional configuration of one pixel. [Figure 24] 13A to 13C are schematic diagrams illustrating an example of a manufacturing process for a back-illuminated semiconductor photodetector element according to a seventh modified example. [Diagram 25] 13A to 13C are schematic diagrams illustrating an example of a manufacturing process for a back-illuminated semiconductor photodetector element according to a seventh modified example. [Figure 26] FIG. 1 is a diagram showing the distribution of impurity concentrations. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and duplicated description will be omitted.

[0016] The configuration of a back-illuminated semiconductor photodetector 1 according to this embodiment will be described with reference to Figs. 1 to 6. Fig. 1 is a plan view of the back-illuminated semiconductor photodetector according to this embodiment. Fig. 2 is a diagram showing a cross-sectional configuration of the back-illuminated semiconductor photodetector according to this embodiment. Fig. 3 is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to this embodiment. Figs. 4 and 5 are SEM images of the textured surface. Fig. 6 is a diagram showing the cross-sectional configuration of one pixel. Hatching representing a cross section is omitted in Fig. 6.

[0017] As shown in FIG. 1 and FIG. 2, the semiconductor photodetector element 1 includes a semiconductor substrate 11. The semiconductor substrate 11 is a substrate made of silicon (Si). The semiconductor substrate 11 has a main surface 11a and a main surface 11b that face each other. The main surface 11a is a light incident surface to the semiconductor substrate 11. The main surface 11a is a back surface, and the main surface 11b is a front surface. The semiconductor substrate 11 has, for example, a polygonal shape in a plan view. In this embodiment, the semiconductor substrate 11 has a rectangular shape in a plan view. The thickness of the semiconductor substrate 11 is, for example, 150 μm. The thickness direction of the semiconductor substrate 11 is, for example, a direction parallel to the Z axis. In this embodiment, the thickness direction of the semiconductor substrate 11 coincides with the direction in which the main surface 11a and the main surface 11b face each other. The thickness direction of the semiconductor substrate 11 coincides with a direction perpendicular to the semiconductor substrate 11, a direction perpendicular to the main surface 11a, and a direction perpendicular to the main surface 11b.

[0018] The semiconductor substrate 11 has a semiconductor region 13 of a first conductivity type, a plurality of semiconductor regions 15 of a second conductivity type, and a semiconductor region 16 of the first conductivity type. Each semiconductor region 15 is disposed on the main surface 11b side of the semiconductor substrate 11. The semiconductor region 16 is disposed on the main surface 11a side of the semiconductor substrate 11. The semiconductor region 16 functions as an accumulation layer. The first conductivity type is, for example, n-type. The second conductivity type is, for example, p-type. When the semiconductor substrate 11 is made of Si, the p-type impurity includes, for example, a Group 13 element, and the n-type impurity includes, for example, a Group 15 element. The p-type impurity is, for example, boron (B). The n-type impurity is, for example, nitrogen (N), phosphorus (P), or arsenic (As). The first conductivity type may be p-type, and the second conductivity type may be n-type.

[0019] The semiconductor region 13 has a low impurity concentration. The semiconductor region 15 and the semiconductor region 16 have a high impurity concentration. The semiconductor region 15 and the semiconductor region 16 have a higher impurity concentration than the semiconductor region 13. The impurity concentration of the semiconductor region 13 is, for example, 5×10 12 cm -3 The impurity concentration of the semiconductor region 15 is, for example, 1×10 19 cm -3The impurity concentration of the semiconductor region 16 is, for example, 1×10 15 cm -3 The maximum thickness of the semiconductor region 15 is, for example, 5 μm, and the thickness of the semiconductor region 16 is, for example, 1 μm.

[0020] The semiconductor regions 15 are two-dimensionally arranged when viewed from a direction perpendicular to the semiconductor substrate 11. In this embodiment, the semiconductor regions 15 are arranged along a first direction and a second direction perpendicular to each other. The semiconductor regions 15 are arranged in M ​​rows and N columns (M and N are integers of 2 or more). The semiconductor regions 15 are arranged along a first direction and a second direction perpendicular to each other. The first direction is, for example, a direction parallel to the X-axis. The second direction is, for example, a direction parallel to the Y-axis. Each semiconductor region 15 has, for example, a polygonal shape when viewed from a direction perpendicular to the semiconductor substrate 11. In this embodiment, each semiconductor region 15 has a rectangular shape. Each semiconductor region 15 may have a circular shape when viewed from a direction perpendicular to the semiconductor substrate 11. In this embodiment, one semiconductor region 15 constitutes one pixel. The semiconductor light detection element 1 has a plurality of pixels arranged two-dimensionally. The semiconductor region 13 and each semiconductor region 15 constitute a pn junction. The pn junction is formed at the boundary between the semiconductor region 13 and each semiconductor region 15. In each pixel, the region including the semiconductor region 15 and the pn junction is the photosensitive region. The rectangular shape includes a shape with chamfered corners and a shape with rounded corners.

[0021] The semiconductor substrate 11 has a semiconductor region 14 of a first conductivity type. The semiconductor region 14 is disposed on the principal surface 11b side of the semiconductor substrate 11. When viewed from a direction perpendicular to the principal surface 11b, the semiconductor region 14 has a frame shape. When viewed from a direction perpendicular to the principal surface 11b, the semiconductor region 14 is provided along the edge of the principal surface 11b so as to surround a region in which a plurality of semiconductor regions 15 are arranged. The semiconductor region 14 functions as a channel stop layer and prevents a depletion layer from reaching the side surface of the semiconductor substrate 11.

[0022] Each semiconductor region 15 has a region 17 having a textured surface TS and a region 19 not having a textured surface TS. The textured surface TS is a surface on which fine irregularities are formed, as shown in Figs. 4 and 5. Region 17 is a region on whose surface fine irregularities are formed. Fine irregularities are formed over the entire surface of region 17. Region 17 has the textured surface TS over the entire surface. The textured surface TS is formed, for example, by wet etching. The textured surface TS may be formed by dry etching or laser irradiation. A region on whose surface is the textured surface TS is a textured region. The textured surface TS shown in Fig. 4 is formed by wet etching. The textured surface TS shown in Fig. 5 is formed by dry etching. In Fig. 3, the region that is the textured surface TS is hatched in order to easily understand the region.

[0023] The unevenness of the textured surface TS is formed irregularly. The unevenness of the textured surface TS being irregular includes at least one of the intervals between the peaks of the unevenness varying irregularly and the height difference of the unevenness varying irregularly. In this embodiment, the intervals between the peaks of the unevenness vary irregularly and the height difference of the unevenness varies irregularly. The intervals between the peaks of the unevenness of the textured surface TS are, for example, 0.1 to 1.0 μm. The height difference of the unevenness of the textured surface TS is, for example, 0.5 to 1.5 μm. The unevenness of the textured surface TS may be formed regularly.

[0024] As shown in FIG. 3, the region 17 is located inside the region 19 when viewed from a direction perpendicular to the semiconductor substrate 11. In this embodiment, the region 17 is surrounded by the region 19 over the entire edge of the region 17 when viewed from a direction perpendicular to the semiconductor substrate 11. The surface of the region 19 is flat. The region 19 has two regions 19a and 19b that are continuous with each other. The region 19a is located along the edge of the semiconductor region 15. The region 19b has the region 19b located at one corner of the semiconductor region 15. The surface of the region 19a and the surface of the region 19b are located on the same plane. When viewed from a direction perpendicular to the semiconductor substrate 11, the region 17 has a rectangular shape with one corner cut out in a rectangular shape. When viewed from a direction perpendicular to the semiconductor substrate 11, the region 17 and the region 19b are adjacent to each other in a direction intersecting the first direction and the second direction, as shown in FIG.

[0025] 6, the thickness TH1 of region 17 at the deepest position of the recess in textured surface TS is smaller than the distance D1 between the surface of region 19 (region 19b) and the deepest position in the thickness direction of semiconductor substrate 11. The deepest position is, for example, the deepest position of the deepest recess among all the recesses. The deepest position may be the deepest position of any one of all the recesses. The deepest position may be the average position of the deepest positions of all the recesses.

[0026] The impurity concentration of the semiconductor region 15 varies with depth from the surface (the distance from the main surface 11b in the thickness direction of the semiconductor substrate 11) as shown in FIG. 7, for example. FIG. 7 is a diagram showing the distribution of the impurity concentration. The impurity concentration distribution shown in FIG. 7 is a distribution when the impurities are thermally diffused by the following process. After the semiconductor region 15 is formed, the textured surface TS is formed. Then, the impurities are thermally diffused by a high-temperature heat treatment. This process will be described later as a manufacturing process of the semiconductor photodetector element 1 according to this embodiment.

[0027] The impurity concentration of the semiconductor region 15 remains high up to a predetermined depth position, and gradually decreases from the predetermined depth position toward the main surface 11a. The semiconductor region 15 has a region R1 located closer to the main surface 11b and a region R2 located closer to the main surface 11a than the region R1 according to the distribution of the impurity concentration. The regions R1 and R2 are continuous. The region R1 is a region with a high impurity concentration. The region R2 is a transition region where the impurity concentration gradually decreases from the impurity concentration in the region R1. In this embodiment, the predetermined depth is, for example, about 3 μm.

[0028] In this embodiment, the deepest position of the depression in the textured surface TS is located near the boundary between region R1 and region R2. That is, the deepest position is located near the region where the impurity concentration of the semiconductor region 15 begins to decrease. In region 17, the proportion occupied by region R2 is greater than the proportion occupied by region R1. Region 17 may be composed of only region R2.

[0029] The thickness of the semiconductor region 15 (regions 17 and 19) is defined, for example, as the distance from the surface to the depth at which the impurity concentration of the semiconductor region 15 is equivalent to the impurity concentration of the semiconductor region 16. This distance is also the distance in the thickness direction of the semiconductor substrate 11. In this case, the thickness TH1 is defined as the distance from the deepest position of the recess in the textured surface TS to the depth at which the impurity concentration of the semiconductor region 15 is equivalent to the impurity concentration of the semiconductor region 16. The deepest position of the recess is, for example, the deepest position of the deepest recess among all the recesses. In this case, the thickness TH1 indicates the minimum value of the thickness of the region 17. The deepest position of the recess may be, for example, the deepest position of the shallowest recess among all the recesses. In this case, the thickness TH1 indicates the maximum value of the thickness of the region 17. The deepest position of the recess may be, for example, the average position of the deepest positions of all the recesses. In this case, the thickness TH1 indicates the average value of the thickness of the region 17. The thickness TH1 is, for example, 0.1 to 1.0 μm.

[0030] The thickness of semiconductor region 15 (regions 17 and 19) may be defined, for example, as the distance from the surface to the position where region R2 ends in the thickness direction of semiconductor substrate 11. The position where region R2 ends is the position where the decrease in the impurity concentration ends, as is clear from Fig. 7. In this case, thickness TH1 is defined as the distance from the deepest position of the depression in textured surface TS to the position where region R2 ends.

[0031] The distance D1 is the depth of the depressions on the textured surface TS. When the deepest position is the deepest position of the deepest depression, the distance D1 is the maximum value of the depth of the depressions on the textured surface TS. When the deepest position is the deepest position of the shallowest depression, the distance D1 is the minimum value of the depth of the depressions on the textured surface TS. When the deepest position is the average position of the deepest positions of all depressions, the distance D1 is the average depth of the depressions on the textured surface TS. The distance D1 is, for example, 1.0 to 2.5 μm.

[0032] A thickness TH2 of the region 19 (region 19b) in the thickness direction of the semiconductor substrate 11 is greater than a thickness TH3 of the region 17 in the thickness direction of the semiconductor substrate 11. The thickness TH2 is, for example, 5 μm. In this embodiment, the thickness TH2 is also the maximum thickness of the semiconductor region 15. The thickness TH3 of the region 17 varies according to the unevenness of the textured surface TS. The thickness TH3 is, for example, the thickness at the deepest position of the depression of the textured surface TS. In this case, the thickness TH3 is equal to the thickness TH1. The thickness TH3 may be, for example, the thickness at the apex position of the textured surface TS. The apex for which the thickness TH3 is defined is, for example, the highest apex of all apexes. The highest apex is the apex located closest to the main surface 11b in the thickness direction of the semiconductor substrate 11. In this case, the thickness TH3 indicates the maximum thickness of the region 17. The apex for which the thickness TH3 is defined may be, for example, the lowest apex of all apexes. The lowest apex is the apex located closest to the main surface 11a in the thickness direction of the semiconductor substrate 11. The thickness TH3 may be, for example, the distance from the average height position of the unevenness of the textured surface TS to the position where the region R2 ends. The thickness TH3 is, for example, 0.1 to 1.5 μm.

[0033] The textured surface TS is located closer to the main surface 11a than the surface of region 19 (regions 19a, 19b) in the thickness direction of the semiconductor substrate 11. That is, the textured surface TS is located closer to the main surface 11a than a virtual plane VP including the surface of region 19 (regions 19a, 19b). The main surface 11b is recessed in region 17. A step is formed between the textured surface TS and the surface of region 19. An edge region TSa of the textured surface TS of region 17 is continuous with the surface of region 19 (regions 19a, 19b) and is inclined with respect to the thickness direction of the semiconductor substrate 11. In this embodiment, the edge region TSa is inclined so that the thickness of region 17 in the edge region TSa gradually increases from region 17 toward region 19.

[0034] The semiconductor photodetector element 1 includes a plurality of insulating films 21, 23, 25, a plurality of pad electrodes 31, a plurality of under-bump metal (UBM) 33, and a plurality of bump electrodes 35. In this embodiment, the semiconductor photodetector element 1 includes one pad electrode 31, one UBM 33, and one bump electrode 35 for each semiconductor region 15. The semiconductor photodetector element 1 includes an electrode (not shown) electrically connected to the semiconductor region 14. The electrode electrically connected to the semiconductor region 14 is disposed on the main surface 11b side.

[0035] The insulating film 21 is disposed on the main surface 11a of the semiconductor substrate 11. The insulating film 21 is formed on the main surface 11a. The insulating film 21 is, for example, an oxide film. In this embodiment, the insulating film 21 is a silicon oxide (SiO 2 ). The insulating film 21 is, for example, a silicon thermal oxide film. The insulating film 21 may be made of silicon nitride (SiN). In this case, the insulating film 21 is formed, for example, by plasma-enhanced chemical vapor deposition (CVD). The insulating film 21 functions as an anti-reflection film. The insulating film 21 has a thickness of, for example, 0.1 μm.

[0036] The insulating film 23 is disposed on the principal surface 11b of the semiconductor substrate 11. The insulating film 23 is formed on the principal surface 11b. The insulating film 23 is, for example, an oxide film. In this embodiment, the insulating film 21 is made of silicon oxide. The insulating film 23 is, for example, a silicon thermal oxide film. The insulating film 23 covers the surface of each semiconductor region 15. The insulating film 23 directly covers the entire textured surface TS. The insulating film 23 may be made of silicon nitride. In this case, the insulating film 23 is formed by low-pressure CVD (Low-pressure Chemical Vapor Deposition). The insulating film 23 is made of aluminum oxide (Al 2 O 3 ). In this case, the insulating film 23 is formed by ALD (Atomic Layer Deposition). The insulating film 23 has a thickness of, for example, 0.2 μm.

[0037] The insulating film 25 is disposed on the main surface 11b of the semiconductor substrate 11. The insulating film 25 is formed on the insulating film 23. The insulating film 25 is in contact with the insulating film 23. The insulating film 25 is, for example, a nitride film. In this embodiment, the insulating film 25 is made of silicon nitride. The insulating film 23 is located between the semiconductor substrate 11 and the insulating film 25. The insulating film 25 is indirectly disposed on the semiconductor substrate 11. The insulating film 25 indirectly covers the surface of each semiconductor region 15. The insulating film 25 directly covers a region of the insulating film 23 corresponding to the region 17. The insulating film 25 indirectly covers the entire texture surface TS. The insulating film 25 may be made of silicon oxide. In this case, the insulating film 25 is formed by, for example, plasma CVD. The insulating film 25 functions as a passivation film. The insulating film 25 has a thickness of, for example, 0.1 to 0.4 μm.

[0038] The pad electrode 31 is disposed in the region 19. In this embodiment, the pad electrode 31 is disposed in the region 19b. The pad electrode 31 is formed on the region 19b and on the insulating film 23. The pad electrode 31 is connected to the region 19b through a contact hole H1 formed in the insulating film 23. The pad electrode 31 is in contact with the region 19 and the insulating film 23. The pad electrode 31 is disposed directly on the region 19b. The pad electrode 31 is in contact with the insulating film 25. The insulating film 25 covers the periphery of the pad electrode 31. The pad electrode 31 is made of a conductive material. The pad electrode 31 is made of, for example, aluminum (Al). In this case, the pad electrode 31 is formed by a sputtering method or a vapor deposition method.

[0039] As shown in FIG. 3, the pad electrode 31 has two electrode regions 31a and 31b. In this embodiment, the pad electrode 31 consists of two electrode regions 31a and 31b. The electrode region 31a is disposed in the region 19. In this embodiment, the electrode region 31a is disposed in the region 19b. The electrode region 31a is in contact with the region 19b. The electrode region 31a is disposed directly on the region 19b. The electrode region 31b is disposed in at least a part of a region of the insulating film 23 corresponding to the region 17. The electrode region 31b is disposed in the region 17 so that the insulating film 23 is located between the region 17 and the electrode region 31b. The electrode region 31b is continuous with the electrode region 31a. When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 overlaps the entire boundary between the region 17 and the region 19b. In this embodiment, the electrode region 31b overlaps with the edge region TSa that is continuous with the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b is indirectly disposed on the edge region TSa. Insulating films 23 and 25 are not shown in FIG.

[0040] The UBM 33 is disposed in the region 19. In this embodiment, the UBM 33 is disposed in the region 19b. The UBM 33 is formed on the region 19b and on the insulating film 25. The UBM 33 is connected to the pad electrode 31 through a contact hole H2 formed in the insulating film 25. The UBM 33 is in contact with the pad electrode 31. The UBM 33 is in contact with the insulating film 25. The UBM 33 is made of a material that has excellent electrical and physical connection with the bump electrode 35. The UBM 33 is made of, for example, a laminate of a layer made of titanium (Ti) and a layer made of platinum (Pt). The UBM 33 is formed by, for example, a layered deposition method.

[0041] The bump electrode 35 is disposed in the region 19. In this embodiment, the bump electrode 35 is disposed in the region 19b. The bump electrode 35 is formed on the UBM 33. The bump electrode 35 is in contact with the UBM 33. The UBM 33 is located between the pad electrode 31 and the bump electrode 35. The bump electrode 35 is indirectly disposed on the region 19. The bump electrode 35 is indirectly disposed on the pad electrode 31. The bump electrode 35 is electrically connected to the region 19b (semiconductor region 15) through the UBM 33 and the pad electrode 31. The bump electrode 35 is made of a solder material. The bump electrode 35 is made of, for example, indium (In). The bump electrode 35 is formed by, for example, a vapor deposition method.

[0042] In the semiconductor photodetector element 1, the semiconductor region 13 is brought into a fully depleted state by application of a bias voltage. That is, a depletion layer spreading from the semiconductor region 15 reaches the semiconductor region 13. The semiconductor region 13 does not have to be fully depleted.

[0043] Next, an example of a manufacturing process for the semiconductor photodetector 1 will be described with reference to Fig. 8 to Fig. 10. Fig. 8 to Fig. 10 are schematic diagrams showing an example of a manufacturing process for the back-illuminated semiconductor photodetector according to this embodiment. Hatching representing cross sections is omitted in Fig. 8 to Fig. 10.

[0044] 8(a), an n-type semiconductor substrate 11 is prepared, and an oxide film 51 is formed on the main surface 11a, and an oxide film 53 is formed on the main surface 11b. The oxide films 51 and 53 are formed, for example, by heating the semiconductor substrate 11 in an oxygen atmosphere. In the state shown in FIG. 8(a), the semiconductor substrate 11 is made of the semiconductor region 13, and does not have the semiconductor region 15 and the semiconductor region 16.

[0045] 8(b), a plurality of semiconductor regions 15 and a semiconductor region 16 are formed in the semiconductor substrate 11. Through this process, the semiconductor substrate 11 having the semiconductor region 13, the plurality of semiconductor regions 15, and the semiconductor region 16 is prepared. The semiconductor region 15 is formed as follows. An opening 53a is formed in the oxide film 53 by patterning the oxide film 53. The opening 53a has a rectangular shape. P-type impurities are added to the semiconductor substrate 11 from the main surface 11b through the opening 53a of the oxide film 53. The added p-type impurities are diffused into the semiconductor substrate 11 by high-temperature heat treatment. The semiconductor region 15 is formed by the p-type impurities diffused at a high concentration from the main surface 11b. By the high-temperature heat treatment, an oxide film 55 is formed on the semiconductor region 15 (see FIG. 8(c)). The semiconductor region 16 is formed as follows. An n-type impurity is added to the semiconductor substrate 11 from the main surface 11a. The added n-type impurity is diffused into the semiconductor substrate 11 by the high-temperature heat treatment. The semiconductor region 16 is formed by the n-type impurity diffused at a high concentration from the main surface 11a.

[0046] 8(c), a contact hole H1 is formed in the oxide film 55 by patterning the oxide film 55. After the contact hole H1 is formed, a silicon nitride film 57 is formed on the oxide films 51 and 55. The silicon nitride film 57 is formed by, for example, low-pressure CVD.

[0047] 9(a), the silicon nitride film 57 formed on the oxide film 55 and the oxide film 55 are patterned to form an opening 59 at a position corresponding to the region 17 of the semiconductor region 15. The opening 59 is formed by, for example, dry etching.

[0048] As shown in Fig. 9(b), the textured surface TS is formed in the region of the semiconductor region 15 exposed through the opening 59. The textured surface TS is formed, for example, by wet etching as described above. In Fig. 9(b) and subsequent figures, the cross-hatched regions are the regions where the textured surface TS is formed.

[0049] 9(c), an oxide film 61 is formed in the region of the semiconductor region 15 exposed from the opening 59. The oxide film 61 is formed on the textured surface TS. The oxide film 61 is formed, for example, by heating the semiconductor substrate 11 in an oxygen atmosphere. The oxide films 53 and 61 constitute the insulating film 23.

[0050] 10(a), the silicon nitride film 57 is removed from the oxide film 51 and the insulating film 23 (oxide films 53, 61). By removing the silicon nitride film 57, the semiconductor region 15 is exposed through the contact hole H1. Thereafter, the pad electrode 31 is formed in the region of the semiconductor region 15 exposed through the contact hole H1. The pad electrode 31 is also formed so as to be located on the region of the insulating film 23 around the contact hole H1. The oxide film 51 constitutes the insulating film 21.

[0051] 10(b), after the insulating film 25 is formed on the insulating film 23, the insulating film 25 is patterned to form a contact hole H2 in the insulating film 25. By forming the contact hole H2, a part of the pad electrode 31 is exposed.

[0052] 10(c), the UBM 33 is formed on the area of ​​the pad electrode 31 exposed from the contact hole H2. The UBM 33 is also formed so as to be located on the area of ​​the insulating film 25 around the contact hole H2. Then, the bump electrode 35 is formed on the UBM 33. Through these processes, the semiconductor photodetector element 1 is obtained.

[0053] Next, the configuration of an electronic component device ED including the semiconductor photodetector element 1 will be described with reference to Fig. 11. Fig. 11 is a diagram showing a cross-sectional configuration of an electronic component device including a back-illuminated semiconductor photodetector element according to this embodiment.

[0054] The electronic component device ED includes a semiconductor light detecting element 1, an electronic component EC on which the semiconductor light detecting element 1 is mounted, and a resin layer RL. The electronic component EC includes, for example, a wiring board or an ASIC (Application Specific Integrated Circuit).

[0055] The electronic component EC includes a plurality of pad electrodes 71, a plurality of UBMs 73, and a plurality of bump electrodes 75. The plurality of pad electrodes 71, the plurality of UBMs 73, and the plurality of bump electrodes 75 are arranged at positions corresponding to the plurality of bump electrodes 35 included in the semiconductor light detecting element 1. The semiconductor light detecting element 1 is mounted on the electronic component EC by bonding the corresponding bump electrodes 35 and bump electrodes 75. An electrode electrically connected to the semiconductor region 14 is also bonded to a bump electrode (not shown) of the electronic component EC.

[0056] The resin layer RL is disposed between the semiconductor light detecting element 1 and the electronic component EC. The resin layer RL functions as an underfill layer. The resin layer RL is formed by hardening a resin material filled in a space formed between the semiconductor light detecting element 1 and the electronic component EC. The resin layer RL contains, for example, an epoxy resin, a urethane resin, a silicone resin, or an acrylic resin.

[0057] As described above, in the semiconductor photodetector element 1, the region 17 of the semiconductor region 15 has the textured surface TS. Light in the long wavelength range has a smaller absorption coefficient than light in the short wavelength range. Therefore, light in the long wavelength range that is incident on the semiconductor substrate 11 from the main surface 11a travels within the semiconductor substrate 11 and reaches the textured surface TS. The light that reaches the textured surface TS is reflected or diffused by the textured surface TS and travels further within the semiconductor substrate 11. Light in the long wavelength range travels a longer distance within the semiconductor substrate 11 and is absorbed by the semiconductor substrate 11. As a result, the semiconductor photodetector element 1 has improved spectral sensitivity characteristics in the long wavelength range.

[0058] Carriers generated when light is absorbed by the semiconductor substrate 11 may recombine in the semiconductor region 15. Carriers recombined in the semiconductor region 15 do not contribute to detection sensitivity, and therefore may degrade the spectral sensitivity characteristics. When the thickness of the semiconductor region 15 is large, carrier recombination is more likely to occur in the semiconductor region 15 than when the thickness of the semiconductor region 15 is small. That is, when the distance from the surface of the semiconductor region 15 to the pn junction is large, carrier recombination is more likely to occur in the semiconductor region 15 than when the distance from the surface of the semiconductor region 15 to the pn junction is small. In the semiconductor photodetector element 1, the thickness TH1 is smaller than the distance D1. In this case, the distance from the textured surface TS to the pn junction is smaller than when the thickness TH1 is equal to or larger than the distance D1. This suppresses recombination of carriers in the semiconductor region 15 caused by light incident on the semiconductor substrate 11. As a result, the semiconductor photodetector element 1 further improves the spectral sensitivity characteristics in the long wavelength range.

[0059] In the above-described manufacturing process, before the texture region (texture surface TS) is formed on the main surface 11b, a plurality of semiconductor regions 15 (a plurality of semiconductor regions 15 2) are formed in a plurality of planned regions. After the plurality of semiconductor regions 15 are formed, in the process of forming the texture region, it is necessary to reliably prevent the texture region from reaching the pn junction. In order to reliably prevent the texture region from reaching the pn junction, it is conceivable to increase the thickness of each semiconductor region 15. However, if the thickness of each semiconductor region 15 is large, as described above, there is a risk that the improvement of the spectral sensitivity characteristics will be suppressed. Although the manufacturing process of the semiconductor light detecting element 1 includes a process of forming a texture region after forming the plurality of semiconductor regions 15, the thickness TH1 is smaller than the distance D1 in the semiconductor light detecting element 1. Therefore, it is difficult to suppress improvement in the spectral sensitivity characteristics of the semiconductor light detecting element 1.

[0060] When stress acts on the semiconductor substrate 11, there is a risk that carriers not caused by the incidence of light will be generated. Carriers not caused by the incidence of light will cause dark current. Stress is more likely to act on the region 19 than the region 17, and carriers not caused by the incidence of light are more likely to be generated in the region 19. In the semiconductor photodetector element 1, the thickness TH2 is greater than the thickness TH3. Therefore, in the semiconductor photodetector element 1, recombination of carriers not caused by the incidence of light is more likely to occur in the region 19 than in a configuration in which the thickness TH2 is equal to or less than the thickness TH3. As a result, the semiconductor photodetector element 1 suppresses the generation of dark current.

[0061] In the semiconductor photodetector element 1, the pad electrode 31 is in contact with the region 19 (region 19b). When the pad electrode 31 is in contact with the semiconductor substrate 11, the material (Al) constituting the pad electrode 31 and the material (Si) constituting the semiconductor substrate 11 may be alloyed, causing an alloy spike in the semiconductor substrate 11. When the alloy spike reaches the pn junction, it increases the leakage current. In the semiconductor photodetector element 1, since the thickness TH2 is greater than the thickness TH3, the alloy spike is less likely to reach the pn junction than in a configuration in which the thickness TH2 is equal to or smaller than the thickness TH3. Therefore, the semiconductor photodetector element 1 suppresses an increase in leakage current.

[0062] In the semiconductor photodetector 1, the textured surface TS is located closer to the main surface 11a than the surface of the region 19 in the thickness direction of the semiconductor substrate 11. That is, the textured surface TS is located closer to the main surface 11a than the imaginary plane VP. In this case, stress is less likely to act on the region 17. Therefore, in the region 17, generation of carriers not caused by the incidence of light is suppressed. As a result, the semiconductor photodetector 1 suppresses the generation of dark current. In the semiconductor photodetector 1, when the textured surface TS is formed in the semiconductor region 15 as in the manufacturing process described above, the distance from the textured surface TS to the pn junction becomes even smaller. Therefore, the semiconductor photodetector 1 further improves the spectral sensitivity characteristics in the long wavelength range.

[0063] The semiconductor photodetector element 1 is mounted on the electronic component EC via bump electrodes 35. Therefore, when the semiconductor photodetector element 1 is mounted on the electronic component EC, stress acts on region 19 (region 19b). Since the textured surface TS is located closer to the main surface 11a than the imaginary plane VP, stress is less likely to act on region 17 even when the semiconductor photodetector element 1 is mounted on the electronic component EC. Therefore, generation of carriers not caused by the incidence of light is suppressed in region 17. The semiconductor photodetector element 1 further suppresses the generation of dark current.

[0064] If the bump electrode 35 (or bump electrode 75) is crushed when the semiconductor photodetector element 1 is mounted on the electronic component EC, the crushed bump electrode 35 (or bump electrode 75) may physically interfere with a portion of the semiconductor photodetector element 1 other than the bump electrode 35 (for example, the wiring or the textured surface TS). If the bump electrode 35 (or bump electrode 75) physically interferes with other wiring, the bump electrode 35 (or bump electrode 75) may be short-circuited with the other wiring. If the bump electrode 35 (or bump electrode 75) physically interferes with the textured surface TS, the textured surface TS may be physically damaged, adversely affecting the spectral sensitivity characteristics in the long wavelength range. In the semiconductor light detecting element 1, the textured surface TS is located closer to the main surface 11a than the imaginary plane VP. A step is formed between the textured surface TS and the surface of the region 19. Therefore, when the semiconductor light detecting element 1 is mounted on the electronic component EC, the crushed bump electrode 35 (or the bump electrode 75) is unlikely to interfere with portions of the semiconductor light detecting element 1 other than the bump electrode 35. The semiconductor light detecting element 1 suppresses the occurrence of short circuits between the bump electrode 35 (or the bump electrode 75) and other wiring, and suppresses adverse effects on the spectral sensitivity characteristics in the long wavelength range.

[0065] When forming the bump electrode 35, there is a risk that the device for forming the bump electrode 35 may physically interfere with the textured surface TS. If the device for forming the bump electrode 35 physically interferes with the textured surface TS, the textured surface TS may be physically damaged, and the spectral sensitivity characteristics in the long wavelength range may be adversely affected. In the semiconductor photodetector 1, the textured surface TS is located closer to the main surface 11a than the imaginary plane VP. Therefore, the device for forming the bump electrodes 35 is unlikely to physically interfere with the textured surface TS. The semiconductor photodetector 1 suppresses the adverse effects on the spectral sensitivity characteristics in the long wavelength range when the bump electrodes 35 are formed.

[0066] In the semiconductor photodetector element 1, the edge region TSa of the textured surface TS is continuous with the surface of the region 19 (regions 19a, 19b) and is inclined with respect to the thickness direction of the semiconductor substrate 11. When the textured surface TS is located closer to the main surface 11a than the imaginary plane VP, stress is more likely to act on the region 19. In the semiconductor photodetector element 1, stress acting on the region 19 is more easily dispersed than in a configuration in which the edge region TSa is parallel to the thickness direction of the semiconductor substrate. Therefore, even if stress acts on the region 19, the concentration of stress on the region 19 is suppressed. The semiconductor photodetector element 1 suppresses the generation of carriers not caused by the incidence of light. As a result, the semiconductor photodetector element 1 further suppresses the generation of dark current.

[0067] In the semiconductor light detecting element 1, the region 19 (regions 19a and 19b) does not have a textured surface TS. In the semiconductor light detecting element 1, it is easier to form the pad electrode 31 in the region 19 (region 19b) than in a configuration in which the region 19 has the textured surface TS.

[0068] As described above, light that reaches the surface of the textured surface TS is reflected or scattered by the textured surface TS. The light reflected or scattered by the textured surface TS travels in various directions intersecting the thickness direction of the semiconductor substrate 11, compared to light reflected by a flat surface. Therefore, there is a risk that the light reflected or scattered by the textured surface TS travels to adjacent pixels, causing crosstalk between pixels. Crosstalk is a cause of noise. In the semiconductor photodetector element 1, the textured surface TS is provided for each semiconductor region 15. The textured surface TS is not provided in any region of the principal surface 11b other than the semiconductor regions 15. A configuration in which the textured surface TS is provided for each semiconductor region 15 limits the occurrence of crosstalk more than a configuration in which the textured surface TS is provided over the entire principal surface 11b. Therefore, the semiconductor photodetector element 1 suppresses the occurrence of crosstalk.

[0069] In the semiconductor light-detecting element 1, the pad electrode 31 has an electrode region 31a and an electrode region 31b. The electrode region 31a is disposed in the region 19 (region 19b). The electrode region 31b is disposed in the region 17 such that the insulating film 23 is located between the region 17 and the electrode region 31a. The electrode region 31a and the electrode region 31b are continuous. That is, the pad electrode 31 is disposed so as to extend over the region 19b and the region 17. In this configuration, the area of ​​the pad electrode 31 is larger than that in the configuration in which the pad electrode 31 is disposed only in the region 19b. The UBM 33 and the bump electrode 35 are disposed in the pad electrode 31 having a larger area. Therefore, the semiconductor light-detecting element 1 improves the reliability and stability of the electrical connection between the semiconductor region 15 (region 19) and the bump electrode 35.

[0070] A configuration in which the area of ​​the textured surface TS (region 17) is large improves the spectral sensitivity characteristics in the long wavelength range compared to a configuration in which the area of ​​the textured surface TS (region 17) is small. Therefore, in order to improve the spectral sensitivity characteristics in the long wavelength range, it is required that the area of ​​region 17 is as large as possible and the area of ​​region 19 (region 19b) is as small as possible.

[0071] The pad electrode 31 contacts the region 19b through the contact hole H1. In order to easily form the contact hole H1, the contact hole H1 is formed in a region of the insulating film 23 located on the region 19b. Since the surface of the region 19b is flat, the contact hole H1 is easily formed in the insulating film 23. If the pad electrode 31 is formed offset from the contact hole H1, the region 19b is exposed through the contact hole H1. In this case, there is a risk of deterioration of the withstand voltage characteristics and a decrease in reliability. Therefore, the area of ​​the pad electrode 31 is set in consideration of the accuracy of the formation position of the contact hole H1 and the formation position of the pad electrode 31. As a result, the area of ​​the pad electrode 31 is inevitably large.

[0072] In a configuration in which the pad electrode 31 does not have the electrode region 31b, the pad electrode 31 and the region 17 do not overlap when viewed from a direction perpendicular to the main surface 11b. In this configuration, in order to secure the area of ​​the pad electrode 31, it is necessary to expand the area of ​​the region 19b, and it is therefore necessary to reduce the area of ​​the region 17. Therefore, in a configuration in which the pad electrode 31 does not have the electrode region 31b, it is difficult to improve the spectral sensitivity characteristics in the long wavelength range. In the semiconductor photodetector element 1, the pad electrode 31 has an electrode region 31b. That is, at least a part of the pad electrode 31 and the region 17 overlap each other when viewed from a direction perpendicular to the main surface 11b. Therefore, even if the area of ​​the pad electrode 31 is secured, the semiconductor photodetector element 1 improves the spectral sensitivity characteristics in the long wavelength range.

[0073] In the semiconductor light detecting element 1, the insulating film 25 covers the periphery of the pad electrode 31. Therefore, the insulating film 25 suppresses peeling of the pad electrode 31. The insulating film 25 suppresses intrusion of material components of the bump electrode 35 from the interface between the pad electrode 31 and the insulating film 23. The insulating film 25 suppresses leakage current and short circuit occurrence.

[0074] In the semiconductor photodetector element 1, the insulating film 25 covers a region of the insulating film 23 corresponding to the region 17. A laminated film formed of the insulating films 23 and 25 covers the entire textured surface TS. By setting the thicknesses of the insulating films 23 and 25 to desired values, the laminated film (insulating films 23, 25) can form a highly reflective film. In a configuration in which the laminated film (insulating films 23, 25) forms a highly reflective film, the spectral sensitivity characteristics in the long wavelength range are further improved.

[0075] The insulating film 23 is an oxide film, and the insulating film 25 is a nitride film. Therefore, the laminated film (insulating films 23 and 25) can easily constitute a highly reflective film. When the insulating film 23 is a silicon thermal oxide film, the unevenness of the textured surface TS is smoothed out by the heat treatment in the process of forming the insulating film 23. When the unevenness of the textured surface TS is smooth, the process of forming the metal wiring including the pad electrode 31 is easy.

[0076] Next, the configuration of the semiconductor photodetector 1 according to a first modified example of the above-mentioned embodiment will be described with reference to FIG. 12 and FIG. 13. FIG. 12 is a diagram showing a cross-sectional configuration of the back-illuminated semiconductor photodetector according to the first modified example. FIG. 13 is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the first modified example. In FIG. 13, the insulating films 23 and 25 are omitted. In FIG. 13, the region that is the textured surface TS is hatched in order to easily understand the region. The first modified example is generally similar to or the same as the above-mentioned embodiment, but the first modified example differs from the above-mentioned embodiment in terms of the configuration of the semiconductor substrate 11. Hereinafter, the differences between the above-mentioned embodiment and the first modified example will be mainly described.

[0077] The semiconductor substrate 11 has a semiconductor region 20 of a first conductivity type. The semiconductor region 20 is disposed on the principal surface 11b side of the semiconductor substrate 11. The semiconductor region 20 has a high impurity concentration. The impurity concentration of the semiconductor region 20 is, for example, 1×10 18 cm -3 The thickness of the semiconductor region 20 is, for example, 1.5 μm. The semiconductor region 20 has a lattice shape when viewed from a direction perpendicular to the main surface 11b. When viewed from a direction perpendicular to the main surface 11b, the semiconductor region 20 is located between the semiconductor regions 15 adjacent to each other in the first direction and between the semiconductor regions 15 adjacent to each other in the second direction. The semiconductor region 20 is continuous with the semiconductor region 14. The semiconductor region 20 functions as a channel stop layer and suppresses the spread of a depletion layer between pixels. The semiconductor region 20 may be divided into a plurality of regions when viewed from a direction perpendicular to the main surface 11b.

[0078] The semiconductor light-detecting element 1 includes a plurality of pad electrodes 41, a plurality of under-bump metals (UBM) 43, and a plurality of bump electrodes 45. Each pad electrode 41 is disposed on the semiconductor region 20. When viewed from a direction perpendicular to the main surface 11b, each pad electrode 41 is disposed at a predetermined interval. The pad electrode 41 is formed on the insulating film 23. The pad electrode 41 is connected to the semiconductor region 20 through a contact hole formed in the insulating film 23. The pad electrode 41 is in contact with the semiconductor region 20 and the insulating film 23. The pad electrode 41 is disposed directly on the semiconductor region 20. The pad electrode 41 is in contact with the insulating film 25. The insulating film 25 covers the periphery of the pad electrode 41. The pad electrode 41 is made of a conductive material. The pad electrode 41 is made of, for example, aluminum. In this case, the pad electrode 41 is formed by a sputtering method or a vapor deposition method.

[0079] The UBM 43 is disposed in the semiconductor region 20. The UBM 43 is formed on the semiconductor region 20 and the insulating film 25. The UBM 43 is connected to the pad electrode 41 through a contact hole formed in the insulating film 25. The UBM 43 is in contact with the pad electrode 41. The UBM 43 is in contact with the insulating film 25. The UBM 43 is made of a material that has excellent electrical and physical connection with the bump electrode 45. The UBM 43 is made of, for example, a laminate of a layer made of titanium and a layer made of platinum. The UBM 43 is formed by, for example, a layered deposition method.

[0080] The bump electrode 45 is disposed on the semiconductor region 20. The bump electrode 45 is formed on the UBM 43. The bump electrode 45 is in contact with the UBM 43. The UBM 43 is located between the pad electrode 41 and the bump electrode 45. The bump electrode 45 is indirectly disposed on the semiconductor region 20. The bump electrode 45 is indirectly disposed on the pad electrode 41. The bump electrode 45 is electrically connected to the semiconductor region 20 through the UBM 43 and the pad electrode 41. The bump electrode 45 is made of a solder material. The bump electrode 45 is made of, for example, indium (In). The bump electrode 45 is formed by, for example, a vapor deposition method.

[0081] Next, the configuration of an electronic component device ED including a semiconductor photodetector element 1 according to a first modified example will be described with reference to Fig. 14. Fig. 14 is a diagram showing a cross-sectional configuration of an electronic component device including a back-illuminated semiconductor photodetector element according to the first modified example.

[0082] The electronic component device ED includes a semiconductor photodetector element 1 according to a first modified example, and an electronic component EC. The electronic component EC includes a plurality of pad electrodes 71, a plurality of UBMs 73, and a plurality of bump electrodes 75. The plurality of pad electrodes 71, the plurality of UBMs 73, and the plurality of bump electrodes 75 are arranged at positions corresponding to the plurality of bump electrodes 35, 45 included in the semiconductor photodetector element 1. The semiconductor photodetector element 1 is mounted on the electronic component EC by bonding the bump electrodes 35, 45 and the bump electrodes 75 that correspond to each other.

[0083] Next, the configuration of the semiconductor photodetector 1 according to the second modified example of the above-mentioned embodiment will be described with reference to FIG. 15 and FIG. 16. FIG. 15 is a diagram showing a cross-sectional configuration of the back-illuminated semiconductor photodetector according to the second modified example. FIG. 16 is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the second modified example. In FIG. 16, the insulating films 23 and 25 are omitted. In FIG. 16, the region that is the textured surface TS is hatched in order to easily understand the region. The second modified example is generally similar to or the same as the above-mentioned embodiment, but the second modified example differs from the above-mentioned embodiment in terms of the configuration of the semiconductor substrate 11. Hereinafter, the differences between the above-mentioned embodiment and the second modified example will be mainly described.

[0084] In the semiconductor substrate 11, trenches TR are formed so as to separate the pixels from one another. The trenches TR open in the main surface 11b. The trenches TR are formed so as to divide the semiconductor region 20 when viewed from a direction perpendicular to the main surface 11b. The trenches TR are formed in a lattice shape so as to pass between the semiconductor regions 15 adjacent in the first direction and between the semiconductor regions 15 adjacent in the second direction when viewed from a direction perpendicular to the main surface 11b. The width of the opening of the trenches TR is, for example, 5 μm. The depth of the trenches TR is greater than the thickness TH2. The depth of the trenches TR is, for example, 50 μm. The trenches TR are formed by, for example, reactive ion etching (RIE). The trenches TR may be formed discontinuously when viewed from a direction perpendicular to the main surface 11b. In this case, for example, a plurality of trenches extending in a first direction when viewed from a direction perpendicular to the main surface 11b, and a plurality of trenches extending in a second direction when viewed from a direction perpendicular to the main surface 11b are formed in the semiconductor substrate 11.

[0085] An insulating film 23 is formed on the inner surface (specifically, the side surface and bottom surface) of the trench TR. The insulating film 23 extends from above the main surface 11b into the trench TR. An insulating film 25 is formed on the insulating film 23 formed on the inner surface of the trench TR. The insulating film 25 extends from above the insulating film 23 located on the main surface 11b into the trench TR. A buried layer may be disposed in the trench TR. The buried layer is made of, for example, a metal. In this case, the buried layer (metal layer) is formed by, for example, CVD or electrolytic plating.

[0086] The trenches TR prevent light reflected or scattered by the textured surface TS from traveling to adjacent pixels. Therefore, the second variant further prevents crosstalk from occurring. The trenches TR also prevent carriers from moving between adjacent pixels.

[0087] The semiconductor photodetector element 1 according to the second modification may be mounted on an electronic component EC as shown in Fig. 11. In this case, the electronic component device ED includes the semiconductor photodetector element 1 according to the second modification and the electronic component EC.

[0088] Next, the configuration of the semiconductor photodetector 1 according to the third modified example of the above-mentioned embodiment will be described with reference to FIG. 17 and FIG. 18. FIG. 17 is a diagram showing a cross-sectional configuration of the back-illuminated semiconductor photodetector according to the third modified example. FIG. 18 is a plan view showing the configuration of the back-illuminated semiconductor photodetector according to the third modified example. In FIG. 18, the insulating films 23 and 25 are omitted. In FIG. 18, the region that is the textured surface TS is hatched in order to easily understand the region. The third modified example is generally similar to or the same as the above-mentioned embodiment, but the third modified example differs from the above-mentioned embodiment in terms of the configuration of the pad electrode 31. Hereinafter, the differences between the above-mentioned embodiment and the third modified example will be mainly described.

[0089] The pad electrode 31 is disposed so as to cover the entire semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b is indirectly disposed on the entire region in the insulating film 23 corresponding to the region 17. When viewed from a direction perpendicular to the semiconductor substrate 11, the electrode region 31b overlaps with the entire edge region TSa that is continuous with the region 19 (regions 19a, 19b). When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 overlaps with the entire boundary between the region 17 and the region 19. The pad electrode 31 is indirectly disposed on the entire semiconductor region 15.

[0090] When the pad electrode 31 is made of Al, there is a risk that the pad electrode 31 will absorb light (for example, near-infrared light) that reaches the pad electrode 31. The absorption of light in the pad electrode 31 will degrade the spectral sensitivity characteristics in the long wavelength range. In the semiconductor photodetector element 1, the insulating films 23, 25 arranged on the textured surface TS reflect or diffuse the light that reaches the insulating films 23, 25. Therefore, the amount of light that passes through the insulating films 23, 25 is reduced. As a result, the semiconductor photodetector element 1 suppresses the degradation of the spectral sensitivity characteristics in the long wavelength range.

[0091] Next, referring to FIG. 19 and FIG. 20, the configuration of the semiconductor photodetector 1 according to the fourth and fifth modified examples of the above-mentioned embodiment will be described. FIG. 19 is a plan view showing the configuration of a back illuminated semiconductor photodetector according to the fourth modified example. FIG. 20 is a plan view showing the configuration of a back illuminated semiconductor photodetector according to the fifth modified example. In FIG. 19 and FIG. 20, the insulating films 23 and 25 are omitted. In FIG. 19 and FIG. 20, the region which is the textured surface TS is hatched in order to easily understand the region. The fourth and fifth modified examples are generally similar to or the same as the above-mentioned embodiment, but the fourth modified example differs from the above-mentioned embodiment in terms of the configuration of the semiconductor region 15, and the fifth modified example differs from the above-mentioned embodiment in terms of the configuration of the semiconductor region 15 and the pad electrode 31. Hereinafter, the differences between the above-mentioned embodiment and the fourth and fifth modified examples will be mainly described.

[0092] 19, the region 19b is located in the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11. The region 19b is separated from the region 19a. The region 17 (textured surface TS) is located between the regions 19a and 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The electrode region 31b overlaps the entire edge region TSa that is continuous with the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The pad electrode 31 overlaps the entire boundary between the region 17 and the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11.

[0093] 20, the region 19b is located at the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as in the fourth modified example. The pad electrode 31 is disposed so as to cover the entire semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as in the third modified example. The electrode region 31b overlaps the entire edge region TSa that is continuous with the region 19a and the entire edge region TSa that is continuous with the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11. The pad electrode 31 overlaps the entire boundary between the region 17 and the region 19a and the entire boundary between the region 17 and the region 19b when viewed from a direction perpendicular to the semiconductor substrate 11.

[0094] In a configuration in which region 19b is located in the center of semiconductor region 15, the carrier travels a shorter distance and the time from when light is incident to when a signal is output is shorter than in a configuration in which region 19b is located at one corner of semiconductor region 15. Therefore, the response speed of each of the semiconductor photodetector elements 1 of the fourth and fifth modified examples is improved.

[0095] Next, the configuration of a semiconductor photodetector 1 according to a sixth modified example of the above-mentioned embodiment will be described with reference to FIG. 21. FIG. 21 is a plan view showing the configuration of a back-illuminated semiconductor photodetector according to the sixth modified example. In FIG. 21, the insulating films 23 and 25 are omitted. In FIG. 21, the region that is the textured surface TS is hatched in order to easily understand the region. The sixth modified example is generally similar to or the same as the above-mentioned embodiment, but differs from the above-mentioned embodiment in terms of the configuration of the semiconductor region 15. Hereinafter, the differences between the above-mentioned embodiment and the sixth modified example will be mainly described.

[0096] The region 17 and the region 19b are adjacent to each other in the first direction when viewed from a direction perpendicular to the semiconductor substrate 11. The region 17 and the regions 19a and 19b are rectangular when viewed from a direction perpendicular to the semiconductor substrate 11. The region 19b is located outside the region 19a. One side constituting the edge of the region 19a is in contact with one side constituting the edge of the region 19b. When viewed from a direction perpendicular to the semiconductor substrate 11, the area of ​​the region 19b is smaller than the area of ​​the region 19a. The pad electrode 31 is not located on the region 17 (textured surface TS). When viewed from a direction perpendicular to the semiconductor substrate 11, the pad electrode 31 does not overlap with the textured surface TS. In the sixth modified example, the semiconductor substrate 11 has the semiconductor region 20, but the semiconductor substrate 11 does not need to have the semiconductor region 20. The region 17 and the region 19b may be adjacent to each other in the second direction when viewed from a direction perpendicular to the semiconductor substrate 11.

[0097] Next, the configuration of a semiconductor photodetector 1 according to a seventh modification of the above-mentioned embodiment will be described with reference to Figs. 22 and 23. Fig. 22 is a diagram showing a cross-sectional configuration of a back-illuminated semiconductor photodetector according to the seventh modification. Fig. 23 is a diagram showing a cross-sectional configuration of one pixel. In Fig. 23, hatching representing a cross section is omitted. The seventh modification is generally similar to or the same as the above-mentioned embodiment, but differs from the above-mentioned embodiment in terms of the configuration of the semiconductor region 15. Below, differences between the above-mentioned embodiment and the seventh modification will be mainly described.

[0098] The region 17 of the semiconductor region 15 is formed along the textured surface TS. The boundary surface between the region 17 and the semiconductor region 13 has an uneven shape corresponding to the uneven shape of the textured surface TS. The boundary surface between the region 17 and the semiconductor region 13 has an uneven shape that is gentler than the uneven shape of the textured surface TS, for example. The region 19 of the semiconductor region 15 is formed along the main surface 11b. The thickness TH2 of the region 19 in the thickness direction of the semiconductor substrate 11 is equal to the thickness TH3 of the region 17 in the thickness direction of the semiconductor substrate 11. As described above, the region 17 is formed along the textured surface TS. Therefore, the thickness TH3 is unlikely to change according to the unevenness of the textured surface TS. In the seventh modified example, the thickness TH3 is, for example, approximately constant. The thickness TH1 of the region 17 at the deepest position of the recess of the textured surface TS is equal to the thickness TH2 and the thickness TH3. The thicknesses TH1, TH2, and TH3 are, for example, 0.5 μm.

[0099] The semiconductor substrate 11 may have a semiconductor region 20, as in the first modification. A trench TR may be formed in the semiconductor substrate 11, as in the second modification. The pad electrode 31 may be disposed so as to cover the entire semiconductor region 15, as in the third modification. The region 19b may be located in the center of the semiconductor region 15 when viewed from a direction perpendicular to the semiconductor substrate 11, as in the fourth and fifth modifications. The region 17 and the region 19b may be adjacent to each other in the first direction or the second direction when viewed from a direction perpendicular to the semiconductor substrate 11, as in the sixth modification.

[0100] Next, an example of a manufacturing process of the semiconductor photodetector 1 according to the seventh modified example will be described with reference to Fig. 24 and Fig. 25. Fig. 24 and Fig. 25 are schematic diagrams showing an example of a manufacturing process of the back-illuminated semiconductor photodetector according to the seventh modified example. In Fig. 24 and Fig. 25, hatching representing a cross section is omitted. Below, differences between the manufacturing process in the above-mentioned embodiment and the manufacturing process in the seventh modified example will be mainly described.

[0101] A semiconductor substrate 11 is prepared in which an oxide film 51 is formed on the main surface 11a and an oxide film 53 is formed on the main surface 11b (see FIG. 9(a)). That is, a semiconductor substrate 11 having a semiconductor region 13 is prepared. The semiconductor substrate 11 has a plurality of planned regions PR on the main surface 11b side in which a plurality of semiconductor regions 15 are to be formed. In FIGS. 24 and 25, only one planned region PR is shown.

[0102] As shown in FIG. 24(a), a semiconductor substrate 11 is provided with a plurality of semiconductor regions 15. 1 and semiconductor region 16 are formed. 1 The semiconductor region 15 is formed in the corresponding one of the plurality of planned regions PR. 1 The semiconductor region 15 is formed by the same process as that of the semiconductor region 15 in the above-described embodiment. 1 is formed by p-type impurities diffused at a high concentration from the main surface 11b. The semiconductor region 16 is formed by the same process as the process for forming the semiconductor region 16 in the above-described embodiment.

[0103] As shown in FIG. 24(b), the contact hole H1, the silicon nitride film 57, and the opening 59 are formed by the same processes as those in the above-described embodiment.

[0104] As shown in FIG. 24(c), the textured surface TS is formed by the same processes as those in the above-described embodiment. 1 The textured regions are formed in the areas exposed from the openings 59. That is, the textured regions are formed on the surfaces of the main surface 11b that are included in the above-mentioned predetermined regions PR. The textured regions are regions whose surfaces are textured surfaces TS. By forming the textured surfaces TS, the semiconductor regions 15 1 The area of ​​the semiconductor region 15 exposed through the opening 59 is removed. 1The region exposed through the opening 59 does not necessarily need to be completely removed, and part of the region may remain. In the figures from Fig. 24(c) onwards, the cross-hatched region is the region where the textured surface TS is formed.

[0105] As shown in FIG. 25(a), a plurality of semiconductor regions 15 are formed on a semiconductor substrate 11. 2 is formed. 2 is formed along the textured surface TS. That is, the semiconductor region 15 2 The semiconductor regions 15 are formed along the surface shape of the textured region. 2 The semiconductor region 15 is formed in the corresponding one of the plurality of planned regions PR. 2 The semiconductor region 15 is formed by the same process as that of the semiconductor region 15 in the above-described embodiment. 2 The p-type impurity is formed by a high concentration of p-type impurities diffused from the main surface 11b. The p-type impurities also diffuse in a direction perpendicular to the thickness direction of the semiconductor substrate 11. Therefore, the semiconductor region 15 2 is semiconductor region 15 1 The semiconductor region 15 is formed in succession. 2 and semiconductor area 15 1 These are integrated to form the semiconductor region 15. 2 constitutes region 17. Semiconductor region 15 1 The semiconductor regions 15 form the regions 19. That is, by this process, a plurality of semiconductor regions 15 are formed in the semiconductor substrate 11. 2 By the high-temperature heat treatment for forming the oxide film 61, an oxide film 61 is formed on the textured surface TS (see FIG. 25(b)). The oxide films 53 and 61 constitute the insulating film 23.

[0106] As shown in FIG. 25B, the silicon nitride film 57 is removed from the oxide film 51 and the insulating film 23 (the oxide films 53 and 61). By removing the silicon nitride film 57, the semiconductor region 15 (semiconductor region 15 1) is exposed through the contact hole H1. Thereafter, as shown in FIG. 25(c), the pad electrode 31, the insulating film 25, the UBM 33, and the bump electrode 35 are formed by the same processes as those in the above-described embodiment. Through these processes, the semiconductor photodetector element 1 according to the seventh modification is obtained. The oxide film 51 constitutes the insulating film 21.

[0107] Semiconductor Area 15 2 The impurity concentration of the semiconductor region 15 varies with the depth from the surface (the distance from the textured surface TS in the thickness direction of the semiconductor substrate 11) as shown in Fig. 26. Fig. 26 is a diagram showing the distribution of the impurity concentration. For convenience of illustration, Fig. 26 shows only the textured surface TS and the semiconductor region 15. 2 Although the interface between the textured surface TS and the semiconductor region 15 is shown as flat, in reality the interface between the textured surface TS and the semiconductor region 15 is flat. 2 As described above, the interface between the semiconductor region 13 and the substrate 10 has minute irregularities.

[0108] Semiconductor Area 15 2 The impurity concentration of the semiconductor region 15 also remains high up to a predetermined depth position, and gradually decreases from the predetermined depth position toward the main surface 11a. 2 The semiconductor region 15 has a region R1 and a region R2 according to the distribution of the impurity concentration. That is, in the seventh modification, the region 17 has a region R1 and a region R2. 2 In (region 17), the proportion occupied by region R2 is greater than the proportion occupied by region R1. In the seventh modification, the deepest position of the depression in the textured surface TS is away from the region where the impurity concentration of the semiconductor region 15 begins to decrease by the thickness of region R1. In the seventh modification, the predetermined depth is, for example, about 0.45 μm.

[0109] In the manufacturing process of the seventh modification, after the texture region is formed on the main surface 11b, a plurality of semiconductor regions 15 (a plurality of semiconductor regions 15 2) are formed in the plurality of planned regions PR. In the process of forming a texture region (texture surface TS) after the formation of the plurality of semiconductor regions 15, the thickness of each semiconductor region 15 must be increased in order to reliably prevent the texture region from reaching the pn junction. Therefore, in the process of forming the plurality of semiconductor regions 15 after the formation of the texture region, the thickness of each semiconductor region 15 can be made smaller than in the process of forming the texture region after the formation of the plurality of semiconductor regions 15. As a result, the semiconductor photodetector element 1 according to the seventh modification can further improve the spectral sensitivity characteristics in the long wavelength range.

[0110] In the manufacturing process of the seventh modification, the semiconductor region 15 2 In this case, the semiconductor region 15 (region 17) is formed along the surface shape of the texture region. 2 The thickness of the region 17 can be further reduced, and therefore the semiconductor photodetector element 1 can reliably achieve further improved spectral sensitivity characteristics in the long wavelength range.

[0111] In the manufacturing process of the seventh modification, the semiconductor region 15 2 The region 17 is formed by doping the planned region PR with a p-type impurity. 2 is easily formed.

[0112] The above describes the embodiments and modifications of the present invention, but the present invention is not necessarily limited to the above-described embodiments and modifications, and various modifications are possible without departing from the spirit of the present invention.

[0113] The textured surface TS does not have to be located closer to the principal surface 11a than the surface of the region 19 in the thickness direction of the semiconductor substrate 11. In other words, the textured surface TS does not have to be located closer to the principal surface 11a than the imaginary plane VP. For example, the peak of the textured surface TS may be at the same position as the imaginary plane VP. When the textured surface TS is located closer to the principal surface 11a than the imaginary plane VP, as described above, the semiconductor light detecting element 1 suppresses the generation of dark current. Edge region TSa may not be continuous with the surface of region 19. For example, edge region TSa may be separated from the step formed by region 17 and region 19. For example, a region not having the textured surface TS may be located between edge region TSa and the step formed by region 17 and region 19. In this case, for example, when viewed from a direction perpendicular to semiconductor substrate 11, edge region TSa may be entirely surrounded by a region not having the textured surface TS. Region 17 may have, for example, a region not having the textured surface TS. The edge region TSa may be approximately parallel to the thickness direction of the semiconductor substrate 11. When the edge region TSa is inclined with respect to the thickness direction of the semiconductor substrate 11, as described above, the semiconductor light detecting element 1 further suppresses the generation of dark current. The bump electrode 35 may be disposed directly on the pad electrode 31. In this case, the semiconductor photodetector element 1 does not include the UBM 33.

[0114] This specification discloses the following notes. (Appendix 1) a semiconductor substrate having a first main surface and a second main surface opposed to each other; the semiconductor substrate has a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting pn junctions with the first semiconductor region, each of the second semiconductor regions includes a first region having a textured surface and a second region; a thickness of the first region at a deepest position of a depression on the textured surface is smaller than a distance between a surface of the second region and the deepest position in a thickness direction of the semiconductor substrate; The first main surface is a light incidence surface on the semiconductor substrate. (Appendix 2) 2. A back-illuminated semiconductor photodetector according to claim 1, wherein a thickness of the second region in the thickness direction of the semiconductor substrate is greater than a thickness of the first region in the thickness direction of the semiconductor substrate. (Appendix 3) 3. A back-illuminated semiconductor photodetector according to claim 2, further comprising an electrode disposed in the second region and in contact with the second region. (Appendix 4) 4. A back-illuminated semiconductor photodetector element according to any one of claims 1 to 3, wherein the textured surface of the first region is located closer to the first main surface than the surface of the second region in the thickness direction of the semiconductor substrate. (Appendix 5) 5. A back-illuminated semiconductor photodetector element as described in claim 4, wherein an edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate. (Appendix 6) 6. A back-illuminated semiconductor photodetector according to any one of claims 1 to 5, wherein the second region does not have a textured surface. In the embodiment of Supplementary Note 1, the second region may have a surface on which projections and recesses are formed. The second region may have, for example, a textured surface. The second region may have, for example, a surface on which projections and recesses are formed in a manner different from that of the textured surface. When the second region has a surface on which projections and recesses are formed, the position of the surface of the second region may be defined as follows. The position of the surface of the second region may be the deepest position of the deepest recess of all the recesses. The position of the surface of the second region may be the deepest position of the shallowest recess of all the recesses. The position of the surface of the second region may be the deepest position of any one of all the recesses. The position of the surface of the second region may be the average position of the deepest positions of all the recesses. The position of the surface of the second region may be defined as the highest apex of all apexes. The position of the surface of the second region may be defined as the lowest apex of all apexes. The position of the surface of the second region may be defined as any one apex of all apexes. The position of the surface of the second region may be defined as the average height position of all apexes. When the second region has a surface having projections and recesses, the thickness of the second region varies according to the projections and recesses of the surface. In this case, the thickness of the second region may be the maximum thickness of the second region or the minimum thickness of the second region. The thickness of the second region may be the average thickness of the second region. The deepest position of the depression in the textured surface in the first region and the thickness of the first region may be defined in the same manner as in the above-described embodiment. In the embodiment of Supplementary Note 1, the second region may have a surface on which projections and recesses are formed and a flat surface. In this case, the position of the surface of the second region may be determined on the surface on which projections and recesses are formed or on the flat surface. The position of the surface of the second region may be the average height position of the surface on which projections and recesses are formed and the flat surface.

[0115] This specification also discloses the following notes. (Appendix 7) a semiconductor substrate having a first main surface and a second main surface opposed to each other; the semiconductor substrate has a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting pn junctions with the first semiconductor region, each of the plurality of second semiconductor regions has a textured surface; a thickness of the second semiconductor region at a deepest position of a depression in the textured surface is smaller than a distance between a peak of the textured surface and the deepest position in a thickness direction of the semiconductor substrate; The first main surface is a light incidence surface on the semiconductor substrate. In the embodiment of Appendix 7, the deepest position may be defined as follows: The deepest position may be the deepest position of the deepest recess among all the recesses. The deepest position may be the deepest position of the shallowest recess among all the recesses. The deepest position may be the deepest position of any one of all the recesses. The deepest position may be the average position of the deepest positions of all the recesses. In the embodiment of Appendix 7, the vertices of the texture surface may be defined as follows: The peak of the textured surface may be the highest peak of all peaks. The peak of the textured surface may be the lowest peak of all peaks. The peak of the textured surface may be any one peak of all peaks. The peak of the textured surface may be the average position of all peaks. In the embodiment of Supplementary Note 7, the distance between the top and the deepest position of the textured surface in the thickness direction of the semiconductor substrate may be defined as follows. The distance may be a maximum value of the height difference of the unevenness, or may be a minimum value of the height difference of the unevenness. The distance may be a height difference of the unevenness at any position on the textured surface. The distance may be an average value of the height difference of the unevenness. In the embodiment of Appendix 7, the entire surface of each second semiconductor region may be a textured surface. [Explanation of symbols]

[0116] 1...back-illuminated semiconductor photodetector, 11...semiconductor substrate, 11a, 11b...main surface, 13, 15...semiconductor region, 17...region having textured surface, 19...region not having textured surface, 31...pad electrode, D1...distance between the surface of the region not having textured surface and the deepest position of the depression in the textured surface, TH1...thickness of the textured surface at the deepest position, TH2...thickness of the region not having textured surface in the thickness direction of the semiconductor substrate, TH3...thickness of the region having textured surface in the thickness direction of the semiconductor substrate, TS...textured surface, TSa...edge region of the textured surface.

Claims

1. a semiconductor substrate having a first main surface and a second main surface opposed to each other; the semiconductor substrate has a first semiconductor region of a first conductivity type, and a plurality of second semiconductor regions of a second conductivity type formed on the second main surface side and constituting pn junctions with the first semiconductor region, each of the second semiconductor regions includes a first region having a textured surface and a second region; the textured surface of the first region is located closer to the first main surface than the surface of the second region in a thickness direction of the semiconductor substrate; The first main surface is a light incidence surface on the semiconductor substrate.

2. The back-illuminated semiconductor photodetector according to claim 1 , wherein a thickness of the second region in the thickness direction of the semiconductor substrate is greater than a thickness of the first region in the thickness direction of the semiconductor substrate.

3. 3. The back-illuminated semiconductor photodetector according to claim 2, further comprising an electrode disposed in and in contact with the second region.

4. 4. The back-illuminated semiconductor photodetector element according to claim 1, wherein a thickness of the second region in the thickness direction of the semiconductor substrate is greater than a distance in the thickness direction of the semiconductor substrate between a surface of the second region and a deepest position of a depression in the textured surface.

5. an interface between the first region and the first semiconductor region has an uneven shape corresponding to the textured surface; 2 . The back-illuminated semiconductor photodetector according to claim 1 , wherein a thickness of the second region in the thickness direction of the semiconductor substrate is equal to a thickness of the first region in the thickness direction of the semiconductor substrate.

6. 6. A back-illuminated semiconductor photodetector element according to claim 1, wherein an edge region of the textured surface of the first region is continuous with the surface of the second region and is inclined with respect to the thickness direction of the semiconductor substrate.

7. 7. The back-illuminated semiconductor photodetector element according to claim 1, wherein a distance between the surface of the second region and a peak of the textured surface in the thickness direction of the semiconductor substrate is greater than a thickness of the first region at a deepest position of a depression in the textured surface.

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