Semiconductor device

Abstract

To provide a novel semiconductor device.SOLUTION: A structure extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The structure includes a third conductor, a first insulator, a first semiconductor, and a second insulator. At a first intersection part where the structure and the first conductor intersect, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and a third insulator are provided concentrically. At a second intersection part where the structure and the second conductor intersect, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically outside the third conductor.SELECTED DRAWING: Figure 19

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter Therefore, one embodiment of the present invention disclosed in the present specification more specifically relates to The technical fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, and imaging devices. Devices, storage devices, signal processing devices, processors, electronic devices, systems, and driving methods thereof, The manufacturing method thereof or the inspection method thereof can be mentioned as an example. [Background technology]

[0003] In recent years, various electronic devices such as personal computers, smartphones, and digital cameras have The device includes a central processing unit (CPU) and a graphics processing unit. The electronic components used are microcomputers such as graphics processing units (GPUs), memory devices, and sensors. Improvements are being made in various areas, including speed and power consumption.

[0004] In particular, the amount of data handled by the above-mentioned electronic devices is increasing, and the storage capacity There is a demand for a large storage device. As a means for increasing the storage capacity, for example, In Patent Document 1 and Patent Document 2, a three-dimensional NA using a metal oxide as a channel formation region is described. A ND memory element is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 3060 Brochure [Patent Document 2] Patent Publication No. 2018-207038 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a highly reliable storage device. An object of one embodiment of the present invention is to provide a storage device with a large storage capacity. An object of one embodiment of the present invention is to provide a novel storage device. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device having a large storage capacity. An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0007] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. This does not preclude the existence of other issues. Other issues may be discussed in the following sections. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by reading the specification or can be derived from drawings and other descriptions, and can be appropriately extracted from these descriptions. In addition, one aspect of the present invention is to achieve at least one of the above-listed objects and other objects. The present invention aims to solve the above problems. You don't need to solve all the problems. [Means for solving the problem]

[0008] One embodiment of the present invention includes a processor and a memory device. The memory device has a plurality of memory cells, each of which has an overlapping area. Each of the memory devices has an oxide semiconductor, is a NAND type, and operates as a RAM. The semiconductor device has the function of:

[0009] One aspect of the present invention is a semiconductor device including a structure extending in a first direction, a first conductor and a second conductor extending in a second direction. a third conductor extending in a first direction; and a second conductor adjacent to the third conductor. a first insulator, a first semiconductor adjacent to the first insulator, and a second insulator adjacent to the first semiconductor; At a first intersection where the structure and the first conductor intersect, a second semiconductor adjacent to the second insulator, and a third insulator adjacent to the second semiconductor; At a second intersection where the structure and the second conductor intersect, the structure is adjacent to the second insulator. a fourth conductor and a fourth insulator adjacent to the fourth conductor, and the first insulator is disposed at the first intersection. The third conductor is connected to the outside of the first semiconductor, the second insulator, the second semiconductor, and the third insulator. A first insulator, a first semiconductor, a second insulator, and a fourth conductor are arranged concentrically at a second intersection. a fourth insulator and a third conductor are provided concentrically outside the third conductor. do.

[0010] The first direction is perpendicular to the second direction. The second intersection functions as a transistor and a capacitance element for reading data. It functions as:

[0011] The first intersection can function as a transistor. The second intersection can function as both a transistor and a capacitor. The semiconductor device can function as, for example, a NAND type memory device. It is possible.

[0012] At least one of the first semiconductor and the second semiconductor is preferably an oxide semiconductor. The semiconductor material preferably contains at least one of indium and zinc.

[0013] In addition, another embodiment of the present invention is a display device comprising at least one of an operation switch, a battery, and a display unit. The present invention also provides an electronic device having the semiconductor device. Effect of the Invention

[0014] According to one embodiment of the present invention, a highly reliable storage device can be provided. It is possible to provide a storage device with a large capacity. Or, it is possible to provide a new storage device. Alternatively, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device having a large capacity. can be done.

[0015] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects are described below. The effects not mentioned in this section are obvious to those skilled in the art in the art from the description or the description. can be derived from drawings and other descriptions, and can be extracted appropriately from these descriptions. In addition, one aspect of the present invention has at least one of the above-listed effects and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, it may not have any effect. [Brief description of the drawings]

[0016] [Figure 1] 1A is a perspective view of a memory cell, and FIG 1B is a cross-sectional view of the memory cell. [Diagram 2] 2(A) and (B) are cross-sectional views of a memory cell. [Diagram 3] 3A and 3B are cross-sectional views of a memory cell. [Figure 4] 4A to 4C are equivalent circuit diagrams of a memory cell. [Diagram 5] 5(A) and (B) are equivalent circuit diagrams of a memory cell. [Figure 6] FIG. 6 is a cross-sectional view of a memory string. [Figure 7] FIG. 7 is an equivalent circuit diagram of a memory string. [Figure 8] FIG. 8 is an equivalent circuit diagram of a memory string. [Figure 9] FIG. 9 is an equivalent circuit diagram of a memory string. [Figure 10] FIG. 10 is an equivalent circuit diagram of a memory string. [Figure 11] 11(A) and (B) are top views of a memory string. [Figure 12] 12(A) and (B) are cross-sectional views of a memory cell. [Figure 13] 13(A) and (B) are cross-sectional views of a memory cell. [Figure 14] FIG. 14 is a cross-sectional view of a memory cell. [Figure 15] FIG. 15 is a cross-sectional view of a memory cell. [Figure 16] 16(A) and (B) are cross-sectional views of a memory cell. [Figure 17] 17(A) and (B) are cross-sectional views of a memory cell. [Figure 18] Figure 18(A) is a perspective view of a memory cell, and Figure 18(B) is a cross-sectional view of the memory cell. [Figure 19]Figure 19(A) is a perspective view of a memory cell, and Figure 19(B) is a cross-sectional view of the memory cell. [Figure 20] 20(A) and (B) are cross-sectional views of a memory cell. [Figure 21] FIG. 21 is a cross-sectional view of a memory cell. [Figure 22] 22(A) and (B) are cross-sectional views of a memory cell. [Diagram 23] 23(A) and (B) are cross-sectional views of a memory cell. [Figure 24] 24(A) and (B) are cross-sectional views of a memory cell. [Diagram 25] 25(A) and (B) are cross-sectional views of a memory cell. [Figure 26] FIG. 26 is a top view of a memory string. [Figure 27] Fig. 27(A) is a diagram for explaining classification of crystal structures of oxide semiconductors, Fig. 27(B) is a diagram for explaining an XRD spectrum of a CAAC-IGZO film, and Fig. 27(C) is a diagram for explaining a micro-electron beam diffraction pattern of a CAAC-IGZO film. [Figure 28] 28(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 29] 29(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 30] 30(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 31] 31(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 32] 32(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 33] 33(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 34] Fig. 34A is a cross-sectional view illustrating a method for manufacturing a memory cell, and Fig. 34B is a perspective view illustrating a method for manufacturing a memory cell. [Diagram 35] 35(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Diagram 36] 36(A) and (B) are cross-sectional views illustrating a method for manufacturing a memory cell. [Figure 37] FIG. 37 is a circuit diagram of the semiconductor device. [Figure 38] 38(A) and (B) are timing charts illustrating an example of the operation of the semiconductor device. [Figure 39] Fig. 39(A) is a perspective view illustrating a configuration example of a semiconductor device, Fig. 39(B) is a top view illustrating a configuration example of a semiconductor device, and Fig. 39(C) is a cross-sectional view illustrating a configuration example of a semiconductor device. [Diagram 40] Fig. 40(A) is a perspective view illustrating a configuration example of a semiconductor device, Fig. 40(B) is a top view illustrating a configuration example of a semiconductor device, and Fig. 40(C) is a cross-sectional view illustrating a configuration example of a semiconductor device. [Diagram 41] 41(A) and (B) are cross-sectional views illustrating a semiconductor device. [Diagram 42] 42(A) and (B) are cross-sectional views illustrating a semiconductor device. [Diagram 43] FIG. 43 is a block diagram illustrating a configuration example of a semiconductor device. [Diagram 44] 44A to 44G are diagrams illustrating examples of circuit configurations of memory cells. [Diagram 45] 45(A) and (B) are diagrams illustrating an example of a circuit configuration of a memory cell. [Figure 46] 46A to 46C are perspective views illustrating configuration examples of a semiconductor device. [Figure 47] FIG. 47(A) is a perspective view showing an example of a semiconductor wafer, FIG. 47(B) is a perspective view showing an example of a chip, and FIGS. 47(C) and (D) are perspective views showing an example of an electronic component. [Figure 48] FIG. 48 is a block diagram illustrating the CPU. [Figure 49] 49(A) and (B) are perspective views of a semiconductor device. [Figure 50] 50(A) and (B) are perspective views of a semiconductor device. [Figure 51] 51(A) and (B) are perspective views of a semiconductor device. [Figure 52] 52(A) and (B) are diagrams showing various storage devices by hierarchical level. [Diagram 53] 53A to 53J are perspective views or schematic diagrams illustrating examples of electronic devices. [Figure 54] 54(A) to 54(E) are perspective views or schematic diagrams illustrating examples of electronic devices. [Figure 55] 55(A) to (C) are diagrams illustrating an example of an electronic device. [Figure 56] FIG. 56 is a diagram for explaining an example of the configuration of a computer system. [Figure 57] Figure 57 is a diagram showing the hierarchical structure of IoT networks and trends in required specifications. [Figure 58] Figure 58 is an image diagram of factory automation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics and is a semiconductor element ( Transistors, diodes, photodiodes, etc.) and devices that have such circuits It also refers to any device that can function by utilizing the characteristics of semiconductors. For example, integrated circuits A chip equipped with an integrated circuit or an electronic component that houses a chip in a package is a type of semiconductor device. These are just a few examples. In addition, storage devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. The body may be a semiconductor device or may have a semiconductor device.

[0018] In addition, in this specification, when it is described that X and Y are connected, X and Y When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are The case where the two are directly connected is considered to be disclosed in the present specification. For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applicable to the connection relationships shown in the drawings or text. Connections other than those shown are also assumed to be disclosed in the drawings or text. X and Y are Assume that the object is an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.) .

[0019] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as an input, output, display device, light-emitting device, or load) are connected between X and Y. The switch has a function that allows the on and off states to be controlled. That is, the switch can be either conductive (on) or non-conductive (off). It has the function of controlling whether or not current flows.

[0020] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion Conversion circuits (digital-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits, etc.) , potential level conversion circuits (power supply circuits (booster circuits, step-down circuits, etc.) level shifter circuits), voltage sources, current sources, switching circuits, amplifier circuits (signal amplitude or Circuits that can increase the amount of current, operational amplifiers, differential amplifier circuits, source follower circuits, buffers There is one or more circuits between X and Y. It is possible to connect X and Y together. For example, However, if the signal output from X is transmitted to Y, then X and Y are functionally connected. It shall be so.

[0021] In addition, when it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically When the two are directly connected (i.e., when another element or circuit is placed between X and Y) X and Y are directly connected (i.e., there is no other (when connected without any element or other circuit in between)

[0022] Also, for example, "X and Y and the source (or first terminal, etc.) and drain ( or the second terminal, etc.) are electrically connected to each other, and X, the source terminal of the transistor, the drain (or second terminal, etc.) of the transistor, the The transistors are electrically connected in the order of the The source (or first terminal, etc.) is electrically connected to X, and the drain ( or the second terminal, etc.) is electrically connected to Y, and X, the source (or 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y, in that order. "X is electrically connected to the The Y and the voltage are connected via the source (or first terminal, etc.) and drain (or second terminal, etc.) X is the source (or first terminal, etc.) of the transistor, The drain (or second terminal, etc.), Y, is provided in this connection order. Using the same representation as these examples, the order of connections in the circuit configuration can be By defining the source (or first terminal, etc.) of a transistor as (or the second terminal, etc.) and the technical scope can be determined by distinguishing them. These representation methods are merely examples, and the present invention is not limited to these representation methods. Here, X and Y are ,The object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) do.

[0023] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0024] In this specification, the term "resistance element" refers to a resistor having a resistance value higher than 0Ω. The resistor element may be a circuit element, a wiring, or the like. are wiring with resistance, transistors with current flowing between the source and drain, and diodes. , coils, etc. Therefore, the term "resistance element" is used to mean "resistance," "load," etc. " ", "area having a resistance value" and so on. The term "region having a resistance value" may be replaced with a term such as "resistance element." The resistance value is, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or less. The impedance can be set to 5Ω or less, and more preferably 10 mΩ or more and 1Ω or less. 1Ω or more 1×10 9 It may be set to Ω or less.

[0025] In this specification, the term "capacitive element" refers to a capacitor having a capacitance value higher than 0 F. Circuit elements having capacitances, wiring regions having capacitances, parasitic capacitances, gate capacitances of transistors Therefore, in this specification, a "capacitive element" refers to a pair of electrodes. The present invention relates to a circuit element including a dielectric layer between the electrodes, and a wiring and a The parasitic capacitance that appears between the gate and the source or drain of a transistor. The term "capacitance element," "parasitic capacitance," and "gate capacitance" also refers to the capacitance of the gate. Terms such as "capacity" can be replaced with terms such as "capacity" and vice versa. The term can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." In addition, the term "pair of electrodes" in "capacitance" can be used to mean "pair of conductors" or "pair of conductive regions." This can be expressed as a "pair of regions" or the like. The capacitance value is, for example, It can be set to 0.05 fF or more and 10 pF or less. Also, for example, 1 pF or more and 10 μF The following may also be used.

[0026] In this specification and the like, a transistor is referred to as having a gate, a source, and a drain. The gate is a control terminal that controls the conductive state of the transistor. The two terminals that function as the source or drain are the input and output terminals of the transistor. The two input / output terminals are connected to the transistor conductivity type (n-channel type, p-channel type) and the Depending on the potential applied to the three terminals of the transistor, one becomes the source and the other becomes the drain. Therefore, in this specification, the terms source and drain are expressed as In addition, in the present specification and the like, when describing the connection relationship of transistors, , "one of the source or drain" (or first electrode, or first terminal), "source or The drain is referred to as the "other electrode" or "second terminal." Depending on the transistor structure, in addition to the three terminals mentioned above, a back gate may be provided. In this case, in this specification and the like, The gate or backgate of the transistor is called the first gate, and the other is called the second gate. Furthermore, in the same transistor, there are cases where the "gate" and the "backgate" are The terms "transistor" and "transistor-equipped device" may be interchangeable. In the case where a gate is provided, the gates are referred to as a first gate, a second gate, and the like in this specification. It is sometimes called the first gate, the second gate, etc.

[0027] In this specification, a node may refer to a terminal, a wiring, or the like depending on a circuit configuration, a device structure, or the like. In other words, a terminal, a wiring, a conductive layer, a conductor, an impurity region, etc. Lines and the like can be referred to as nodes.

[0028] In addition, in this specification, the terms "voltage" and "electric potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, If we use the term potential (ground potential), we can say that "voltage" is "potential." Round potential does not necessarily mean 0V. Also, potential is relative, By changing the reference potential, the potential given to the wiring, the potential applied to the circuit, etc. The potential output from the input terminal, the output terminal, and the like also change.

[0029] In the present specification, the term "high level potential" refers to a potential at which a "Low level potential (also called "H")" "Low level potential (also called "L potential", "L potential", or "L")" The term "voltage" does not refer to a specific potential. For example, If both are described as "functioning as wiring that supplies high-level potential," The high level potentials provided by both wirings do not have to be equal to each other. In addition, it is written that both of the two wires "function as wires that supply low-level potential." If both wirings are mounted on the same board, the low-level potentials provided by the two wirings will not be equal to each other. Good too.

[0030] "Current" refers to the phenomenon of the movement of electric charges (electrical conduction). For example, "the electric current of a positively charged The statement "electrical conduction is occurring in the opposite direction" should be interpreted as "electrical conduction is occurring in the opposite direction for negatively charged bodies." In other words, the term "current" is used in this specification and the like unless otherwise specified. In this case, the term "electrical conduction" refers to the phenomenon of charge transfer accompanying the movement of carriers. Carriers include electrons, holes, anions, cations, complex ions, etc., and are the carriers through which electric current flows. The carriers differ depending on the system (e.g., semiconductor, metal, electrolyte, vacuum, etc.). The "direction of current" in a wire is the direction in which positive carriers move, and the amount of current is recorded as a positive value. In other words, the direction in which the negative carriers move is opposite to the direction of the current, The flow rate is expressed as a negative value. Therefore, in this specification, the positive and negative currents (or the direction of the current) Unless otherwise specified, a statement such as "current flows from element A to element B" should be interpreted as "current flows from element B This can be rephrased as "current flows from element A to element B". A statement such as "current is input" can be rephrased as "current is output from element A" It is possible.

[0031] In addition, in this specification, the ordinal numbers "first," "second," and "third" refer to the components of the The above is added to avoid confusion, and does not limit the number of components. In addition, the order of the components is not limited. A component referred to as "first" in the above description may be used in other embodiments or in the claims. In addition, for example, the present specification and the like may refer to the second component. The components referred to as "first" in one embodiment may be used in other embodiments or in the patent. It may be omitted in the claims.

[0032] In addition, the terms "above" and "below" refer to the positional relationship of a component directly above or below and directly connected to it. For example, if the expression is "electrode B on insulating layer A," It is not necessary that the electrode B is formed directly on the insulating layer A. This does not exclude the inclusion of other components in between.

[0033] Furthermore, the positional relationship between the components changes appropriately depending on the direction in which each component is depicted. Therefore, the present invention is not limited to the words and phrases described in the specification, etc., and can be rephrased appropriately according to the situation. For example, in this specification, the words "above" and "below" that indicate the arrangement are used to refer to the configuration. The positional relationship of elements may be used for convenience in explaining the drawings. Therefore, in the expression "insulation located on top of a conductor," the orientation of the drawing shown is rotated 180 degrees. By rotating it, it can be said that it is "an insulator located on the bottom surface of a conductor". In addition, in the expression "insulator located on the top surface of the conductor," the orientation of the drawing shown is rotated 90 degrees. By doing so, it can be rephrased as "the insulator located on the left (or right) surface of the conductor." This can be done.

[0034] Similarly, in this specification, the term "overlap" refers to the stacking order of components. For example, if the expression is "electrode B overlapping insulating layer A," it is written as "insulating layer The state is not limited to "electrode B is formed on insulating layer A," but rather "electrode B is formed under insulating layer A." or "electrode B is formed on the right (or left) side of insulating layer A." This does not exclude any.

[0035] In this specification, the terms "adjacent" and "close" mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" means It is not necessary that the insulating layer A and the electrode B are directly in contact with each other, and no other structure is required between the insulating layer A and the electrode B. This does not exclude those that include compositional elements.

[0036] In addition, in this specification, the terms "film" and "layer" are interchangeable depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer." Or, in some cases or circumstances, it may be possible to change the term to " Depending on the circumstances, it is possible to replace the terms "film" and "layer" with other terms instead of using the terms "film" and "layer". For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Alternatively, for example, the terms "insulating layer" and "insulating film" may be changed to "insulating It may be possible to change the term to "body."

[0037] In addition, in this specification, terms such as "electrode," "wiring," and "terminal" refer to these components. There is no functional limitation. For example, an "electrode" can be used as a part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes" and "wires." This also includes cases where the "electrode" and "wiring" are integrally formed. is sometimes used as part of a "wire" or "electrode", and vice versa. In addition, the term "terminal" refers to a device that is formed by integrating multiple "electrodes," "wiring," "terminals," etc. For example, an "electrode" may be considered a part of a "wire" or a "terminal." For example, a "terminal" can be a part of a "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be used interchangeably with "area," etc. It may be replaced by a word.

[0038] In addition, in this specification and the like, the terms "wiring", "signal line", "power line", etc. may be used interchangeably. They can be interchanged depending on the situation. For example, "wiring" In some cases, it may be possible to change the term to "signal line". In some cases, it may be possible to change the term "wiring" to a term such as "power line." And vice versa, terms such as "signal line" and "power line" will be changed to the term "wiring". It may be possible to change terms such as "power line" to terms such as "signal line." In addition, the opposite is also true, and terms such as "signal line" may be used interchangeably with "power line" In addition, the term "potential" applied to the wiring may be changed to another term. In some cases or situations, the term "signal" may be changed to "signal" or similar. And vice versa, terms such as "signal" may be used interchangeably with "potential." In some cases, it may be possible to change the term to something like this:

[0039] In this specification, impurities in a semiconductor include, for example, substances other than the main components constituting a semiconductor layer. For example, an element with a concentration of less than 0.1 atomic percent is an impurity. For example, the density of defect states in semiconductors increases, carrier mobility decreases, and When the semiconductor is an oxide semiconductor, the crystallinity may be decreased. Impurities that change the properties of a conductor include, for example, elements of Group 1, Group 2, and Group 13. Elements of Group 14, Group 15, transition metals other than the main component, etc. (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, if the semiconductor is a silicon layer, impurities that change the properties of the semiconductor may be present. Examples of the elements include oxygen, elements of Group 1 except hydrogen, elements of Group 2, elements of Group 13, elements of Group 15, Group elements, etc.

[0040] In this specification, a switch refers to a device that is in a conductive state (on state) or a non-conductive state (off state). A switch that is in a "switchable state" and has the function of controlling whether or not current flows. A switch is a device that has the function of selecting and switching the path through which an electric current flows. The switch may be an electrical switch, a mechanical switch, or the like. The current control device is not limited to a specific one as long as it can control the current.

[0041] An example of an electrical switch is a transistor (e.g., a bipolar transistor, M OS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) diode , MIS (Metal Insulator Semiconductor) diode diode-connected transistors, or logic circuits that combine these When using a transistor as a switch, the "conduction state" of the transistor This means that the source and drain electrodes of the transistor can be considered to be electrically shorted. The "non-conducting state" of a transistor refers to the state in which the source electrode and the drain electrode of the transistor are in a non-conducting state. This refers to a state in which the gate electrodes can be considered to be electrically disconnected. When the transistor is operated as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is the MEMS (Micro-Electro-Mechanical System). There are switches that use the technology known as "electrode-coupled switch." These switches have electrodes that can be moved mechanically. The electrode moves to control conduction and non-conduction.

[0043] In this specification, the term "on-state current" refers to the current flowing between the source and the The term "off-state current" can also refer to the current that flows between the drain and the transistor. It can refer to the current that flows between the source and drain when in the off state.

[0044] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" or "approximately parallel" means that the angle between the two straight lines is between -30° and 30°. "Perpendicular" means that the angle between two straight lines is between 80° and 100°. Therefore, it includes the case where the angle is between 85° and 95°. "Almost perpendicular" or "approximately perpendicular" means that two straight lines are arranged at an angle of 60° or more and 120° or less. "Orthogonal" means that the angle between the two straight lines is between 80° and 100°. This refers to a state in which the object is arranged at an angle. Therefore, this includes cases in which the angle is between 85° and 95°. .

[0045] In this specification and elsewhere, references to counts and measurements or to counts or measurements With respect to convertible objects, methods, and events, use the words "same," "same," "equal," or When we say "uniform," we mean a margin of error of plus or minus 20% unless otherwise specified. This includes:

[0046] In this specification, the term "metal oxide" refers to a metal oxide in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). , oxide semiconductor (also called OS) For example, when a metal oxide is used in the active layer of a transistor, the metal oxide In other words, metal oxides have the functions of amplification, rectification, and forming a channel forming region of a transistor having at least one switching function. When the metal oxide can be formed, the metal oxide is called a metal oxide semiconductor. In addition, it can be called an OS transistor. In this case, the transistor can be referred to as a transistor having a metal oxide or an oxide semiconductor. Cut.

[0047] In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met de). It may also be called tetrahydrofuran (tetrahydrofuran) oxynitride.

[0048] In addition, in this specification and the like, the configurations shown in each embodiment may be used in combination with the configurations shown in other embodiments. The above-mentioned embodiments may be combined in any suitable manner to form one aspect of the present invention. When multiple configuration examples are shown, the configuration examples can be combined with each other as appropriate.

[0049] In addition, the contents (or even a part of the contents) described in one embodiment may be used in the embodiment. Another content (or a part of the content) described in one or more other embodiments Apply or combine with at least one of the contents to be described (or a part of the contents) , or substitution, etc. can be performed.

[0050] The contents described in the embodiments are explained in detail with reference to various figures in each embodiment. This refers to what is stated or what is stated using the text in the specification.

[0051] In addition, a figure (or a part thereof) described in one embodiment may be different from another part of the figure, Another figure (or a part thereof) described in the embodiment and one or more other embodiments A combination of at least one of the figures (or a part of the figure) described in the form of By doing so, even more figures can be constructed.

[0052] The embodiments described in this specification will be described with reference to the drawings. The present invention may be embodied in many different forms and may be practiced without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the form and details of the present invention may be modified in various ways. Therefore, the present invention should not be construed as being limited to the description of the embodiment. In the configuration of the embodiment of the invention, the same parts or parts having similar functions are denoted by the same reference numerals. Reference numerals may be used in common between different drawings, and repeated explanations may be omitted. In order to make it easier to understand the surface, some of the components are shown in perspective views or top views. It may be omitted.

[0053] Also, in the drawings of this specification, the sizes, layer thicknesses, or areas may be exaggerated for clarity. Therefore, the size and aspect ratio are not necessarily limited to the above. The drawings are schematic representations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or timing These may include signal, voltage, or current variations due to timing misalignment.

[0054] In this specification and the like, when the same reference numeral is used for a plurality of elements, there is no need to distinguish between them. When there is a code, an identification code such as “_1”, “[n]”, “[m,n]”, etc. is added to the code. For example, one of two wirings GL is written as wiring GL[1], The other one may be written as wiring GL[2].

[0055] (Embodiment 1) FIG. 1A illustrates a perspective view of a memory cell 100 according to one embodiment of the present invention. 1A, the memory cell 10 is a memory device having a three-dimensional stacked structure. In order to make the internal structure of the memory cell 100 easier to understand, a part of the memory cell 100 is omitted. In the drawings, arrows indicating the X direction, the Y direction, and the Z direction may be used. The X direction and the Z direction are mutually perpendicular directions. One of the X, Y, or Z directions is sometimes called the "first direction" or "primary direction." The other one may be called the "second direction" or "second direction". One of the directions may be called the "third direction" or the "third direction." In FIG. 1 and the like, the central axis 10 The direction parallel to 8 is the Z direction.

[0056] <Memory cell configuration example> FIG. 1B is a cross-sectional view showing a part of the memory cell 100 shown in FIG. 1(B) is a cross-sectional view of a portion of the memory cell 100 as viewed from the Y direction. 3A is a cross-sectional view of the XZ plane passing through the central axis 108. FIG. 3B is a cross-sectional view of the portion A1-A2 shown in FIG. 1B, as viewed from the Z direction. 1 is a cross-sectional view of a portion B1-B2 indicated by a dashed line as viewed from the Z direction.

[0057] The memory cell 100 includes a plurality of insulators 101 disposed above a substrate (not shown). The multiple insulators 101 are stacked in order from the substrate side. (i is an integer of 1 or more) is denoted as insulator 101[i]. An insulator 101[i+1] is disposed above an insulator 101[i], and an insulator 101[i+1 ] and the insulator 101[i+2] disposed above the insulator 101[ The conductor 102 is disposed between the insulator 101[i+1] and the insulator 101[i+1]. The conductor 103 is disposed between the insulator 101[i+2]. The conductor 103 extends along the Y direction.

[0058] The memory cell 100 also includes a structure 130. The structure 130 is aligned along the central axis 108. The structure 130 extends in the Z direction. The structure 130 has a columnar or cylindrical shape. The structure 130 includes an insulator 111, a conductor 112, a semiconductor 113, a semiconductor 114, and an insulator. 115, a semiconductor 116, an insulator 117, and a conductor 118. A cross-sectional view is shown in which the illustration of the structure 130 is omitted.

[0059] In this embodiment, when the structure 130 is viewed from the Z direction, the outer periphery of the structure 130 Although the shape is shown as being circular, the outer periphery of the structure 130 does not have to be circular. For example, the structure 130 may have a polygonal shape such as a triangle or a rectangle. It may be made up of curved lines, or may be made up of a combination of curved lines and straight lines. As shown in FIG. 2, the structure 130 has projections and recesses on its side surface extending in the Z direction.

[0060] The memory cell 100 also includes a region 132. The region 132 is In the process, a part of the insulator 101 and the conductor 103 is removed to form a region. In addition, the region 132 includes a semiconductor 121, an insulator 122, an insulator 123, and a conductor 1. 02, etc. are provided. In order to make the area 132 easier to recognize, FIG. 2 is a cross-sectional view in which the illustration of components provided in is omitted.

[0061] The region 132 is provided around the structure 130. The region 132 is also provided in a direction perpendicular to the Z direction. When viewed from the direction, a region 135 overlapping with the concave portion of the structure 130 and a region 136 overlapping with the convex portion of the structure 130 are The region 136 is an insulator 10. A region overlapping with the structure 130 through the conductor 103 and a region overlapping with the structure 130 through the conductor 103. It has a region.

[0062] As described above, the structure 130 has a columnar or cylindrical shape. 18 extends in the Z direction along the central axis 108, and an insulator 117 is disposed adjacent to the conductor 118. The semiconductor 116 is disposed adjacent to the insulator 117. The insulator 115 is disposed adjacent to the semiconductor 116. Also, the semiconductor 114 is disposed adjacent to the insulator 11 5. In addition, in the protruding portion of the structure 130, the semiconductor 113 is 114, the conductor 112 is disposed adjacent to the semiconductor 113, and the insulator 1 11 is provided adjacent to the conductor 112.

[0063] As shown in FIG. 3A, in the recess of the structure 130, the insulator 117, the semiconductor 116, The insulator 115 and the semiconductor 114 are disposed concentrically outside the conductor 118 . In addition, in the recess of the structure 130, a semiconductor 121 is provided adjacent to the semiconductor 114. An insulator 122 is provided adjacent to the conductor 121. In addition, the conductor 10 extending in the Y direction 2 intersects with the recess of the structure 130.

[0064] The conductor 118 and the insulator 102 of the structure 130 are arranged in a region where the structure 130 intersects with the conductor 102 (overlapping region). 17, semiconductor 116, insulator 115, and semiconductor 114, and semiconductor 121, insulator 12 2, and the conductor 102 function as the transistor WTr. Tr can be said to be formed at the intersection of structure 130 and conductor 102.

[0065] In the memory cell 100, the conductor 102 functions as the gate electrode of the transistor WTr. Therefore, the insulator 122 functions as a gate insulator. The semiconductor 114 can function as a semiconductor in which a channel is formed. In addition, the conductor 118 may function as a back gate electrode. 117, semiconductor 116, and insulator 115 may function as a back gate insulator. FIG. 3A is also a cross-sectional view of the transistor WTr as viewed from the Z direction.

[0066] As shown in FIG. 3B, the insulator 117 and the semiconductor 118 are disposed on the protruding portion of the structure 130. 16, insulator 115, semiconductor 114, semiconductor 113, conductor 112, and insulator 111 The conductor 118 is provided concentrically outside the conductor 118. The conductor 10 extending in the Y direction 3 intersects with the convex portion of the structure 130.

[0067] The conductor 118 and the insulator 103 of the structure 130 are arranged in a region where the conductor 118 and the insulator 103 intersect (overlap) with each other. 17, semiconductor 116, insulator 115, semiconductor 114, semiconductor 113, and conductor 112 The conductor 103, the insulator 111, and the conductor The region where the body 112 overlaps functions as a capacitance element Cs. It can be said that the capacitance element Cs is formed at the intersection of the structure 130 and the conductor 103.

[0068] In the transistor RTr, the conductor 112 functions as the gate electrode of the transistor RTr. The semiconductor 113 and the semiconductor 114 also function as the gate electrode of the transistor RTr. In the transistor RTr, the insulator 115 serves as a gate insulating layer. The semiconductor 116 functions as a semiconductor in which a channel is formed. In some cases, the conductor 118 functions as a back gate electrode. It may function as a back gate insulating layer. Figure 3(B) shows the transistor viewed from the Z direction. 1 is a cross-sectional view of the starter RTr and the capacitance element Cs.

[0069] FIG. 4A shows an equivalent circuit diagram of a memory cell 100. In FIG. Either the source or the drain of the WTr is electrically connected to the conductor 112. The other of the source or drain of WTr is electrically connected to the gate of the transistor RTr. The gate of the transistor WTr is electrically connected to the conductor 102. One electrode is electrically connected to the gate of the transistor RTr, and the other electrode of the capacitance element Cs is The pole is electrically connected to the conductor 103 .

[0070] In this specification and the like, the gate of the transistor RTr, the source or drain of the transistor WTr The node where the other electrode of the drain and one electrode of the capacitance element Cs are electrically connected is called node ND. say.

[0071] A part of the semiconductor 116 functions as a channel formation region of the transistor RTr. Another portion of the conductor 116 functions as the source or drain of the transistor RTr. The transistor RTr shown in FIG. 4A is a transistor having a back gate. In this embodiment, a part of the conductor 118 functions as a back gate of the transistor RTr. In addition, a part of the conductor 102 functions as the gate of the transistor WTr. A part of the conductor 103 functions as the other electrode of the capacitance element Cs. functions as either the source or the drain of the transistor WTr.

[0072] Moreover, as shown in FIG. 4B, the transistor RTr does not need to have a back gate. FIG. 4B corresponds to an equivalent circuit diagram of a memory cell 100H, which will be described later. As shown in FIG. 4C, the transistor WTr may be provided with a back gate. 1 shows an example of a circuit configuration in which the back gate of the transistor WTr is electrically connected to the conductor 118. However, the conductor electrically connected to the back gate of the transistor WTr is other than the conductor 118. Alternatively, the circuit may be configured as shown in FIG. 5(A) or FIG. 5(B).

[0073] FIG. 6 shows four memory cells 100 (memory cell 100[1] to memory cell 100[4]). FIG. 7 shows a cross-sectional view of a memory string 200 including an equivalent circuit. The memory string 200 has a structure in which four memory cells 100 are connected in series. Thus, the memory string 200 is a NAND-type like memory device.

[0074] In the equivalent circuit diagram, the transistor is preferably an OS transistor. In order to clarify, the circuit symbol for a transistor may be marked with "OS". The transistor is preferably a Si transistor (a semiconductor layer in which a channel is formed is made of silicon In order to clearly indicate that the transistor is a silicon-based transistor, the circuit symbol for the transistor is marked with "Si In FIG. 7, the transistors WTr and RTr are O This indicates that it is an S transistor.

[0075] The memory string 200 shown in FIG. 6 includes nine layers of insulator 101 (insulator 101[1] to insulator 101[9]) and four layers of conductor 102 (conductor 102[1] to conductor 10 2[4]), four layers of conductor 103 (conductor 103[1] to conductor 103[4]), Equipped with.

[0076] In addition, in FIG. 7, the memory cell 100[1] includes a transistor WTr, The capacitance element RTr and the capacitance element Cs are respectively the transistor WTr[1], the transistor R The memory cells 100[2] to 100[3] are shown. The rechargeable battery 100[4] includes a transistor WTr, a transistor RTr, and a capacitance element Cs is shown similarly.

[0077] The number of memory cells 100 included in the memory string 200 is not limited to four. If the number of memory cells 100 included in the memory string 200 is n, n is 2 or more. Any integer above is acceptable.

[0078] In addition, the term "a configuration in which a plurality of memory cells 100 are connected in series" refers to a configuration in which the memory cells 100[k ] (k is an integer between 1 and n) The source of the transistor WTr[k+1] included in the memory cell 100[k+1] The transistor included in the memory cell 100[k] is electrically connected to the source (or drain) of the The drain (or source) of the transistor RTr[k] is included in the memory cell 100[k+1]. The transistor RTr[k+1] is electrically connected to the source (or drain) of the transistor RTr[k+1]. It means success.

[0079] The semiconductor in which the channels of the transistors WTr and RTr are formed is a single crystal. Semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either alone or in combination. Examples of semiconductor materials include silicon and germanium. Silicon germanium, silicon carbide, gallium arsenide, etc. can also be used. Compound semiconductors such as oxide semiconductors and nitride semiconductors may also be used.

[0080] Note that the semiconductor used in the transistor may be a stack of semiconductor layers. In this case, semiconductors having different crystal states may be used. A conductive material may also be used.

[0081] In particular, the transistor WTr has a semiconductor layer in which the channel is formed, which is a type of metal oxide. A transistor including an oxide semiconductor (also referred to as an "OS transistor") is preferably used. Since the band gap of an oxide semiconductor is 2 eV or more, the off-current is significantly small. If an OS transistor is used for the transistor WTr, the node ND (called the "storage node") The memory cell 100 can retain the charge written therein for a long period of time. When an OS transistor is used as the transistor, the memory cell 100 is called an “OS memory.” A memory string 200 including the memory cell 100 can also be referred to as a It can be called "OS memory."

[0082] NAND type storage devices that include OS memory are referred to as "OS NAND type" or "OS NAND Also called "OS type storage device." OS memory is a type of storage device that has multiple OS memories stacked in the Z direction. S NAND type storage devices are referred to as "3D OS NAND type" or "3D OS NAND It is also called a "type of memory device."

[0083] The transistor RTr is a transistor that uses silicon for the semiconductor layer in which the channel is formed. The transistor RTr may be a Si transistor. The transistor WTr may be an OS transistor. In the above, an OS transistor is used as the transistor WTr, and a Si transistor is used as the transistor RTr. 2 shows an equivalent circuit diagram of a memory string 200 when transistors are used.

[0084] OS memory can be written for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered non-volatile. It is also possible.

[0085] In addition, since the amount of charge written to the OS memory is unlikely to change over a long period of time, the OS memory is a binary ( It is possible to hold not only 1 bit but also multi-value (multi-bit) information.

[0086] In addition, since OS memory writes charge to the node via the OS transistor, Eliminates the need for the high voltage required by conventional flash memory and enables high-speed write operations In addition, the erase operation before rewriting data in the flash memory is performed in the OS memory. In addition, the charge injection and extraction from the floating gate or the charge trapping layer is not required. Since no data is written to the OS memory, data can be written and read an unlimited number of times. The OS memory is less susceptible to degradation and has higher reliability than conventional flash memory. Reliability is gained.

[0087] In addition, the OS memory is magnetoresistive memory (MRAM) or resistive random access memory (ReRAM ) does not involve structural changes at the atomic level when data is rewritten. The memory has a higher rewrite endurance than the magnetoresistive memory and the resistance change memory.

[0088] In addition, the off-state current of OS transistors hardly increases even in high-temperature environments. The off-state current hardly increases even in environments with temperatures between 200°C and 300°C. The on-current is unlikely to decrease even in high-temperature environments. In addition, the OS transistor has a high insulation between the source and drain. By using OS transistors as transistors that constitute a semiconductor device, This makes it possible to realize a semiconductor device that operates stably even in a high-temperature environment and has good reliability.

[0089] As shown in FIG. 9, depending on the purpose or application, the transistor WTr may be S Alternatively, an i transistor may be used as the transistor RTr, and an OS transistor may be used as the transistor RTr. In addition, as shown in FIG. 10, depending on the purpose or application, the transistors WTr and Both of the transistors RTr may be Si transistors.

[0090] Like the memory string 200, a plurality of memory cells 100 are arranged continuously in the Z direction. This allows for an increase in storage capacity per unit area.

[0091] In addition, the memory capacity of a semiconductor device using the memory cell 100 or the memory string 200 is If you want to increase the number of memory cells 100 or memory strings 200, you can stagger them. The electrodes may be arranged in a lattice pattern (see FIG. 11(A)) or a lattice pattern (see FIG. 11(B)). FIG. 1 is a top view of a memory string.

[0092] Table 1 shows the 3D NAND memory device fabricated with Si transistors and the 3D OS NA A comparison table of ND type memory devices is shown below.

[0093] [Table 1]

[0094] [Modifications] Next, a description will be given of a modification of the memory cell 100. The examples can be appropriately combined with other memory cells shown in this specification and the like.

[0095] FIG. 12A shows a cross-sectional view of the memory cell 100A. 00. Therefore, in the present embodiment and the like, the memory cell 100A is mainly The differences from cell 100 will be described.

[0096] A memory cell according to one embodiment of the present invention has a structure similar to that of a memory cell 100A shown in FIG. When viewed from the Z direction, in an area that does not overlap with the insulator 101 and / or the conductor 103, The semiconductor 121, the insulator 122, and the conductor 102 may be removed. The insulator 123 of the module 100A has a region in contact with the insulator 101 and a region in contact with the conductor 103. A region in contact with the semiconductor 121, a region in contact with the insulator 122, and a region in contact with the conductor 102 are and a contacting region.

[0097] FIG. 12B shows a cross-sectional view of the memory cell 100B. The memory cell 100B is a modified example of the memory cell 100A. In the memory cell 100B, the region of the structure 130 that crosses the conductor 102 (overlapping region) The conductor 118, the insulator 117, the semiconductor 116, the insulator 115, and the semiconductor 11 4, the insulator 122, and the conductor 102 function as a transistor WTr. By not providing 121, the manufacturing process can be simplified and the productivity of the memory device can be improved. do.

[0098] FIG. 13A shows a cross-sectional view of the memory cell 100C. This is a modification of the memory cell 100A. Like the memory cell 100C, the formation of the semiconductor 113 is omitted, and the conductive The conductor 112 and the semiconductor 114 may be in contact with each other. The conductor 118, the insulator 117, and the conductor 103 of the conductor 130 are intersected (overlapped) in the region. The semiconductor 116, the insulator 115, the semiconductor 114, and the conductor 112 form a transistor RTr. By not providing the semiconductor 113, the manufacturing process is simplified and the memory device can be produced. This can increase productivity.

[0099] FIG. 13B shows a cross-sectional view of the memory cell 100D. It is a modification of memory cell 100B and a modification of memory cell 100C. As shown in FIG. 1, the semiconductor 113 may be omitted and the conductor 112 and the semiconductor 114 may be in contact with each other. The transistor WTr in the memory cell 100D has the same structure as the memory cell 100B. The transistor RTr in the memory cell 100D has a structure similar to that of the memory cell 10 The semiconductor 113 and the semiconductor 121 are not provided, so that the manufacturing process This simplifies the process and increases the productivity of the storage device.

[0100] FIG 14 shows a cross-sectional view of the memory cell 100E. In FIG 14, the memory cell 100E[k] and 1 shows a cross-sectional view of a memory cell 100E[k+1] adjacent to a memory cell 100E[k]. The memory cell 100E is a modified example of the memory cell 100A. As shown in the figure, the insulator 101 may be omitted, and the conductor 103 and the semiconductor 121 may be in contact with each other. By not providing the insulator 101, the manufacturing process is simplified, and the productivity of the memory device is improved. It is possible.

[0101] FIG. 15 shows a cross-sectional view of a memory cell 100F. In FIG. 15, a memory cell 100F[k] and 1 shows a cross-sectional view of a memory cell 100F[k+1] adjacent to a memory cell 100F[k]. The memory cell 100F is a modified example of the memory cell 100B. As shown in the figure, the formation of the insulator 101 may be omitted, and the conductor 103 and the insulator 122 may be in contact with each other. Also, like the memory cell 100D, the formation of the semiconductor 113 may be omitted. By not providing the body 101 and / or the semiconductor 113, the manufacturing process is simplified, and the memory device This can increase the productivity of the facility.

[0102] FIG. 16A shows a cross-sectional view of the memory cell 100G. Like memory cell 100G, semiconductor 114 is replaced with semiconductor 114a. 16A, the semiconductor 114b may be stacked on the insulator 115. In this example, a semiconductor 114a is provided, and a semiconductor 114b is provided in contact with the semiconductor 114a. In the case where the semiconductor 116 is a multi-layered semiconductor, the number of layers is not limited to two, and may be three or more. In the case where the semiconductor 114 is a stack of oxide semiconductors, the composition and the like are More details will be provided later.

[0103] FIG. 16B shows a cross-sectional view of the memory cell 100H. This is a modification of the memory cell 100A. Unlike the memory cell 100H, the conductor 118 does not need to be provided. In FIG. 16B, an insulator 117 is used instead of the conductor 118. By not providing the conductor 118, the manufacturing process is simplified and the memory device This can increase the productivity of the facility.

[0104] In the memory cell 100H, the region of the structure 130 that intersects with the conductor 102 (overlapping region) In the region, the semiconductor 116, the insulator 115, and the semiconductor 114, and the semiconductor 121, the insulator 1 22 and the conductor 102 function as the transistor WTr. In 0H, the semiconductor 116 in the region where the structure 130 intersects with the conductor 103 (overlapping region) is , the insulator 115, the semiconductor 114, the semiconductor 113, and the conductor 112 form a transistor RT It functions as r.

[0105] FIG. 17A shows a cross-sectional view of the memory cell 100I. This is a modification of memory cell 100. Unlike memory cell 100I, the semiconductor 121 does not need to be provided. By not providing the semiconductor 121, the manufacturing process is simplified and the productivity of the memory device is improved. The memory cell 100I is also a modified example of the memory cell 100B. The transistors WTr and RTr in the memory cell 100I are It has the same configuration as B.

[0106] FIG. 17B shows a cross-sectional view of the memory cell 100J. 00 and also a modification of memory cell 100D. The semiconductor 121 and the semiconductor 113 may not be provided. By not providing the insulating film, the manufacturing process can be simplified and the productivity of the memory device can be improved. In addition, the memory cell 100J is a modified example of the memory cell 100I. The transistors WTr and RTr in the memory cell 100D have the same structure as the memory cell 100D. It has a composition.

[0107] FIG. 18A shows a perspective view of a memory cell 100K. FIG. 18B shows a perspective view of a memory cell 18A is a cross-sectional view showing a part of the memory cell 100K. In order to make the internal structure easier to understand, some of the memory cells 100K are omitted.

[0108] The memory cell 100K is a modification of the memory cell 100G. The body 114 is a stack of semiconductors 114a and 114b. The semiconductor 116 is further formed into a stack of semiconductors 116a, 116b, and 116c. Note that the composition and the like of the semiconductor 116 in the case where the semiconductor 116 is a stack of oxide semiconductors are not particularly limited. More details will be provided later.

[0109] In FIG. 18, a semiconductor 116a is provided in contact with an insulator 117, and a semiconductor A semiconductor 116b is provided, a semiconductor 116c is provided in contact with the semiconductor 116b, and a In this example, the insulator 115 is formed by stacking a plurality of insulators. The insulator 115 may have a layer structure. This will be described in more detail later.

[0110] The memory cell 100K includes a semiconductor 116a, a semiconductor 116b, a semiconductor 116c, an insulator 11 5. A laminated structure of a semiconductor 114a, a semiconductor 114b, a semiconductor 121, and an insulator 122 The region may function like a superlattice. The insulator 122 may have a laminated structure in which a plurality of insulators are combined. The combination of layers will be described in detail later.

[0111] In the memory cell 100K, the conductor 102 is a stack of the conductor 102f and the conductor 102s. In FIG. 18, the conductor 102f is provided in contact with the insulator 122. The conductor 102s is provided in contact with the conductor 102. This will be described in more detail later.

[0112] FIG. 19A shows a perspective view of a memory cell 100L. FIG. 19A is a cross-sectional view showing a part of the memory cell 100L. In order to make the partial structure easier to understand, some of the memory cells 100L are omitted.

[0113] The memory cell 100L is a modified example of the memory cell 100. The following mainly describes the differences between memory cell 100L and memory cell 100. The memory cell 100L has a structure in which the semiconductor 113 and the semiconductor 114 are omitted from the memory cell 100. By not providing the semiconductor 113 and the semiconductor 114, the manufacturing process is simplified and the memory The productivity of the device can be increased.

[0114] In the memory cell 100L, a part of the semiconductor 121 is a channel forming region of the transistor WTr. Therefore, the semiconductor 121 used in the memory cell 100L functions as a 0 or the semiconductor 114b in memory cell 100G. The material should be used.

[0115] FIG. 20A shows a cross-sectional view of the memory cell 100M. FIG. 20B shows a cross-sectional view of the memory cell 100M. 1 shows a cross-sectional view of memory cell 100M and memory cell 100N. Therefore, in the present embodiment and the like, the memory cell 100M and The following mainly describes the differences between memory cell 100A and memory cell 100N.

[0116] Memory cell 100M is memory cell 100A without semiconductor 113 and semiconductor 114. The memory cell 100N has a structure in which the semiconductor 114 is omitted from the memory cell 100A. By not providing the semiconductor 113 and / or the semiconductor 114, the manufacturing process is simplified. This simplifies the process and increases the productivity of the storage device.

[0117] The memory cells 100M and 100N are modified versions of the memory cell 100L. Therefore, in the memory cell 100M and the memory cell 100N, the semiconductor 12 A part of the memory cell 100M functions as a channel forming region of the transistor WTr. Also in the semiconductor 121 used in the memory cell 100N, The semiconductor 114 or the semiconductor 114b in the memory cell 100G is made of the same material. That's good.

[0118] FIG. 21 shows a cross-sectional view of the memory cell 100P. FIG. 22(A) shows the structure shown by the dashed line in FIG. FIG. 22(B) is a cross-sectional view of the portion C1-C2 in FIG. 21, which is shown by a dashed line. 1 is a cross-sectional view of the portion D1-D2 shown in FIG. Therefore, in the present embodiment and the like, the memory cell 100P is The differences from cell 100 will be mainly described.

[0119] The memory cell 100P includes the memory cell 100, the conductor 102, and the conductor 103, etc. Through the center of the memory cell 100, along the direction in which the conductors 102 and 103 extend In the present embodiment and the like, the insulating material 124 is provided in the divided regions. However, the insulator 124 may be provided as necessary.

[0120] Insulator 101, conductor 102, conductor 103, semiconductor 121, insulator 122, and structure Each of the bodies 130 includes an insulator 101a (not shown) and an insulator 101b (not shown), and a conductor. The conductor 102a and the conductor 102b, the conductor 103a and the conductor 103b, the semiconductor 121a and the semiconductor The structure is divided into a conductor 121b, an insulator 122a and an insulator 122b, a structure 130a and a structure 130b. It is allocated.

[0121] The structure 130 includes an insulator 111, a conductor 112, a semiconductor 113, a semiconductor 114, Each of the insulator 115, the semiconductor 116, the insulator 117, and the conductor 118 is an insulator. 111a and insulator 111b, conductor 112a and conductor 112b, semiconductor 113a and semiconductor 113b, semiconductor 114a and semiconductor 114b, insulator 115a and insulator 115b, semiconductor 116a and semiconductor 116b, insulator 117a and insulator 117b, conductor 118a and conductor It is divided into 118b.

[0122] Thus, the structure 130a includes an insulator 111a, a conductor 112a, a semiconductor 113a, and a semiconductor 114a, insulator 115a, semiconductor 116a, insulator 117a, and conductor 118a. The structure 130b includes an insulator 111b, a conductor 112b, a semiconductor 113b, a semiconductor A conductor 114b, an insulator 115b, a semiconductor 116b, an insulator 117b, and a conductor 118 Includes b.

[0123] In addition, the memory cell 100P is divided into a memory cell 100Pa and a memory cell 100Pb. Therefore, the memory cell 100P has an area that functions as the memory cell 100Pa and It can be said that the memory cell 100Pa has an area that functions as a memory cell 100Pb. includes structure 130a, etc., memory cell 100Pb includes structure 130b, etc.

[0124] Thus, the memory cell 100P includes a transistor RTr, a transistor WTr, and a capacitor Each of the elements Cs is a transistor RTrA, a transistor RTrB, and a transistor W It is divided into transistors TrA and WTrB, and capacitance elements CsA and CsB. The transistor RTrA, the transistor WTrA, and the capacitance element CsA form a memory cell 10 0Pa. Transistor RTrB, transistor WTrB, and capacitance element Cs B is included in memory cell 100Pb.

[0125] Conductor 112a, semiconductor 113a, semiconductor 114a, insulator 115a, semiconductor 116a, The region where the insulator 117a and the conductor 118a overlap functions as the transistor RTrA. The conductor 112b, the semiconductor 113b, the semiconductor 114b, the insulator 115b, and the semiconductor 1 The region where 16b, the insulator 117b, and the conductor 118b overlap is the transistor RTrB. The region where the conductor 103a, the insulator 111a, and the conductor 112a overlap each other The conductor 103b, the insulator 111b, and the conductor 1 The area where the conductor 102a and the conductor 112b overlap functions as a capacitance element CsB. a, semiconductor 121a, semiconductor 114a, insulator 115a, semiconductor 116a, insulator 117 The area where the conductor 118a and the conductor 118b overlap functions as the transistor WTrA. body 102b, conductor 112b, semiconductor 121b, semiconductor 114b, insulator 115b, The region where the body 116b, the insulator 117b, and the conductor 118b overlap is the transistor WT Functions as rB.

[0126] By dividing the memory cell 100 into memory cells 100P, the memory density (per unit area) can be increased. Therefore, the semiconductor device including the memory cell 100 can The memory capacity can be increased. Even in this case, the memory cell can be divided in the same manner as in the memory cell 100P.

[0127] Also, the memory cell may be divided along the X direction (see FIG. 23(A)). In the case where the memory cell is divided by the conductor 102, the insulator 124 completely connects the conductor 102 and the conductor 103. Just make sure it doesn't cross at all.

[0128] Also, when viewed from the Z direction, the memory cells are arranged along a diagonal direction (a direction intersecting the X and Y directions). (See FIG. 23(B)). It is also possible to divide the memory cell along a diagonal direction. In other words, it is sufficient that the insulator 124 does not completely cross the conductor 102 and the conductor 103. stomach.

[0129] The number of divisions of the memory cell is not limited to 2. For example, as shown in FIG. In FIG. 24A, the Y-shaped insulator 124 is used as a boundary to form a structure 130. , the semiconductor 121, and the insulator 122 are formed into structures 130a, 130b, 130c, Semiconductor 121a, semiconductor 121b, semiconductor 121c, insulator 122a, insulator 122b, 12 shows a state in which the insulating body 122 is divided into an insulating body 122c.

[0130] As shown in FIG. 24B, the shape of the insulator 124 when viewed from the Z direction is such that the curved portion

[0043]

[0131] Also, as shown in FIG. 25(A), the memory cell may be divided into four. In FIG. 25(A), The structure 130, the semiconductor 121, and the insulator 122 are arranged with the cross-shaped insulator 124 as a boundary. Structure 130a, structure 130b, structure 130c, structure 130d, semiconductor 121a, Conductor 121b, semiconductor 121c, semiconductor 121d, insulator 122a, insulator 122b, insulator 13 shows a state in which the insulating body 122c and the insulating body 122d are separated.

[0132] As shown in FIG. 25B, the insulator 124 is disposed between the conductor 102a and the conductor 102b. Similarly, the insulator 124 may be provided so as not to completely cross the conductors 103a and b. It is sufficient to provide the conductor 103b so as not to completely cross the conductor 103a in the X direction. If there is no element, it may have an element extending in the Y direction.

[0133] Also, as shown in FIG. 11(A) and FIG. 11(B), a plurality of memory cells 100 or When multiple memory strings 200 are provided, the memory cells 100 are arranged as shown in FIG. Alternatively, the shape of the insulator 124 used to divide the memory string 200 may be different from that of the memory cell 100. Alternatively, the memory strings 200 may differ from each other. The division of the zero or memory strings 200 may be done by a common insulator 124 .

[0134] [Memory cell constituent materials] Next, constituent materials that can be used for the memory cell 100 and the like will be described.

[0135] [substrate] The memory cells 100 and the memory strings 200 may be provided on a substrate. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. The plate may be, for example, a glass substrate, a quartz substrate, a sapphire substrate, or a stabilized zirconia substrate ( Yttria-stabilized zirconia substrates, resin substrates, etc. The semiconductor substrate may be made of, for example, silicon or germanium, or silicon carbide or silicon Silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, nitride There are also compound semiconductor substrates made of gallium arsenide (GaN). A semiconductor substrate having an insulating region therein, such as SOI (Silicon On Ins Conductive substrates include graphite substrates, metal substrates, alloy substrates, Conductive resin substrates, etc., or substrates with metal nitrides, substrates with metal oxides, etc. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, and semiconductor A substrate having a conductor or insulator provided thereon, a conductive substrate having a semiconductor or insulator provided thereon, Alternatively, a substrate having elements provided thereon may be used. The elements provided on the plate include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element. etc.

[0136] [Insulator] The insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. , metal oxide nitrides, and metal nitride oxides.

[0137] In this specification, the term "oxynitride" refers to a material that contains more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In the present specification and the like, the term "nitride oxide" refers to a material having a higher nitrogen content than oxygen content. "Aluminum oxide nitride" refers to an aluminum material that contains more nitrogen than oxygen. This indicates the aluminum material.

[0138] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. , leakage current, and other problems may occur. By using igh-k materials, the voltage required for transistor operation can be reduced while maintaining the physical thickness. On the other hand, the insulator that functions as the interlayer film should be made of a material with a low dielectric constant. Therefore, the parasitic capacitance between the wirings can be reduced. It is advisable to select materials accordingly.

[0139] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides containing aluminum, aluminum and hafnium, oxides containing aluminum and hafnium oxide-nitride with silicon and hafnium; oxide-nitride with silicon and hafnium; or nitrides with silicon and hafnium.

[0140] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon Silicon oxide with added hydrogen and nitrogen, silicon oxide with voids, or resin. do.

[0141] In addition, OS transistors have the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator, the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities and oxygen include boron, Carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, gallium Um, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, Alternatively, an insulator containing tantalum may be used in a single layer or a multilayer structure. Aluminum oxide is an insulator that has the function of suppressing the permeation of impurities such as aluminum oxide and oxygen. , magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Metal oxides such as tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide Metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used. can.

[0142] Also, the semiconductor 116, the semiconductor 114, the semiconductor 113, and / or the semiconductor 121 may be provided with an acid. When a nitride semiconductor is used, the insulator that functions as the gate insulator is an oxide that is desorbed by heating. For example, the insulator may be an insulator having a region containing oxygen that is desorbed by heating. The semiconductor 114 and / or the semiconductor By making the semiconductor 114 and / or the semiconductor 116 contact each other, This can compensate for the oxygen deficiency that occurs.

[0143] In addition, an insulating layer formed of the above-mentioned material may be used as an insulator in a single layer. A plurality of insulating layers may be formed in layers.

[0144] For example, when an insulator is provided in contact with a conductor, the insulator is preferably made of a material that prevents oxidation of the conductor. It is preferable to use an insulator having a function of suppressing oxygen permeation. As the material, hafnium oxide, aluminum oxide, silicon nitride, or the like is preferably used. I wish.

[0145] In addition, when an insulator is laminated adjacent to a conductor, the insulator in contact with the conductor is oxygen-free. It is preferable to use an insulator that has a function of suppressing the transmission of hafnium oxide. An insulator is formed in contact with a conductor using silicon oxynitride. An insulator may be formed.

[0146] [conductor] Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Zn, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium nium, zirconium, beryllium, indium, ruthenium, iridium, strontium a metal element selected from the group consisting of lanthanum, lanthanum, etc., or an alloy containing the above-mentioned metal elements; It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride , titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use oxides containing lanthanum and nickel. Tantalum, titanium nitride, titanium and aluminum nitride, tantalum and aluminum nitride Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, oxides containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is preferable because it is a material that maintains its conductivity even if it contains impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, and silicon silicides, such as nickel silicide, are A reside may also be used.

[0147] A single conductive layer made of the above-mentioned material may be used as the conductor. For example, a conductive layer formed of the material containing the metal element described above may be stacked. A laminated structure combining the above-mentioned gold and a conductive material containing oxygen may also be used. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing nitrogen are combined. In addition, the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen A laminated structure in which the above and the above are combined may also be used.

[0148] Note that an oxide semiconductor, which is a type of metal oxide, is used for a channel formation region of a transistor. In this case, the conductor functioning as the gate electrode includes a material containing the above-mentioned metal element, It is preferable to use a laminated structure in which a conductive material containing oxygen is combined. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By providing the conductive material on the channel formation region side, oxygen released from the conductive material is This will make it easier for the supply to be provided to the region.

[0149] In particular, the oxide semiconductor in which the channel is formed is used as a conductor functioning as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the conductive material. A conductive material containing a metal element and nitrogen may be used. For example, titanium nitride, tantalum nitride, etc. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide doped with silicon may also be used. The use of such a material allows the channel to be formed. In some cases, hydrogen contained in the oxide semiconductor formed on the surface of the oxide film can be captured. In some cases, it may be possible to capture hydrogen that is mixed in through insulators, etc.

[0150] [Oxide semiconductor] Semiconductors 116, 114, 113, and / or 121 may include semiconductors It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. It is preferable to use an oxide semiconductor for the memory cell 100. An oxide semiconductor will be described.

[0151] The oxide semiconductor preferably contains at least indium or zinc. In addition to these, aluminum, gallium, and zinc are preferably included. It is preferable that the alloy contains boron, titanium, iron, nickel, etc. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide One selected from among fluorine, tantalum, tungsten, magnesium, cobalt, etc. Or multiple types may be included.

[0152] Here, the oxide semiconductor is an In-M-Zn oxide having indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, and and tin. Other elements applicable to element M include , boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum , cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt However, there are cases where the element M may be a combination of multiple of the above elements. do.

[0153] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to FIG. FIG. 27A shows a structure of an oxide semiconductor, typically IGZO (In, Ga, and Zn) FIG. 1 is a diagram for explaining the classification of crystal structures of metal oxides containing ZnO.

[0154] As shown in FIG. 27A, oxide semiconductors are roughly divided into “amorphous” and “non-morphous” oxide semiconductors. "Crystalline" and "Crystal" In addition, "Amorphous" is classified as completely amo rphous. Also, in "Crystalline", CAAC (c- axis-aligned crystalline), nc(nanocrystal line), and CAC (cloud-aligned composite). The classification of "Crystalline" includes single crystal, Poly crystal and completely amorphous are excluded. In addition, "Crystal" includes single crystal and pol Contains y crystal.

[0155] The structures in the bold frames in Figure 27(A) are classified into "Amorphous" and "C It is an intermediate state between "crystal" and "new cryst" and is considered to be a new boundary region. In other words, this structure belongs to the energetic It is completely different from the unstable "Amorphous" and "Crystal". This can be rephrased as a different structure.

[0156] The crystal structure of the film or substrate was determined by X-ray diffraction (XRD). It can be evaluated using the "Crystalline" spectrum. CAAC-IGZO films classified as Grazing-Incidence The XRD spectrum obtained by the GIXD measurement is shown in FIG. It is also called the thin film method or the Seemann-Bohlin method. The XRD spectrum obtained by the XD measurement is simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in B) is In:Ga:Zn=4:2:3 [atomic ratio] The thickness of the CAAC-IGZO film shown in FIG. 27(B) is 500 nm. do.

[0157] As shown in FIG. 27(B), the XRD spectrum of the CAAC-IGZO film shows clear crystalline Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating In the case of the Cr-Si alloy, a peak indicating the c-axis orientation is detected near 2θ=31°. As shown in the figure, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity was detected. It is.

[0158] The crystal structure of the film or substrate was also analyzed by nano-beam electron diffraction (NBED). Diffraction patterns observed by electron diffraction (microelectron It can be evaluated by the diffraction pattern of CAAC-IGZO film. The pattern is shown in FIG. 27(C). FIG. 27(C) shows the pattern obtained by irradiating the electron beam parallel to the substrate. The diffraction pattern observed by the NBED shown in FIG. The composition of the IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the ultrafine electron beam diffraction method, electron beam diffraction is performed with a probe diameter of 1 nm.

[0159] As shown in FIG. 27(C), the diffraction pattern of the CAAC-IGZO film shows a c-axis orientation. Multiple spots are observed.

[0160] [Structure of oxide semiconductor] Note that oxide semiconductors may be classified differently from those in FIG. 27A in terms of their crystal structures. For example, oxide semiconductors include single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor uctor), and nc-OS (nanocrystalline oxide Se In addition, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors. amorphous oxide semiconductor (a-like OS) xide semiconductor, amorphous oxide semiconductor, etc.

[0161] Next, details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be , and provide an explanation.

[0162] [CAAC-OS] CAAC-OS has multiple crystalline regions, and the multiple crystalline regions have c-axes aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. The normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. A crystalline region is a region in which the atomic arrangement has periodicity. When considered as an arrangement, the crystalline region is also a region with a uniform lattice arrangement. S has a region in which multiple crystal regions are connected in the ab-plane direction, and the region has distortion. The distortion may occur in the lattice arrangement in the area where multiple crystal regions are connected. A place where the lattice orientation changes between a uniform area and a different uniform area. In other words, CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that does not have a

[0163] Each of the multiple crystalline regions is made up of one or more minute crystals (maximum diameter 10n If the crystalline region is made up of a single tiny crystal, The maximum diameter of the crystalline region is less than 10 nm. In addition, the crystalline region is composed of many tiny crystals. In such a case, the size of the crystalline region may be approximately several tens of nm.

[0164] In the In-M-Zn oxide, the CAAC-OS contains indium (In) and A layer containing oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, The (M,Zn) layer and the (M,Zn) layer are stacked on top of each other. Indium and element M can be substituted for each other. Therefore, the (M,Zn) layer The In layer may contain indium. The In layer may contain the element M. The In layer may also contain Zn. The layered structure can be observed, for example, by high-resolution TEM. In the image, it is observed as a lattice image.

[0165] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ shift In the out-of-plane XRD measurement using a slit, the peak indicating the c-axis orientation was = 31° or in the vicinity. Note that the position of the peak indicating the c-axis orientation (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0166] For example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) ) is observed. Note that one spot and another spot are the same as the incident electron beam that has passed through the sample. The spot (also called the direct spot) is the center of symmetry, and the points are observed at positions that are point-symmetric. do.

[0167] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is a hexagonal lattice. The unit cell is not necessarily a regular hexagon, but may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In the OS, clear grain boundaries were confirmed even in the vicinity of the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is dense in the ab-plane direction. The lack of a metal atom and the change in bond distance between atoms due to the substitution of metal atoms, This is believed to be because distortion can be tolerated.

[0168] The crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries act as recombination centers, trapping carriers and forming on-states in transistors. It is highly likely that this will cause a decrease in the on-state current and a decrease in the field effect mobility. CAAC-OS, in which no grain boundaries are observed, has a crystal structure suitable for the semiconductor layer of a transistor. CAAC-OS is one of the crystalline oxides that have Zn. For example, In-Zn oxide and In-Ga-Zn oxide are In oxides. This is preferable since it can suppress the generation of grain boundaries more effectively than oxides.

[0169] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. In addition, the crystallinity of an oxide semiconductor may be reduced due to the inclusion of impurities or the generation of defects. Therefore, CAAC-OS is similar to oxide semiconductors with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor having the CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS have high heat resistance and reliability. -OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process Therefore, using CAAC-OS for OS transistors will expand the flexibility of the manufacturing process. It becomes possible to do so.

[0170] [nc-OS] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). In other words, nc-OS has a periodic atomic arrangement in the region of microscopic The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. In particular, since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. No orientation is observed. Therefore, depending on the analysis method, nc-OS may be considered as a-like In some cases, it may be difficult to distinguish between OS and amorphous oxide semiconductors. For example, for an nc-OS film, When the structure was analyzed using an XRD device, out-of-plain In the XRD measurement, no peaks indicating crystallinity were detected. Electron diffraction using an electron beam with a probe diameter larger than that of nanocrystals (e.g., 50 nm or more) When electron diffraction (also called selected area electron diffraction) is performed, a halo-like diffraction pattern is observed. On the other hand, for the nc-OS film, the size of the nanocrystals was close to or smaller than that of the nanocrystals. Electron diffraction (nanobeam electron diffraction) using an electron beam with a lobe diameter (e.g., 1 nm to 30 nm) When direct beam diffraction is performed, multiple diffraction patterns are generated within a ring-shaped area centered on the direct spot. An electron diffraction pattern may be obtained in which multiple spots are observed.

[0171] [a-like OS] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has a lower crystallinity than the nc-OS and CAAC-OS. e-OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0172] [Oxide semiconductor composition] Next, the details of the above-mentioned CAC-OS will be described. Regarding.

[0173] [CAC-OS] CAC-OS is, for example, a metal oxide made up of elements with a size of 0.5 nm to 10 nm. Preferably, the material is unevenly distributed in a size range of 1 nm to 3 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in a metal oxide. The region having the metal element has a thickness of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A state where the pixels are mixed at or near the size is called a mosaic or patch pattern.

[0174] Furthermore, CAC-OS is a mosaic material that is separated into a first region and a second region. The first region is in a cloud-like shape, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud-like shape). In other words, the CAC-OS is a system in which the first region and the second region are mixed. It is a composite metal oxide having the following structure.

[0175] Here, the In ratio to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of In, Ga, and Zn are expressed as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is In this region, [In] is larger than [In] in the composition of the CAC-OS film. The second region is where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has a higher [In] than the second region. The first region is larger than the second region, and [Ga] is smaller than [Ga] in the first region. In the second region, [Ga] is larger than [Ga] in the first region, and [In ] is a region smaller than [In] in the first region.

[0176] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region in which gallium oxide, gallium zinc oxide, etc. In other words, the first region is called the region in which In is the main component. The second region can be rephrased as a region containing Ga as the main component. This can be done.

[0177] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0178] For example, in the case of CAC-OS made of In-Ga-Zn oxide, energy dispersive X-ray spectroscopy Law(EDX:Energy Dispersive X-ray spectrosco The EDX mapping obtained using the py method identified the region containing In as the main component (the first region ) and a region (second region) mainly composed of Ga are unevenly distributed and mixed. It can be confirmed that:

[0179] When the CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are The insulating properties caused by the above function complementarily to provide a switching function (On / Off). In other words, CAC-OS is A part of the material has a conductive function and a part of the material has an insulating function, and the whole material has The function of the conductive material is that of a semiconductor. Therefore, the use of CAC-OS in transistors is This results in a high on-state current (I on ), high field-effect mobility (μ), and good switching It is possible to realize a locking operation.

[0180] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and CA Two or more of C-OS, nc-OS, and CAAC-OS may be included.

[0181] [Transistor Having Oxide Semiconductor] Next, the case where the oxide semiconductor is used for a transistor will be described.

[0182] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

[0183] An oxide semiconductor with a low carrier concentration can be used for the channel formation region of a transistor. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 18 c m -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than , 1×10 16 cm -3 More preferably, it is less than 1×1013 cm -3 Less than More preferably, 1×10 12 cm -3 It is even more preferable that the amount is less than 1000 μm. In addition, when the carrier concentration of the oxide semiconductor film is reduced, impurities in the oxide semiconductor film In this specification, the impurity concentration is low, and the defect level density is low. A material with a low density of defect states is called high purity intrinsic or substantially high purity intrinsic. The oxide semiconductor having a low concentration of arsenic is treated as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. In addition, high purity authenticity or substantially high purity authenticity is sometimes called Type I or Actual. In terms of quality, it is sometimes called type I.

[0184] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap state density may be low.

[0185] In addition, it takes a long time for the charges trapped in the trap states of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There are cases.

[0186] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the adjacent film. These include potassium metal, alkaline earth metals, iron, nickel, silicon, etc.

[0187] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0188] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, it becomes an oxide. Defect levels are formed in the semiconductor. The concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon near the interface with the channel formation region of the oxide semiconductor and carbon concentration (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by s Spectrometry) is calculated as 2×10 18 atoms / c m 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0189] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals may form carriers. A transistor using an oxide semiconductor containing such a metal oxide tends to be normally on. Therefore, the alkali metal or is the concentration of alkaline earth metals, 1×10 18 atoms / cm 3 Below, preferably 2 x 1 0 16 atoms / cm 3 To the following:

[0190] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The concentration increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. However, when nitrogen is contained, trap states may be formed. The electrical characteristics may become unstable. The nitrogen concentration in the channel formation region is set to 5×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below Lower, and more preferably 5×10 17 atoms / cm 3 To the following:

[0191] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom to form a carbide. Therefore, it is necessary to use an oxide semiconductor that contains hydrogen. Therefore, the transistor with the oxide semiconductor channel is likely to be normally on. It is preferable that the amount of hydrogen in the formation region is reduced as much as possible. The hydrogen concentration obtained by SIMS in the channel formation region of the nitride semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 Less than, better Preferably 1×10 19 atoms / cm 3 less than 5×10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3Make it less than.

[0192] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor Thus, stable electrical characteristics can be imparted.

[0193] [Other semiconductor materials] It can be used for semiconductor 116, semiconductor 114, semiconductor 113, and semiconductor 121. The semiconductor material is not limited to the oxide semiconductors described above. 113, and semiconductor materials having a band gap (zero gap Semiconductor materials that are not semiconductors may also be used. For example, semiconductors of elemental elements such as silicon , compound semiconductors such as gallium arsenide, layered materials that function as semiconductors (atomic layer materials, secondary (Also called the base material, etc.) may be used as a semiconductor material. In particular, Layered materials are preferably used as semiconductor materials.

[0194] In this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The crystal structure of is formed by layers of covalent and ionic bonds, which are bound by van der Waals forces. It is a structure in which layers are formed through bonds weaker than covalent or ionic bonds, such as those mentioned above. The quality is that the electrical conductivity within the unit layer is high, that is, the two-dimensional electrical conductivity is high. By using a material with high two-dimensional electrical conductivity in the channel formation region, It is possible to provide a transistor with a large on-current.

[0195] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are Chalcogen is a general term for elements in group 16. They include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. The cogenides include transition metal chalcogenides and group 13 chalcogenides.

[0196] As a semiconductor material used in the semiconductor device according to one embodiment of the present invention, for example, Specifically, molybdenum sulfide (representatively, MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (represented by WS2), tungsten selenide (represented by Tungsten telluride (representatively WSe2), hafnium sulfide (representatively WTe2), Typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (Typically ZrS2), zirconium selenide (Typically ZrSe2), etc. can be.

[0197] [Film formation method] Conductors, insulators, and semiconductors are formed by sputtering, CVD, and molecular beam epitaxy ( MBE:Molecular Beam Epitaxy, Pulsed Laser Deposition (PL Pulsed Laser Deposition (D) or Atomic Layer Deposition (ALD) This can be done using a method such as atomic layer deposition.

[0198] The CVD method is a method that uses plasma, called plasma enhanced CVD (PECVD). enhanced CVD method, and thermal CVD (TCVD: Thermal CVD) method D) method, photo CVD method, etc. Depending on the source gas, metal CVD (MCVD) method, metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0199] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device etc. may become charged up by receiving an electric charge from the plasma. Accumulated electric charges can destroy wiring, electrodes, elements, etc., contained in semiconductor devices. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage does not occur. Therefore, the yield of the semiconductor device can be increased. Since no plasma damage occurs during deposition, a film with few defects can be obtained.

[0200] In addition, the ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0201] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less susceptible to the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of films with high aspect ratios. However, the ALD method has a relatively low deposition rate. Because the deposition rate is slow, it can be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases this is preferable.

[0202] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, the film formed can be By changing the flow rate ratio of the source gas while maintaining the temperature, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to deposition by a vacuum, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0203] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first thin film. A thin layer is formed, and then reacts with a second source gas introduced later, and the second thin layer is formed on the first thin layer. The gas introduction sequence is controlled until the desired thickness is reached. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness of the thin film is The thickness can be precisely adjusted by changing the number of times the gas introduction sequence is repeated. This makes it suitable for fabricating miniaturized FETs.

[0204] Thermal CVD methods such as MOCVD and ALD are used to produce a variety of films, including metal films, semiconductor films, and inorganic insulating films. For example, when forming an In-Ga-Zn-O film, Methylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and and dimethyl zinc (Zn(CH3)2). Not specified, triethylgallium (Ga(C2H5)3) is used instead of trimethylgallium. Dimethyl zinc can be replaced by diethyl zinc (Zn(C2H5)2). It is also possible.

[0205] For example, when forming a hafnium oxide film using a deposition system that uses ALD, the solvent and Liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethylamine, etc.) Midhafnium (TDMAH, hafnium amide such as Hf[N(CH3)2]4) Two types of gases are used: vaporized raw gas and ozone (O3) as an oxidizing agent. Examples of materials include tetrakis(ethylmethylamido)hafnium.

[0206] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, a solvent and a liquid containing an aluminum precursor compound (trimethylaluminum (TMA, Al(CH 3) Two types of gases are used: the raw gas vaporized from 3) etc., and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedioate) Nath, etc.

[0207] For example, when forming a silicon oxide film using a deposition system that uses ALD, The silane is adsorbed on the surface to be coated and the radicals of oxidizing gases (O2, nitrous oxide) are provided. is fed to react with the adsorbate.

[0208] For example, when forming a tungsten film using a deposition system that uses ALD, WF6 gas is used. The initial tungsten film is formed by repeatedly introducing B2H6 gas and WF6 The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. Alternatively, SiH4 gas may be used.

[0209] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are repeatedly introduced to form a GaO Then, Zn(CH3)2 gas and O3 gas are repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. By using this method, mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O layers are formed. Alternatively, H obtained by bubbling water with an inert gas such as Ar instead of O3 gas may be used. Although 2O gas may be used, it is preferable to use O3 gas that does not contain H. Instead of the gas, In(C2H5)3 may be used. Ga(C2H5)3 gas may be used instead of Zn(CH3)2 gas. Instead of gas, Zn(C2H5)2 gas may be used.

[0210] <Example of how to make a memory device> Next, an example of a method for manufacturing the memory cell 100 will be described.

[0211] First, a laminate 140 shown in FIG. 28(A) is fabricated. The laminate 140 is made of an insulator 101. The insulator 101[i] includes a sacrificial layer 141 and a conductor 103. The insulator 101[i] is a substrate (not shown). ), the sacrificial layer 141 is disposed on the insulator 101[i], and the insulator 101 [i+1] is disposed on the sacrificial layer 141, and the conductor 103 is disposed on the insulator 101[i+1]. and insulator 101[i+2] is disposed on conductor 103.

[0212] Various materials can be used for the sacrificial layer 141. For example, silicon nitride, oxide, Alternatively, an insulator such as silicon oxide or aluminum oxide may be used. Semiconductors such as aluminum, copper, titanium, tantalum, etc. may also be used. Alternatively, conductors such as tinsten and tantalum may be used. Alternatively, acrylic resin, polyimide Alternatively, organic materials such as phenolic resin and epoxy resin may be used. Therefore, the sacrificial layer 141 is to be removed by etching. It is only necessary to use a material that has a selectivity with respect to the material to be used.

[0213] The insulator 101 is a material with a reduced concentration of impurities such as water or hydrogen. For example, the amount of hydrogen molecules desorbed from the insulator 101 per unit area is preferably Thermal Desorption Spectroscopy (TDS) )) in the range of 50°C to 500°C, 2×10 15 molecu les / cm 2 Less than or equal to 1×10 15 molecules / cm 2 The following is better Preferably 5 x 10 14 molecules / cm 2 The insulator 10 may be The insulator 101 may be an insulator that releases oxygen when heated. The materials that can be used are not limited to those described above.

[0214] The insulator 101 may have a laminated structure of a plurality of insulators. The insulating layer 101 may be a laminate of hafnium oxide and silicon oxynitride. Among the insulators, the insulator in contact with the conductor 103 has the function of suppressing the permeation of oxygen as described above. It is preferable to use an insulating material that has a good resistance to heat.

[0215] Next, a resist mask was formed on the laminate 140, and the resist mask was used as a mask. The insulator 101, the conductor 103, and a portion of the sacrificial layer 141 are removed by an etching process. 28B, the opening 131 is formed in the laminate 140.

[0216] The resist mask is formed by, for example, a lithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by the inkjet method, a photomask Since no etching is used, manufacturing costs may be reduced. The etching method may be a dry etching method or a wet etching method, or both may be used. The etching method is suitable for microfabrication.

[0217] In addition, the formation of a resist mask by the lithography method is carried out by first forming a resist, then The resist is exposed through a photomask. The exposed areas are then developed using a developer. The resist mask is formed by removing or leaving the layer.

[0218] By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. are used to A resist mask can be formed by exposing the photoresist to light. A liquid immersion technique may be used in which the substrate is filled with liquid (e.g., water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the photomask is not necessary. The dry etching process is performed, the wet etching process is performed, and the dry etching process is performed. Then, wet etching is performed, or wet etching is performed followed by dry etching. This can be removed by performing filtering.

[0219] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that is to be a hard mask material is formed on a conductive film. A resist mask is then formed on the hard mask, and the hard mask material is etched to obtain a desired shape. A hard mask having a shape similar to that of the first embodiment can be formed.

[0220] Dry etching equipment for performing etching by the dry etching method includes: For example, a capacitively coupled plasma (CCP) with parallel plate electrodes A parallel plate type (Parallel Coupled Plasma) etching device can be used. The capacitively coupled plasma etching apparatus has parallel plate electrodes, one of which is connected to a high frequency Alternatively, a plurality of different high-frequency power sources may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a configuration in which a high-frequency voltage with a different frequency is applied to each of the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high density plasma source may be used. A dry etching apparatus having a high-density plasma source can be used, for example, inductively coupled Inductively Coupled Plasma (ICP) etching A chipping device or the like can be used.

[0221] Next, the insulator 111 is formed along the side surface of the opening 131 (see FIG. 29(A)). The sides of the insulator 101, the conductor 103, and the sacrificial layer 141 exposed in the cavity 31 are It is covered with an insulator 111 .

[0222] The insulator 111 may have a laminated structure of a plurality of insulators. Among the multiple insulators, the insulator in contact with the conductor 103 and / or the conductor 112 is It is preferable to use an insulator that has a function of suppressing the permeation of oxygen. For example, 111 may be a stack of hafnium oxide and silicon oxynitride. The 111 may have a three-layer structure with hafnium oxide sandwiched between two layers of silicon oxynitride. For example, the insulator 111 may have a three-layer structure in which silicon oxynitride is sandwiched between two layers of hafnium oxide. It may also be constructed as such.

[0223] Next, the conductor 112 is formed along the surface of the insulator 111 (see FIG. 29(B)). The body 112 is processed in a later step to form the transistor WTr and / or the transistor RTr. and serves as the gate of transistor RTr. It functions as one electrode of the capacitance element Cs.

[0224] The conductor 112 is preferably made of a material having a high electrical conductivity. For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, tungsten Nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum In one embodiment of the present invention, a nitride containing tantalum is preferably used. Nitrides are particularly preferred. For example, ruthenium oxide, ruthenium nitride, strontium Alternatively, an oxide containing ruthenium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are conductive materials that are resistant to oxidation or that maintain their conductivity even when they absorb oxygen. This is preferable because it is a

[0225] In particular, when an oxide semiconductor is used as a semiconductor, the conductor 112 can be, for example, It is preferable to use a conductive material that has a function of suppressing the permeation of impurities such as water or hydrogen. In this case, the conductor 112 may be tantalum, tantalum nitride, titanium, or titanium nitride. It is preferable to use ruthenium or ruthenium oxide.

[0226] For example, when the conductor 112 is a laminate of multiple layers, water or hydrogen is added to the insulator 111 side. A conductive material that has the function of suppressing the permeation of impurities is used to oxidize the semiconductor 113 side. A highly conductive material or a material that maintains its conductivity even when it absorbs oxygen may be used.

[0227] Next, the semiconductor 113 is formed along the surface of the conductor 112 (see FIG. 30(A)). In the embodiment, the semiconductor 113 has an atomic ratio of In:Ga:Zn=1:3:4 or The composition of the oxide semiconductor is a desired atomic ratio. Includes a range of ±30%.

[0228] The semiconductor material used for the semiconductor 113 is, for example, In:Ga:Zn=1:3:4. , In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1, and Alternatively, a metal oxide having a composition in the vicinity of the above may be used.

[0229] Next, the semiconductor 114 is formed along the surface of the semiconductor 113 (see FIG. 30(B)). In the embodiment, the semiconductor 114 is In:Ga:Zn=4:2:3 [atomic ratio] or In the present embodiment, an oxide semiconductor having a composition in the vicinity of

[0230] The semiconductor material used for the semiconductor 114 is, for example, In:Ga:Zn=4:2:3. 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:G The compositions are In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, and their vicinity. A metal oxide having a similar composition may be used. The compositions of In:Zn=5:1 and In:Zn=10:1 and their neighboring compositions are Alternatively, the semiconductor 114 may be made of indium oxide. good.

[0231] The semiconductor material used for the semiconductor 121 to be formed later is, for example, In:Ga:Zn =1:3:4, In:Ga:Zn=1:3:2, or In:Ga:Zn=1:1:1 Metal oxides having compositions similar to or close to the above composition may also be used.

[0232] When an oxide semiconductor is used for the semiconductor 121 and the semiconductor 114, The bodies 114 preferably contain a common metal element. Furthermore, the bodies 114 may contain multiple common metal elements. In addition, it is preferable that the semiconductor 121 and the semiconductor 114 have a common plurality of metal elements. The semiconductor 121 and the semiconductor 114 each contain a plurality of metal elements, and the atomic ratio of the plurality of metal elements is It is preferable that they are different.

[0233] For example, the semiconductor 121 and the semiconductor 114 are In When M-Zn oxide is used, the atomic ratio of element M among the metal elements contained in semiconductor 121 is is preferably greater than the atomic ratio of element M in the metal elements contained in the semiconductor 114. In addition, the atomic ratio of element M to In in the semiconductor 121 is It is preferable that the atomic ratio of element M to In is larger than that of element In. The atomic ratio of In to element M in the semiconductor 121 is A ratio larger than this is preferred.

[0234] In addition, the energy of the conduction band minimum of the semiconductor 121 is smaller than the energy of the conduction band minimum of the semiconductor 114. In other words, it is preferable that the electron affinity of the semiconductor 121 is higher than that of the semiconductor 121. It is preferable that the electron affinity is smaller than that of the conductor 114 .

[0235] Here, at the junction between the semiconductor 121 and the semiconductor 114, the energy level at the bottom of the conduction band is In other words, the potential at the junction of the semiconductor 121 and the semiconductor 114 changes gradually. The energy level of the conduction band edge changes continuously or can be said to be a continuous junction. In order to achieve this, a layer is formed at the interface between the semiconductor 121 and the semiconductor 114. It is advantageous to reduce the defect level density in the mixed layer.

[0236] Specifically, the semiconductor 121 and the semiconductor 114 have a common element other than oxygen (main component and By this, a mixed layer having a low defect level density can be formed. In the case of Ga-Zn oxide, the semiconductor 121 is In-Ga-Zn oxide, Ga-Zn oxide It is preferable to use gallium oxide or gallium carbide.

[0237] At this time, the main path of the carriers is the semiconductor 114. This can reduce the defect state density at the interface between the semiconductor 121 and the semiconductor 114. Therefore, the effect of interface scattering on carrier conduction is reduced, and the transistor W Tr can obtain a high on-current.

[0238] In addition, by including the semiconductor 121, the diffusion of impurities from the semiconductor 121 side to the semiconductor 114 is prevented. The thickness of the semiconductor 121 is set to 1 nm or more and 10 nm or less, or 1 nm or more and 5 It should be less than nm.

[0239] Also, as in the memory cell 100G shown in FIG. 16(A), the semiconductor 114 is replaced with a semiconductor 114a. In the case of laminating the semiconductor 114b, the semiconductor 114b has the same configuration as the semiconductor 114. The semiconductor 114 a may have a structure similar to that of the semiconductor 121 .

[0240] For example, the semiconductor 114a may have an atomic ratio of In:Ga:Zn=1:3:4 or approximately Alternatively, an oxide semiconductor having a similar composition may be used. For example, the semiconductor 114 may have a thickness of 1 nm or less, or 1 nm to 5 nm. b is an oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close to that As described above, the semiconductor 114b may be an In:Ga:Zn=5 An oxide semiconductor having an atomic ratio of 1:1:3 or a composition close to that ratio may be used. The thickness of the body 114b is 5 nm or more and 20 nm or less, or 5 nm or more and 15 nm or less. Good.

[0241] In this way, the junction between the semiconductor 121 and the semiconductor 114b and the semiconductor 114 At the junction between the semiconductor 114a and the semiconductor 114b, the energy level at the bottom of the conduction band changes gradually. In addition, the interface between the semiconductor 121 and the semiconductor 114b, and the interface between the semiconductor 114b and the semiconductor 11 At the interface 4a, a mixed layer having a low density of defect states can be formed at each interface.

[0242] By providing the semiconductor 121 and the semiconductor 114a with the semiconductor 114b in between, the light is scattered by the interface. This reduces the effect on carrier conduction, thereby enabling the on-state current of the transistor to be increased.

[0243] In addition, by including the semiconductor 114a, impurities from the semiconductor 114a to the semiconductor 114b The spread of can be suppressed.

[0244] In addition, during the manufacturing process of the memory cell, the surface of the semiconductor 114 is exposed and then heated. The heat treatment is preferably performed at a temperature of, for example, 100° C. or higher and 600° C. or lower. The heat treatment may be performed at a temperature of 350°C to 550°C. Active gas atmosphere or oxidizing gas of 10ppm or more, 1% or more, or 10% or more For example, the heat treatment is preferably performed in an oxygen atmosphere. Supplying oxygen to the semiconductor 114 to eliminate oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure or in an atmosphere of nitrogen gas or an inert gas. After heat treatment in the atmosphere, oxidizing gas is added at 10 ppm or more to compensate for the oxygen that is removed. The treatment may be carried out in an atmosphere containing 1% or more, or 10% or more of oxidizing gas. After heat treatment in an atmosphere containing more than m, 1% or more, or 10% or more, nitrogen gas is continuously Alternatively, the heat treatment may be performed in an inert gas atmosphere.

[0245] Note that a process for supplying oxygen to the semiconductor 114 (also referred to as an “oxygen supplying process”) is performed. In other words, oxygen vacancies in the semiconductor 114 are repaired by the supplied oxygen. O + O→null reaction can be promoted. The hydrogen reacts with the oxygen supplied, and the hydrogen is removed as H2O (dehydration). As a result, hydrogen remaining in the semiconductor 114 recombines with the oxygen vacancies. V O The formation of H can be suppressed.

[0246] In addition, by performing microwave treatment in an oxygen-containing atmosphere, oxygen-addition treatment can be performed. In this case, the semiconductor 114 is exposed to microwaves, high frequency waves such as RF, oxygen plasma, oxygen laser, etc. The microwave treatment is, for example, a high-density plasma using microwaves. It is preferable to use a microwave processing device having a power source that generates microwaves. The microwave processing device may have a power source that applies RF to the substrate side. This allows high-density oxygen radicals to be generated. By applying F, oxygen ions generated by high-density plasma can be efficiently removed by aperture 1. The microwave treatment can be preferably carried out under reduced pressure. The pressure is 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, More preferably, the pressure is set to 400 Pa or more. In addition, the oxygen flow ratio O2 / (O2+Ar) The treatment temperature is 750 The heating may be performed at a temperature of 500° C. or less, preferably 500° C. or less, for example, about 400° C. After the treatment, a heat treatment may be carried out successively without exposure to the outside air.

[0247] The V contained in the semiconductor 114 is O H is split off, hydrogen H can be removed from the semiconductor 114. That is, in the semiconductor 114, "V O H →H+V O)" and "V O +O→null" reaction occurs, and the water in semiconductor 114 Therefore, the oxygen vacancies in the semiconductor 114 and the V O Low H This can reduce the carrier concentration.

[0248] Next, an insulator 115 is formed along the surface of the semiconductor 114 (see FIG. 31(A)). When an oxide semiconductor is used for the body 114, the insulator 115 may be, for example, silicon oxide. Silicon oxynitride or the like may be used as appropriate. By this, oxygen vacancies in the semiconductor 114 can be reduced, and the reliability of the transistor can be improved. do.

[0249] Specifically, the insulator 115 is an oxide material from which a portion of oxygen is released by heating, in other words, In this case, it is preferable to use an insulating material having an excess oxygen region. The oxides that are considered to be oxides are those that have a desorption rate of oxygen molecules of 1.0 x 10 18 Molecule es / cm 3 More than 1.0×10 19 molecules / cm 3 That's all. Preferably 2.0 x 10 19 molecules / cm 3 or more than 3.0×10 2 0 molecules / cm 3 The oxide film is as above. The surface temperature of the film is 100°C to 700°C or 100°C to 400°C. The thickness of the insulator 115 is preferably in the range of 3 nm to 15 nm, or more than 3 nm. It would be better to make it 10nm or less.

[0250] After the insulator 115 is formed, the above-mentioned oxygen-adding treatment may be performed.

[0251] When an oxide semiconductor is used for the semiconductor 116 and the semiconductor 114, the insulator 115 is heated. It is preferable that the insulator 115 has a region containing oxygen that is more easily released. For example, the semiconductor 116 and the semiconductor 114 may have a laminated structure of multiple insulators. In the case of using an oxide semiconductor, the insulator 115 is formed of silicon oxide or silicon oxynitride. , hafnium oxide or aluminum oxide, and silicon oxide or silicon oxynitride It may also be a layered structure, i.e., two layers of silicon oxide or silicon oxynitride and one layer of oxide. Alternatively, the insulator 115 may have a structure in which hafnium oxide or aluminum oxide is sandwiched. It may be a laminated structure of four layers, or a laminated structure of four or more layers.

[0252] Next, the semiconductor 116 is formed along the surface of the insulator 115 (see FIG. 31(B)). In the present embodiment, the semiconductor 116 has an atomic ratio of In:Ga:Zn=4:2:3 or In the present embodiment, an oxide semiconductor having a composition in the vicinity of

[0253] The semiconductor material used for the semiconductor 116 is, for example, In:Ga:Zn=4:2:3. 4.1, In:Ga:Zn=1:1:1, In:Ga:Zn=5:1:6, In:G The compositions are In:Ga:Zn=5:1:3, In:Ga:Zn=10:1:3, and their vicinity. A metal oxide having a similar composition may be used. The compositions of In:Zn=5:1 and In:Zn=10:1 and their neighboring compositions are Alternatively, the semiconductor 116 may be made of indium oxide. good.

[0254] In the case where an oxide semiconductor is used as the semiconductor 116, oxygen addition treatment is performed after the formation of the semiconductor 116. may be carried out.

[0255] When a Si transistor is used as the transistor RTr, the semiconductor 116 is Silicon may be formed.

[0256] As in the memory cell 100K shown in FIG. 18, the semiconductor 116 is a semiconductor 116a, and the semiconductor 1 In the case of stacking the semiconductor 116a and the semiconductor 116b, the semiconductor 116c is stacked. The semiconductor 116c has a similar structure to the semiconductor 114a, and the semiconductor 116b has a similar structure to the semiconductor 114b. Just do that.

[0257] Next, an insulator 117 is formed along the surface of the semiconductor 116 (see FIG. 32(A)). The insulator 117 may be formed of the same material and by the same method as the insulator 115. Formation of the insulator 117 A subsequent oxygen addition treatment may be carried out.

[0258] The insulator 117 may have a stacked structure of a plurality of insulators. When the semiconductor 116 is used, the insulator 117 is made up of a plurality of insulators. It is preferable to use an insulator having a region containing oxygen that is released by heating. In addition, the insulator in contact with the conductor 118 has the function of suppressing the permeation of oxygen as described above. For example, among the multiple insulators constituting the insulator 117, a semiconductor Silicon oxide or silicon oxynitride may be used as the insulator in contact with 116. Among the multiple insulators constituting the insulator 117, the insulator in contact with the conductor 118 is Hafnium oxide or aluminum oxide may also be used.

[0259] For example, the insulator 117 may be made of silicon oxide or silicon oxynitride and aluminum oxide. Alternatively, the insulator 117 may be a laminate of silicon and silicon nitride. In this case, it is preferable to use silicon nitride, which has a low hydrogen content.

[0260] Next, after the insulator 117 is formed, the conductor 118 is formed (see FIG. 32(B)). In this embodiment, tungsten is used as the conductor 118. Note that the conductor 118 is a multi-conductor. Of the multiple conductors constituting the conductor 118, the insulator 11 may have a laminated structure. It is preferable to use a conductive material that is difficult to oxidize for the conductor in contact with 7. Titanium nitride may be used as the conductor in contact with the insulator 117 of the body 118. For example, Alternatively, the conductor 118 may be a laminate of titanium nitride and tungsten.

[0261] Insulator 111, conductor 112, semiconductor 113, semiconductor 114 (semiconductor 114a, semiconductor 1 14b), insulator 115, semiconductor 116 (semiconductor 116a, semiconductor 116b, semiconductor 11 6c), the insulator 117, and the conductor 118 are formed by a CVD method (MOCVD method, etc.) This can be done continuously using the ALD method or the like.

[0262] In this manner, the structure 130a is formed in the opening 131. Next, the structure 130a is A portion of the laminate 140 is removed in an area that does not overlap with the body 130a to form a region 132 ( (See FIG. 33(A)). Region 132 can be formed in a manner similar to that for opening 131.

[0263] Next, the sacrificial layer 141 is removed (see FIG. 33(B)). The sacrificial layer 141 is removed by dry etching. Either etching or wet etching may be used, or both may be used.

[0264] Next, the insulator 111, the conductor 112, and the semiconductor that overlap the area where the sacrificial layer 141 was removed are removed. The conductor 113 is removed to expose a part of the semiconductor 114 (see FIG. 34(A)). The removal of 11, the conductor 112, and the semiconductor 113 can be performed by either dry etching or wet etching. The etching method may be used or both may be used. Also, depending on the material to be removed, the etching method may be selected. The etching method and etching conditions may be changed. The removal of the semiconductor 112 and the semiconductor 113 may be performed consecutively. The steps from the step of forming the semiconductor 113 to the step of removing the semiconductor 113 may be performed in succession. will be done.

[0265] After this, oxygen addition treatment may be performed. For example, microwave treatment may be performed in an atmosphere containing 10% oxygen. At this time, the oxygen 10 is supplied from the region 132, but as shown in FIG. Oxygen 10 may be supplied via a terminal outlet shown in FIG. 34(B). 1 is a perspective view of a laminate 140 in the vicinity of a terminal extraction portion. FIG.

[0266] Next, the insulator 101, the conductor 103, the insulator 111, and the conductor 102 exposed by the formation of the region 132 are A semiconductor 121 is formed along the surfaces of the dielectric 112, the semiconductor 113, and the semiconductor 114. (See FIG. 35(A)). After the semiconductor 121 is formed, oxygen addition treatment may be performed.

[0267] Next, an insulator 122 is formed along the surface of the semiconductor 121 (see FIG. 35(A)). After the formation of the insulator 122, an oxygen-adding treatment may be performed. The insulating layer 11 may be formed of any of the materials described above.

[0268] The insulator 122 may have a stacked structure of a plurality of insulators. When a conductor is used, the insulator 122 is made up of a plurality of insulators that are in contact with the semiconductor 121. The insulator to be used may be an insulator having a region containing oxygen that is desorbed by heating. It is preferable that the insulator in contact with the conductor 102 has the function of suppressing the permeation of oxygen as described above. For example, the insulator 122 may be made of a plurality of insulators. Among them, silicon oxide or silicon oxynitride is used as an insulator in contact with the semiconductor 121. In addition, among the multiple insulators constituting the insulator 122, the insulator in contact with the conductor 102 may be Hafnium oxide may be used as the insulator.

[0269] For example, the insulator 122 may be made of silicon oxide or silicon oxynitride and aluminum oxide. Alternatively, the insulator 122 may be a laminate of silicon and silicon nitride. In this case, it is preferable to use silicon nitride, which has a low hydrogen content.

[0270] Next, the conductor 102 is formed along the surface of the insulator 122 (see FIG. 35(B)). Although the conductor 102 is shown as a single layer in this embodiment, it may be a laminate of multiple layers.

[0271] For example, in the memory cell 100K shown in FIG. 18, the conductor 102 is replaced with a conductor 102f. When the conductor 102s is laminated, the conductor 102f in contact with the insulator 122 is less likely to oxidize. For example, titanium nitride is used for the conductor 102f. The conductive material 102s may be made of tungsten.

[0272] Next, a part of the conductor 102 is removed to expose a part of the insulator 122 (see FIG. 36(A)). see).

[0273] Next, an insulator 123 is formed along a part of the exposed insulator 122 and the surface of the conductor 102. As the insulator 123, for example, impurities such as water and hydrogen are used. It is preferable to use an insulating material having a function of suppressing the transmission of the light. For example, the insulator 12 For 3, aluminum oxide or the like may be used.

[0274] The insulator 123 may have a laminated structure of a plurality of insulators. The insulating layer 123 may be a laminate of hafnium oxide and silicon oxynitride. Among the insulators, the insulator in contact with the conductor 102 has the function of suppressing the permeation of oxygen as described above. It is preferable to use an insulating material that has a good resistance to heat.

[0275] In this manner, the memory cell 100 can be fabricated.

[0276] In addition, like the memory cell 100P shown in FIG. 21 and FIG. 22, the memory cell 100 If the memory cell 100 is to be divided into several parts, a slit is then formed to divide the memory cell 100 into several parts. After the slit is formed, an insulator 124 is provided in the slit. The insulator 124 may be formed using a material similar to that of the insulator 123.

[0277] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0278] (Embodiment 2) In this embodiment, a circuit configuration example of a semiconductor device 300 including a plurality of memory strings 200 is shown. An example of the operation method will be described with reference to the drawings.

[0279] <Circuit configuration example> The circuit configuration of the semiconductor device 300 will be described with reference to FIG. The memory strings 200 are m in number. In the present embodiment, the first memory string The m-th memory string 200 is denoted as memory string 200[1], and the m-th memory string 200 is denoted as memory string 200[2]. The jth memory string is denoted as 200[m] (m is an integer equal to or greater than 1). The ring 200 is denoted as a memory string 200[j] (j is an integer between 1 and m).

[0280] Also, the memory string 200 has n memory cells 100. In FIG. The cell 100 shown in FIG. 4A has a memory cell 100 having a circuit configuration as shown in FIG. (B), memory cell 10 having the circuit configuration shown in FIG. 4(C), FIG. 5(A), and FIG. 5(B) In the present embodiment, the j-th memory string 200 includes The k-th memory cell 100 included in the array is denoted as memory cell 100[k,j].

[0281] The semiconductor device 300 shown in FIG. 37 includes n wirings WWL, n wirings RWL, and m wirings W BL, m wirings RBL, and m wirings BGL. The wire WWL and wire RWL of the th wire are respectively defined as wire WWL[k] and wire RWL[ k]. The j-th wiring WBL, wiring RBL, and wiring BGL are respectively These are denoted as wiring WBL[j], wiring RBL[j], and wiring BGL[j].

[0282] The wiring WWL[1] is connected to the memory cells 100[1,1] to 100[1,m]. The gates (conductors 102) of the transistors WTr included in each of the first and second electrodes are electrically connected. The wiring WWL[k] is a wiring for the memory cells 100[k,1] to 100[k,m]. The gates (conductors 102) of the transistors WTr included in each of the first and second electrodes are electrically connected. The wiring WWL[n] is connected to the memory cells 100[n,1] to 100[n,m]. The gates (conductors 102) of the transistors WTr included in each of the first and second electrodes are electrically connected.

[0283] The wiring RWL[1] is connected to the memory cells 100[1,1] to 100[1,m]. The wiring RWL[k] is electrically connected to the capacitance element Cs included in each of the memory cells. A capacitance element Cs included in each of memory cells 100[k,1] to 100[k,m] The wiring RWL[n] is electrically connected to the memory cells 100[n,1] to 100[n,2]. 100[n,m] are electrically connected to the capacitance element Cs included in each of the wiring RWL is connected to the gate (conductor 112) of the transistor RTr via a capacitance element Cs.

[0284] The wiring WBL[1] is a source of the transistor WTr included in the memory cell 100[1,1]. The wiring WBL[j] is electrically connected to either the source or drain (conductor 112). One of the source or drain of the transistor WTr included in the memory cell 100[1,j] The wiring WBL[m] is electrically connected to the memory cell 100[1 , m], and are electrically connected.

[0285] The wiring RBL[1] is a source of the transistor RTr included in the memory cell 100[1,1]. The wiring RBL[j] is electrically connected to either the source or drain (semiconductor 116). One of the sources or drains of the transistor RTr included in the memory cell 100[1,j] The wiring RBL[m] is electrically connected to the memory cell 100[1 , m], and are electrically connected.

[0286] The wiring BGL[1] is connected to the memory cells 100[1,1] to 100[n,1]. The back gate (conductor 118) of the transistor RTr included in each of the The wiring BGL[j] is connected to the memory cells 100[1,j] to 100[n,j]. ] and the back gate (conductor 118) of the transistor RTr included in each of The wiring BGL[m] is connected to the memory cells 100[1,m] to 100[ The back gate (conductor 118) of the transistor RTr included in each of the transistors [n, m] and are electrically connected.

[0287] The wiring WWL functions as a write word line, and the wiring RWL functions as a read word line. The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. It works.

[0288] In addition, in the memory string 200[1] shown in FIG. ] is a region electrically connected to the other of the source or drain of the transistor RTr included in The source of the transistor RTr included in the memory cell 100[n,1] is denoted as node N1[1]. The region electrically connected to one of the drains is indicated as node N2[1]. Nodes N1 and N2 of the list ring 200[j] are called nodes N1[j]. and node N2[j]. Also, nodes N1 and N2[j] of memory string 200[m] Node N1 and node N2 are denoted as node N1[m] and node N2[m], respectively.

[0289] <Example of operation method> Next, an example of an operation method of the semiconductor device 300 shown in FIG. In this embodiment, the operation of writing data to the memory cell 100 included in the memory string 200[1] is An example of the operation of reading data will be described below.

[0290] In the following description, the low level potential (Low) and the high level potential (High) are It does not mean a specific potential, and the specific potential may be different if the wiring is different. For example, the low level potential and the high level potential applied to the wiring WWL are The potential may be different from the low level potential and high level potential applied to L.

[0291] In this example of the operation method, the wiring BGL includes a transistor RTr and a transistor WT It is assumed that a potential within the range in which r operates normally is applied in advance.

[0292] FIG. 38A is a timing chart for explaining an example of an operation for writing data to the memory string 200[1]. FIG. 38(B) is a timing chart showing data transfer from memory string 200[1]. 38(A) and 38(B) are timing charts for explaining an example of a read operation. The timing chart of the wiring WWL[1], wiring WWL[2] or wiring WWL[n- 1], wiring WWL[n], wiring RWL[1], wiring RWL[2] or wiring RWL[n- 1], the magnitude of the potential of the wiring RWL[n], the node N1[1], and the node N2[1] Also, the wiring WBL[1] changes depending on the data supplied to the wiring WBL[1]. This shows the following.

[0293] FIG. 38A shows data D[1] to D[n] stored in memory cells 10 100[n,1] to 100[1,1]. The data D[1] to D[n] can be binary or multi-valued. Data D[1] to D[n] are supplied from wiring WBL[1].

[0294] Data is written to the memory string 200[1] from the memory cell 100[n,1]. This is performed in sequence from memory cell 100[1,1] to memory cell 100[1,1]. After writing the data, if you try to write data to memory cell 100[2,1], The data stored in memory cell 100[1,1] is The data is lost when you write it to memory cell 100[1,1]. It becomes necessary to read the written data and save it in another location.

[0295] In the circuit configuration of the memory string 200, data is written to the memory cell 100[k,1]. When writing, the data is stored in memory cells 100[n,1] to 100[k+1,1]. In order to prevent the rewriting of data stored in the wiring WWL[n] to the wiring WWL[k+1], A low-level potential is supplied to the memory cells 100[n,1] to 100[k+1, 1] is turned off. The data stored in memory cells 100[n,1] to 100[k+1,1] are This allows the data to be protected.

[0296] When writing data to the memory cell 100[k,1], the data is transferred to the wiring WBL[1]. Since the potential is supplied from the line WWL[1] to the line WWL[k], a high-level potential is supplied to the line WWL[1] to the line WWL[k]. , the transistors of the memory cells 100[1,1] to 100[k,1] This causes the write operation of the memory cell 100[k,1] to be completed. The data can be stored in the storage node.

[0297] Note that when data is written to the memory cells 100[1,1] to 100[n,1] In this case, the wiring RBL[1] can be controlled independently, so it does not need to be at a specific potential. For example, In this case, the potential of the wiring RBL[1] may be set to a low level potential. The potential of the node N2[1] may be set to a low level potential.

[0298] <<Write operation>> Based on the above, an example of a write operation will be explained using the timing chart in FIG. In the period T10, the wirings WWL[1] to WWL[n] and the wiring RWL[1] to wiring RWL[n], wiring WBL[1], node N1[1], and node N2[1] The potentials of the respective terminals are set to low level potentials.

[0299] In a period T11, a high-level potential is supplied to the wirings WWL[1] to WWL[n]. As a result, the memory cells 100[1,1] to 100[n,1] The transistor WTr in each of them is fully on. Then, the wiring WBL[1] Data D[n] is supplied to memory cells 100[1,1] to 100[1,2]. Since the transistors WTr in each of [n,1] are fully on, Data D[n] is provided to the storage node of memory cell 100[n,1].

[0300] In the period T12, a low-level potential is supplied to the wiring WWL[n]. A high-level potential continues to be supplied to the wirings WWL[-1] to WWL[1]. The transistor WTr in the memory cell 100[n,1] is turned off, and the memory cell The transistors included in each of the memory cells 100[n-1,1] to 100[1,1] WTr is maintained in the on state. And the data D[n-1] is carried on the wiring WBL[1]. Each of the memory cells 100[n-1,1] to 100[1,1] is supplied Since the transistor WTr is fully on, the data D[n-1] is supplied to the storage node of the memory cell 100[n-1,1]. Since the transistor WTr of 0[n,1] is in the off state, The data D[n] written to memory cell 100[n,1] is retained.

[0301] In the period T13, similarly to the periods T11 and T12, the memory cell 100[n-2, ] to memory cell 100[2,1] are sequentially stored with data D[n-2] to D[ 2] is written.

[0302] Specifically, the memory cells 100[n,1] to 100[n,2] in which data has already been written The transistor WTr in 0[k+1,1] is turned off, and data is written. The transistors included in the memory cells 100[k,1] to 100[1,1] By fully turning on the WTr and supplying data D[k] from the wiring WBL, memory cell 1 Write data D[k ] is written, the transistor WTr of the memory cell 100[k,1] is Then, data D[k-1] is supplied from the wiring WBL[1] to the memory A write operation is performed on the storage node of cell 100[k-1,1].

[0303] The write operation when k is 1 will be described in the period T14. A low-level potential is supplied to the lines WWL[n] to WWL[2], and a low-level potential is supplied to the lines WWL[1] A high-level potential continues to be supplied to the memory cell 100[n,1]. The transistor WTr in the memory cell 100[2,1] is turned off, and the memory The transistor WTr in the cell 100[1,1] remains on. Data D[1] is supplied to the line WBL[1]. Since the transistor WTr is fully on, the data D[1] is The charge reaches the memory node of memory cell 100[1,1] and is written. The transistors WTr of the memory cells 100[n,1] to 100[2,1] are in the off state. In order to store the data, the data is stored in each of the memory cells 100[n,1] to 100[2,1]. The stored data D[n] through D[2] are retained.

[0304] In this way, data is stored in the memory cells 100[1,1] to 100[n,1]. Can be written.

[0305] In this embodiment, the write operation will be described with a focus on the memory string 200[1]. However, in the circuit configuration of the semiconductor device 300, a high-level potential is supplied to the wiring WWL[k]. Then, all the transistors WTr electrically connected to the wiring WWL[k] are turned on. For this reason, not only memory string 200[1] but also memory string 200[2] At the same time, data is written to memory string 200[m].

[0306] The memory cell 100 shown in this embodiment is an OS memory. The semiconductor device 300 including the above-mentioned memory cell does not require an erase operation before rewriting data, and can perform high-speed write operations. This makes it possible to create works.

[0307] When data is written (rewritten) to the memory cell 100 close to the wiring WBL, When data is written to the memory cell 100 located farther from the line WBL than the memory cell 100 in question, For example, when writing data to memory cell 100[1,1], the write operation can be omitted. When writing (rewriting), the memory cells 100[2,1] to 100[n, In addition, the data write operation to the memory cell 100[2, When writing data to memory cell 100[3,1] to memory cell 100[n , 1] can be omitted.

[0308] Data that is frequently rewritten is stored in the memory cell 100 close to the wiring WBL. This reduces the time required to write (rewrite) data. The writing (rewriting) speed can be increased.

[0309] By operating in this way, the memory of OS NAND type (including 3D OS NAND type) The memory device can be made to act like a RAM.

[0310] <<Read operation>> FIG. 38B shows data D[1] to data D[n] stored in memory cells 100[1 In this example, the data is read from memory cells 100[n,1] to 100[n,1]. In order to maintain the data stored in each memory cell 100, the transistor WTr is turned off. Therefore, the memory cells 100[1,1] to 100[2,3] are required to be in the When reading data from the wiring WWL[1] to the wiring WWL[n,1], The potential of [n] is a low level potential.

[0311] In the circuit configuration of the semiconductor device 300 shown in FIG. When reading, the transistor RTr of the other memory cell 100 is fully turned on. Then, the transistor RTr of the memory cell 100 to be read is set to the saturated region. That is, the transistor RTr of the memory cell 100 to be read is operated. The magnitude of the current flowing between the source and drain depends on the voltage between the source and drain and the read It is determined according to the data stored in the target memory cell 100.

[0312] For example, consider the case where data stored in memory cell 100[k,1] is read. In a read operation, the memory cells 100[1,1] except for the memory cell 100[k,1] are ] to memory cell 100[n,1] have transistors RTr sufficiently turned on. In order to achieve this state, high-speed wiring RWL[1] to RWL[n] except for wiring RWL[k] are A level potential is provided.

[0313] On the other hand, the transistor RTr in the memory cell 100[k,1] is k, 1] to switch between on and off states according to the data stored in the wiring R The potential of WL[k] is the same as that when the data was written to the memory cell 100[k,1]. In this case, the arrangement during the write operation and the read operation is The potential of the line RWL[k] is considered as a low-level potential.

[0314] For example, a potential of +3 V is applied to node N1[1] and a potential of 0 V is applied to node N2[1]. Node N2[1] is left floating, and the voltage at node N2[1] is then measured. The potential of the wiring RWL[1] to the wiring RWL[n] except for the wiring RWL[k] is set to a high level. When the memory cell 100[k,1] is set to the memory cell potential, the memory cells 100[1,1] except for the memory cell 100[k,1] The transistors RTr in each of the memory cells 100[n,1] are in a fully on state. It becomes.

[0315] On the other hand, between the source and drain of the transistor RTr of the memory cell 100[k,1] The voltage is determined by the gate potential of the transistor RTr and the potential of the node N1[1]. Therefore, the potential of the node N2[1] is held at the memory node of the memory cell 100[k,1]. It depends on the data collected.

[0316] In this manner, the data stored in the memory cell 100[k,1] can be read. can.

[0317] Based on the above, an example of a read operation will be explained using the timing chart in FIG. In the period T20, the wirings WWL[1] to WWL[n] and the wiring RWL[1] to those of the wiring RWL[n], the wiring WBL, the node N1[1], and the node N2[1] Each potential is at a low level. In particular, node N2[1] is floating. Then, the memory cells 100[1,1] to 100[n,1 ], data D[1] to D[n] are stored in the storage nodes, respectively. Let us assume that.

[0318] In a period T21, a low-level potential is supplied to the wiring RWL[1], and a low-level potential is supplied to the wiring RWL[2 A high-level potential is supplied to the wirings RWL[n] to RWL[n]. The transistors RTr included in each of the memory cells 100[2,1] to 100[n,1] are Then, the transistor RTr of the memory cell 100[1,1] is fully turned on. The memory cell 100[1,1] is turned on in response to the data D[1] stored in the memory node. The on and off states are determined.

[0319] In addition, the potential V R This causes the potential of node N1[1] to V R The potential of the node N2[1] is V Rand memory cell 10 It depends on the data stored in the storage node of 0 [1,1]. Here, node N2 The potential of [1] is V D[1] Then, the potential V of the node N2[1] D[1] Measure By this, the data D[1 ] can be read out.

[0320] In a period T22, a low-level potential is supplied to the wirings RWL[1] to RWL[n]. A low level potential is supplied to the node N2[1], and then the node N2[ That is, in the period T22, the wirings RWL[1] to The potentials of the wiring RWL[n] and the node N2[1] are the same as those in the period T20. Oh, the wiring RBL[1] continues to have a potential of V R Alternatively, low level power may be provided. In this operation example, the wiring RBL[1] is supplied with a potential V R but Therefore, the potential V R continues to be supplied Let us assume that.

[0321] In the period T23, a low-level potential is supplied to the wiring RWL[2], and A high-level potential is supplied to the wirings RWL[1] to RWL[n] and the wirings RWL[3] to RWL[n]. The memory cells 100[1,1], 100[3,1], 100[4,1], 100[5,1], 100[6,1], 100[7,1], 100[8,1], 100[9,1], 100[10,1], 100[11,1], 100[12,1], 100[13,1], n, 1] has a transistor RTr in a fully on state. The transistor RTr of the memory cell 100[2,1] is The on or off state is determined according to the data D[2] stored in the mode. The wiring RBL[1] has a potential of V R This causes the potential of node N2[1] to is the potential V of node N1[1] R and stored in the storage node of memory cell 100[2,1] Here, the potential of node N2[1] is determined by V D[2] Let's say. The potential V of node N2[1] D[2] By measuring The data D[2] stored in the storage node [1, 2, 1] can be read out.

[0322] In the period T24, similar to the read operations in the periods T22 and T23, the memory cell 10 Data D[3] to D[n-1,1] are sequentially stored in the memory cells 100[3,1] to 100[n-1,1]. The data D[n-1] is read out.

[0323] Specifically, when data D[k] is read from memory cell 100[k,1], node N The potential of node N2[1] is set to a low level potential and node N2[1] is set to a floating state. After that, a high-level voltage is applied to the wiring RWL[1] to the wiring RWL[n] except for the wiring RWL[k]. By supplying a position, the memory cells 100[1,1] to 100[k,1] except for the memory cell 100[k,1] are The transistor RTr in the memory cell 100[n,1] is fully turned on. The transistor RTr in the module 100[k,1] is turned on in accordance with the data D[k]. Next, the potential of node N1[1] is set to V R By setting The potential corresponds to the data D[k], and the data D[k] can be read by measuring this potential. The data D[k] stored in the memory cell 100[k,1] can be read. After the readout is completed, the wiring RWL[1] to the wiring RWL[2] are used to prepare for the next read operation. [n] and supply a low-level potential to node N2[1], and then Node N2[1] is left floating.

[0324] In a period T25, a low-level potential is supplied to the wirings RWL[1] to RWL[n]. A low level potential is supplied to the node N2[1], and then the node N2[ That is, in the period T25, the wirings RWL[1] to RWL[1] are set in a floating state. The potentials of the wiring RWL[n] and the node N2[1] are the same as those in the period T20. do.

[0325] In the period T26, a low-level potential is supplied to the wiring RWL[n], and A high-level potential is supplied to the wirings RWL[n-1] to RWL[n-1]. The transistors included in each of the memory cells 100[1,1] to 100[n-1,1] RTr is fully on. Then, the transistor R Tr corresponds to the data D[n] stored in the storage node of the memory cell 100[n,1]. In addition, the line RBL[1] is connected to a potential V R continues to be supplied. As a result, the potential of the node N2[1] becomes equal to the potential V R and memory cell 10 0[n,1] and the data held in the storage nodes. Here, node N2 The potential of [1] is V D[n] Then, the potential V of the node N2[1] D[n] Measure By this, the data D[n ] can be read out.

[0326] In this way, the data is stored in memory cells 100[1,1] to 100[n,1]. The data stored in the memory can be read.

[0327] In this embodiment, the read operation will be described with attention to the memory string 200[1]. However, in the circuit configuration of the semiconductor device 300, not only the memory string 200[1], The data read from memory string 200[2] to memory string 200[m] is also performed in the same manner. Also, by turning off the transistor WTr, data can be read. The data stored in the storage node is not corrupted during the read operation. Only the data contained in the list ring 200 can be read.

[0328] <Structural example of semiconductor device> Next, a structural example of the semiconductor device 300 will be described.

[0329] 39(A) to 39(C) are schematic diagrams showing an example of a part of a semiconductor device 300. FIG. 39(A) shows a perspective view of a portion of the semiconductor device, and FIG. 39(B) shows the semiconductor device. FIG. 39(C) shows a top view of a portion of the conductor device. A cross-sectional view corresponding to Z1-Z2 is shown.

[0330] The semiconductor device includes a wiring WL (wiring WWL or wiring RWL) and an insulator (FIG. 39(A) The structure has a laminated structure in which (a) a layered structure including a layered structure (a region not hatched in (C) through (C)) and (b) a layered structure including a layered structure (a region not hatched in (C) through (C)).

[0331] An opening is formed in the structure so as to penetrate the insulator and the wiring WL at once. In order to provide the memory cell 100 in the region AR through which the wiring WL penetrates, An insulator, a conductor, and a semiconductor are formed in the opening. The memory cell 100 functions as a source electrode or a drain electrode of the transistor. The semiconductor functions as a channel formation region of the transistor included in the memory cell 100. In addition, the conductor is not formed, and a channel forming region and a low resistance region are formed in the semiconductor. The low resistance region may then be used as the source or drain of a transistor.

[0332] In FIG. 39(A) to (C), an insulator, a conductor, and a semiconductor are formed in the opening. In particular, in FIG. 39(A), the inside of the structure is The region HL in the memory cell 100 is indicated by a dashed line. When a back gate is provided in the region HL, the conductor in the region HL is It may also function as a wiring BGL for electrically connecting to the memory string. The memory string 200 is formed in the region HL. The memory string 200 is formed in the region SA. do.

[0333] Incidentally, the region TM where the wiring WL is exposed is a connection terminal for applying a potential to the wiring WL. In other words, the wiring WL and any other wiring can be electrically connected in the region TM. By this, a potential can be applied to the gate of the transistor in the memory cell 100. Note that the wiring WL corresponds to the conductor 102 or the conductor 103 in FIG. do.

[0334] The shape of the region TM is not limited to the configuration examples shown in FIGS. 39(A) to 39(C). The configuration of a semiconductor device 300 according to one embodiment of the present invention is shown in, for example, FIG. As shown in FIG. 3C, an insulator is formed on the region TM, an opening is provided in the insulator, and the A conductor PG may be formed so as to fill the opening.

[0335] FIG. 40(A) shows a perspective view of a part of the semiconductor device, and FIG. 40(B) shows the semiconductor device. FIG. 40(C) shows a top view of a portion of the body device. The cross-sectional view corresponds to 1-Z2. Note that the wiring ER is formed on the conductor PG. As a result, the wiring ER and the wiring WL are electrically connected to each other. In FIG. 1, the conductor PG provided inside the structure is illustrated by a dashed line, and the dashed line of the region HL is omitted. is doing.

[0336] <Example of connection to peripheral circuits> The semiconductor device 300 according to one embodiment of the present invention includes a read circuit, a precharge circuit, and In this case, a peripheral circuit of a memory cell array such as a silicon substrate may be formed. Then, a silicon transistor is formed on the peripheral circuit to form the peripheral circuit. FIG. 41(A) shows a semiconductor device 300 according to an embodiment of the present invention. A semiconductor device 300 according to one embodiment of the present invention is configured as an upper layer of the silicon transistor. FIG. 42(A) shows a cross-sectional view of a peripheral circuit formed of a FIN type Si transistor. 1 is a cross-sectional view of a semiconductor device 300 according to an embodiment of the present invention formed on the upper layer of the substrate. do.

[0337] In FIG. 41(A) and FIG. 42(A), the Si transistors constituting the peripheral circuits are formed on a substrate 1. The element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed to extend in the channel width direction. is connected to a conductor 1712 (not shown).

[0338] The substrate 1700 may be any of the substrates shown in the above embodiment modes. Single crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, silicon germanium A compound semiconductor substrate made of silicon, an SOI substrate, or the like can be used.

[0339] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, or the like. Plates, flexible substrates, laminated films, paper containing fibrous materials, or base films, etc. Also, a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. The conductive elements may be transposed. In FIG. 41(A) and FIG. 42(A), as an example, Figure 0 shows an example using a single crystal silicon wafer.

[0340] In FIG. 41(A) and FIG. 42(A), in the area SA, The provided conductor 1221, conductor 1222, conductor 1223, and insulator 1202 The conductor 1221 is connected to the transistor R It is electrically connected to the source or drain of the transistor.

[0341] The insulator 1202 is provided to cover the conductor 1221. The conductor 1222 is The conductor 12 is embedded in the insulator 1202 in the area where it overlaps with the conductor 12. 23 is provided above the insulator 1202 and is electrically connected to the conductor 118 via the conductor 1222. are connected to the network.

[0342] In addition, in FIG. 41(A) and FIG. 42(A), the conductor 1223, the insulator 1202, and An insulator 1203 is formed so as to cover the memory string 200 and the like. 03) Use an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. It is preferable that the insulator 1203 has a function of suppressing the permeation of impurities such as hydrogen and oxygen. By using an insulator with this property, impurities from the outside world (e.g., water molecules, hydrogen atoms, hydrogen molecules) can be prevented from entering the , oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.) The diffusion of the above-mentioned substances into the memory string 200 can be suppressed.

[0343] Here, the details of the Si transistor will be described. The Si transistor is a planar type transistor shown in FIG. 41(B) which shows a cross section in the channel length direction. The Si transistor is shown in a cross-sectional view in the channel width direction. A channel forming region 1793 and a low concentration impurity region 1794 are provided in the channel 1792. A high-concentration impurity region 1795 (collectively referred to simply as an impurity region) and the impurity region A conductive region 1796 is provided in contact with the channel forming region 1793. A gate insulating film 1797, a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has a sidewall insulating layer 1798 and a sidewall insulating layer 1799 provided on the side of the gate electrode 1790. The conductive region 1796 may be made of metal silicide or the like.

[0344] The FIN type Si transistor shown in FIG. 42(A) is a cross-sectional view in the channel length direction. The FIN type Si transistor shown in FIG. 42(B) is a cross-sectional view in the channel width direction. In the Si transistor shown in FIG. 42(A) and (B), the channel formation region 1793 is It has a convex shape, and the gate insulating film 1797 and the gate electrode 17 In this embodiment, a protrusion is formed by processing a part of a semiconductor substrate. However, the SOI substrate may be processed to form a semiconductor layer having a convex shape. The symbols shown in Figures 42(A) and (B) are the same as those shown in Figures 41(A) and (B).

[0345] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0346] (Embodiment 3) In this embodiment, a semiconductor device 400 including a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device 400 can function as a memory device.

[0347] 43 is a block diagram showing a configuration example of a semiconductor device 400. The semiconductor device shown in FIG. 400 includes a driving circuit 410 and a memory array 420. The memory array 420 includes 43, a memory array 420 is arranged in a matrix. 1 shows an example having a plurality of memory cells 30 arranged in a matrix.

[0348] The drive circuit 410 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 4. The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412 (Cont control circuit), and a voltage generating circuit 428.

[0349] In the semiconductor device 400, the circuits, signals, and voltages may be omitted as necessary. Alternatively, other circuits or other signals may be added. CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1 The signal PON2 is an input signal from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0350] Signals BW, CE, and GW are control signals. Signal CE is a chip enable signal. signal GW is a global write enable signal, signal BW is a bypass signal, The signal ADDR is an address signal. The signal WDA is a write enable signal. Signal PON1 and signal PON2 are write data and signal RDA are read data. The signals PON1 and PON2 are signals for controlling power gating. It may be generated by the control circuit 412.

[0351] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit 412 outputs signals CE, GW, and BW. The operation mode of the semiconductor device 400 (for example, write operation, read operation, ) or the control circuit 412 determines whether or not this mode of operation is to be performed. , and generates control signals for the peripheral circuit 411.

[0352] The voltage generating circuit 428 has a function of generating a negative voltage. For example, the signal WAKE has a function of controlling the input to the voltage generating circuit 428. When the signal from the line is given, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 4 28 generates a negative voltage.

[0353] The peripheral circuit 411 is used to write and read data to and from the memory cell 30. The peripheral circuit 411 includes a row decoder 441, a column decoder 442, and a Column Decoder 442, Row Driver 423 er), a column driver 424, an input circuit 425 t Cir.), an output circuit 426 (Output Cir.), and a sense amplifier 42 7 (Sense Amplifier).

[0354] The row decoder 441 and the column decoder 442 have the function of decoding the signal ADDR. The row decoder 441 is a circuit for specifying a row to be accessed, and the column decoder 442 is a circuit for specifying a row to be accessed. is a circuit for specifying a column to be accessed. The column driver 424 has a function of selecting the wiring WL designated by the column driver 424. A function for writing data to the memory cell 30, a function for reading data from the memory cell 30, and a function for storing the read data. It has functions such as retaining information.

[0355] The input circuit 425 has a function of holding the signal WDA. The output data of the input circuit 425 is output to the column driver 424. The data (Din) that the column driver 424 reads from the memory cell 30 is written to the The data (Dout) is output to the output circuit 426. The output circuit 426 stores the Dout. The output circuit 426 outputs Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is the signal RDA.

[0356] PSW241 is the V to the peripheral circuit 415 DD It has the function of controlling the supply of PSW242. V to row driver 423 HM In this embodiment, the semiconductor device A high power supply voltage of 400 V DD and the low power supply voltage is GND (ground potential). Also, V HM is the high power supply voltage used to drive the word line high, and V DD Higher than The signal PON1 controls the on / off of the PSW241, and the signal PON2 controls the In FIG. 43, in the peripheral circuit 415, V DD The number of power domains to which the power is supplied is set to one, but it can be multiple. In this case, A power switch may be provided for each power domain.

[0357] A memory string 200 can be used as the memory cell 30. A memory cell other than the memory string 200 may be used as the memory string 30. Next, an example of a memory cell configuration that can be applied to the memory cell 30 will be described.

[0358] [DOSRAM] FIG. 44A shows an example of the circuit configuration of a memory cell of a DRAM. DRAM using S transistors is called DOSRAM (Dynamic Oxide Se It is called a memory cell. The filter 31 includes a transistor M1 and a capacitance element CA. The transistor M1 , a front gate (sometimes simply referred to as the gate), and a back gate.

[0359] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA. The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M2 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the first terminal is connected to the wiring CAL.

[0360] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. AL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, the CAL line is connected to a low-level potential (reference potential It is preferable to apply a voltage of 100 V.

[0361] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 is The pressure can be increased or decreased.

[0362] Data is written and read by applying a high-level potential to the wiring WOL and This is achieved by making M1 conductive and connecting the wiring BIL to the first terminal of the capacitance element CA. can be.

[0363] In addition, the memory cell that can be used for the memory cell 30 is not limited to the memory cell 31. For example, the memory cell 3 shown in FIG. In the memory cell 32, the back gate of the transistor M1 is connected to the wiring BGL Instead, it is connected to the wiring WOL. , the same potential as that of the gate of the transistor M1 is applied to the back gate of the transistor M1. Therefore, when the transistor M1 is in a conductive state, the current flowing through the transistor M1 is The current that can be supplied can be increased.

[0364] Also, for example, a memory cell that can be used for the memory cell 30 has a single gate structure. A memory cell configured with a transistor M1 that does not have a back gate. An example of the circuit configuration of the memory cell is shown in FIG. The memory cell 33 has a configuration similar to that of the memory cell 31 except that the back gate is removed from the transistor M1. By applying the memory cell 33 to the memory cell 30, Since the transistor M1 does not have a back gate, the manufacturing process of the memory cell 30 is the same as that of the memory cell 31. and can be shorter than memory cell 32.

[0365] It is preferable to use an OS transistor as the transistor M1. The OS transistor M1 has the characteristic of having an extremely small off-state current. By using a transistor, the leakage current of the transistor M1 can be made very low. In other words, the written data can be held for a long time by the transistor M1. This reduces the frequency of refreshing the memory cells. This eliminates the need for memory cell refresh operations and has very low leakage current. Therefore, multi-value data or address is stored in the memory cell 31, the memory cell 32, and the memory cell 33. Analog data can be stored.

[0366] [NOSRAM] FIG. 44(D) shows an example of the circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 34 includes a transistor M2, a transistor M3, a capacitance element CB, The transistor M2 has a front gate and a back gate. In the specification, etc., it is stated that the gain cell type memory device uses an OS transistor for the transistor M2. A memory device having a resettable state is called a nonvolatile oxide random access memory (NOSRAM). It is called microconductor RAM.

[0367] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M2 The second terminal of the transistor M1 is connected to the wiring WBL, and the gate of the transistor M2 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the line CAL. The first terminal of the transistor M2 is connected to the line RB The second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M3 is connected to the line SL. The gate of the capacitance element CB is connected to the first terminal of the capacitance element CB.

[0368] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The line CAL functions as a second terminal of the capacitance element CB, and the line WOL functions as a word line. It functions as a wiring for applying a specific potential to the transistor. When writing data, data is retained. During the data read operation, the line CAL is supplied with a low-level potential (called the reference potential). In some cases, it is preferable to apply

[0369] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 is The pressure can be controlled.

[0370] To write data, a high-level potential is applied to the wiring WOL to turn on the transistor M2. The wiring WBL and the first terminal of the capacitance element CB are connected to each other. When the transistor M2 is in a conductive state, a potential corresponding to the information to be recorded in the wiring WBL is applied. and writes the potential to the first terminal of the capacitance element CB and the gate of the transistor M3. After that, a low-level potential is applied to the wiring WOL to make the transistor M2 non-conductive. As a result, the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3 are Hold.

[0371] Data is read by applying a predetermined potential to the line SL. The current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 is determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential of the wiring RBL connected to the first terminal of the transistor M3 is read out. By this, a current is held at the first terminal of the capacitance element CB (or the gate of the transistor M3). In other words, the potential stored in the first terminal of the capacitance element CB (or the transistor The potential held at the gate of transistor M3 indicates the information written to this memory cell. The information can be read out.

[0372] In addition, the memory cells that can be used for the memory cell 30 are not limited to the memory cell 34. The circuit configuration can be changed as appropriate.

[0373] For example, a memory cell that can be used for the memory cell 30 is as shown in FIG. The memory cell 35 may have the same structure as the memory cell 32 shown in FIG. Similarly to the transistor M1, the back gate of the transistor M2 is connected to the wiring BGL. In this configuration, the traf?c is connected to the WOL wiring. The same potential as that of the gate of transistor M2 can be applied to the back gate of transistor M1. Therefore, when the transistor M2 is in a conductive state, the current flowing through the transistor M2 is The flow can be increased.

[0374] Also, for example, a memory cell that can be used for the memory cell 30 does not have a back gate. The memory cell may be configured with a transistor M2 that does not include the transistor M1. An example of the configuration is shown in FIG. 44(F). The memory cell 36 is a The back gate is omitted. By this, since the transistor M2 does not have a back gate, The manufacturing process can be made shorter than that of memory cell 34 and memory cell 35.

[0375] In addition, for example, the wiring WBL and the wiring RBL are integrated into one wiring BIL. An example of the circuit configuration of the memory cell is shown in FIG. The wiring WBL and the wiring RBL of the cell 34 are connected to a single wiring BIL. A terminal of the transistor M1 and a first terminal of the transistor M2 are connected to the wiring BIL. That is, the memory cell 37 has a write bit line and a read bit line connected to a single line. It is configured to operate as a wiring BIL.

[0376] In addition, the channel forming region of the transistor M2 and / or the transistor M3 is provided with an indium ion implantation layer. An oxide semiconductor containing at least one of indium, element M, and zinc can be used. In other words, the transistor M2 and / or the transistor M3 are OS transistors. In particular, the channel of the transistor M2 and / or the transistor M3 is preferably It is preferable that the panel forming region contains an oxide semiconductor containing indium, gallium, and zinc. stomach.

[0377] OS transistors have the characteristic of having an extremely small off-state current. By using an OS transistor as transistor M2 and / or transistor M3, , transistor M2 and / or transistor M3 have very low leakage current. In particular, the written data can be held for a long time by the transistor M2. This allows the memory cells to be refreshed less frequently. This eliminates the need for a re-cell refresh operation. Also, the leakage current is extremely low. Therefore, the memory cells 34, 35, 36, and 37 are multi-valued. It can hold digital or analog data.

[0378] A memory cell 34 and a memory cell 35 in which an OS transistor is used as the transistor M2, The memory cells 36 and 37 are one embodiment of NOSRAM.

[0379] It should be noted that a Si transistor may be used as the transistor M3. Depending on the crystal state of the silicon used in the semiconductor layer, the field effect transition is more pronounced than in OS transistors. The mobility may be high.

[0380] In addition, when an OS transistor is used as the transistor M3, the memory cell is a unipolar circuit. It can be composed of:

[0381] FIG. 45(A) shows a gain cell type memory cell having three transistors and one capacitance element. The memory cell 38 includes transistors M4 to M6 and a capacitance element CC. The transistor M4 has a front gate and a back gate.

[0382] The first terminal of the transistor M4 is connected to the first terminal of the capacitance element CC. The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M2 is connected to the wiring WWL. The back gate of the transistor M4 is electrically connected to the wiring BGL. The second terminal of the element CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6. The gate of the transistor M5 is connected to the first terminal of the capacitance element CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL. is connected.

[0383] The wiring BIL functions as a bit line, and the wiring WWL functions as a write word line. The line RWL functions as a read word line.

[0384] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M4. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M4 is The pressure can be increased or decreased.

[0385] The wiring GNDL is a wiring that provides a low level potential.

[0386] To write data, a high-level potential is applied to the wiring WWL to turn on the transistor M4. The wiring BIL is connected to the first terminal of the capacitance element CC. When the transistor M4 is in a conductive state, a potential corresponding to the information to be recorded in the wiring BIL is and writes the potential to the first terminal of the capacitance element CC and the gate of the transistor M5. After that, a low-level potential is applied to the wiring WWL to make the transistor M4 non-conductive. As a result, the potential of the first terminal of the capacitance element CC and the potential of the gate of the transistor M5 are Hold.

[0387] To read data, a predetermined potential is precharged to the line BIL, and then the line BIL is This is done by putting the wiring RWL in an electrically floating state and applying a high-level potential to the wiring RWL. Since the line RWL is at a high level potential, the transistor M6 is in a conductive state, and the line BI L and the second terminal of the transistor M5 are electrically connected to each other. The potential of the wiring BIL is applied to the second terminal of the capacitor CC. Depending on the potential held on the The potential of the second terminal of the transistor 5 and the potential of the wiring BIL change. By reading out, the first terminal of the capacitance element CC (or the gate of the transistor M5) In other words, the potential held in the first terminal of the capacitance element CC (or The potential held at the gate of transistor M5 indicates that the data is being written to this memory cell. The information stored in the memory can be read out.

[0388] In addition, the memory cell that can be used for the memory cell 30 can be changed appropriately in terms of the circuit configuration. For example, the transistor M1 of the memory cell 32 shown in FIG. Like transistor M2 of memory cell 35 shown in FIG. 44(E), memory cell 38 has a transistor The back gate of transistor M4 is connected to wiring WOL instead of wiring BGL. By using such a configuration, the back of the transistor M4 Since the same potential as that of the gate of transistor M4 can be applied to the gate, When transistor M4 is in a conductive state, the current flowing through transistor M4 can be increased. For example, the transistor M1 of the memory cell 33 shown in FIG. Like transistor M2 of memory cell 36 shown in FIG. 44(F), memory cell 38 has a transistor The transistor M4 may have a configuration without a back gate. As a result, the transistor M4 does not have a back gate, and the manufacturing process of the memory cell is shortened. It is possible.

[0389] Note that it is preferable to use OS transistors as the transistors M4 to M6. Since the OS transistor has a characteristic of having an extremely small off-state current, By using OS transistors as the transistors M4 to M6, The leakage current of the transistors M4 to M6 can be made very low. The written data can be held for a long time by transistor M4, so The frequency of refreshing the memory cells can be reduced. This can eliminate the need for a flash operation.

[0390] In addition, Si transistors are used as the transistors M5 and M6 described in this embodiment. As mentioned above, the crystal state of the silicon used in the semiconductor layer of a Si transistor is In some cases, the field-effect mobility of a semiconductor transistor may be higher than that of an OS transistor.

[0391] In addition, when OS transistors are used as the transistors M5 and M6, the memory cell It can be constructed with a unipolar circuit.

[0392] [OS-SRAM] FIG. 45B shows a static random access memory (SRAM) using OS transistors. In this specification and the like, an OS transistor is The SRAM used is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 39 shown in FIG. 45(B) is a backup-capable SRAM. The memory cell is

[0393] The memory cell 39 includes transistors M7 to M10 and transistors MS1 to The transistor MS4, the capacitance element CD1, and the capacitance element CD2 are included. Transistors M7 to M10 each have a front gate and a back gate. The transistors MS1 and MS2 are p-channel transistors. The transistor MS3 and the transistor MS4 are n-channel transistors. do.

[0394] A first terminal of the transistor M7 is connected to the wiring BIL, and a second terminal of the transistor M7 is , a first terminal of the transistor MS1, a first terminal of the transistor MS3, and a transistor M a gate of transistor S2, a gate of transistor MS4, and a first terminal of transistor M10; The gate of the transistor M7 is connected to the wiring WOL. The back gate of transistor M7 is connected to the wiring BGL1. The second terminal of the transistor M8 is connected to the line BILB. a first terminal of the transistor MS4; a gate of the transistor MS1; The gate of transistor M1 is connected to the gate of transistor M2 and the first terminal of transistor M3. The gate of transistor M8 is connected to the wiring WOL, and the back gate of transistor M8 is connected to the wiring BGL It is connected to 2.

[0395] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. The second terminal of the transistor MS2 is electrically connected to the wiring VDL. The second terminal of the transistor MS4 is electrically connected to the wiring GNDL. It is electrically connected to the line GNDL.

[0396] The second terminal of the transistor M9 is connected to the first terminal of the capacitance element CD1. The gate of the transistor M9 is connected to the wiring BGL. 3. The second terminal of the transistor M10 is connected to the first terminal of the capacitive element CD2. The gate of the transistor M10 is connected to the wiring BRL. The back gate is connected to a wiring BGL4.

[0397] The second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is It is connected to the wiring GNDL.

[0398] The wiring BIL and the wiring BILB function as bit lines, and the wiring WOL functions as a word line. The wiring BRL controls the conductive state of the transistor M9 and the transistor M10. This is wiring that controls the conduction state.

[0399] The wirings BGL1 to BGL4 are the transistors M7 to M10, respectively. The wirings BGL1 to BGL By applying an arbitrary potential to transistors M7 to M4, The threshold voltage of 10 can be increased or decreased.

[0400] The wiring VDL is a wiring that provides a high-level potential, and the wiring GNDL is a wiring that provides a low-level potential. This is the wiring.

[0401] To write data, a high-level potential is applied to the line WOL and a high-level potential is applied to the line BRL. Specifically, when transistor M10 is in a conducting state, A potential corresponding to the information to be recorded is applied to the wiring BIL, and the second terminal of the transistor M10 The potential is written on the side.

[0402] The memory cell 39 is integrated by transistors MS1 and MS2. Since the inverter loop is formed, a potential corresponding to the potential is applied to the second terminal of the transistor M8. The inverted signal of the data signal is input. Since the transistor M8 is in a conductive state, the line BI LB is a potential applied to the wiring BIL, that is, a signal input to the wiring BIL. In addition, the transistor M9 and the transistor M10 are in a conductive state. Since the transistor M7 is in the low-state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are The potentials are held at the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively. After that, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL. By applying a voltage Vcc to transistors M7 through M10 and turning them off, The potential of the first terminal of the capacitance element CD1 and the potential of the first terminal of the capacitance element CD2 are held.

[0403] To read data, the lines BIL and BILB are precharged to a predetermined potential. After the wiring WOL is turned on, a high-level potential is applied to the wiring BRL. As a result, the potential of the first terminal of the capacitance element CD1 is The first capacitance element CD2 is refreshed by the first refresh and output to the wiring BILB. The potential of the terminal is refreshed by the inverter loop of the memory cell 39, and the potential of the wiring BI The wiring BIL and the wiring BILB are each precharged to a potential The potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1 change from In order to read the potential held in the memory cell from the potential of the wiring BIL or the wiring BILB, It can be put out.

[0404] Note that OS transistors are used as the transistors M7 to M10. In particular, the transistors M7 to M10 each have a channel forming region including: It is preferable that the oxide semiconductor contains indium, gallium, and zinc. OS transistors using oxide semiconductors containing gallium and zinc have extremely low off-state current Since the transistors M7 to M10 have the characteristic of being small, By using transistors, the leakage of transistors M7 to M10 In particular, the current can be made very low by passing the written data through the transistors M7 to The transistor M10 allows long-term retention, so the memory cell can be refreshed Alternatively, the frequency of the refresh operation of the memory cells can be reduced. It is possible.

[0405] Note that Si transistors may be used as the transistors MS1 to MS4. stomach.

[0406] By using the memory string 200 as the memory cell 30, the semiconductor device 40 0 can be used as a NAND type memory device. By using the memory cells 31 to 39, the semiconductor device 400 is It can be used as a storage device.

[0407] The driving circuit 410 and the memory array 420 of the semiconductor device 400 may be provided on the same plane. As shown in FIG. 46(A), the driving circuit 410 and the memory array 420 are overlapped. By overlapping the driver circuit 410 and the memory array 420, the signal propagation distance can be reduced. In addition, as shown in FIG. 46B, a memory on the driver circuit 410 can be The rear array 420 may be provided in multiple layers.

[0408] As shown in FIG. 46C, the memory array 4 is disposed above and below the driving circuit 410. In FIG. 46C, the driver circuit 410 may have a first layer and a second layer. In the example shown, multiple memory arrays 420 are provided. By arranging them so that 410 is sandwiched between them, the signal propagation distance can be further shortened. A memory array 420 is stacked on the upper layer of the driving circuit 410, and a memory array 420 is stacked on the lower layer of the driving circuit 410. The number of layers of the memory array 420 to be stacked may be one or more. The number of memory arrays 420 stacked on the upper layer of the driving circuit 410 and the number of memory arrays 420 stacked on the lower layer of the driving circuit 410 are The number of rearrays 420 is preferably equal.

[0409] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0410] (Embodiment 4) In this embodiment mode, a semiconductor wafer on which the semiconductor device or the like shown in the above embodiment mode is formed, An example of an electronic component incorporating the semiconductor device is also shown.

[0411] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. do.

[0412] The semiconductor wafer 4800 shown in FIG. 47(A) includes a wafer 4801 and an upper surface of the wafer 4801. and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. The portion without the circuit portion 4802 is a spacing 4803, which is an area for dicing. do.

[0413] A semiconductor wafer 4800 has a plurality of circuit parts formed on the surface of a wafer 4801 by a previous process. The wafer 4801 can be fabricated by forming a semiconductor device 4802. The surface of the wafer 4801 opposite to the surface on which the circuit portion 4802 is formed is ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for smaller components. It is possible.

[0414] The next step is the dicing process. The scribe line SCL1 and the scribe line SCL2 (dicing line, or cutting line) The spacing 4803 is the same as the dicing. In order to facilitate the process, multiple scribe lines SCL1 are provided in parallel. The scribe lines SCL2 are arranged parallel to each other. It is preferable that the scribe line SCL2 is provided vertically.

[0415] By carrying out a dicing process, a chip 4800a as shown in FIG. The chip 4800a can be cut from the wafer 4801a. , a circuit portion 4802, and spacing 4803a. It is preferable that 3a is as small as possible. In this case, the adjacent circuit portions 4802 The width of the spacing 4803 between the scribe line SCL1 and the scribe The length should be approximately the same as the cut length of the live line SCL2.

[0416] Note that the shape of the element substrate according to one embodiment of the present invention is a semiconductor wafer 480 shown in FIG. The shape of the element substrate is not limited to a rectangular shape. For example, the element substrate may be a semiconductor wafer having a rectangular shape. The shape of the element may be appropriately changed depending on the manufacturing process and the device for manufacturing the element. This can be done.

[0417] <Electronic components> FIG. 47C shows an electronic component 4700 and a substrate on which the electronic component 4700 is mounted (mounting substrate 4 47(C) shows an electronic component 4700 in a mold 4711. The chip 4800a includes a memory according to one embodiment of the present invention. A device or the like can be used.

[0418] FIG. 47C is a partial omission to show the inside of the electronic component 4700. The mold 4700 has a land 4712 on the outside of the mold 4711. The land 4712 is an electrode The electrode pad 4713 is electrically connected to the chip 4800a and the wire 4 The electronic component 4700 is electrically connected to a printed circuit board 47 02. Multiple such electronic components are combined and each is mounted on a printed circuit board. By electrically connecting on 4702, a mounting board 4704 is completed.

[0419] FIG. 47D shows a perspective view of the electronic component 4730. The electronic component 4730 is a SiP (System in Package) tem in package) or MCM (Multi Chip Module) The electronic component 4730 is an example of an in-chip device mounted on a package substrate 4732 (printed circuit board). An interposer 4731 is provided, and a semiconductor device 4735 and and a plurality of semiconductor devices 4710.

[0420] The semiconductor device 4710 may be, for example, a chip 4800a, a semiconductor device as described in the above embodiment, or the like. Semiconductor devices, High Bandwidth Memory (HBM), etc. The semiconductor device 4735 may include a CPU, a GPU, an FPGA, a memory device, An integrated circuit (semiconductor device) such as a

[0421] The package substrate 4732 is a ceramic substrate, a plastic substrate, or a glass epoxy. The interposer 4731 can be a silicon interposer, A resin interposer or the like can be used.

[0422] The interposer 4731 has multiple wirings and connects multiple integrated circuits with different terminal pitches. The wiring has a function of electrically connecting the wiring. The wiring is provided in a single layer or in multiple layers. The interposer 4731 is a package substrate that supports an integrated circuit provided on the interposer 4731. It has a function of electrically connecting to the electrode provided on the plate 4732. The interposer is sometimes called a "rewiring board" or "intermediate board." A through electrode is provided in the through hole 4731, and the through electrode is used to connect the integrated circuit and the package substrate 473 2 may be electrically connected. In addition, in silicon interposers, , TSV (Through Silicon Via) can also be used.

[0423] It is preferable to use a silicon interposer as the interposer 4731. Since there is no need to provide active elements in the interposer, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring of the silicon interposer is formed by the semiconductor process. This makes it easy to form fine wiring that is difficult to achieve with a resin interposer.

[0424] In HBM, many wires must be connected to achieve a wide memory bandwidth. Therefore, the interposer that mounts HBM requires fine and high-density wiring. Therefore, the interposer for mounting HBM should be a silicon interposer. is preferred.

[0425] In addition, in SiP and MCM using silicon interposers, the integrated circuit and the interposer The reliability is less likely to decrease due to the difference in the expansion coefficient between the silicon interposer. The silicon interposer has a highly flat surface, so the integrated circuit and silicon interposer can be easily mounted on the silicon interposer. In particular, it is difficult to cause connection failure between interposers. In 2.5D packaging (2.5-dimensional assembly), silicon interposers are used to place It is preferable to use:

[0426] A heat sink (heat dissipation plate) may be provided on top of the electronic component 4730. When providing the interposer 4731, it is preferable to align the height of the integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, the semiconductor device 4710 and the semiconductor It is preferable to align the height of the devices 4735 .

[0427] In order to mount the electronic component 4730 on another substrate, electrodes 47 are attached to the bottom of the package substrate 4732. 47(D) shows an example in which the electrode 4733 is formed by a solder ball. By providing solder balls in a matrix on the bottom of the package substrate 4732, GA (Ball Grid Array) mounting can be realized. In addition, the electrode 4733 is conductive. The bottom of the package substrate 4732 may be provided with a matrix of conductive pins. By arranging the pins in a shape similar to that of a semiconductor device, PGA (Pin Grid Array) mounting can be achieved.

[0428] Electronic components 4730 are not limited to BGA and PGA, but can be mounted on other boards using various mounting methods. For example, SPGA (Staggered Pin Grid Arrangement) ray), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ(Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) A mounting method can be used.

[0429] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0430] (Embodiment 5) In this embodiment mode, a semiconductor device such as the memory device described in the above embodiment mode may be provided. An example of a processing device that can perform the above-mentioned processing will be described.

[0431] FIG. 48 shows a block diagram of the central processing unit 1100. 11 shows an example of a configuration of a CPU that can be used in the device 1100.

[0432] The central processing unit 1100 shown in FIG. 48 includes an ALU 1191 (ALU :Arithmetic logic unit, ALU controller 11 92, instruction decoder 1193, interrupt controller 1194, tie A timing controller 1195, a register 1196, a register controller 1197, and a bus Interface 1198, Cache 1199, and Cache Interface 1 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface. The cache 1199 and the cache interface 1189 may be provided on a separate chip.

[0433] The cache 1199 is a main memory and cache interface on a separate chip. The cache interface 1189 is connected to the main memory. The cache 1199 has a function of supplying a part of the data held in the cache 1199. The data storage device 1199 has a function of storing the data.

[0434] The central processing unit 1100 shown in FIG. 48 is merely an example showing a simplified configuration. The actual central processing unit 1100 has a wide variety of configurations depending on its application. For example, the central processing unit 1100 shown in FIG. 48 or a configuration including an arithmetic circuit is regarded as one core. A configuration that includes multiple cores and operates in parallel, such as a GPU. Also, the central processing unit 1100 may be configured as an internal processing circuit or a data bus. The number of bits that can be handled can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc. This can be done.

[0435] An instruction input to the central processing unit 1100 via the bus interface 1198 is The instruction is input to the instruction decoder 1193, decoded, and then passed to the ALU controller. controller 1192, interrupt controller 1194, register controller 1197, timer The signal is input to the timing controller 1195.

[0436] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the central processing unit During program execution, 1100 receives interrupt requests from external I / O devices and peripheral circuits. The register controller 1197 processes the registers according to their priority and mask state. The address of register 1196 is generated and the address of register 1196 is written according to the state of the central processing unit 1100. 196 reads and writes.

[0437] The timing controller 1195 also includes the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the operation timing of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generating unit supplies an internal clock signal to the various circuits described above.

[0438] In the central processing unit 1100 shown in FIG. A storage device is provided in the memory device 9. As the storage device, for example, A storage device or the like can be used.

[0439] In the central processing unit 1100 shown in FIG. According to the instruction from the LU 1191, the holding operation in the register 1196 is selected. That is, in the memory cell of the register 1196, the flip-flop The flip-flop selects whether to hold the data or to hold the data by a capacitive element. When data retention by the power supply is selected, the memory cells in the register 1196 are If data retention is selected in the capacitive element, a voltage is supplied to the capacitive element. The data is rewritten, and the supply of the power supply voltage to the memory cells in the register 1196 is stopped. It can be stopped.

[0440] The semiconductor device 400 and the central processing unit 1100 shown in the above embodiment are stacked. 49(A) and (B) show perspective views of the semiconductor device 1150A. The device 1150A includes a semiconductor device that functions as a memory device on the central processing unit 1100. The central processing unit 1100 and the semiconductor device 400 overlap each other. In order to make the configuration of the semiconductor device 1150A easier to understand, the center The processor 1100 and the semiconductor device 400 are shown separately.

[0441] By stacking the semiconductor device 400 and the central processing unit 1100, the connection distance between them is Therefore, the communication speed between the two can be increased. Since the distance is short, power consumption can be reduced.

[0442] As shown in the above embodiment, the semiconductor device 400 uses an OS NAND type memory device. In this way, a part or all of the memory cells 30 of the semiconductor device 400 can be used as a RAM. Therefore, the semiconductor device 400 can function as a main memory. The semiconductor device 400 functioning as a main memory can be implemented using a cache interface. The memory 1180 is connected to a cache 1199 via an interface 1189 .

[0443] The semiconductor device 400 functions as a main memory (RAM) or as a storage. The control circuit 412 shown in FIG. The circuit 412 controls the semiconductor device 4 based on a signal supplied from the central processing unit 1100. A part of the memory cells 30 in the memory cell array 00 can be made to function as a RAM.

[0444] The semiconductor device 400 functions as a RAM with some of the memory cells 30 functioning as a RAM and as a The semiconductor device 400 can function as an OS NAND type storage. By using this device, it has both main memory and storage functions. The semiconductor device 400 according to one aspect of the present invention can be used as, for example, a universal memory. It can function as.

[0445] In addition, when the semiconductor device 400 is used as a main memory, its storage capacity can be increased as needed. In addition, when the semiconductor device 400 is used as a cache, its storage capacity is required. This can be increased or decreased as needed.

[0446] The control circuit 412 shown in FIG. 43 serves as a storage for the semiconductor device 400. When moving or duplicating data between the area that functions and the area that functions as main memory , Error Check and Correction (ECC) function The control circuit 412 may also include a semiconductor device. The data is moved between the area functioning as the main memory of the device 400 and the cache 1199. The memory device may have a function for performing ECC when storing or copying the data.

[0447] In addition, a plurality of semiconductor devices 400 may be provided on top of the central processing unit 1100. 50(A) and (B) are perspective views of the semiconductor device 1150B. The central processing unit 1100 includes a semiconductor device 400a and a semiconductor device 400b. The central processing unit 1100, the semiconductor device 400a, and the semiconductor device 400b are In order to make the configuration of the semiconductor device 1150B easier to understand, the semiconductor device 1150B has an overlapping region. In FIG. 0(B), a central processing unit 1100, a semiconductor device 400a, and a semiconductor device 400b are shown separately.

[0448] The semiconductor device 400a and the semiconductor device 400b function as memory devices. The semiconductor device 400a may be a NOR type memory device. A NAND type memory device may be used as the NOR type memory device. Therefore, for example, a part of the semiconductor device 400a can be used as a main memory and The semiconductor device 400a and the semiconductor memory device 400b may be used as a memory and / or a cache 1199. The semiconductor device 400b may be stacked in the reverse order.

[0449] 51(A) and (B) show perspective views of the semiconductor device 1150C. C has a central processing unit 1100 sandwiched between a semiconductor device 400a and a semiconductor device 400b. Therefore, the central processing unit 1100, the semiconductor device 400a, and the semiconductor The device 400b has an overlapping area. In order to simplify the description, in FIG. 51(B), the central processing unit 1100, the semiconductor device 400a, and the semiconductor device Conductor arrangement 400b is shown in isolation.

[0450] By configuring the semiconductor device 1150C, the semiconductor device 400a and the central processing unit 11 00 and the communication speed between the semiconductor device 400b and the central processing unit 1100. In addition, the power consumption can be reduced more than that of the semiconductor device 1150B. .

[0451] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0452] (Embodiment 6) In this embodiment, application examples of a storage device according to one embodiment of the present invention will be described.

[0453] Generally, various memory devices are used in semiconductor devices such as computers depending on the application. FIG. 52A shows various memory devices used in a semiconductor device by layer. The higher the storage device is placed, the faster the operating speed is required, and the lower the storage device is placed, the larger the storage capacity is required. In Fig. 52(A), the top layer is the area where the CPU and other processors are located. SRAM (Static Random Access Memory) is a memory embedded in a processor as a register. ic Random Access Memory), DRAM (Dynamic Ra The reference refers to 3D NAND memory, or 3D NAND Access Memory.

[0454] The memory embedded as a register in a CPU or other arithmetic processing device is used for temporary storage of calculation results. Therefore, the frequency of access from the processor is high. Fast operating speed is required. Also, registers are used to hold setting information for the arithmetic processing unit. It also has Noh.

[0455] SRAM is used, for example, for caches. Caches are used to store data in the main memory. The function of replicating and storing part of the data stored in the main memory. By duplicating and storing frequently used data in the cache, The cache requires less memory than the main memory. Although the size of the cache is smaller than that of the main memory, it is required to operate faster than the main memory. The obtained data is replicated and provided to the main memory.

[0456] DRAM is used, for example, as a main memory. It has the function of storing programs and data read from the DRAM. The density is approximately 0.1Gbit / mm 2 More than 0.3Gbit / mm 2 The following is the result.

[0457] 3D NAND memory is used, for example, in storage. Storage is used for data that needs to be stored for a long period of time. It has the function of storing necessary data and various programs used by the processing unit. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. The recording density of the memory device used for storage is approximately 0.6 Gbit / mm 2 End of 6. 0Gbit / mm 2 The following is the result.

[0458] A storage device according to one embodiment of the present invention has high operation speed and can retain data for a long period of time. A storage device according to one aspect of the present invention has a hierarchy in which a cache is located and a hierarchy in which a main memory is located. It can be suitably used as a storage device located in a boundary area 901 that includes both hierarchical levels. In addition, in the storage device according to one aspect of the present invention, a hierarchy in which a main memory is located and a storage are located. The storage device can be suitably used as a storage device located in the boundary area 902 including both the hierarchical layers to be placed. Cut.

[0459] In addition, in the storage device according to one aspect of the present invention, a hierarchy in which a main memory is located and a storage are located. In addition, the storage device according to one embodiment of the present invention can be suitably used for both a layer in which the memory is placed and a layer in which the memory is placed. , it can be suitably used in the hierarchy where the cache is located. ) shows the hierarchy of various storage devices that are different from the

[0460] In FIG. 52(B), from the top layer, the registers are embedded in a processor such as a CPU. This refers to the memory used as a cache, SRAM, and 3D OS NAND memory. The cache, the main memory, and the storage are provided with a storage device according to one aspect of the present invention. It should be noted that a high-speed memory of 1 GHz or more is required for the cache. In such a case, the cache is integrated into a processor such as a CPU.

[0461] Furthermore, the memory device according to one embodiment of the present invention is not limited to a NAND type and may be a NOR type. Also, the NAND type and the NOR type may be used in combination.

[0462] The storage device according to one aspect of the present invention is, for example, a storage device for various electronic devices (for example, an information terminal, a computer, Data, smartphones, e-book readers, digital still cameras, video cameras, recording and playback The present invention can be applied to the storage devices of various equipment (e.g., image processing devices, navigation systems, game consoles, etc.). Used in sensors, IoT (Internet of Things), healthcare, etc. In this case, the computer can be a tablet computer or a notebook computer. In addition to large-scale computers such as server systems, This includes computers of the same type.

[0463] An example of an electronic device including a memory device of one embodiment of the present invention will be described. 53(A) to 53(J) and 54(A) to 54(E) show a power supply having the storage device. The figure shows how a child component 4700 or an electronic component 4730 is included in each electronic device. .

[0464] [mobile phone] The information terminal 5500 shown in FIG. 53(A) is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the case. The sensor 5510 is provided with a sensor body 5510.

[0465] The information terminal 5500 uses a storage device according to one embodiment of the present invention to execute an application. Temporary files that are generated when running applications (for example, cache files when using a web browser) It is possible to hold

[0466] [Wearable devices] FIG. 53(B) illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, an operation switch 5903, and an operation The optical fiber 5902 has an operational switch 5904, a band 5905, etc.

[0467] The wearable terminal, like the information terminal 5500 described above, includes a storage device according to one embodiment of the present invention. By applying this setting, you can store temporary files that are generated when the application is executed. It is possible.

[0468] [Information terminal] Also, FIG. 53C shows a desktop information terminal 5300. The laptop type information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard. 5303.

[0469] The desktop information terminal 5300 is an embodiment of the present invention, similar to the information terminal 5500 described above. By applying the above-mentioned storage device, temporary files generated during application execution can be The file can be held.

[0470] In the above, the electronic devices are smartphones, wearable devices, and desktop information devices. As an example of a communication terminal, the following are shown in Figs. 53(A) to (C). The present invention can be applied to information terminals other than wearable terminals and desktop information terminals. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include For example, PDA (Personal Digital Assistant), notebook type information Examples include terminals and workstations.

[0471] [electric appliances] FIG. 53(D) illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, and a freezer door 5803. 3. For example, the electric refrigerator-freezer 5800 is IoT (Internet of Things) This is an electric refrigerator-freezer that is compatible with the Refrigerator and Other Items.

[0472] A memory device according to one embodiment of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 is a refrigerator that can store food items stored in the refrigerator-freezer 5800 and consume those food items. Information such as deadlines can be sent and received to information terminals via the Internet, etc. The electric refrigerator-freezer 5800 stores the temporary file generated when transmitting the information. , can be stored in the storage device.

[0473] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances may also be used. For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, Water server, heating and cooling appliances including air conditioner, washing machine, dryer, audio Examples of such equipment include audiovisual equipment.

[0474] [Game consoles] FIG. 53(E) illustrates a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display unit 5202, buttons 5203, etc. .

[0475] Furthermore, FIG. 53(F) illustrates a stationary game machine 7500, which is an example of a game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 is connected to a controller 7522 by wire or wirelessly. Although not shown in FIG. 53(F), the controller 7522 can The display unit displays the image of the game, and the touch panel and screen serve as input interfaces other than buttons. It can have a tick, a rotary knob, a sliding knob, etc. The controller 7522 is not limited to the shape shown in FIG. 53(F), and may be changed according to the genre of the game. The shape of the controller 7522 may be changed in various ways. For example, the FPS (First Pressing System) In shooting games such as Robot Shooter, the trigger is a button, A controller shaped like a gun can be used. For example, in music games, In addition, controllers that mimic musical instruments and other musical equipment can be used. Stand-alone game consoles do not use controllers, but instead use cameras, depth sensors, and microphones. The game is equipped with a variety of functions, such as a gamepad, and can be controlled by the game player's gestures and / or voice. The format may also be as follows.

[0476] In addition, the images of the above-mentioned game machines can be displayed on television sets, displays for personal computers, etc. Display devices such as play, game displays, and head-mounted displays It can be output.

[0477] The portable game machine 5200 or the stationary game machine 7500 is By applying the memory device, a low-power portable game machine 5200 or a low-power It is possible to realize a stationary game machine 7500. In addition, due to the low power consumption, This reduces heat generation from the circuit itself, the surrounding circuits, and the module. This reduces the impact on the system.

[0478] Furthermore, the portable game machine 5200 or the stationary game machine 7500 may include the By applying this storage device, temporary files required for calculations that occur during game execution can be It is possible to hold files, etc.

[0479] As an example of a game machine, a portable game machine is shown in Fig. 53(E). Also, Fig. 53(F) shows a home game machine. Note that the electronic device of one embodiment of the present invention is not limited to this. As an example of an electronic device according to the present invention, an amusement facility (game center, amusement park, etc.) arcade game machines installed in sports facilities, and batting practice pitches installed in sports facilities Machines, etc.

[0480] [Mobile object] The storage device described in the above embodiment is used in a vehicle, which is a moving object, and in the vicinity of the driver's seat of the vehicle. can be applied to.

[0481] FIG. 53(G) shows an automobile 5700 as an example of a moving object.

[0482] Around the driver's seat of the 5700 car are a speedometer, tachometer, mileage and fuel gauge. The instrument panel provides various information by displaying the vehicle's speed, gear status, and air conditioning settings. The vehicle is equipped with a display panel that displays the information. It may be provided.

[0483] In particular, the display device receives an image from an imaging device (not shown) installed in the automobile 5700. By projecting an image, it is possible to compensate for visibility obstructed by pillars, blind spots around the driver's seat, etc. That is, the imaging device provided on the outside of the automobile 5700 can detect the vehicle and improve safety. By displaying images from the device, blind spots can be filled and safety can be increased.

[0484] The storage device described in the above embodiment can temporarily store information. For example, the storage device may be used for an automatic driving system of an automobile 5700, road guidance, risk prediction, etc. The display device can be used to temporarily store necessary information in a system or the like. In addition, temporary information such as road guidance and risk prediction may be displayed. The configuration may be such that the video recorded by a driving recorder installed in the vehicle 5700 is stored.

[0485] In the above description, an automobile is used as an example of a moving object. For example, the moving object may be a train, a monorail, a ship, or an aircraft (helicopter). , unmanned aerial vehicles (drones), airplanes, and rockets).

[0486] [camera] The storage device described in the above embodiment can be applied to a camera.

[0487] FIG. 53(H) shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, and a shutter. The digital camera 6240 has a detachable lens. In this example, the digital camera 6240 is attached with a lens 62 The lens 6246 can be removed from the housing 6241 and replaced. The housing 6241 may be integrated with the electronic device 6240. A camera device, a viewfinder, etc. may be separately attached.

[0488] By applying the storage device described in the above embodiment to the digital camera 6240, It is possible to realize a digital camera 6240 with low power consumption. Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and This reduces the impact on the system and modules.

[0489] [Video camera] The storage device described in the above embodiment can be applied to a video camera.

[0490] FIG. 53(I) shows a video camera 6300, which is an example of an imaging device. The digital camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, and an operation switch. The switch 6304, the lens 6305, the connection part 6306, etc. The lens 6305 is provided in the first housing 6301, and the display unit 6303 is provided in the second housing 63 The first housing 6301 and the second housing 6302 are connected to each other via a connection portion 63 6306, and the angle between the first housing 6301 and the second housing 6302 is The video on the display unit 6303 can be changed by the connection unit 6306. Alternatively, the switching may be performed according to the angle between the first housing 6301 and the second housing 6302. good.

[0491] When recording images taken with the 6300 video camera, the encoding is done according to the data recording format. By using the above-mentioned storage device, the video camera 6300 This allows you to store temporary files that are generated during encoding.

[0492] [ICD] The storage device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD). can.

[0493] FIG. 53(J) is a schematic cross-sectional view showing an example of an ICD. The ICD main body 5400 is a battery. A lee 5401, an electronic component 4700, a regulator, a control circuit, and an antenna 5404 , a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0494] The ICD body 5400 is placed in the body by surgery, and the two wires are inserted into the subclavian vein 5 405 and the superior vena cava 5406, one wire tip is inserted into the right ventricle, the other wire The catheter tip is placed in the right atrium.

[0495] The ICD main unit 5400 has a function as a pacemaker and detects when the heart rate is out of the specified range. In addition, if pacing does not improve the heart rate, In some cases (such as fast ventricular tachycardia or ventricular fibrillation), treatment is with an electric shock.

[0496] The ICD 5400 constantly monitors the heart rate to ensure proper pacing and shock delivery. It is necessary to monitor the heart rate. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 also stores the heart rate data acquired by the sensor. The electronic component 4700 can store the data, the number of times pacing therapy was performed, the time, etc. can.

[0497] In addition, the antenna 5404 can receive power, which is then used to charge the battery 5401. In addition, the ICD body 5400 has multiple batteries, which increases safety. Specifically, if some of the batteries in the ICD unit 5400 become unusable, Even if the power is turned off, the remaining battery can still function, so it can also function as an auxiliary power source.

[0498] In addition to the antenna 5404 capable of receiving power, an antenna capable of transmitting physiological signals is provided. For example, physiological signals such as pulse, respiratory rate, heart rate, and temperature may be monitored by an external monitor. The system may be configured to monitor cardiac activity such that it can be seen at the device.

[0499] [Extension device for PC] The storage device described in the above embodiment is a personal computer (PC), etc. The present invention can be applied to any computer or expansion device for information terminals.

[0500] FIG. 54(A) shows an example of the expansion device, which is portable and capable of storing information. The figure shows an expansion device 6100 that is external to a PC and has a chip mounted thereon. For example, the 6100 uses USB (Universal Serial Bus) By connecting it to a PC, information can be stored in the chip. FIG. 6A illustrates a portable expansion device 6100. The expansion device according to the embodiment is not limited to this, and may be, for example, a comparatively large expansion device equipped with a cooling fan or the like. A relatively large form of expansion device may also be used.

[0501] The expansion device 6100 includes a housing 6101, a cap 6102, a USB connector 6103, and The substrate 6104 is housed in a housing 6101. The memory device 04 is provided with a circuit for driving the memory device described in the above embodiment. For example, the electronic component 4700 and the controller chip 6106 are attached to the substrate 6104. The USB connector 6103 is an interface for connecting to an external device. It works like this.

[0502] [SD card] The storage device described in the above embodiment is installed in electronic devices such as information terminals and digital cameras. This can be applied to SD cards that can be attached.

[0503] Figure 54(B) is a schematic diagram of the external appearance of an SD card, and Figure 54(C) shows the internal structure of an SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate. A connector 5112 serves as an interface for connecting to an external device. The board 5113 is housed in a housing 5111. For example, the substrate 5113 includes electronic components. The electronic component 4700 has a controller chip 5115 attached thereto. The circuit configurations of the controller chip 5115 and the controller chip 5116 are not limited to those described above. The circuit configuration may be changed as appropriate depending on the circumstances. For example, The reading circuit, row driver, readout circuit, etc. are not electronic components 4700 but controller chips. It may also be configured so that it is incorporated into cup 5115.

[0504] By providing electronic components 4700 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. In addition, a wireless chip having a wireless communication function is provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110. This makes it possible to read and write data from and to the electronic component 4700.

[0505] [SSD] The storage device described in the above embodiment is an SSD that can be installed in electronic devices such as information terminals. (Solid State Drive).

[0506] FIG. 54(D) is a schematic diagram of the external appearance of an SSD, and FIG. 54(E) is a schematic diagram of the internal structure of an SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. A connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in a housing 5151. The board 5153 includes a storage device and a A circuit for driving the device is provided. For example, the substrate 5153 includes electronic components 4700, A memory chip 5155 and a controller chip 5156 are attached to the board 515. By installing electronic components 4700 on the back side of 3, the capacity of the SSD5150 can be increased. The memory chip 5155 has a built-in working memory. The chip 5155 may be a DRAM chip. The controller chip 5156 may be a It includes a processor, ECC circuit, etc. The circuit configurations of the chip 5155 and the controller chip 5156 are as described above. The circuit configuration may be changed as appropriate depending on the situation. For example, The processor 5156 may also be provided with a memory that functions as a work memory.

[0507] [Calculator] The computer 5600 shown in FIG. 55(A) is an example of a large-scale computer. The computer 5600 includes: A rack 5610 stores a plurality of rack-mounted computers 5620 .

[0508] The computer 5620 can have the configuration shown in the perspective view of FIG. In FIG. 5(B), a computer 5620 includes a motherboard 5630. 30 has a plurality of slots 5631 and a plurality of connection terminals. A C card 5621 is inserted. In addition, the PC card 5621 has a connection terminal 5623, The connector 5624 and the connector 5625 are connected to a motherboard 5630. It is being done.

[0509] The PC card 5621 shown in FIG. 55(C) is a processing The PC card 5621 includes a board 5622. 622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, and a semiconductor device. 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. In addition, in FIG. 55C, a semiconductor device 5626, a semiconductor device 5627, and a semiconductor Although semiconductor devices other than the body device 5628 are shown, the following description of those semiconductor devices will be provided. The semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 will be described below. Just take Ming into consideration.

[0510] The connection terminal 5629 is shaped so that it can be inserted into a slot 5631 of a motherboard 5630. The connection terminal 5629 connects the PC card 5621 and the motherboard 5630. It functions as an interface for connecting a 5629 connector. For example, PCIe is one example.

[0511] The connection terminals 5623, 5624, and 5625 are, for example, a PC card 562 It can be used as an interface for supplying power, inputting signals, etc. to 1. Also, for example, the interface for outputting signals calculated by the PC card 5621 is The connection terminal 5623, the connection terminal 5624, and the connection terminal 56 The 25 standards are, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Compute r System Interface). Also, connection terminal 5623, When outputting video signals from the connection terminals 5624 and 5625, An example of such a standard is HDMI (registered trademark).

[0512] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals. The terminal is inserted into a socket (not shown) provided on the board 5622, The device 5626 and the board 5622 can be electrically connected.

[0513] The semiconductor device 5627 has a plurality of terminals. The semiconductor device 5627 and the board are connected to each other by, for example, reflow soldering the wires. The semiconductor device 5627 can be, for example, FPGA (Field Programmable Gate Array), GPU, The semiconductor device 5627 may be, for example, an electronic component 4730. It is possible.

[0514] The semiconductor device 5628 has a plurality of terminals. The semiconductor device 5628 and the board are connected to each other by, for example, reflow soldering the wires. The semiconductor device 5628 can be, for example, As the semiconductor device 5628, for example, the electronic component 4700 is used. There can be.

[0515] The computer 5600 can also function as a parallel computer. This makes it possible to carry out the large-scale calculations required for artificial intelligence training and inference, for example. Cut.

[0516] By using the semiconductor device of one embodiment of the present invention in the various electronic devices described above, In addition, the semiconductor device according to one embodiment of the present invention can be made smaller, faster, or consumes less power. The semiconductor device consumes less power, so heat generated by the circuit can be reduced. The adverse effects of heat generation on the circuit itself, peripheral circuits, and modules can be reduced. By using the semiconductor device of one embodiment of the present invention, the operation is stable even in a high-temperature environment. Therefore, the reliability of the electronic device can be improved.

[0517] Next, a configuration example of a computer system applicable to the computer 5600 will be described. FIG. 56 is a diagram for explaining a configuration example of a computer system 700. The 700 system is a combination of software and hardware. The hardware included in the computer system is called an information processing device. There are cases where this happens.

[0518] The software constituting the computer system 700 includes device drivers. Operating systems, middleware, various development environments, AI-related applications AI Application, non-AI related applications Examples include programs (applications).

[0519] Device drivers include those that control external devices such as secondary storage devices, displays, and printers. This includes application programs for controlling the device.

[0520] The hardware constituting the computer system 700 includes a first arithmetic processing unit, a second arithmetic processing unit, The second arithmetic processing unit includes a second storage device. Yes.

[0521] The first processing unit may be, for example, a central processing unit such as a Noff OS CPU. It is recommended to use the Noff OS CPU with a storage means (e.g. , non-volatile memory), and when no operation is required, the necessary information is stored in the storage means. The first processor has a function to stop the power supply to the central processing unit. By using the f OS CPU, the power consumption of the computer system 700 can be reduced. do.

[0522] As the second arithmetic processing device, for example, a GPU or an FPGA can be used. It is preferable to use an AI OS Accelerator as the second arithmetic processing device. The AI ​​OS Accelerator is constructed using OS transistors and performs multiplication and addition operations. AI OS Accelerator has a computing means such as a general GPU. It consumes less power than other processors. AI OS Accelerato By using r, the power consumption of the computer system 700 can be reduced.

[0523] It is preferable to use a storage device according to one embodiment of the present invention as the first storage device and the second storage device. For example, it is preferable to use a 3D OS NAND type storage device. S NAND type storage devices function as cache, main memory, and storage. In addition, by using a 3D OS NAND type storage device, it is possible to achieve a non-Von Neumann type This makes it easier to realize a computer system.

[0524] 3D OS NAND type memory devices are 3D NAND type memory devices that use Si transistors. It consumes less power than a 3D OS NAND type memory device. This reduces the power consumption of the computer system 700. NAND type storage devices function as universal memory, making them ideal for computer systems. This allows the number of parts of the storage device required to configure the system 700 to be reduced.

[0525] The semiconductor device constituting the hardware is configured with a semiconductor device including an OS transistor. The hardware monolith includes a central processing unit, a processor, and a memory device. By making the hardware monolithic, it becomes possible to make the device smaller, lighter, and thinner. This not only simplifies the process but also facilitates further reduction in power consumption.

[0526] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0527] (Embodiment 7) Using a storage device according to one embodiment of the present invention, It is also called "U".) It is possible to realize the Noff-CPU. A normally-off transistor that is off even at 0V. It is an integrated circuit including:

[0528] The Noff-CPU stops supplying power to circuits in the Noff-CPU that are not required to operate, The circuit can be put into standby mode. When the power supply is stopped, the circuit in standby mode will not No power is consumed. Therefore, the Noff-CPU can minimize power consumption. In addition, the Noff-CPU can retain the necessary information for operation, such as settings, even if the power supply is cut off. The information can be retained for a long period of time. When the device returns from the standby state, the power supply to the circuit is resumed. It is not necessary to rewrite the settings, etc. In this way, the Noff-CPU can recover without significantly slowing down its operation speed. Power consumption can be reduced.

[0529] As a storage device to hold information such as settings when power to the Noff-CPU is cut off In addition, the memory device according to one embodiment of the present invention can be used. The memory device can also be used as a cache for the Noff-CPU. The storage device according to the present invention can also be used as the main memory of a Noff-CPU.

[0530] Noff-CPU is, for example, in the IoT (Internet of Things) field. IoT end devices (also called "endpoint microcontrollers"), small-scale systems such as 803 It can be suitably used for the following:

[0531] Figure 57 shows the hierarchical structure of the IoT network and the trend of required specifications. The power consumption 804 and processing performance 805 are shown as the hierarchical structure of the IoT network. The cloud is divided into an upper layer, the cloud field 801, and a lower layer, the embedded field 802. The loud domain 801 includes, for example, servers. The embedded domain 802 includes, for example, machines. This includes industrial robots, automotive equipment, home appliances, etc.

[0532] The higher the layer, the more the processing performance is required rather than the power consumption. In 01, we will develop high-performance CPUs, high-performance GPUs, and large-scale SoCs (System on a Chip). p) are used. Also, the lower the layer, the more important it is to consume less power than to have high processing performance. The number of devices will also increase explosively. This can be suitably used for communication devices of required IoT terminal devices.

[0533] The term "endpoint" refers to a terminal area of ​​the embedded field 802. Examples of devices used in this field include those used in factories, home appliances, infrastructure, agriculture, etc. This applies to microcontrollers.

[0534] Figure 58 shows an example of an application of an endpoint microcontroller in factory automation. The page diagram is shown below. Factory 884 is connected to the cloud via the Internet. Cloud 883 is connected to the server via the Internet. The Internet is connected to the home 881 and the office 882. For example, in the case of a wireless communication system, The semiconductor device according to one embodiment of the present invention is used in a device for a fourth-generation mobile communication system (4G) or Wireless communication can be performed according to communication standards such as the 5th generation mobile communication system (5G). In addition, Factory 884 is connected to Factory 885 and Factory 886 via the Internet. Good too.

[0535] The factory 884 has a master device (control device) 831. The master device 831 has a function of connecting to the loudspeaker 883 and transmitting and receiving information. , multiple industrial robots 842 included in IoT terminal devices 841 and M2M (Machi The M2M interface is connected via a network to machine (M2M) interface 832. The interface 832 may be, for example, an industrial Ethernet (" "Ethernet" is a registered trademark) or local 5G, a type of wireless communication method. good.

[0536] Factory managers can manage the factory from home 881 or office 882 via cloud 883. You can connect to 884 to find out the operating status. You can also check for incorrect or missing items, and check the storage location. It is possible to give instructions, measure takt time, etc.

[0537] In recent years, the introduction of IoT into factories, known as "smart factories," has been progressing worldwide. In the case of the Mart factory, not only was the endpoint microcomputer used for simple inspection and auditing, but also for failure detection and There have been reported cases where it has also been used to detect faults and predict anomalies.

[0538] Small-scale systems such as endpoint microcontrollers consume little power during operation. Therefore, the proportion of power consumption that is consumed by the CPU tends to be large. In small-scale systems such as endpoint microcontrollers, the Noff-CPU is used during standby operation. The power saving effect is large. On the other hand, in the embedded field of IoT, quick response is required. However, by using a Noff-CPU, high-speed recovery from standby mode can be achieved.

[0539] The configuration, structure, method, etc. shown in this embodiment may be the same as the configuration, structure, method, etc. shown in other embodiments. The method can be used in combination with other methods. [Explanation of symbols]

[0540] 100 memory cells 101 Insulators 102 Conductor 103 Conductors 108 Center axis 111 Insulators 112 Conductors 113 Semiconductors 114 Semiconductors 115 Insulators 116 Semiconductors 117 Insulators 118 Conductor 121 Semiconductors 122 Insulators 123 Insulator 130 Structure 131 Aperture 132 areas 135 areas 136 areas 140 Laminate 141 Sacrificial Layer

Claims

[Claim 1] A structure extending in a first direction; a first conductor extending in a second direction; a second conductor extending in the second direction; The structure comprises: a third conductor extending in the first direction; a first insulator adjacent to the third conductor; a first semiconductor adjacent to the first insulator; a second insulator adjacent to the first semiconductor; having At a first intersection where the structure and the first conductor intersect, Between the structure and the first conductor, a second semiconductor adjacent to the second insulator; a third insulator adjacent to the second semiconductor; At a second intersection where the structure and the second conductor intersect, The structure comprises: a fourth conductor adjacent to the second insulator; a fourth insulator adjacent to the fourth conductor; At the first intersection, the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator are provided concentrically outside the third conductor; A semiconductor device, wherein at the second intersection, the first insulator, the first semiconductor, the second insulator, the fourth conductor, and the fourth insulator are concentrically arranged outside the third conductor.

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