Liquid crystal display device and driving method of the same

Abstract

To provide a liquid crystal display device characterized in that refreshing is performed perfectly synchronously with an externally inputted image signal, and inhibit degradation of display quality due to a deviation in the polarity of a data voltage.SOLUTION: A drive control circuit 100 that controls the operation of a liquid crystal drive circuit (gate driver and source driver) includes a counter 130 that counts a polarity deviation value which represents a deviation in the polarity of a data voltage applied to a liquid crystal capacity. During a scan frame period in which the polarity deviation value at an input initiation point of an image signal DIN for one frame is larger than a predetermined upper limit value, the drive control circuit 100 controls the operation of the liquid crystal drive circuit so that the polarity deviation value gets smaller. During a scan frame period in which the polarity deviation value at the input initiation point of the image signal DIA for one frame is smaller than a predetermined lower limit value, the drive control circuit 100 controls the operation of the liquid crystal drive circuit so that the polarity deviation value gets larger.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The following disclosure relates to a liquid crystal display device that performs pause driving and a method for driving the same. [Background technology]

[0002] Conventionally, liquid crystal display devices having a display section including a plurality of source bus lines (video signal lines) and a plurality of gate bus lines (scanning signal lines) have been known. At the intersections of the source bus lines and the gate bus lines, pixel formation sections for forming pixels are provided. Each pixel formation section includes a thin film transistor (TFT) that is a switching element having a gate terminal connected to the gate bus line passing through the corresponding intersection and a source terminal connected to the source bus line passing through the intersection, a liquid crystal capacitance for holding a data voltage, and the like. Such liquid crystal display devices are used in various electronic devices such as in-vehicle displays such as television receivers and car navigation devices, notebook computers, and mobile terminals such as smartphones and tablet terminals.

[0003] In recent years, there has been an increasing demand for lower power consumption in liquid crystal display devices. Conventional liquid crystal display devices are driven at a drive frequency (frame frequency) of 60 Hz. However, the higher the drive frequency, the greater the power consumption. Therefore, there has been active development of technology to reduce the drive frequency in order to reduce power consumption. One such technology is known as "pause drive," which provides a pause frame period during which the operation of writing data voltages to the liquid crystal capacitance is paused. In liquid crystal display devices that employ pause drive, there is no need to provide control signals to the liquid crystal drive circuit (gate driver or source driver) during the pause frame period. As a result, the drive frequency of the liquid crystal drive circuit as a whole is reduced, making it possible to reduce power consumption. Note that pause drive is also called "low frequency drive" or "intermittent drive."

[0004] Here, referring to FIG. 12, the problem regarding the pause drive will be described. In FIG. 12, the shaded rectangular portion in the column marked "DIN" represents the period during which an image signal is input from the outside to the liquid crystal display device, the shaded rectangular portion in the column marked "UPDATE" represents the period during which a data voltage is written (updated) to the liquid crystal capacitance based on the image signal input from the outside, and the shaded rectangular portion in the column marked "UPDATE" represents the period during which a data voltage is written (updated) to the liquid crystal capacitance based on the image signal stored in the frame memory or the like. In addition, the column marked "Polarity" represents the polarity of the data voltage applied to the liquid crystal capacitance in a certain pixel formation portion. This also applies to FIG. 4 to FIG. 8 and FIG. 13. In the example shown in FIG. 12, the polarity of the data voltage is inverted irregularly, and the total length of the negative polarity period is longer than the total length of the positive polarity period for the data voltage applied to the liquid crystal capacitance in the corresponding pixel formation portion. As a result, the display quality is degraded, such as the occurrence of flicker. In the following description, the term "refresh" refers to updating a display image by writing a data voltage to the liquid crystal capacitance in each pixel formation portion in the display portion by sequentially and selectively driving a plurality of gate bus lines in the display portion.

[0005] As a measure to address the degradation of display quality caused by irregular polarity reversals of the data voltage, a driving method (hereinafter referred to as the "conventional method") has been proposed in which "a polarity bias value that indicates the bias in the polarity of the data voltage is counted, and when the polarity bias value reaches a threshold value (upper limit and lower limit), the polarity of the data voltage is reversed to refresh the display" (see, for example, the pamphlet of International Publication No. 2015 / 087587).

[0006] The above-mentioned conventional method will be described with reference to FIG. 13. In FIG. 13, the part marked with the reference symbol 8 shows the change in the polarity bias value. Pmax is the upper limit (positive threshold) of the polarity bias value, and -Pmax is the lower limit (negative threshold) of the polarity bias value. The same applies to FIG. 4, FIG. 6, and FIG. 8. As shown in FIG. 13, the polarity bias value increases during a period in which the polarity of the data voltage applied to the liquid crystal capacitance in a certain pixel formation portion is positive, and decreases during a period in which the polarity of the data voltage applied to the liquid crystal capacitance in the certain pixel formation portion is negative. For example, during the period from time t91 to time t92, the polarity of the data voltage is negative, and the polarity bias value decreases continuously. Then, at time t92, the polarity bias value reaches the lower limit (-Pmax). Therefore, at time t92, a refresh is performed with the polarity of the data voltage reversed. After that, in the period from time t92 to time t93, the polarity of the data voltage is positive, and the polarity bias value continues to increase. Then, at time t93, the polarity bias value reaches the upper limit value (Pmax). Therefore, at time t93, refresh is performed with the polarity of the data voltage reversed. In this way, the polarity bias value changes within the range from the lower limit value to the upper limit value. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2015 / 087587 Brochure Summary of the Invention [Problem to be solved by the invention]

[0008] According to the conventional method (see FIG. 13), the polarity of the data voltage applied to each liquid crystal capacitance is balanced, so that the degradation of display quality caused by irregular polarity inversion of the data voltage is suppressed. However, the conventional method can only be adopted in a liquid crystal display device that can perform refreshing asynchronously with the input of an image signal. In other words, the conventional method cannot be adopted for a liquid crystal display device in which refreshing is performed completely in synchronization with the input of an image signal. In other words, the conventional method cannot be adopted in a system in which a host that provides an image signal to a liquid crystal display device and the driving of the liquid crystal display device are performed completely in synchronization.

[0009] Therefore, the following disclosure aims to suppress the degradation of display quality caused by the bias of the polarity of the data voltage in a liquid crystal display device in which refreshing is performed completely in synchronization with an image signal input from the outside. [Means for solving the problem]

[0010] (1) A liquid crystal display device according to some embodiments of the present invention has a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to correspond to respective intersections of the plurality of video signal lines and the plurality of scanning signal lines, and is provided with a scanning frame period during which the plurality of scanning signal lines are selectively driven in sequence in synchronization with an externally input image signal, and a pause frame period during which driving of the plurality of scanning signal lines is paused, a video signal line drive circuit that drives the plurality of video signal lines so that a data voltage corresponding to the image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; a drive control circuit including a counter that counts a polarity bias value that indicates a polarity bias of the data voltage applied to the liquid crystal capacitance, and controls operations of the video signal line drive circuit and the scanning signal line drive circuit in response to the polarity bias value; Equipped with during a scanning frame period in which the polarity bias value is greater than a predetermined upper limit value at the time when input of one frame of the image signal is started, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so as to reduce the polarity bias value; during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes larger; During a scanning frame period in which the polarity bias value is greater than or equal to the lower limit value and less than or equal to the upper limit value at the time when input of one frame's worth of the image signal begins, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so that a data voltage of opposite polarity to the data voltage applied to the liquid crystal capacitance during the immediately preceding scanning frame period is applied to the liquid crystal capacitance.

[0011] (2) Furthermore, a liquid crystal display device according to some embodiments of the present invention includes the configuration of (1) above, The counter counts the polarity bias value throughout the scan frame period and the pause frame period.

[0012] (3) Furthermore, a liquid crystal display device according to some embodiments of the present invention includes the configuration of (1) above, the scanning frame period includes a vertical blanking period; The counter counts the polarity bias value throughout the vertical blanking period and the pause frame period.

[0013] (4) Furthermore, a liquid crystal display device according to some embodiments of the present invention includes the configuration of (3) above, the drive control circuit includes an average pixel value calculation circuit that calculates an average pixel value that is an average value of pixel values ​​of the plurality of pixel formation portions based on the image signal for one frame, If the coefficient corresponding to the average pixel value is represented by K and a predetermined constant is represented by C, the counter increases or decreases the polarity bias value by K×C per unit time depending on the polarity of the data voltage applied to the liquid crystal capacitance.

[0014] (5) Furthermore, a liquid crystal display device according to some embodiments of the present invention includes any one of the configurations (1) to (4) above, The drive control circuit determines whether or not the polarity bias value is equal to or greater than the lower limit and equal to or less than the upper limit at the time when input of the image signal for one frame starts, based on flag data which is binary data.

[0015] (6) Furthermore, a liquid crystal display device according to some embodiments of the present invention includes the configuration of (5) above, The flag data is updated every time the polarity bias value changes, based on the changed polarity bias value.

[0016] (7) Furthermore, a liquid crystal display device according to some embodiments of the present invention includes the configuration of (5) above, The flag data is updated based on the polarity bias value at the time when input of one frame of the image signal starts.

[0017] (8) Furthermore, a liquid crystal display device according to some embodiments of the present invention has a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to correspond to respective intersections of the plurality of video signal lines and the plurality of scanning signal lines, and is provided with a scanning frame period during which the plurality of scanning signal lines are selectively driven in sequence and a pause frame period during which driving of the plurality of scanning signal lines is paused, a video signal line driving circuit that drives the plurality of video signal lines so that a data voltage corresponding to an externally input image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; a drive control circuit including a counter that counts a polarity bias value that indicates a polarity bias of the data voltage applied to the liquid crystal capacitance, and controls operations of the video signal line drive circuit and the scanning signal line drive circuit in response to the polarity bias value; a frame memory for storing one frame of the image signal; Equipped with a driving system is dynamically switched between a first system in which the plurality of scanning signal lines are driven in synchronization with the image signal and a second system in which the plurality of scanning signal lines are driven asynchronously with the image signal; When the drive system is the first system, during a scanning frame period in which the polarity bias value is greater than a predetermined upper limit value at the time when input of one frame of the image signal is started, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so as to reduce the polarity bias value; during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes larger; during a scanning frame period in which the polarity bias value is equal to or greater than the lower limit value and equal to or less than the upper limit value at the time when input of one frame of the image signal is started, the drive control circuit controls operations of the video signal line drive circuit and the scanning signal line drive circuit so that a data voltage having a polarity opposite to that of the data voltage applied to the liquid crystal capacitance in the immediately preceding scanning frame period is applied to the liquid crystal capacitance; When the drive system is the second system, when the polarity bias value reaches the upper limit value, the drive control circuit uses the image signal stored in the frame memory to control the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes smaller; when the polarity bias value reaches the lower limit value, the drive control circuit uses the image signal stored in the frame memory to control the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes larger; During a scanning frame period in which the polarity bias value has not reached either the upper limit value or the lower limit value, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so that a data voltage of an opposite polarity to the polarity of the data voltage applied to the liquid crystal capacitance during the immediately preceding scanning frame period is applied to the liquid crystal capacitance.

[0018] (9) According to some embodiments of the present invention, there is provided a driving method for a liquid crystal display device having a scanning frame period in which a plurality of scanning signal lines are selectively driven in sequence in synchronization with an externally input image signal, and a pause frame period in which driving of the plurality of scanning signal lines is paused, the method comprising the steps of: The liquid crystal display device includes: a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to respectively correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines; a video signal line drive circuit that drives the plurality of video signal lines so that a data voltage corresponding to the image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; Equipped with The driving method includes: a polarity bias value counting step of counting a polarity bias value representing a polarity bias of the data voltage applied to the liquid crystal capacitance; a drive control step of controlling operations of the video signal line drive circuit and the scanning signal line drive circuit in accordance with the polarity bias value during the scanning frame period; Including, In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is greater than a predetermined upper limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes smaller; In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes larger; In the drive control step during a scanning frame period in which the polarity bias value is equal to or greater than the lower limit value and equal to or less than the upper limit value at the time when input of one frame's worth of the image signal is started, the operation of the video signal line drive circuit and the scanning signal line drive circuit is controlled so that a data voltage of opposite polarity to the data voltage applied to the liquid crystal capacitance during the immediately preceding scanning frame period is applied to the liquid crystal capacitance.

[0019] (10) According to some embodiments of the present invention, there is provided a driving method for a liquid crystal display device having a scanning frame period in which a plurality of scanning signal lines are selectively driven in sequence and a pause frame period in which driving of the plurality of scanning signal lines is paused, the driving method comprising the steps of: The liquid crystal display device includes: a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to respectively correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines; a video signal line driving circuit that drives the plurality of video signal lines so that a data voltage corresponding to an externally input image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; a frame memory for storing one frame of the image signal; Equipped with In the liquid crystal display device, a drive system is dynamically switched between a first system in which the plurality of scanning signal lines are driven in synchronization with the image signal and a second system in which the plurality of scanning signal lines are driven asynchronously with the image signal, The driving method includes: a polarity bias value counting step of counting a polarity bias value representing a polarity bias of the data voltage applied to the liquid crystal capacitance; a drive control step of controlling operations of the video signal line drive circuit and the scanning signal line drive circuit in accordance with the polarity bias value during the scanning frame period; Including, When the drive system is the first system, In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is greater than a predetermined upper limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes smaller; In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes larger; in the drive control step in a scanning frame period in which the polarity bias value is equal to or greater than the lower limit value and equal to or less than the upper limit value at the time when input of the image signal for one frame is started, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that a data voltage having a polarity opposite to a polarity of a data voltage applied to the liquid crystal capacitance in the immediately preceding scanning frame period is applied to the liquid crystal capacitance, When the drive system is the second system, When the polarity bias value reaches the upper limit value, in the drive control step, the operation of the video signal line drive circuit and the scanning signal line drive circuit is controlled using the image signal stored in the frame memory so that the polarity bias value becomes smaller, When the polarity bias value reaches the lower limit value, in the drive control step, the operation of the video signal line drive circuit and the scanning signal line drive circuit is controlled using the image signal stored in the frame memory so that the polarity bias value increases by applying the data voltage to the liquid crystal capacitance, In the drive control step during a scanning frame period in which the polarity bias value has not reached either the upper limit value or the lower limit value, the operation of the video signal line drive circuit and the scanning signal line drive circuit is controlled so that a data voltage of opposite polarity to the data voltage applied to the liquid crystal capacitance during the immediately preceding scanning frame period is applied to the liquid crystal capacitance. Effect of the Invention

[0020] According to some embodiments of the liquid crystal display device of the present invention, refresh (writing data voltages into liquid crystal capacitances in each pixel formation section in the display section by sequentially and selectively driving a plurality of scanning signal lines in the display section to update a display image) is performed in synchronization with an image signal input from the outside. In such a liquid crystal display device, a drive control circuit that controls the operation of a liquid crystal drive circuit (scanning signal line drive circuit and video signal line drive circuit) is provided with a counter that counts a polarity bias value that indicates a polarity bias of the data voltage. Then, when an image signal is input, the operation of the liquid crystal drive circuit is controlled as follows based on the polarity bias value. For a scanning frame period in which the polarity bias value at the start of input of one frame's worth of image signal is greater than the upper limit value, the operation of the liquid crystal drive circuit is controlled so that the polarity bias value becomes smaller, and for a scanning frame period in which the polarity bias value at the start of input of one frame's worth of image signal is less than the lower limit value, the operation of the liquid crystal drive circuit is controlled so that the polarity bias value becomes larger. Therefore, by appropriately setting the upper limit value and the lower limit value, it is possible to prevent the polarity of the data voltage from becoming so greatly biased that it affects the display quality. As described above, in a liquid crystal display device in which refreshing is performed completely in synchronization with an externally input image signal, degradation of display quality caused by bias in the polarity of data voltages is suppressed. [Brief description of the drawings]

[0021] [Figure 1] 1 is a block diagram showing a configuration of a drive control circuit in a first embodiment. [Diagram 2] FIG. 2 is a block diagram showing an overall configuration of a liquid crystal display device in the first embodiment. [Diagram 3] FIG. 11 is a diagram for explaining dot inversion driving. [Figure 4] FIG. 4 is a diagram for explaining an example of operation in the first embodiment. [Diagram 5] FIG. 5 is an enlarged view of a portion indicated by reference numeral 51 in FIG. [Figure 6] FIG. 11 is a diagram for explaining a change timing of a fixed mode flag in a modification of the first embodiment. [Figure 7] FIG. 11 is a diagram illustrating a vertical blanking period in the second embodiment. [Figure 8] FIG. 13 is a diagram for explaining a change in polarity bias value in the second embodiment. [Figure 9] FIG. 13 is a block diagram showing a configuration of a drive control circuit in a modified example of the second embodiment. [Figure 10] FIG. 13 is a block diagram showing a configuration of a drive control circuit in a third embodiment. [Figure 11] FIG. 13 is a diagram for explaining switching of a drive system in the third embodiment. [Figure 12] FIG. 13 is a diagram for explaining a problem related to pause driving. [Figure 13] FIG. 1 is a diagram for explaining a conventional method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Regarding the second and third embodiments, differences from the first embodiment will be mainly described. Note that the "polarity bias of the data voltage applied to the liquid crystal capacitance" is sometimes simply referred to as "polarity bias."

[0023] <1. First embodiment> <1.1 Overall configuration and operation overview> Fig. 2 is a block diagram showing the overall configuration of an active matrix type liquid crystal display device 1 according to the first embodiment. This liquid crystal display device 1 includes a drive control circuit 100, a gate driver (scanning signal line drive circuit) 200, a source driver (video signal line drive circuit) 300, and a display unit 400. As shown in Fig. 2, this liquid crystal display device 1 is connected to a host 2, and receives from the host 2 an image signal DIN representing an image to be displayed, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync.

[0024] The display section 400 is provided with a plurality (n) of source bus lines (video signal lines) SL1 to SLn and a plurality (m) of gate bus lines (scanning signal lines) GL1 to GLm. A pixel formation section 4 for forming pixels is provided at each intersection of the n source bus lines SL1 to SLn and the m gate bus lines GL1 to GLm. That is, the display section 400 includes a plurality (n×m) of pixel formation sections 4. Each pixel formation section 4 includes a thin film transistor (TFT) 40, which is a switching element having a gate terminal connected to a gate bus line GL passing through the corresponding intersection and a source terminal connected to a source bus line SL passing through the intersection, a pixel electrode 41 connected to the drain terminal of the thin film transistor 40, a common electrode 44 and an auxiliary capacitance electrode 45 provided in common to the plurality of pixel formation sections 4, a liquid crystal capacitance 42 formed by the pixel electrode 41 and the common electrode 44, and an auxiliary capacitance 43 formed by the pixel electrode 41 and the auxiliary capacitance electrode 45. The liquid crystal capacitance 42 and the auxiliary capacitance 43 form a pixel capacitance 46. It is also possible to adopt a configuration that does not include the auxiliary capacitance 43. Note that only one pixel formation portion 4 is shown in FIG.

[0025] The drive control circuit 100 receives an image signal DIN, a vertical synchronization signal Vsync, and a horizontal synchronization signal Hsync, and outputs a digital video signal DV, a gate control signal GCTL for controlling the operation of the gate driver 200, a source control signal SCTL for controlling the operation of the source driver 300, and a polarity control signal POL for controlling the polarity of the data voltage applied to each liquid crystal capacitance 42. In this manner, the drive control circuit 100 controls the operation of the gate driver 200 and the source driver 300. The gate control signal GCTL includes, for example, a gate start pulse signal, a clear signal, and a gate clock signal. The source control signal SCTL includes, for example, a source start pulse signal, a source clock signal, and a latch strobe signal.

[0026] Based on a gate control signal GCTL sent from the drive control circuit 100, the gate driver 200 selectively drives the m gate bus lines GL1 to GLm in sequence.

[0027] The source driver 300 drives n source bus lines SL1 to SLn based on a digital video signal DV, a source control signal SCTL, and a polarity control signal POL sent from the drive control circuit 100. At this time, the source driver 300 sequentially holds a digital video signal DV indicating a voltage to be applied to each source bus line SL at a timing when a pulse of a source clock signal is generated. Then, at a timing when a pulse of a latch strobe signal is generated, the held digital video signal DV is converted into a data voltage, which is an analog voltage, taking into account the polarity control signal POL. The data voltage is applied simultaneously to the n source bus lines SL1 to SLn as a driving video signal.

[0028] In this manner, a data voltage is applied to the n source bus lines SL1 to SLn, and the m gate bus lines GL1 to GLm are selectively driven in sequence, whereby an image based on the image signal DIN is displayed on the display unit 400.

[0029] Incidentally, the operating period of the liquid crystal display device 1 according to this embodiment includes a scan frame period (i.e., a scan frame period in which a refresh is performed) in which the m gate bus lines GL1 to GLm are selectively driven in sequence to write a data voltage to the liquid crystal capacitance 42 in each pixel formation portion 4 in the display unit 400, and a pause frame period in which the driving of the m gate bus lines GL1 to GLm is paused. That is, the liquid crystal display device 1 according to this embodiment employs pause driving. Furthermore, in the liquid crystal display device 1 according to this embodiment, refresh is performed in synchronization with the image signal DIN. In other words, the liquid crystal display device 1 according to this embodiment is driven in complete synchronization with the output of a signal (image signal DIN) by the host 2.

[0030] The method of polarity inversion of the data voltage is not particularly limited, but it is assumed in this embodiment that dot inversion driving is adopted. The dot inversion driving is a driving method that inverts the polarity between adjacent pixel formation parts in the direction in which the gate bus lines GL extend, and inverts the polarity between adjacent pixel formation parts in the direction in which the source bus lines SL extend. Also, for example, when attention is paid to the polarity of the data voltage (liquid crystal application voltage) in the (16×8) pixel formation parts 4 provided corresponding to the intersections of the 16 gate bus lines GL1 to GL16 and the 8 source bus lines SL1 to SL8, if the state before polarity inversion is as shown in part A of FIG. 3, the state after polarity inversion will be as shown in part B of FIG. 3.

[0031] <1.2 Drive control circuit> Next, the drive control circuit 100 will be described.

[0032] <1.2.1 Specific data> First, the specific data used in the drive control circuit 100 will be described. The liquid crystal display device 1 according to this embodiment employs pause driving, and polarity inversion is performed irregularly. Therefore, it is necessary to be able to grasp the polarity of the data voltage in the plurality of pixel formation parts 4 in the display part 400 throughout the period during which the liquid crystal display device 1 is in operation. Therefore, polarity information is used that indicates whether the polarity state of the data voltage is as shown in part A of FIG. 3 or as shown in part B of FIG. 3. In the following, for convenience, attention is paid to the polarity of the data voltage in the pixel formation part 4 provided corresponding to the intersection of the gate bus line GL1 of the first row and the source bus line SL1 of the first column. Therefore, a description to the effect that "the polarity of the data voltage is positive" means that the polarity state of the data voltage is as shown in part A of FIG. 3, and a description to the effect that "the polarity of the data voltage is negative" means that the polarity state of the data voltage is as shown in part B of FIG. 3.

[0033] In order to suppress the deterioration of the display quality caused by the polarity bias of the data voltage, it is necessary to be able to grasp the degree of polarity bias throughout the period during which the liquid crystal display device 1 is operating. Therefore, a polarity bias value that indicates the polarity bias of the data voltage applied to the liquid crystal capacitance 42 is used. The polarity bias is the difference between the total time during which a positive data voltage is applied to a certain pixel formation portion 4 and the total time during which a negative data voltage is applied to the certain pixel formation portion 4. In addition, in order to prevent the polarity bias from becoming too large, an upper limit value and a lower limit value are set as threshold values ​​to be compared with the polarity bias value. Then, a flag (flag data) is used to indicate whether the polarity bias value is within the range from the lower limit value to the upper limit value. Incidentally, as will be described in detail later, when the polarity bias value becomes smaller than the lower limit value, the polarity of the data voltage is fixed to positive polarity, and when the polarity bias value becomes larger than the upper limit value, the polarity of the data voltage is fixed to negative polarity. An operation mode in which the polarity of the data voltage is fixed in this manner is called a "fixed mode". Therefore, the flag indicating whether the polarity bias value is within the range from the lower limit to the upper limit is called the "fixed mode flag." During the period in which the polarity bias value is maintained within the range from the lower limit to the upper limit, polarity inversion is performed every time one frame of image signal DIN is input. Therefore, the operating mode during the period in which the polarity bias value is maintained within the range from the lower limit to the upper limit is called the "inversion mode." Hereinafter, it is assumed that when the fixed mode flag is ON, the operating mode is the fixed mode, and when the fixed mode flag is OFF, the operating mode is the inversion mode.

[0034] <1.2.2 Configuration> In light of the above, the configuration of the drive control circuit in this embodiment will be described with reference to the block diagram shown in Fig. 1. As shown in Fig. 1, the drive control circuit 100 includes a polarity control circuit 110, a polarity information register 120, a counter 130, a mode register 140, and a mode control circuit 150.

[0035] The polarity information register 120 holds the above-mentioned polarity information. The polarity information is binary data. The counter 130 counts the above-mentioned polarity bias value based on the polarity information held in the polarity information register 120. The counter 130 counts the polarity bias value throughout the scan frame period and the pause frame period. In this regard, the polarity bias value increases during a period in which the polarity of the data voltage is positive, and decreases during a period in which the polarity of the data voltage is negative.

[0036] The fixed mode flag described above is held in the mode register 140. The fixed mode flag is binary data. Every time the polarity bias value counted by the counter 130 changes, the mode control circuit 150 compares the changed polarity bias value with the lower limit value and the upper limit value, and updates the fixed mode flag held in the mode register 140 based on the result of the comparison. In this regard, when the polarity bias value changes from a state where it is greater than or equal to the lower limit to a state where it is less than the lower limit, the mode control circuit 150 updates the fixed mode flag from OFF to ON, when the polarity bias value changes from a state where it is less than the lower limit to a state where it is greater than or equal to the lower limit, the mode control circuit 150 updates the fixed mode flag from ON to OFF, when the polarity bias value changes from a state where it is less than the upper limit to a state where it is greater than the upper limit, the mode control circuit 150 updates the fixed mode flag from OFF to ON, and when the polarity bias value changes from a state where it is greater than the upper limit to a state where it is less than the upper limit, the mode control circuit 150 updates the fixed mode flag from ON to OFF.

[0037] At the start of input of one frame's worth of image signal DIN to the drive control circuit 100, the polarity control circuit 110 determines the polarity of the data voltage to be applied to the liquid crystal capacitance 42 during the scanning frame period corresponding to that one frame's worth of image signal DIN, based on the polarity information held in the polarity information register 120, the polarity bias value output from the counter 130, and the fixed mode flag held in the mode register 140. Then, the polarity control circuit 110 outputs a polarity control signal POL indicating the determined polarity. In this regard, specifically, the polarity control circuit 110 determines the polarity of the data voltage as follows.

[0038] If the fixed mode flag is ON and the polarity bias value is greater than the upper limit, the polarity control circuit 110 determines the polarity of the data voltage to be negative. If the polarity fixed mode flag is ON and the polarity bias value is less than the lower limit, the polarity control circuit 110 determines the polarity of the data voltage to be positive. If the fixed mode flag is OFF, the polarity control circuit 110 determines the polarity of the data voltage to be the opposite polarity to the polarity indicated by the polarity information held in the polarity information register 120. After determining the polarity of the data voltage in each scanning frame period, the polarity control circuit 110 updates the polarity information held in the polarity information register 120.

[0039] As described above, during a scanning frame period in which the polarity bias value at the time when the input of one frame of the image signal DIN starts is greater than a predetermined upper limit value, the drive control circuit 100 controls the operation of the source driver 300 and the gate driver 200 so as to reduce the polarity bias value. During a scanning frame period in which the polarity bias value at the time when the input of one frame of the image signal DIN starts is less than a predetermined lower limit value, the drive control circuit 100 controls the operation of the source driver 300 and the gate driver 200 so as to increase the polarity bias value (so as to reduce the absolute value of the polarity bias value). During a scanning frame period in which the polarity bias value at the time when the input of one frame of the image signal DIN starts is greater than or equal to the lower limit value and less than or equal to the upper limit value, the drive control circuit 100 controls the operation of the source driver 300 and the gate driver 200 so as to apply to the liquid crystal capacitance 42 a data voltage of the opposite polarity to the polarity of the data voltage applied to the liquid crystal capacitance 42 in the immediately preceding scanning frame period.

[0040] The polarity bias value counting step is realized by the operation of the counter 130 counting the polarity bias value, and the drive control step is realized by the operation of the drive control circuit 100 controlling the operation of the source driver 300 and the gate driver 200 based on the polarity bias value.

[0041] <1.2.3 Example of operation> An operation example in this embodiment will be described with reference to FIG. 4 and FIG. 5. FIG. 5 is an enlarged view of a portion marked with a symbol 51 in FIG. 4. In FIG. 5, an arrow marked with a symbol SF indicates a scanning frame period, and an arrow marked with a symbol BF indicates a pause frame period. For convenience of explanation, it is assumed here that the length of one scanning frame period and the length of one pause frame period are equal to the length of one frame period when normal driving is performed with a driving frequency of 60 Hz. For example, in the period represented by the arrow marked with a symbol T01 in FIG. 5, one frame of image signal DIN is input for each frame period when normal driving is performed, and in the period represented by the arrow marked with a symbol T02 in FIG. 5, the image signal DIN is not input for a period equivalent to the length of four frame periods when normal driving is performed. In this way, in this embodiment, one frame of image signal DIN may be input for each frame period when normal driving is performed, or a state in which no image signal DIN is input from the outside may continue for any period.

[0042] Please refer to Figure 4. During the period when the polarity bias value is fluctuating between the lower limit and the upper limit, the fixed mode flag is maintained at OFF. During this period, the operation mode is inversion mode, and polarity inversion is performed every time one frame of image signal DIN is input. Below, we will focus on a part of the period in Figure 4.

[0043] At time t1, the polarity bias value changes from a state where it is equal to or greater than the lower limit to a state where it is smaller than the lower limit. This causes the fixed mode flag to change from OFF to ON. At time t2, input of one frame of image signal DIN begins. At that time t2, the fixed mode flag is ON, and the polarity bias value is smaller than the lower limit. Therefore, the polarity of the data voltage in the scanning frame period starting from time t2 becomes positive. As described above, the polarity here is the polarity of the data voltage in the pixel formation portion 4 provided corresponding to the intersection of the gate bus line GL1 and the source bus line SL1. Therefore, for example, for the pixel formation portion 4 provided corresponding to the intersection of the gate bus line GL2 and the source bus line SL1, the polarity of the data voltage in the scanning frame period starting from time t2 becomes negative.

[0044] At time t3, input of one frame of image signal DIN begins. At that time t3, the fixed mode flag is still ON (i.e., the operation mode is fixed mode), and the polarity bias value is smaller than the lower limit value. Therefore, the polarity of the data voltage in the scanning frame period starting from time t3 is maintained as positive polarity. At time t4, the polarity bias value changes from a state in which it is smaller than the lower limit value to a state in which it is equal to or greater than the lower limit value. This causes the fixed mode flag to change from ON to OFF.

[0045] At time t5, input of one frame of image signal DIN starts. At that time t5, the fixed mode flag is OFF. At this time, since the polarity of the data voltage in the scanning frame period that started from time t3 was positive, the polarity indicated by the polarity information held in the polarity information register 120 is positive. Therefore, the polarity of the data voltage in the scanning frame period that starts from time t5 becomes negative.

[0046] At time t6, the polarity bias value changes from a state where it is equal to or less than the upper limit value to a state where it is greater than the upper limit value. This causes the fixed mode flag to change from OFF to ON. At time t7, input of one frame of image signal DIN begins. At that time t7, the fixed mode flag is ON and the polarity bias value is greater than the upper limit value. Therefore, the polarity of the data voltage in the scanning frame period starting from time t7 becomes negative.

[0047] At time t8, input of one frame of image signal DIN begins. At that time t8, the fixed mode flag is still ON (i.e., the operation mode is fixed mode), and the polarity bias value is greater than the upper limit value. Therefore, the polarity of the data voltage in the scanning frame period starting from time t8 is maintained as negative polarity. At time t9, the polarity bias value changes from a state in which it is greater than the upper limit value to a state in which it is equal to or less than the upper limit value. This causes the fixed mode flag to change from ON to OFF.

[0048] At time t10, input of one frame of image signal DIN starts. At that time t10, the fixed mode flag is OFF. At this time, since the polarity of the data voltage in the scanning frame period that started from time t8 was negative, the polarity indicated by the polarity information held in the polarity information register 120 is negative. Therefore, the polarity of the data voltage in the scanning frame period that starts from time t10 becomes positive.

[0049] As described above, when the polarity bias value becomes smaller than the lower limit, the polarity of the data voltage when refreshing is performed is fixed to positive until the polarity bias value becomes equal to or greater than the lower limit, and when the polarity bias value becomes larger than the upper limit, the polarity of the data voltage when refreshing is performed is fixed to negative until the polarity bias value becomes equal to or less than the upper limit. Also, during the period when the polarity bias value is maintained within the range from the lower limit to the upper limit, refreshing is performed with the polarity of the data voltage inverted in response to the input of one frame of image signal DIN.

[0050] <1.3 Effects> In the liquid crystal display device 1 according to this embodiment, refreshing (writing data voltages into the liquid crystal capacitances 42 in each pixel formation section 4 in the display section 400 by sequentially selectively driving a plurality of gate bus lines GL in the display section 400 to update a display image) is performed in synchronization with the image signal DIN sent from the host 2. In such a liquid crystal display device 1, a drive control circuit 100 that controls the operation of the gate driver 200 and the source driver 300 is provided with a counter 130 that counts a polarity bias value that indicates a bias in the polarity of the data voltage. When the image signal DIN is input, the polarity of the data voltage is determined as follows based on the polarity bias value, and refreshing is performed. For a scanning frame period in which the polarity bias value at the start of input of one frame of the image signal DIN is greater than the upper limit value, the polarity of the data voltage is determined so that the polarity bias value becomes smaller, and for a scanning frame period in which the polarity bias value at the start of input of one frame of the image signal DIN is less than the lower limit value, the polarity of the data voltage is determined so that the polarity bias value becomes larger. Therefore, by appropriately setting the upper and lower limits, it is possible to prevent the polarity of the data voltage from becoming so biased that it affects the display quality. As described above, according to this embodiment, in the liquid crystal display device 1 in which the refresh is performed completely in synchronization with the image signal DIN input from the outside, the degradation of the display quality caused by the polarity bias of the data voltage is suppressed.

[0051] <1.4 Modification> In the first embodiment, the fixed mode flag was changed when the polarity bias value changed across the thresholds (upper limit, lower limit). For example, the fixed mode flag was changed from OFF to ON when the polarity bias value changed from a state where it was equal to or greater than the lower limit to a state where it was smaller than the lower limit. However, the present invention is not limited to this. As shown in FIG. 6, the fixed mode flag may be changed at the start of input of the first one frame of image signal DIN after the polarity bias value changed across the thresholds (upper limit, lower limit). In this way, in this modified example, the fixed mode flag is updated based on the polarity bias value at the start of input of one frame of image signal DIN.

[0052] <2. Second embodiment> <2.1 Overview> Generally, the scanning frame period SF includes a vertical blanking period BP during which no vertical scanning is performed, as shown in Fig. 7. In this embodiment, unlike the first embodiment, the counter 130 counts the polarity bias value throughout the vertical blanking period and the pause frame period. Other points are the same as those of the first embodiment.

[0053] <2.2 Example of operation> An example of operation in this embodiment will be described with reference to Fig. 8. As described above, the counter 130 counts the polarity bias value throughout the vertical blanking period and the pause frame period. In other words, the counter 130 does not count the polarity bias value during a period in which a plurality of gate bus lines GL are actually selectively driven in sequence. Therefore, as shown in Fig. 8, the polarity bias value does not change during a period in which a plurality of gate bus lines GL are actually selectively driven in sequence.

[0054] Hereinafter, attention will be focused on a part of the period in FIG. 8. At time t11, the polarity bias value changes from a state where it is equal to or greater than the lower limit to a state where it is smaller than the lower limit. This causes the fixed mode flag to change from OFF to ON. At time t12, the input of one frame of image signal DIN begins. At that time t12, the fixed mode flag is ON, and the polarity bias value is smaller than the lower limit. Therefore, the polarity of the data voltage in the scanning frame period starting from time t12 becomes positive. The polarity bias value does not change during the period from time t12 to time t13, and starts to increase at time t13, which is the start of the vertical blanking period.

[0055] At time t14, input of one frame of image signal DIN begins. At that time t14, the fixed mode flag is still ON (i.e., the operation mode is fixed mode), and the polarity bias value is smaller than the lower limit value. Therefore, the polarity of the data voltage in the scanning frame period starting from time t14 is maintained as positive polarity. At time t15, the polarity bias value changes from a state in which it is smaller than the lower limit value to a state in which it is equal to or greater than the lower limit value. This causes the fixed mode flag to change from ON to OFF.

[0056] At time t16, input of one frame of image signal DIN starts. At that time t16, the fixed mode flag is OFF. At this time, since the polarity of the data voltage in the scanning frame period that started from time t14 was positive, the polarity indicated by the polarity information held in the polarity information register 120 is positive. Therefore, the polarity of the data voltage in the scanning frame period that starts from time t16 becomes negative.

[0057] <2.3 Effects> According to this embodiment, as in the first embodiment described above, in a liquid crystal display device 1 in which refreshing is performed in perfect synchronization with an externally input image signal DIN, degradation of display quality caused by bias in the polarity of the data voltage is suppressed.

[0058] <2.4 Modifications> The degree of charge bias due to the bias in polarity of the data voltage depends on the display grayscale (liquid crystal applied voltage). Therefore, in this modified example, a configuration is adopted in which the polarity bias value increases or decreases according to the average pixel value by counting by the counter 130.

[0059] 9 is a block diagram showing the configuration of the drive control circuit 100 in this modified example. In addition to the components in the first embodiment (see FIG. 1), this drive control circuit 100 includes an average pixel value calculation circuit 160. Focusing on each scanning frame period, the counter 130 counts the polarity bias value during the vertical blanking period. Therefore, at the start of the vertical blanking period of each scanning frame period, the average pixel value calculation circuit 160 calculates the average pixel value during that scanning frame period (the average value of the pixel values ​​of all pixel formation portions 4 in the display unit 400) based on one frame's worth of image signal DIN.

[0060] If the coefficient according to the average pixel value calculated by the average pixel value calculation circuit 160 is represented by K and the predetermined constant is represented by C, in this modification, the counter 130 changes the polarity bias value by K×C per unit time. In this regard, the polarity bias value increases during a period in which the polarity of the data voltage applied to the liquid crystal capacitance 42 is positive, and the polarity bias value decreases during a period in which the polarity of the data voltage applied to the liquid crystal capacitance 42 is negative. As described above, in this modification, the counter 130 increases or decreases the polarity bias value by K×C per unit time according to the polarity of the data voltage applied to the liquid crystal capacitance 42. The constant C is determined in consideration of the characteristics of the panel of the liquid crystal display device 1. In addition, if K×C is represented by Z, Z may be held in the form of a table, or Z may be held as a function with the pixel value as an input value.

[0061] With the above configuration, it is possible to change the polarity bias value more significantly as the average pixel value increases, and vice versa. Thus, according to this modification, it is possible to change the polarity bias value more significantly as the liquid crystal applied voltage increases. This makes it possible to effectively reduce the degree of charge bias in the liquid crystal capacitance 42. As a result, degradation of display quality is more effectively suppressed.

[0062] <3. Third embodiment> <3.1 Overview> There are systems using liquid crystal display devices that dynamically switch between systems in which the liquid crystal display device is driven in synchronization with an input signal and systems in which the liquid crystal display device is driven asynchronously with the input signal. For example, there is a system in which PSR (Panel Self Refresh) driving (a driving method for displaying images using data stored in a frame memory to reduce power consumption) is enabled when displaying still images, and PSR driving is disabled when displaying moving images. Hereinafter, an embodiment in which the present invention is applied to such a system will be described as the third embodiment. The overall configuration is the same as that of the first embodiment (see FIG. 2).

[0063] <3.2 Drive system> In this embodiment, the drive system is dynamically switched between a first system in which the liquid crystal display device 1 (drives a plurality of gate bus lines GL) is driven in synchronization with an image signal DIN sent from a host 2, and a second system in which the liquid crystal display device 1 (drives a plurality of gate bus lines GL) is driven asynchronously with the image signal DIN. When the drive system is the first system, PSR drive is disabled, and when the drive system is the second system, PSR drive is enabled. When still image display is switched to moving image display, the drive system is switched from the second system to the first system, and when moving image display is switched to still image display, the drive system is switched from the first system to the second system.

[0064] <3.3 Drive control circuit> 10 is a block diagram showing the configuration of a drive control circuit 100 in this embodiment. In addition to the components in the first embodiment (see FIG. 1), this drive control circuit 100 includes a frame memory 170. The frame memory 170 holds the most recent frame of image signal DIN sent from the host 2.

[0065] When the drive system is the first system, the drive control circuit 100 operates in the same manner as in the first embodiment. At this time, since the PSR drive is disabled, the frame memory 170 is not used. That is, in the drive control circuit 100, the digital video signal DV is generated directly using the image signal DIN sent from the host 2.

[0066] When the drive system is the second system, the drive control circuit 100 operates so that the polarity bias value changes in the same manner as the conventional method (see FIG. 13) described above. At this time, when the polarity bias value reaches the upper limit, the polarity of the data voltage is changed to negative polarity using the image signal DIN held in the frame memory 170, and a refresh is performed. However, as described above, the polarity here is the polarity of the data voltage in the pixel formation section 4 provided corresponding to the intersection of the gate bus line GL1 and the source bus line SL1, so that the polarity of the data voltage in the pixel formation section 4 provided corresponding to the intersection of the gate bus line GL2 and the source bus line SL1, for example, becomes positive polarity. Also, when the polarity bias value reaches the lower limit, the polarity of the data voltage is changed to positive polarity using the image signal DIN held in the frame memory 170, and a refresh is performed. Also, when the image signal DIN sent from the host 2 is input, a refresh is performed so that a data voltage of the opposite polarity to the polarity of the data voltage applied to the liquid crystal capacitance 42 in the immediately preceding scanning frame period is applied to the liquid crystal capacitance 42.

[0067] From the above, when the drive system is the second system, the drive control circuit 100 operates as follows. When the polarity bias value reaches the upper limit, the drive control circuit 100 uses the image signal DIN held in the frame memory 170 to control the operation of the source driver 300 and the gate driver 200 so that the polarity bias value becomes smaller. When the polarity bias value reaches the lower limit, the drive control circuit 100 uses the image signal DIN held in the frame memory 170 to control the operation of the source driver 300 and the gate driver 200 so that the polarity bias value becomes larger. During a scanning frame period in which the polarity bias value has not reached either the upper limit or the lower limit, the drive control circuit 100 controls the operation of the source driver 300 and the gate driver 200 so that a data voltage of the opposite polarity to the polarity of the data voltage applied to the liquid crystal capacitance 42 in the immediately preceding scanning frame period is applied to the liquid crystal capacitance 42.

[0068] Incidentally, the drive control circuit 100 switches its operation based on a PSR control signal Spsr sent from the host 2. For example, as shown in FIG. 11, during a period when the drive system should be the first system, the host 2 sends a low-level PSR control signal Spsr to the liquid crystal display device 1, and during a period when the drive system should be the second system, the host 2 sends a high-level PSR control signal Spsr to the liquid crystal display device 1. During a period when the PSR control signal Spsr is at a high level, PSR driving is enabled, and the drive control circuit 100 controls the operations of the source driver 300 and the gate driver 200 using the image signal DIN held in the frame memory 170. Note that the operation of the drive control circuit 100 may be switched by sending a command for switching the drive system between the first system and the second system from the host 2 to the liquid crystal display device 1.

[0069] <3.4 Effects> According to this embodiment, in a system in which switching is dynamically performed between a system in which the liquid crystal display device 1 is driven synchronously with an input signal and a system in which the liquid crystal display device 1 is driven asynchronously with the input signal, it is possible to reduce power consumption while suppressing degradation of display quality caused by bias in the polarity of the data voltage.

[0070] <4.Other> Although the present invention has been described in detail above, the above description is illustrative in all respects and is not restrictive, and it will be understood that many other changes and modifications can be made without departing from the scope of the present invention. [Explanation of symbols]

[0071] 1...Liquid crystal display device 2. Host 4...Pixel formation section 42…LCD volume 100...Drive control circuit 110...Polarity control circuit 120...Polarity information register 130…Counter 140...Mode register 150...Mode control circuit 160...Average pixel value calculation circuit 170…Frame memory 200...Gate driver (scanning signal line driving circuit) 300...Source driver (video signal line driving circuit) 400...Display section DIN: Image signal

Claims

1. A liquid crystal display device having a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively, and provided with a scanning frame period during which the plurality of scanning signal lines are selectively driven in sequence in synchronization with an image signal input from an external device, and a pause frame period during which driving of the plurality of scanning signal lines is paused, a video signal line drive circuit that drives the plurality of video signal lines so that a data voltage corresponding to the image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; a drive control circuit including a counter that counts a polarity bias value that indicates a polarity bias of the data voltage applied to the liquid crystal capacitance, and controls operations of the video signal line drive circuit and the scanning signal line drive circuit in response to the polarity bias value; Equipped with during a scanning frame period in which the polarity bias value is greater than a predetermined upper limit value at the time when input of one frame of the image signal is started, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so as to reduce the polarity bias value; during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes larger; a data voltage applied to the liquid crystal capacitance in a polarity opposite to that of the data voltage applied to the liquid crystal capacitance in a scanning frame period immediately before the scanning frame period, the data voltage having ...

2. 2. The liquid crystal display device according to claim 1, wherein the counter counts the polarity bias value throughout the scan frame period and the pause frame period.

3. the scanning frame period includes a vertical blanking period; 2. The liquid crystal display device according to claim 1, wherein the counter counts the polarity bias value throughout the vertical blanking period and the pause frame period.

4. the drive control circuit includes an average pixel value calculation circuit that calculates an average pixel value that is an average value of pixel values ​​of the plurality of pixel formation portions based on the image signal for one frame, 4. The liquid crystal display device according to claim 3, wherein, when a coefficient according to the average pixel value is represented by K and a predetermined constant is represented by C, the counter increases or decreases the polarity bias value by K×C per unit time according to the polarity of the data voltage applied to the liquid crystal capacitance.

5. 5. The liquid crystal display device according to claim 1, wherein the drive control circuit determines whether the polarity bias value at the time when the input of one frame of the image signal starts is greater than or equal to the lower limit value and less than or equal to the upper limit value based on flag data which is binary data.

6. 6. The liquid crystal display device according to claim 5, wherein the flag data is updated every time the polarity bias value is changed, based on the changed polarity bias value.

7. 6. The liquid crystal display device according to claim 5, wherein the flag data is updated based on the polarity bias value at a time point when input of the image signal for one frame is started.

8. A liquid crystal display device having a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines, respectively, and provided with a scanning frame period during which the plurality of scanning signal lines are selectively driven in sequence and a pause frame period during which driving of the plurality of scanning signal lines is paused, a video signal line driving circuit that drives the plurality of video signal lines so that a data voltage corresponding to an externally input image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; a drive control circuit including a counter that counts a polarity bias value that indicates a polarity bias of the data voltage applied to the liquid crystal capacitance, and controls operations of the video signal line drive circuit and the scanning signal line drive circuit in response to the polarity bias value; a frame memory for storing one frame of the image signal; Equipped with a driving system is dynamically switched between a first system in which the driving of the plurality of scanning signal lines is performed in synchronization with the image signal and a second system in which the driving of the plurality of scanning signal lines is performed asynchronously with the image signal; When the drive system is the first system, during a scanning frame period in which the polarity bias value is greater than a predetermined upper limit value at the time when input of one frame of the image signal is started, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so as to reduce the polarity bias value; during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, the drive control circuit controls the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes larger; during a scanning frame period in which the polarity bias value is equal to or greater than the lower limit value and equal to or less than the upper limit value at a time point when input of one frame of the image signal is started, the drive control circuit controls operations of the video signal line drive circuit and the scanning signal line drive circuit so that a data voltage having a polarity opposite to that of the data voltage applied to the liquid crystal capacitance in the immediately preceding scanning frame period is applied to the liquid crystal capacitance; When the drive system is the second system, when the polarity bias value reaches the upper limit value, the drive control circuit uses the image signal stored in the frame memory to control the operation of the video signal line drive circuit and the scanning signal line drive circuit so as to reduce the polarity bias value; when the polarity bias value reaches the lower limit value, the drive control circuit uses the image signal stored in the frame memory to control the operation of the video signal line drive circuit and the scanning signal line drive circuit so that the polarity bias value becomes larger; a data voltage having a polarity opposite to that of the data voltage applied to the liquid crystal capacitance in a scanning frame period immediately before the scanning frame period, the data voltage having a polarity opposite to that of the data voltage applied to the liquid crystal capacitance in a scanning frame period immediately before the scanning frame period, the data voltage being ..., the data voltage being applied to the liquid crystal capacitance in a scanning frame period immediately before the scanning frame period, the data voltage being applied to the liquid crystal capacitance in a scanning frame period, the data voltage being applied to the liquid crystal capacitance in a scanning frame period immediately before the scanning frame period, the data voltage being applied to the liquid crystal capacitance in a scanning frame period, the data voltage

9. 1. A method for driving a liquid crystal display device, which is provided with a scanning frame period in which a plurality of scanning signal lines are selectively driven in sequence in synchronization with an externally input image signal, and a pause frame period in which driving of the plurality of scanning signal lines is paused, comprising: The liquid crystal display device includes: a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to respectively correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines; a video signal line drive circuit that drives the plurality of video signal lines so that a data voltage corresponding to the image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; Equipped with The driving method includes: a polarity bias value counting step of counting a polarity bias value representing a polarity bias of the data voltage applied to the liquid crystal capacitance; a drive control step of controlling operations of the video signal line drive circuit and the scanning signal line drive circuit in accordance with the polarity bias value during the scanning frame period; Including, In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is greater than a predetermined upper limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes smaller; In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes larger; a driving method, characterized in that in the drive control step during a scanning frame period in which the polarity bias value is equal to or greater than the lower limit value and equal to or less than the upper limit value at the time when input of one frame's worth of the image signal is started, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that a data voltage of an opposite polarity to a data voltage applied to the liquid crystal capacitance in a immediately preceding scanning frame period is applied to the liquid crystal capacitance.

10. 1. A method for driving a liquid crystal display device, comprising: a scanning frame period in which a plurality of scanning signal lines are selectively driven in sequence; and a pause frame period in which driving of the plurality of scanning signal lines is paused, the method comprising the steps of: The liquid crystal display device includes: a display section including a plurality of video signal lines, a plurality of scanning signal lines intersecting the plurality of video signal lines, and a plurality of pixel formation sections provided to respectively correspond to intersections of the plurality of video signal lines and the plurality of scanning signal lines; a video signal line driving circuit that drives the plurality of video signal lines so that a data voltage corresponding to an externally input image signal is applied to a liquid crystal capacitance included in each of the plurality of pixel formation portions; a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines in sequence; a frame memory for storing one frame of the image signal; Equipped with In the liquid crystal display device, a drive system is dynamically switched between a first system in which the plurality of scanning signal lines are driven in synchronization with the image signal and a second system in which the plurality of scanning signal lines are driven asynchronously with the image signal, The driving method includes: a polarity bias value counting step of counting a polarity bias value representing a polarity bias of the data voltage applied to the liquid crystal capacitance; a drive control step of controlling operations of the video signal line drive circuit and the scanning signal line drive circuit in accordance with the polarity bias value during the scanning frame period; Including, When the drive system is the first system, In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is greater than a predetermined upper limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes smaller; In the drive control step during a scanning frame period in which the polarity bias value at the time when input of one frame of the image signal is started is smaller than a predetermined lower limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that the polarity bias value becomes larger; in the drive control step in a scanning frame period in which the polarity bias value is equal to or greater than the lower limit value and equal to or less than the upper limit value at the time when input of the image signal for one frame is started, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that a data voltage having a polarity opposite to a polarity of a data voltage applied to the liquid crystal capacitance in the immediately preceding scanning frame period is applied to the liquid crystal capacitance, When the drive system is the second system, When the polarity bias value reaches the upper limit value, in the drive control step, the operation of the video signal line drive circuit and the scanning signal line drive circuit is controlled using the image signal stored in the frame memory so that the polarity bias value becomes smaller, When the polarity bias value reaches the lower limit value, in the drive control step, the operation of the video signal line drive circuit and the scanning signal line drive circuit is controlled using the image signal stored in the frame memory so that the polarity bias value increases by applying the data voltage to the liquid crystal capacitance, a driving method, characterized in that in the drive control step during a scanning frame period in which the polarity bias value has not reached either the upper limit value or the lower limit value, operations of the video signal line drive circuit and the scanning signal line drive circuit are controlled so that a data voltage of an opposite polarity to a polarity of a data voltage applied to the liquid crystal capacitance during the immediately preceding scanning frame period is applied to the liquid crystal capacitance.

Images