Signal output circuit

Abstract

To suppress an increase in the number of signal lines for controlling a device.SOLUTION: A signal output circuit includes a control part for outputting data to each of a plurality of signal lines, and a device for inputting the data outputted by the plurality of signal lines, and outputting the data. The control part further outputs N selection signals that periodically change to sequentially select the data, the device includes a decoder for converting N (N is a positive integer) selection signals into M (M is an integer larger than N) outputs, and a storage part provided corresponding to the data outputted by the plurality of signal lines to be an enable state by the outputs of the decoder, and the storage part stores data in the enable state, and continuously outputs the stored data.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a signal output circuit. [Background technology]

[0002] There is known a technology for inputting a common control signal to multiple devices and collectively controlling the input / output of the multiple devices (for example, Patent Document 1). According to the technology described in Patent Document 1, in addition to the write / read signals, a signal line for an interrupt signal is provided. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6160822 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when adding signal lines for interrupt signals in addition to the write / read signals in order to centrally control input and output, there is a problem in that the number of signal lines required to control devices from the microcontroller increases.

[0005] The present invention has been made in view of the above, and an object of the present invention is to provide a signal output circuit that can suppress an increase in the number of signal lines for controlling a device. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object, the signal output circuit disclosed herein is a signal output circuit including a control unit that outputs data to each of a plurality of signal lines, and a device that inputs data output by the plurality of signal lines and outputs the data, wherein the control unit further outputs N selection signals that change periodically to sequentially select the data, and the device includes a decoder that converts N (N is a positive integer) selection signals into M (M is an integer greater than N) outputs, and a memory unit that is provided corresponding to the data output by the plurality of signal lines and is enabled by the output of the decoder, and the memory unit stores data when enabled and continues to output the stored data. Effect of the Invention

[0007] According to the present invention, it is possible to suppress an increase in the number of signal lines for controlling devices. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a configuration of a signal output circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating the operation of the control board shown in FIG. [Diagram 3] FIG. 3 is a diagram showing an example of a signal output from an output device. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of an output device. [Diagram 5] FIG. 5 is a diagram illustrating an example of the configuration of an input device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In the following description of each embodiment, the same or equivalent components as those in other embodiments are given the same reference numerals, and their description will be simplified or omitted. The present invention is not limited to each embodiment. In addition, the components of each embodiment include those that are replaceable and easy for a person skilled in the art, or those that are substantially the same. The configurations described below can be combined as appropriate. The configurations can be omitted, replaced, or modified without departing from the spirit of the invention.

[0010] (composition) Fig. 1 is a block diagram showing the configuration of a signal output circuit according to an embodiment of the present disclosure. In Fig. 1, a control board 100 corresponds to the signal output circuit of the present disclosure. The control board 100 includes a control unit 20 and output devices 10, 11, 12, and 13.

[0011] The control unit 20 outputs data DATA[2:0] and a selection signal SEL[1:0]. The data DATA[2:0] and the selection signal SEL[1:0] are input to each of the output devices 10, 11, 12, and 13. Here, [2:0] means that data is output to three signal lines from "0" to "2." [1:0] means that a selection signal is output to two signal lines from "0" to "1."

[0012] The output device 10 receives three data signals, "0" through "2." The output device 10 outputs three signals, "OUT0" through "OUT2."

[0013] The output device 11 receives three data signals, "0" through "2." The output device 11 outputs three signals, "OUT3" through "OUT5."

[0014] The output device 12 receives three data signals, "0" through "2," and outputs three signals, "OUT6" through "OUT8."

[0015] The output device 13 receives three data signals "0" through "2". The output device 13 outputs three signals "OUT9" through "OUT11".

[0016] The output devices 10, 11, 12, and 13 can be constructed using a programmable logic device such as a CPLD (Complex Programmable Logic Device) or an FPGA (Field Programmable Gate Array).

[0017] The control unit 20 is, for example, an MCU (Micro Controller Unit). The control unit 20 includes, for example, a CPU (Central Processing Unit) as an arithmetic processing device, a RAM (Random Access Memory), a ROM (Read Only Memory), and the like. The CPU of the control unit 20 can read out a control program. The CPU of the control unit 20 executes the control program, thereby enabling it to output a data signal and a selection signal.

[0018] (Control board operation) Fig. 2 is a diagram for explaining the operation of the control board 100 shown in Fig. 1. In Fig. 2, the horizontal axis represents time t, and the vertical axis represents each signal.

[0019] In FIG. 2, in this example, after data DATA0 changes from "L" level to "H" level, data DATA1 changes from "L" level to "H" level. After data DATA1 changes from "L" level to "H" level, data DATA2 changes from "L" level to "H" level. Also, after data DATA0 changes from "H" level to "L" level, data DATA1 changes from "H" level to "L" level. After data DATA1 changes from "H" level to "L" level, data DATA2 changes from "H" level to "L" level. In this example, the level changes of data DATA0, data DATA1, and data DATA2 are repeated as described above.

[0020] 2, the period from time t1 to time t2 is the valid period T10 of the output device 10. During the valid period T10, the selection signal SEL0 is at the "L" level, and the selection signal SEL1 is at the "L" level. During the valid period T10, the output signal OUT0 has the content of data DATA0, the output signal OUT1 has the content of data DATA1, and the output signal OUT2 has the content of data DATA2. For the other output signals OUT3 to OUT11, the contents of data DATA0, data DATA1, and data DATA2 are not output.

[0021] The period from time t2 to time t3 is the valid period T11 of the output device 11. During the valid period T11, the selection signal SEL0 is at the "H" level, and the selection signal SEL1 is at the "L" level. During the valid period T11, the output signal OUT3 has the content of data DATA0, the output signal OUT4 has the content of data DATA1, and the output signal OUT5 has the content of data DATA2. For the other output signals OUT0 to OUT2 and output signals OUT6 to OUT11, the contents of data DATA0, data DATA1, and data DATA2 are not output.

[0022] The period from time t3 to time t4 is the valid period T12 of the output device 12. During the valid period T12, the selection signal SEL0 is at the "L" level, and the selection signal SEL1 is at the "H" level. During the valid period T12, the output signal OUT6 has the content of data DATA0, the output signal OUT7 has the content of data DATA1, and the output signal OUT8 has the content of data DATA2. For the other output signals OUT0 to OUT5 and output signals OUT9 to OUT11, the contents of data DATA0, data DATA1, and data DATA2 are not output.

[0023] The period from time t4 to time t5 is the valid period T13 of the output device 13. During the valid period T13, the selection signal SEL0 is at the "H" level, and the selection signal SEL1 is at the "H" level. During the valid period T13, the output signal OUT9 has the content of data DATA0, the output signal OUT10 has the content of data DATA1, and the output signal OUT11 has the content of data DATA2. For the other output signals OUT0 to OUT8, the contents of data DATA0, data DATA1, and data DATA2 are not output.

[0024] The period from time t5 to time t6 is the valid period T14 of the output device 10. During the valid period T14, the state is the same as that of the valid period T10, and the selection signal SEL0 is at the "L" level and the selection signal SEL1 is at the "L" level. In other words, the selection signals SEL0 and SEL1 change periodically and repeatedly.

[0025] During the valid period T14, the output signal OUT0 has the content of data DATA0, the output signal OUT1 has the content of data DATA1, and the output signal OUT2 has the content of data DATA2. The other output signals OUT3 to OUT11 do not output the contents of data DATA0, data DATA1, or data DATA2. Note that the same operation as above is repeated even after time t6 in FIG. 2.

[0026] (Example of signal output) 3 is a diagram showing an example of a signal output from an output device, showing the contents of 12 signals from output signals OUT0 to OUT11 in response to changes in the levels of selection signals SEL0 and SEL1.

[0027] In Fig. 3, the levels of the selection signals SEL0 and SEL1 change periodically to sequentially select data. Contents selected based on the levels of the selection signals SEL0 and SEL1 are output as output signals OUT0 to OUT11. In Fig. 3, "hold" means to hold the output state before the state change.

[0028] When the selection signal SEL0 is at the "L" level and the selection signal SEL1 is at the "L" level, the output signal OUT0 has the content of data DATA0, the output signal OUT1 has the content of data DATA1, and the output signal OUT2 has the content of data DATA2. The output contents of the other output signals OUT3 to OUT11 do not change, and the previous output state is maintained.

[0029] When the selection signal SEL0 is at the "H" level and the selection signal SEL1 is at the "L" level, the output signal OUT3 has the content of data DATA0, the output signal OUT4 has the content of data DATA1, and the output signal OUT5 has the content of data DATA2. The output contents of the other output signals OUT0 to OUT2 and output signals OUT6 to OUT11 do not change, and the previous output state is maintained.

[0030] When the selection signal SEL0 is at the "L" level and the selection signal SEL1 is at the "H" level, the output signal OUT6 has the content of data DATA0, the output signal OUT7 has the content of data DATA1, and the output signal OUT8 has the content of data DATA2. The output contents of the other output signals OUT0 to OUT5 and output signals OUT9 to OUT11 do not change, and the previous output state is maintained.

[0031] When the selection signal SEL0 is at the "H" level and the selection signal SEL1 is at the "H" level, the output signal OUT9 has the content of data DATA0, the output signal OUT10 has the content of data DATA1, and the output signal OUT11 has the content of data DATA2. The output contents of the other output signals OUT0 to OUT8 do not change, and the previous output state is maintained.

[0032] (Output Device) Fig. 4 is a diagram showing a configuration example of an output device. In Fig. 4, the output device 13 includes a decoder 30 and D latch circuits 31, 32, and 33. The output device 13 receives data DATA0, data DATA1, and data DATA2 as input. The output device 13 outputs an output signal OUT9, an output signal OUT10, and an output signal OUT11.

[0033] Each of the D latch circuits 31, 32, and 33 has an input D terminal, an output Q terminal, and an enable EN terminal. When an "H" level is input to the enable EN terminal, the D latch circuits 31, 32, and 33 are enabled. When the D latch circuits 31, 32, and 33 are enabled, they take in and output data input to the input D terminal. The enable EN terminal is a terminal for selecting whether the output of each D latch circuit is enabled or disabled. When the input to the enable EN terminal changes from an "H" level to an "L" level, the D latch circuit stores the last output content when it was at the "H" level, and continues to output that content. This makes it possible to avoid a state in which no signal is output. The D latch circuit corresponds to the storage unit of this disclosure.

[0034] That is, the D latch circuit 31 outputs the data DATA0 input to the input D terminal as the output signal OUT9. The D latch circuit 32 outputs the data DATA1 input to the input D terminal as the output signal OUT10. The D latch circuit 33 outputs the data DATA2 input to the input D terminal as the output signal OUT11.

[0035] In this example, the decoder 30 receives two selection signals SEL0 and SEL1 as input. The decoder 30 outputs a decoded signal 300 corresponding to the input selection signals SEL0 and SEL1. The decoder 30 outputs the decoded result as the decoded signal 300. The decoder 30 outputs one of the outputs "0", "1", "2", and "3" as an "H" level. In this example, the output "3" of the decoder 30 is input to each enable EN terminal of the D latch circuits 31, 32, and 33.

[0036] In this example, when the selection signal SEL0 is at the "H" level and the selection signal SEL1 is at the "H" level, the "3" output of the decoded signal 300 becomes "H" level. This causes the D latch circuits 31, 32, and 33, which have the "3" output as an input to their enable EN terminals, to enter an enable state.

[0037] Furthermore, if the selection signal SEL0 is at the "L" level and the selection signal SEL1 is at the "L" level, the "0" output of the decoded signal 300 becomes the "H" level. This causes the D latch circuit (not shown) that receives the "0" output as an input to its enable EN terminal to become enabled.

[0038] Furthermore, if the selection signal SEL0 is at the "H" level and the selection signal SEL1 is at the "L" level, the "1" output of the decoded signal 300 becomes the "H" level. As a result, the D latch circuit (not shown) that receives the "1" output as an input to its enable EN terminal becomes enabled.

[0039] Furthermore, if the selection signal SEL0 is at the "L" level and the selection signal SEL1 is at the "H" level, the "2" output of the decoded signal 300 becomes the "H" level. This causes the D latch circuit (not shown) that uses the "2" output as an input to its enable EN terminal to become enabled.

[0040] In this example, an LED (light-emitting diode) which is a light-emitting element is connected to the output side of the output device 13. The cathode of the LED 41 is connected to the output Q terminal of the D latch circuit 31. The anode of the LED 41 is connected to the power supply Vcc via a resistor 51. Therefore, when the output Q terminal of the D latch circuit 31 becomes the "L" level, a current flows through the LED 41 via the resistor 51, causing the LED 41 to emit light.

[0041] The D latch circuit 31 continues to output the content that it output in the enable state even in a state other than the enable state. In other words, the content that it output in the enable state is held. Therefore, the LED 41 that emitted light in the enable state continues to emit light as long as the output of the D latch circuit 31 is held at the "L" level.

[0042] The cathode of the LED 42 is connected to the output Q terminal of the D latch circuit 32. The anode of the LED 42 is connected to the power supply Vcc via a resistor 52. Therefore, when the output Q terminal of the D latch circuit 32 becomes the "L" level, a current flows through the LED 42 via the resistor 52, causing the LED 42 to emit light.

[0043] The D latch circuit 32 continues to output the content that was output in the enable state even in a state other than the enable state. That is, the content that was output in the enable state is held. Therefore, the LED 42 that was emitting light in the enable state continues to emit light as long as the output of the D latch circuit 32 is held at the "L" level.

[0044] The cathode of the LED 43 is connected to the output Q terminal of the D latch circuit 33. The anode of the LED 43 is connected to the power supply Vcc via a resistor 53. Therefore, when the output Q terminal of the D latch circuit 33 becomes the "L" level, a current flows through the LED 43 via the resistor 53, causing the LED 43 to emit light.

[0045] The D latch circuit 33 continues to output the content that was output in the enable state even in a state other than the enable state. That is, the content that was output in the enable state is held. Therefore, the LED 43 that was emitting light in the enable state continues to emit light as long as the output of the D latch circuit 33 is held at the "L" level.

[0046] 4, when an alarm is in an on or off state, a signal for notifying an upper device of on or off information can be input to the D latch circuit and output. Also, a signal for sounding a buzzer can be input to the D latch circuit and output. Control signals for controlling motors and actuators can be input to the D latch circuit and output.

[0047] Although the above describes a case where the decoder 30 converts two selection signals into four outputs, the present invention is not limited to this, and one selection signal may be converted into two outputs, or three or more selection signals may be converted into a greater number of outputs. In other words, a decoder that converts N selection signals (N is a positive integer) into M outputs (M is an integer greater than N) may be used.

[0048] As described above, by using the decoder 30 and the D latch circuits 31, 32, and 33, a total of 12 data lines, from data DATA0 to data DATA11, can be output by a total of five signals, namely, two selection signals and three data signals. This makes it possible to suppress an increase in the number of signal lines for controlling the device and to expand the number of signal lines.

[0049] (Input Devices) Although the above describes a case where the present disclosure is applied to an output device that outputs data, the present disclosure may also be applied to an input device that inputs data. Fig. 5 is a diagram showing an example of the configuration of an input device. In Fig. 5, an input device 70 includes a decoder 60 and D latch circuits 61, 62, and 63. The input device 70 receives data INA, data INB, and data INC as inputs. The input device 70 outputs output signals DATAA, DATAB, and DATAC.

[0050] The D latch circuits 61, 62, and 63 each have an input D terminal, an output Q terminal, and an enable EN terminal. When an "H" level is input to the enable EN terminal, the D latch circuits 61, 62, and 63 enter an enable state. When the D latch circuits 61, 62, and 63 are in the enable state, they capture and output data input to the input D terminal.

[0051] That is, the D latch circuit 61 outputs the data INA input to the input D terminal as data DATAA. The D latch circuit 62 outputs the data INB input to the input D terminal as data DATAB. The D latch circuit 63 outputs the data INC input to the input D terminal as data DATAC.

[0052] The decoder 60 receives the selection signals SELA and SELB as input. The decoder 60 outputs a decoded signal 600 corresponding to the input selection signals SELA and SELB. The decoder 60 outputs the decoded result as the decoded signal 600. The decoder 60 outputs one of the signals included in the decoded signal 600 as an "H" level. In this example, a signal 601 included in the decoded signal 600 of the decoder 60 is input to each enable EN terminal of the D latch circuits 61, 62, and 63. When the signal 601 is at an "H" level, the D latch circuits 61, 62, and 63 are enabled. The D latch circuits 61, 62, and 63 capture the contents that were input in the enabled state, and continue to output them even in states other than the enabled state.

[0053] The decoder 60 outputs signals corresponding to the combination of levels of the selection signals SELA and SELB for signals other than the signal 601 included in the decoded signal 600. Other D latch circuits (not shown) to whose enable EN terminals a signal included in the decoded signal 600 is input are also enabled depending on the combination of levels of the selection signals SELA and SELB, and continue to capture and output contents that were input in the enabled state even in states other than the enabled state.

[0054] 5, data INA, data INB, and data INC input when a switch (not shown) is in an on or off state can be taken into and output by the D latch circuits 61, 62, and 63. Similarly, data INA, data INB, and data INC input based on the detection result of a sensor (not shown) can be taken into and output by the D latch circuits 61, 62, and 63. Similarly, data INA, data INB, and data INC input based on the detection result of a command signal from a higher-level device (not shown) can be taken into and output by the D latch circuits 61, 62, and 63.

[0055] Although the above describes a case where the decoder 60 converts two selection signals into four outputs, the present invention is not limited to this, and one selection signal may be converted into two outputs, or three or more selection signals may be converted into a greater number of outputs. In other words, a decoder that converts N selection signals (N is a positive integer) into M outputs (M is an integer greater than N) may be used.

[0056] As described above, by using the decoder 60 and the D latch circuits 61, 62, and 63, a total of 12 data lines, from data DATA0 to data DATA11, can be output by a total of five signals, namely, two selection signals and three data signals. This makes it possible to suppress an increase in the number of signal lines for controlling the device and to expand the number of signal lines. [Explanation of symbols]

[0057] 10~13 Output device 20 Control section 30, 60 Decoder 31~33, 61~63 D latch circuit 51~53 Resistance 70 Input Devices 100 Control Board SEL0, SEL1 selection signals

Claims

1. a control unit that outputs data to each of a plurality of signal lines; a device which receives data output by the plurality of signal lines and outputs the data; A signal output circuit comprising: The control unit further outputs N selection signals that change periodically to sequentially select the data; The device comprises: a decoder for converting N selection signals (N being a positive integer) into M selection signals (M being an integer greater than N); a memory section provided in correspondence with the data output by the plurality of signal lines and enabled by an output of the decoder; Equipped with The storage unit stores data when in an enabled state and continues to output the stored data. Signal output circuit.

2. the storage unit is a D latch circuit having an enable terminal, The output of the decoder is input to the enable terminal.

2. The signal output circuit according to claim 1.

3. The light-emitting device further includes a light-emitting element provided in correspondence with the memory unit, The light emitting element emits light based on the data stored in the memory unit.

3. The signal output circuit according to claim 1.

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