Manufacturing method for substrate for display panel

Abstract

To improve the removal efficiency for foreign matters easily.SOLUTION: A manufacturing method for a substrate 30 for a display panel includes a first film forming step S11 of forming a first transparent electrode film L1 on an upper layer side of an insulating substrate GS, a first etching step S12 of patterning, by etching, the first transparent electrode film L1 formed by the first film forming step S11, a first heating step S13 of forming a first electrode 35 by crystallizing the first transparent electrode film by heating after the first etching step S12, and a second etching step S15 of etching away a foreign matter 80 adhering on the first electrode 35 using an acid corrosive after the first heating step S13.SELECTED DRAWING: Figure 8E

Description

[Technical field]

[0001] The present technology relates to a method for manufacturing a display panel substrate. [Background technology]

[0002] In a display panel such as a liquid crystal panel or an organic EL panel, a large number of pixels are arranged in a matrix, and a desired image is displayed by controlling the voltage applied to the pixel electrode of each pixel. The pixel electrodes and the common electrode to which a reference potential is applied are made of a transparent electrode film such as ITO (Indium Tin Oxide), and an example of a manufacturing method thereof is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2009-295461 A

[0004] The method for manufacturing an ITO layer described in Patent Document 1 requires a step of washing the ITO layer with hot water at 30°C to 60°C. In the washing step using hot water, a glass substrate on which an ITO layer is formed is immersed in hot water, which causes a chemical reaction between the water and conductive foreign matter (tin-excess oxide SnO) generated during the formation of the ITO film. This is said to reduce the adhesion strength of the tin-excess oxide, causing it to peel off from the ITO layer and removing the foreign matter. As a result, it is possible to prevent a situation in which a short circuit occurs due to conductive foreign matter adhering to the ITO layer, causing display defects in the display panel. Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the above-mentioned cleaning process using hot water is used, there is a problem that the conventional manufacturing equipment cannot be used as is, and the manufacturing process becomes complicated. Also, since a chemical reaction with water is used, the removal efficiency is not necessarily high.

[0006] The technology described in this specification was completed based on the above-mentioned circumstances, and aims to simply and easily improve the efficiency of removing foreign matter. [Means for solving the problem]

[0007] (1) A manufacturing method of a display panel substrate related to the technology described in the present specification includes a first film formation step of forming a first transparent electrode film on an upper layer side of an insulating substrate, a first etching step of etching and patterning the first transparent electrode film formed in the first film formation step, a first heating step of crystallizing the first transparent electrode film by heating to form a first electrode after the first etching step, and a second etching step of removing foreign matter adhering to the first electrode by etching with an acidic corrosive after the first heating step.

[0008] (2) In addition to the above (1), the manufacturing method for a display panel substrate may further include a second film formation step, which is performed after the first heating step and before the second etching step, of forming a metal film on the first electrode to which the foreign matter is attached, and the second etching step may remove the metal film and the foreign matter.

[0009] (3) In addition to the above (2), the manufacturing method for the display panel substrate may further include the step of: the corrosive agent used in the first etching step is a chemical solution containing oxalic acid as a main component; and the acidic corrosive agent used in the second etching step is a chemical solution containing a mixture of phosphoric acid, nitric acid, and acetic acid.

[0010] (4) Moreover, in addition to the above (1), in the method for manufacturing a display panel substrate, the second etching step may remove the foreign matter and half-etch the first electrode.

[0011] (5) In addition to the above (4), in the method for manufacturing a display panel substrate, the corrosive agent used in the first etching step and the acidic corrosive agent used in the second etching step may both be chemical solutions containing oxalic acid as a main component.

[0012] (6) In addition to any one of (1) to (5) above, the method for manufacturing a display panel substrate may further include a third film formation step of forming an interlayer insulating film on the first electrode after the second etching step, and a fourth film formation step of forming a second transparent electrode film on the interlayer insulating film after the third film formation step. Effect of the Invention

[0013] According to the technology described in the present specification, the efficiency of removing foreign matter can be easily improved. [Brief description of the drawings]

[0014] [Figure 1] 1 is a schematic plan view of a liquid crystal panel according to a first embodiment; [Diagram 2] Cross-section of a liquid crystal panel [Diagram 3] Equivalent circuit diagram of a display pixel [Figure 4] FIG. 2 is a plan view showing pixel electrodes in a meshed pattern in the layout pattern of the array substrate; [Diagram 5] FIG. 2 is a plan view showing a common electrode in a meshed manner in the layout pattern of the array substrate; [Figure 6] Cross section of line II in Figure 4 [Figure 7] Cross-sectional view of line II-II in Figure 5 [Figure 8A] 8A to 8C are diagrams showing a manufacturing process of the array substrate shown in FIG. [Figure 8B] FIG. 8B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 8A; [Figure 8C] FIG. 8C is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 8B. [Figure 8D] FIG. 8C shows a manufacturing process of the array substrate. [Figure 8E] FIG. 8D shows a manufacturing process of the array substrate. [Figure 8F] FIG. 8C is a diagram showing a manufacturing process of the array substrate, subsequent to FIG. 8E. [Figure 8G] FIG. 8F shows a manufacturing process of the array substrate. [Figure 9] 6 is a cross-sectional view of the array substrate according to Comparative Example 1 taken along line II-II in FIG. [Figure 10A] 8A to 8C are diagrams illustrating a manufacturing process according to the second embodiment of the array substrate shown in FIG. 7. [Figure 10B] FIG. 10B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 10A; [Figure 10C] FIG. 10B is a diagram showing a manufacturing process of the array substrate; [Figure 10D] FIG. 10C is a diagram showing a manufacturing process of the array substrate; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] <Embodiment 1> A liquid crystal panel 10 (one example of a display panel) according to embodiment 1 will be described with reference to Fig. 1 to Fig. 8G. Note that the X-axis, Y-axis, and Z-axis are shown in some of the drawings, and each axis direction is drawn to be a common direction in each drawing. Also, the +Z-axis direction is the front side, and the -Z-axis direction is the back side.

[0016] As shown in Fig. 1, the liquid crystal panel 10 is divided into a display area (active area) AA that can display an image and is located at the center, and a non-display area (non-active area) NAA that is located on the outer periphery of the display area AA and has a frame-like (picture frame-like) shape in a plan view. In Fig. 1, the dashed line represents the outer shape of the display area AA, and the area outside the dashed line is the non-display area NAA. The planar shape of the liquid crystal panel 10 is not limited, but in this embodiment, the liquid crystal panel 10 has a vertically long rectangular shape as a whole, with the short side direction coinciding with the X-axis direction, the long side direction coinciding with the Y-axis direction in each drawing, and the plate thickness direction coinciding with the Z-axis direction.

[0017] A driver 13 for driving the display and a flexible substrate 14 are mounted on the liquid crystal panel 10. A control substrate 15 for supplying various input signals to the driver 13 from the outside is connected to the flexible substrate 14.

[0018] 2, the liquid crystal panel 10 has two opposing substrates 20, 30 (one example of a display panel substrate), a liquid crystal layer 18, and a sealing section 50. The liquid crystal layer 18 is sandwiched between the two substrates 20, 30, and contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The sealing section 50 is disposed in the non-display area NAA so as to surround the liquid crystal layer 18, and is interposed between the two substrates 20, 30 to seal the liquid crystal layer 18 while maintaining a cell gap equal to the thickness of the liquid crystal layer 18.

[0019] Of the two substrates 20, 30, the front side is a CF substrate (color filter substrate, counter substrate) 20, and the back side is an array substrate (active matrix substrate, TFT substrate) 30. In the CF substrate 20 and the array substrate 30, various films are laminated on the liquid crystal layer 18 side of a glass substrate GS (an example of an insulating substrate) by a known photolithography method. Polarizing plates 10C, 10D are attached to the outer surface sides (opposite the liquid crystal layer 18) of both substrates 20, 30, respectively.

[0020] In the display area AA of the CF substrate 20, a large number of color filters are arranged in a matrix. The color filters are arranged in a predetermined order with three colored films of R (red), G (green), and B (blue). In the array substrate 30, pixel electrodes 34 (an example of a second electrode) described later are arranged at positions facing each colored film. Each of the R, G, and B colored films and a set of three pixel electrodes 34 facing each of them constitutes one display pixel PX, which is a display unit.

[0021] 3, a large number of TFTs 32, which are switching elements, and pixel electrodes 34 are arranged in a matrix in the display area AA of the array substrate 30. Gate wiring (scanning lines) 36G and source wiring (data lines, signal lines) 36S are arranged in a lattice shape so as to surround the TFTs 32 and the pixel electrodes 34.

[0022] The TFT 32 has a gate electrode 32G connected to the gate line 36G, a source electrode 32S connected to the source line 36S, and a drain electrode 32D connected to the pixel electrode 34. The TFT 32 also has a semiconductor film having one end connected to the source electrode 32S and the other end connected to the drain electrode 32D. The TFT 32 is driven based on a gate signal supplied to the gate line 36G. When a source signal is supplied to the source line 36S during a gate writing period in which the gate signal is equal to or higher than a gate threshold voltage, a current flows between the source electrode 32S and the drain electrode 32D via a channel made of the semiconductor film, and the pixel electrode 34 is charged to a potential according to the source signal.

[0023] An example of a planar layout pattern of each element described above is shown in Fig. 4. The planar layout pattern can be appropriately changed according to the specifications of the liquid crystal panel 10, etc. In Fig. 4, the gate electrode 32G branches off from the gate wiring 36G and protrudes from the gate wiring 36G to the pixel electrode 34 side (upper side) along the Y-axis direction. The source electrode 32S branches off from the source wiring 36S and protrudes to the gate electrode 32G side (right side) along the X-axis direction, with a portion of the electrode overlapping the gate electrode 32G. The drain electrode 32D is spaced apart from the source electrode 32S in the X-axis direction, with a portion of the electrode overlapping the gate electrode 32G.

[0024] The source wiring 36S, the gate wiring 36G, the source electrode 32S, the drain electrode 32D, and the gate electrode 32G are made of a single layer film of a metal, such as aluminum (Al) or molybdenum (Mo), or an alloy, or a laminated film of these. The semiconductor film is disposed so as to overlap the gate electrode 32G via a gate insulating film made of an inorganic insulating material. The semiconductor film is made of an oxide semiconductor (for example, IGZO (Indium Gallium Zinc Oxide)), but amorphous silicon or polysilicon (LTPS) may also be used.

[0025] The pixel electrode 34 is made of a transparent electrode film (e.g., ITO, IZO (Indium Zinc Oxide)) and is disposed on the upper side of the TFT 32. The pixel electrode 34 shown in FIG. 4 has a vertically long rectangular shape as a whole, and three elongated slits 34A that extend along the long sides and are slightly bent are formed. A part of the pixel electrode 34 protrudes toward the drain electrode 32D along the Y-axis direction and overlaps with the drain electrode 32D. The pixel electrode 34 has a contact portion 34B at a portion that overlaps with the drain electrode 32D. As shown in FIG. 6, the contact portion 34B penetrates between the pixel electrode 34 and the drain electrode 32D (specifically, a second interlayer insulating film 38 and a planarizing film 39 described later) and is connected to the drain electrode 32D on the lower layer side. The pixel electrode 34 and the drain electrode 32D are electrically connected to each other by the contact portion 34B.

[0026] Moreover, a common electrode 35 (an example of a first electrode) is formed in a generally solid shape in the display area AA of the array substrate 30. A reference potential is applied to the common electrode 35. The common electrode 35 is made of a transparent electrode film (e.g., ITO, IZO). The common electrode 35 shown in FIG. 5 has an opening 35A and is formed in a solid shape except for this opening 35A.

[0027] Next, the laminated structure of various films of the array substrate 30 will be described. As shown in Fig. 6, the array substrate 30 has a drain electrode 32D, a first interlayer insulating film 37, a planarizing film 39, a common electrode 35, a second interlayer insulating film 38, and a pixel electrode 34 laminated in this order on the glass substrate GS around the contact portion 34B. As shown in Fig. 7, the array substrate 30 has a first interlayer insulating film 37, a planarizing film 39, a common electrode 35, a second interlayer insulating film 38, and a pixel electrode 34 laminated in this order on the glass substrate GS around the pixel electrode 34 where the TFT 32 is not provided. An alignment film is applied to the top layer of the array substrate 30 (the layer closest to the liquid crystal layer 18) so as to cover these various laminated films.

[0028] Both the pixel electrode 34 and the common electrode 35 are formed by a transparent electrode film. Of the two transparent electrode films, one on the lower layer side is called a first transparent electrode film, and the other on the upper layer side is called a second transparent electrode film. In this embodiment, as shown in FIG. 7, the common electrode 35 is provided on the lower layer side of the pixel electrode 34 via a second interlayer insulating film 38. Therefore, the common electrode 35 is an example of a first electrode made of a first transparent electrode film, and the pixel electrode 34 is an example of a second electrode made of a second transparent electrode film. Depending on the configuration of the array substrate 30, the pixel electrode 34 may be a first electrode formed of a first transparent electrode film on the lower layer side, and the common electrode 35 may be a second electrode formed of a second transparent electrode film on the upper layer side.

[0029] During the gate writing period, when a potential difference occurs between the pixel electrode 34 and the common electrode 35, a fringe electric field is applied to the liquid crystal layer 18, which includes a component along the plate surface (XY plane) of the array substrate 30 as well as a component in the normal direction (Z-axis direction) to the plate surface of the array substrate 30. This fringe electric field changes the alignment state of the liquid crystal molecules in the liquid crystal layer 18. As a result, the transmittance of light passing through the liquid crystal panel 10 changes, and the display state of the display pixel PX changes. Note that the driving method of the liquid crystal panel 10 is not limited to FFS (Fringe Field Switching) mode, and may be other methods such as IPS (In Plane Switching) mode.

[0030] The first interlayer insulating film 37 and the second interlayer insulating film 38 are made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2). The planarizing film 39 is made of a transparent organic insulating material such as an acrylic resin (PMMA, etc.) or a polyimide resin, and its thickness is larger than that of the other insulating films (the second interlayer insulating film 38, etc.). The planarizing film 39 planarizes the surface of the display area AA of the array substrate 30. For example, when the thickness of the second interlayer insulating film 38 is about 150 nm to 200 nm, the thickness of the planarizing film 39 is about 2700 nm. In the second interlayer insulating film 38 and the planarizing film 39, as shown in FIG. 6, a contact hole CH is opened and formed to penetrate them. The second interlayer insulating film 38 and the planarizing film 39 are formed in a solid shape in the display area AA except for the contact hole CH.

[0031] Next, a method for manufacturing the array substrate 30 will be described. The process for forming the common electrode 35 on the glass substrate GS in the above-mentioned stacking order can be appropriately performed using the same manufacturing process as the known photolithography method. In the following, the manufacturing process after the formation of the planarizing film 39 will be described in detail with reference to Figures 8A to 8G, taking the stacking process of the cross-sectional portion shown in Figure 7 as an example.

[0032] First, the first transparent electrode film L1 is formed on the planarization film 39 by using a sputtering method, a CVD method, or the like (FIG. 8A, first film formation step S11). The first transparent electrode film L1 is made of, for example, ITO. The formed first transparent electrode film L1 is etched and patterned using a mask having a predetermined pattern, and the mask is peeled off (removed) (FIG. 8B, first etching step S12). Here, the mask is formed to have a predetermined pattern by a known method (for example, applying a resist film on the first transparent electrode film L1, exposing it to light, and developing it). The corrosive agent for the first transparent electrode film L1 used in the first etching step S12 is, for example, an oxalic acid-based chemical solution containing oxalic acid as a main component.

[0033] After the first etching step S12, the patterned first transparent electrode film L1 is heated and crystallized to form the common electrode 35 (FIG. 8C, first heating step S13). The thickness of the common electrode 35 thus formed is, for example, about 60 nm.

[0034] However, in the above-mentioned first film forming step S11, it is extremely difficult to completely prevent the inclusion of the foreign matter 80, and the foreign matter 80 adheres to and is included in the first transparent electrode film L1. For example, when the first transparent electrode film L1 is ITO, the foreign matter 80 is often an indium-based oxide having electrical conductivity, and due to the composition of ITO, it may also contain tin-based oxide. The size of the foreign matter 80 is large, about 500 nm, for example, when the film thickness of the common electrode 35 made of the first transparent electrode film L1 is about 60 nm. When the conductive foreign matter 80 of such a size adheres to the common electrode 35, when the film thickness of the second interlayer insulating film 38 is, for example, a general range of about 150 nm to 200 nm, the foreign matter 80 is not covered from above by the second interlayer insulating film 38 and comes into contact with the pixel electrode 34 (see the array substrate 930 according to Comparative Example 1 shown in FIG. 9). As a result, the pixel electrode 34 and the common electrode 35 are short-circuited by the foreign matter, causing a leak current to flow, which causes a display defect (for example, a black dot display).

[0035] Therefore, in this embodiment, after the first heating step S13, a second film forming step S14 and a second etching step S15 are performed to remove the foreign matter 80. The second film forming step S14 is a step of forming a metal film L2 on the common electrode 35 to which the foreign matter 80 is attached after the first heating step S13 (FIG. 8D). The metal film L2 can be made of the same material as the metal film used for the source wiring 36S, the gate wiring 36G, the source electrode 32S, the drain electrode 32D, and the gate electrode 32G. For example, the metal film L2 is a single layer film of aluminum (Al) or molybdenum (Mo). The thickness of the metal film L2 is preferably about the same as the size of the foreign matter 80. For example, when the size of the foreign matter 80 is about 500 nm, the thickness of the metal film L2 is preferably about 500 nm.

[0036] The second etching process S15 is a process of removing the foreign matter 80 and the metal film L2 by etching after the second film forming process S14 (FIG. 8E). In the second film forming process S14, which is a process preceding the second etching process S15, the common electrode 35 is covered with the metal film L2, so that a reduction in the film thickness of the common electrode 35 in the second etching process S15 can be suppressed.

[0037] The corrosive agent used to remove the foreign matter 80 and the metal film L2 in the second etching step S15 is preferably one that has excellent reactivity to the foreign matter 80 and the metal film L2, but has low reactivity to the common electrode 35 (i.e., the first transparent electrode film L1). In other words, it is preferable that the etching speed of the foreign matter 80 and the metal film L2 is higher than that of the common electrode 35 (the first transparent electrode film L1). The corrosive agent used to remove the foreign matter 80 and the metal film L2 in the second etching step S15 is different from the corrosive agent used to etch the first transparent electrode film L1 in the first etching step S12, and is, for example, a mixed acidic chemical solution of phosphoric acid, nitric acid, and acetic acid. This makes it easier to prevent the common electrode 35 from being reduced in thickness even if the common electrode 35 is exposed to the corrosive agent after the metal film L2 and the foreign matter 80 are removed.

[0038] After the second etching step S15, a second interlayer insulating film 38 is formed on the common electrode 35 by appropriately using the same manufacturing process as a known photolithography method (FIG. 8F, third film forming step S16). The second interlayer insulating film 38 is, for example, silicon nitride (SiNx) having a film thickness of about 150 nm to 200 nm. Next, a second transparent electrode film L3 is formed on the second interlayer insulating film 38 (FIG. 8G, fourth film forming step S17). The formed second transparent electrode film L3 is etched and patterned using a resist film having a predetermined pattern as a mask, and the mask is peeled off (removed). Thereafter, the patterned second transparent electrode film L3 is heated and crystallized to form the common electrode 35 (FIG. 7).

[0039] According to the above-mentioned second etching step S15, an acidic corrosive agent having high reactivity with the foreign matter 80 can be used compared to the cleaning step using warm water described in Patent Document 1, and therefore the removal rate of the foreign matter 80 can be improved. In addition, a manufacturing device for a conventional photolithography method can be used as is, and the removal rate of the foreign matter 80 can be easily improved without complicating the manufacturing process.

[0040] <Embodiment 2> A manufacturing method of an array substrate 30 according to embodiment 2 will be described with reference to Fig. 10A to Fig. 10D. The main difference between embodiment 2 and embodiment 1 is that the second film-forming process S14 is not included. Note that redundant descriptions of the manufacturing process, actions, and effects similar to those of embodiment 1 will be omitted.

[0041] In this embodiment, after the first film forming step S21 (FIG. 10A), the first etching step S22 (FIG. 10B), and the first heating step S23 (FIG. 10C) are performed in order, the second etching step S25 is performed (FIG. 10D) without performing the second film forming step S14 (the film forming step of the metal film L2) of the first embodiment. The second etching step S25 is a step of removing the foreign matter 80 by etching and so-called half-etching the common electrode 35 (reducing the film thickness to, for example, about 50% to 70%). The corrosive agent used in the second etching step S25 does not need to be different from the corrosive agent used in the first etching step S22. For example, an oxalic acid-based chemical solution that is the same as the corrosive agent used in the first etching step S22 can be used. After the second etching step S25, the same manufacturing steps as those of the first embodiment are performed.

[0042] In this way, the foreign matter 80 can be removed without adding the second film-forming step S14 as in embodiment 1. Although the film thickness of the common electrode 35 is reduced by the second etching step S25, the film thickness of the first transparent electrode film L1 in the first film-forming step S21 may be set large in advance in consideration of this film thickness reduction.

[0043] <Other embodiments> The technology described in this specification is not limited to the embodiments described above with reference to the drawings, and for example, the following embodiments are also included within the technical scope of the present invention.

[0044] (1) The layer configuration and layout pattern of the array substrate 30 are not limited to those shown in the drawings. For example, the shapes of the pixel electrodes 34 and the common electrode 35 can be changed as appropriate, and the TFT 32 can be a top-gate type or a dual-gate type TFT. Also, for example, the second interlayer insulating film 38 and the planarizing film 39 can each be composed of two or more insulating films.

[0045] (2) Depending on the driving method of the liquid crystal panel 10, the common electrode 35 may be provided on the CF substrate 20. In that case, the present technology is applicable as a method for removing foreign matter 80 adhering to the common electrode 35 of the CF substrate 20. If the liquid crystal panel 10 is not a color display, the CF substrate 20 does not need to be provided with a color filter.

[0046] (2) The present technology can be applied to display panels other than the liquid crystal panel 10. For example, the technology can be applied to a display panel in which functional organic molecules (medium layer) other than the liquid crystal layer 18 are sandwiched between two substrates 20 and 30, and to a self-luminous display panel such as an organic EL (electro-luminescence) panel. [Explanation of symbols]

[0047] 10... liquid crystal panel (display panel), 30... array substrate (substrate for display panel), 34... pixel electrode (second electrode), 35... common electrode (first electrode), 38... second interlayer insulating film, GS... glass substrate (insulating substrate), L1... first transparent electrode film, L2... metal film, L3... second transparent electrode film, S11, S21... first film formation step, S12, S22... first etching step, S13, S23... first heating step, S14... second film formation step, S15, S25... second etching step, S16... third film formation step

Claims

1. a first film formation step of forming a first transparent electrode film on an upper layer side of an insulating substrate; a first etching step of etching and patterning the first transparent electrode film formed in the first film forming step; a first heating step of crystallizing the first transparent electrode film by heating after the first etching step to form a first electrode; a second etching step of removing foreign matter adhering to the first electrode by etching with an acidic etching agent after the first heating step.

2. a second film formation step, which is performed after the first heating step and before the second etching step, of forming a metal film on the first electrode to which the foreign matter is attached; The method for manufacturing a display panel substrate according to claim 1 , wherein the second etching step removes the metal film and the foreign matter.

3. 3. The method for manufacturing a display panel substrate according to claim 2, wherein the corrosive agent used in the first etching process is a chemical solution mainly composed of oxalic acid, and the acidic corrosive agent used in the second etching process is a chemical solution containing a mixture of phosphoric acid, nitric acid, and acetic acid.

4. 2 . The method of claim 1 , wherein the second etching step removes the foreign matter and half-etches the first electrode.

5. 5. The method for manufacturing a display panel substrate according to claim 4, wherein the corrosive agent used in the first etching step and the acidic corrosive agent used in the second etching step are both chemical solutions containing oxalic acid as a main component.

6. a third film formation step of forming an interlayer insulating film on the first electrode after the second etching step; 6. The method for manufacturing a display panel substrate according to claim 1, further comprising: a fourth film-forming step of forming a second transparent electrode film on the interlayer insulating film after the third film-forming step.

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